arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33 #include "trace.h"
  34
  35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  36
  37 MODULE_AUTHOR("Qumranet");
  38 MODULE_LICENSE("GPL");
  39
  40 #define IOPM_ALLOC_ORDER 2
  41 #define MSRPM_ALLOC_ORDER 1
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_FEATURE_SVML (1 << 2)
  49
  50 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  51 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  52 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  53
  54 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  55
  56 /* Turn on to get debugging output*/
  57 /* #define NESTED_DEBUG */
  58
  59 #ifdef NESTED_DEBUG
  60 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  61 #else
  62 #define nsvm_printk(fmt, args...) do {} while(0)
  63 #endif
  64
  65 static const u32 host_save_user_msrs[] = {
  66 #ifdef CONFIG_X86_64
  67         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  68         MSR_FS_BASE,
  69 #endif
  70         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  71 };
  72
  73 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  74
  75 struct kvm_vcpu;
  76
  77 struct nested_state {
  78         struct vmcb *hsave;
  79         u64 hsave_msr;
  80         u64 vmcb;
  81
  82         /* These are the merged vectors */
  83         u32 *msrpm;
  84
  85         /* gpa pointers to the real vectors */
  86         u64 vmcb_msrpm;
  87
  88         /* cache for intercepts of the guest */
  89         u16 intercept_cr_read;
  90         u16 intercept_cr_write;
  91         u16 intercept_dr_read;
  92         u16 intercept_dr_write;
  93         u32 intercept_exceptions;
  94         u64 intercept;
  95
  96 };
  97
  98 struct vcpu_svm {
  99         struct kvm_vcpu vcpu;
 100         struct vmcb *vmcb;
 101         unsigned long vmcb_pa;
 102         struct svm_cpu_data *svm_data;
 103         uint64_t asid_generation;
 104         uint64_t sysenter_esp;
 105         uint64_t sysenter_eip;
 106
 107         u64 next_rip;
 108
 109         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 110         u64 host_gs_base;
 111
 112         u32 *msrpm;
 113
 114         struct nested_state nested;
 115 };
 116
 117 /* enable NPT for AMD64 and X86 with PAE */
 118 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 119 static bool npt_enabled = true;
 120 #else
 121 static bool npt_enabled = false;
 122 #endif
 123 static int npt = 1;
 124
 125 module_param(npt, int, S_IRUGO);
 126
 127 static int nested = 1;
 128 module_param(nested, int, S_IRUGO);
 129
 130 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 131 static void svm_complete_interrupts(struct vcpu_svm *svm);
 132
 133 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 134 static int nested_svm_vmexit(struct vcpu_svm *svm);
 135 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 136                                       bool has_error_code, u32 error_code);
 137
 138 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 139 {
 140         return container_of(vcpu, struct vcpu_svm, vcpu);
 141 }
 142
 143 static inline bool is_nested(struct vcpu_svm *svm)
 144 {
 145         return svm->nested.vmcb;
 146 }
 147
 148 static inline void enable_gif(struct vcpu_svm *svm)
 149 {
 150         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 151 }
 152
 153 static inline void disable_gif(struct vcpu_svm *svm)
 154 {
 155         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 156 }
 157
 158 static inline bool gif_set(struct vcpu_svm *svm)
 159 {
 160         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 161 }
 162
 163 static unsigned long iopm_base;
 164
 165 struct kvm_ldttss_desc {
 166         u16 limit0;
 167         u16 base0;
 168         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
 169         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
 170         u32 base3;
 171         u32 zero1;
 172 } __attribute__((packed));
 173
 174 struct svm_cpu_data {
 175         int cpu;
 176
 177         u64 asid_generation;
 178         u32 max_asid;
 179         u32 next_asid;
 180         struct kvm_ldttss_desc *tss_desc;
 181
 182         struct page *save_area;
 183 };
 184
 185 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 186 static uint32_t svm_features;
 187
 188 struct svm_init_data {
 189         int cpu;
 190         int r;
 191 };
 192
 193 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 194
 195 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 196 #define MSRS_RANGE_SIZE 2048
 197 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 198
 199 #define MAX_INST_SIZE 15
 200
 201 static inline u32 svm_has(u32 feat)
 202 {
 203         return svm_features & feat;
 204 }
 205
 206 static inline void clgi(void)
 207 {
 208         asm volatile (__ex(SVM_CLGI));
 209 }
 210
 211 static inline void stgi(void)
 212 {
 213         asm volatile (__ex(SVM_STGI));
 214 }
 215
 216 static inline void invlpga(unsigned long addr, u32 asid)
 217 {
 218         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 219 }
 220
 221 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 222 {
 223         to_svm(vcpu)->asid_generation--;
 224 }
 225
 226 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 227 {
 228         force_new_asid(vcpu);
 229 }
 230
 231 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 232 {
 233         if (!npt_enabled && !(efer & EFER_LMA))
 234                 efer &= ~EFER_LME;
 235
 236         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 237         vcpu->arch.shadow_efer = efer;
 238 }
 239
 240 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 241                                 bool has_error_code, u32 error_code)
 242 {
 243         struct vcpu_svm *svm = to_svm(vcpu);
 244
 245         /* If we are within a nested VM we'd better #VMEXIT and let the
 246            guest handle the exception */
 247         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 248                 return;
 249
 250         svm->vmcb->control.event_inj = nr
 251                 | SVM_EVTINJ_VALID
 252                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 253                 | SVM_EVTINJ_TYPE_EXEPT;
 254         svm->vmcb->control.event_inj_err = error_code;
 255 }
 256
 257 static int is_external_interrupt(u32 info)
 258 {
 259         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 260         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 261 }
 262
 263 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 264 {
 265         struct vcpu_svm *svm = to_svm(vcpu);
 266         u32 ret = 0;
 267
 268         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 269                 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
 270         return ret & mask;
 271 }
 272
 273 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 274 {
 275         struct vcpu_svm *svm = to_svm(vcpu);
 276
 277         if (mask == 0)
 278                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 279         else
 280                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 281
 282 }
 283
 284 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 285 {
 286         struct vcpu_svm *svm = to_svm(vcpu);
 287
 288         if (!svm->next_rip) {
 289                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 290                                 EMULATE_DONE)
 291                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 292                 return;
 293         }
 294         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 295                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 296                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 297
 298         kvm_rip_write(vcpu, svm->next_rip);
 299         svm_set_interrupt_shadow(vcpu, 0);
 300 }
 301
 302 static int has_svm(void)
 303 {
 304         const char *msg;
 305
 306         if (!cpu_has_svm(&msg)) {
 307                 printk(KERN_INFO "has_svm: %s\n", msg);
 308                 return 0;
 309         }
 310
 311         return 1;
 312 }
 313
 314 static void svm_hardware_disable(void *garbage)
 315 {
 316         cpu_svm_disable();
 317 }
 318
 319 static int svm_hardware_enable(void *garbage)
 320 {
 321
 322         struct svm_cpu_data *svm_data;
 323         uint64_t efer;
 324         struct descriptor_table gdt_descr;
 325         struct desc_struct *gdt;
 326         int me = raw_smp_processor_id();
 327
 328         rdmsrl(MSR_EFER, efer);
 329         if (efer & EFER_SVME)
 330                 return -EBUSY;
 331
 332         if (!has_svm()) {
 333                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 334                        me);
 335                 return -EINVAL;
 336         }
 337         svm_data = per_cpu(svm_data, me);
 338
 339         if (!svm_data) {
 340                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 341                        me);
 342                 return -EINVAL;
 343         }
 344
 345         svm_data->asid_generation = 1;
 346         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 347         svm_data->next_asid = svm_data->max_asid + 1;
 348
 349         kvm_get_gdt(&gdt_descr);
 350         gdt = (struct desc_struct *)gdt_descr.base;
 351         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 352
 353         wrmsrl(MSR_EFER, efer | EFER_SVME);
 354
 355         wrmsrl(MSR_VM_HSAVE_PA,
 356                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 357
 358         return 0;
 359 }
 360
 361 static void svm_cpu_uninit(int cpu)
 362 {
 363         struct svm_cpu_data *svm_data
 364                 = per_cpu(svm_data, raw_smp_processor_id());
 365
 366         if (!svm_data)
 367                 return;
 368
 369         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 370         __free_page(svm_data->save_area);
 371         kfree(svm_data);
 372 }
 373
 374 static int svm_cpu_init(int cpu)
 375 {
 376         struct svm_cpu_data *svm_data;
 377         int r;
 378
 379         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 380         if (!svm_data)
 381                 return -ENOMEM;
 382         svm_data->cpu = cpu;
 383         svm_data->save_area = alloc_page(GFP_KERNEL);
 384         r = -ENOMEM;
 385         if (!svm_data->save_area)
 386                 goto err_1;
 387
 388         per_cpu(svm_data, cpu) = svm_data;
 389
 390         return 0;
 391
 392 err_1:
 393         kfree(svm_data);
 394         return r;
 395
 396 }
 397
 398 static void set_msr_interception(u32 *msrpm, unsigned msr,
 399                                  int read, int write)
 400 {
 401         int i;
 402
 403         for (i = 0; i < NUM_MSR_MAPS; i++) {
 404                 if (msr >= msrpm_ranges[i] &&
 405                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 406                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 407                                           msrpm_ranges[i]) * 2;
 408
 409                         u32 *base = msrpm + (msr_offset / 32);
 410                         u32 msr_shift = msr_offset % 32;
 411                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 412                         *base = (*base & ~(0x3 << msr_shift)) |
 413                                 (mask << msr_shift);
 414                         return;
 415                 }
 416         }
 417         BUG();
 418 }
 419
 420 static void svm_vcpu_init_msrpm(u32 *msrpm)
 421 {
 422         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 423
 424 #ifdef CONFIG_X86_64
 425         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 426         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 427         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 428         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 429         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 430         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 431 #endif
 432         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 433         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 434 }
 435
 436 static void svm_enable_lbrv(struct vcpu_svm *svm)
 437 {
 438         u32 *msrpm = svm->msrpm;
 439
 440         svm->vmcb->control.lbr_ctl = 1;
 441         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 442         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 443         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 444         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 445 }
 446
 447 static void svm_disable_lbrv(struct vcpu_svm *svm)
 448 {
 449         u32 *msrpm = svm->msrpm;
 450
 451         svm->vmcb->control.lbr_ctl = 0;
 452         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 453         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 454         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 455         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 456 }
 457
 458 static __init int svm_hardware_setup(void)
 459 {
 460         int cpu;
 461         struct page *iopm_pages;
 462         void *iopm_va;
 463         int r;
 464
 465         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 466
 467         if (!iopm_pages)
 468                 return -ENOMEM;
 469
 470         iopm_va = page_address(iopm_pages);
 471         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 472         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 473
 474         if (boot_cpu_has(X86_FEATURE_NX))
 475                 kvm_enable_efer_bits(EFER_NX);
 476
 477         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 478                 kvm_enable_efer_bits(EFER_FFXSR);
 479
 480         if (nested) {
 481                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 482                 kvm_enable_efer_bits(EFER_SVME);
 483         }
 484
 485         for_each_possible_cpu(cpu) {
 486                 r = svm_cpu_init(cpu);
 487                 if (r)
 488                         goto err;
 489         }
 490
 491         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 492
 493         if (!svm_has(SVM_FEATURE_NPT))
 494                 npt_enabled = false;
 495
 496         if (npt_enabled && !npt) {
 497                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 498                 npt_enabled = false;
 499         }
 500
 501         if (npt_enabled) {
 502                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 503                 kvm_enable_tdp();
 504         } else
 505                 kvm_disable_tdp();
 506
 507         return 0;
 508
 509 err:
 510         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 511         iopm_base = 0;
 512         return r;
 513 }
 514
 515 static __exit void svm_hardware_unsetup(void)
 516 {
 517         int cpu;
 518
 519         for_each_possible_cpu(cpu)
 520                 svm_cpu_uninit(cpu);
 521
 522         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 523         iopm_base = 0;
 524 }
 525
 526 static void init_seg(struct vmcb_seg *seg)
 527 {
 528         seg->selector = 0;
 529         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 530                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 531         seg->limit = 0xffff;
 532         seg->base = 0;
 533 }
 534
 535 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 536 {
 537         seg->selector = 0;
 538         seg->attrib = SVM_SELECTOR_P_MASK | type;
 539         seg->limit = 0xffff;
 540         seg->base = 0;
 541 }
 542
 543 static void init_vmcb(struct vcpu_svm *svm)
 544 {
 545         struct vmcb_control_area *control = &svm->vmcb->control;
 546         struct vmcb_save_area *save = &svm->vmcb->save;
 547
 548         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 549                                         INTERCEPT_CR3_MASK |
 550                                         INTERCEPT_CR4_MASK;
 551
 552         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 553                                         INTERCEPT_CR3_MASK |
 554                                         INTERCEPT_CR4_MASK |
 555                                         INTERCEPT_CR8_MASK;
 556
 557         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 558                                         INTERCEPT_DR1_MASK |
 559                                         INTERCEPT_DR2_MASK |
 560                                         INTERCEPT_DR3_MASK;
 561
 562         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 563                                         INTERCEPT_DR1_MASK |
 564                                         INTERCEPT_DR2_MASK |
 565                                         INTERCEPT_DR3_MASK |
 566                                         INTERCEPT_DR5_MASK |
 567                                         INTERCEPT_DR7_MASK;
 568
 569         control->intercept_exceptions = (1 << PF_VECTOR) |
 570                                         (1 << UD_VECTOR) |
 571                                         (1 << MC_VECTOR);
 572
 573
 574         control->intercept =    (1ULL << INTERCEPT_INTR) |
 575                                 (1ULL << INTERCEPT_NMI) |
 576                                 (1ULL << INTERCEPT_SMI) |
 577                                 (1ULL << INTERCEPT_CPUID) |
 578                                 (1ULL << INTERCEPT_INVD) |
 579                                 (1ULL << INTERCEPT_HLT) |
 580                                 (1ULL << INTERCEPT_INVLPG) |
 581                                 (1ULL << INTERCEPT_INVLPGA) |
 582                                 (1ULL << INTERCEPT_IOIO_PROT) |
 583                                 (1ULL << INTERCEPT_MSR_PROT) |
 584                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 585                                 (1ULL << INTERCEPT_SHUTDOWN) |
 586                                 (1ULL << INTERCEPT_VMRUN) |
 587                                 (1ULL << INTERCEPT_VMMCALL) |
 588                                 (1ULL << INTERCEPT_VMLOAD) |
 589                                 (1ULL << INTERCEPT_VMSAVE) |
 590                                 (1ULL << INTERCEPT_STGI) |
 591                                 (1ULL << INTERCEPT_CLGI) |
 592                                 (1ULL << INTERCEPT_SKINIT) |
 593                                 (1ULL << INTERCEPT_WBINVD) |
 594                                 (1ULL << INTERCEPT_MONITOR) |
 595                                 (1ULL << INTERCEPT_MWAIT);
 596
 597         control->iopm_base_pa = iopm_base;
 598         control->msrpm_base_pa = __pa(svm->msrpm);
 599         control->tsc_offset = 0;
 600         control->int_ctl = V_INTR_MASKING_MASK;
 601
 602         init_seg(&save->es);
 603         init_seg(&save->ss);
 604         init_seg(&save->ds);
 605         init_seg(&save->fs);
 606         init_seg(&save->gs);
 607
 608         save->cs.selector = 0xf000;
 609         /* Executable/Readable Code Segment */
 610         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 611                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 612         save->cs.limit = 0xffff;
 613         /*
 614          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 615          * be consistent with it.
 616          *
 617          * Replace when we have real mode working for vmx.
 618          */
 619         save->cs.base = 0xf0000;
 620
 621         save->gdtr.limit = 0xffff;
 622         save->idtr.limit = 0xffff;
 623
 624         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 625         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 626
 627         save->efer = EFER_SVME;
 628         save->dr6 = 0xffff0ff0;
 629         save->dr7 = 0x400;
 630         save->rflags = 2;
 631         save->rip = 0x0000fff0;
 632         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 633
 634         /*
 635          * cr0 val on cpu init should be 0x60000010, we enable cpu
 636          * cache by default. the orderly way is to enable cache in bios.
 637          */
 638         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 639         save->cr4 = X86_CR4_PAE;
 640         /* rdx = ?? */
 641
 642         if (npt_enabled) {
 643                 /* Setup VMCB for Nested Paging */
 644                 control->nested_ctl = 1;
 645                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 646                                         (1ULL << INTERCEPT_INVLPG));
 647                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 648                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 649                                                 INTERCEPT_CR3_MASK);
 650                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 651                                                  INTERCEPT_CR3_MASK);
 652                 save->g_pat = 0x0007040600070406ULL;
 653                 /* enable caching because the QEMU Bios doesn't enable it */
 654                 save->cr0 = X86_CR0_ET;
 655                 save->cr3 = 0;
 656                 save->cr4 = 0;
 657         }
 658         force_new_asid(&svm->vcpu);
 659
 660         svm->nested.vmcb = 0;
 661         svm->vcpu.arch.hflags = 0;
 662
 663         enable_gif(svm);
 664 }
 665
 666 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 667 {
 668         struct vcpu_svm *svm = to_svm(vcpu);
 669
 670         init_vmcb(svm);
 671
 672         if (!kvm_vcpu_is_bsp(vcpu)) {
 673                 kvm_rip_write(vcpu, 0);
 674                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 675                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 676         }
 677         vcpu->arch.regs_avail = ~0;
 678         vcpu->arch.regs_dirty = ~0;
 679
 680         return 0;
 681 }
 682
 683 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 684 {
 685         struct vcpu_svm *svm;
 686         struct page *page;
 687         struct page *msrpm_pages;
 688         struct page *hsave_page;
 689         struct page *nested_msrpm_pages;
 690         int err;
 691
 692         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 693         if (!svm) {
 694                 err = -ENOMEM;
 695                 goto out;
 696         }
 697
 698         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 699         if (err)
 700                 goto free_svm;
 701
 702         page = alloc_page(GFP_KERNEL);
 703         if (!page) {
 704                 err = -ENOMEM;
 705                 goto uninit;
 706         }
 707
 708         err = -ENOMEM;
 709         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 710         if (!msrpm_pages)
 711                 goto uninit;
 712
 713         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 714         if (!nested_msrpm_pages)
 715                 goto uninit;
 716
 717         svm->msrpm = page_address(msrpm_pages);
 718         svm_vcpu_init_msrpm(svm->msrpm);
 719
 720         hsave_page = alloc_page(GFP_KERNEL);
 721         if (!hsave_page)
 722                 goto uninit;
 723         svm->nested.hsave = page_address(hsave_page);
 724
 725         svm->nested.msrpm = page_address(nested_msrpm_pages);
 726
 727         svm->vmcb = page_address(page);
 728         clear_page(svm->vmcb);
 729         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 730         svm->asid_generation = 0;
 731         init_vmcb(svm);
 732
 733         fx_init(&svm->vcpu);
 734         svm->vcpu.fpu_active = 1;
 735         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 736         if (kvm_vcpu_is_bsp(&svm->vcpu))
 737                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 738
 739         return &svm->vcpu;
 740
 741 uninit:
 742         kvm_vcpu_uninit(&svm->vcpu);
 743 free_svm:
 744         kmem_cache_free(kvm_vcpu_cache, svm);
 745 out:
 746         return ERR_PTR(err);
 747 }
 748
 749 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 750 {
 751         struct vcpu_svm *svm = to_svm(vcpu);
 752
 753         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 754         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 755         __free_page(virt_to_page(svm->nested.hsave));
 756         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 757         kvm_vcpu_uninit(vcpu);
 758         kmem_cache_free(kvm_vcpu_cache, svm);
 759 }
 760
 761 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 762 {
 763         struct vcpu_svm *svm = to_svm(vcpu);
 764         int i;
 765
 766         if (unlikely(cpu != vcpu->cpu)) {
 767                 u64 delta;
 768
 769                 /*
 770                  * Make sure that the guest sees a monotonically
 771                  * increasing TSC.
 772                  */
 773                 delta = vcpu->arch.host_tsc - native_read_tsc();
 774                 svm->vmcb->control.tsc_offset += delta;
 775                 if (is_nested(svm))
 776                         svm->nested.hsave->control.tsc_offset += delta;
 777                 vcpu->cpu = cpu;
 778                 kvm_migrate_timers(vcpu);
 779                 svm->asid_generation = 0;
 780         }
 781
 782         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 783                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 784 }
 785
 786 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 787 {
 788         struct vcpu_svm *svm = to_svm(vcpu);
 789         int i;
 790
 791         ++vcpu->stat.host_state_reload;
 792         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 793                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 794
 795         vcpu->arch.host_tsc = native_read_tsc();
 796 }
 797
 798 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 799 {
 800         return to_svm(vcpu)->vmcb->save.rflags;
 801 }
 802
 803 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 804 {
 805         to_svm(vcpu)->vmcb->save.rflags = rflags;
 806 }
 807
 808 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 809 {
 810         switch (reg) {
 811         case VCPU_EXREG_PDPTR:
 812                 BUG_ON(!npt_enabled);
 813                 load_pdptrs(vcpu, vcpu->arch.cr3);
 814                 break;
 815         default:
 816                 BUG();
 817         }
 818 }
 819
 820 static void svm_set_vintr(struct vcpu_svm *svm)
 821 {
 822         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 823 }
 824
 825 static void svm_clear_vintr(struct vcpu_svm *svm)
 826 {
 827         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 828 }
 829
 830 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 831 {
 832         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 833
 834         switch (seg) {
 835         case VCPU_SREG_CS: return &save->cs;
 836         case VCPU_SREG_DS: return &save->ds;
 837         case VCPU_SREG_ES: return &save->es;
 838         case VCPU_SREG_FS: return &save->fs;
 839         case VCPU_SREG_GS: return &save->gs;
 840         case VCPU_SREG_SS: return &save->ss;
 841         case VCPU_SREG_TR: return &save->tr;
 842         case VCPU_SREG_LDTR: return &save->ldtr;
 843         }
 844         BUG();
 845         return NULL;
 846 }
 847
 848 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 849 {
 850         struct vmcb_seg *s = svm_seg(vcpu, seg);
 851
 852         return s->base;
 853 }
 854
 855 static void svm_get_segment(struct kvm_vcpu *vcpu,
 856                             struct kvm_segment *var, int seg)
 857 {
 858         struct vmcb_seg *s = svm_seg(vcpu, seg);
 859
 860         var->base = s->base;
 861         var->limit = s->limit;
 862         var->selector = s->selector;
 863         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 864         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 865         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 866         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 867         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 868         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 869         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 870         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 871
 872         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 873          * for cross vendor migration purposes by "not present"
 874          */
 875         var->unusable = !var->present || (var->type == 0);
 876
 877         switch (seg) {
 878         case VCPU_SREG_CS:
 879                 /*
 880                  * SVM always stores 0 for the 'G' bit in the CS selector in
 881                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 882                  * Intel's VMENTRY has a check on the 'G' bit.
 883                  */
 884                 var->g = s->limit > 0xfffff;
 885                 break;
 886         case VCPU_SREG_TR:
 887                 /*
 888                  * Work around a bug where the busy flag in the tr selector
 889                  * isn't exposed
 890                  */
 891                 var->type |= 0x2;
 892                 break;
 893         case VCPU_SREG_DS:
 894         case VCPU_SREG_ES:
 895         case VCPU_SREG_FS:
 896         case VCPU_SREG_GS:
 897                 /*
 898                  * The accessed bit must always be set in the segment
 899                  * descriptor cache, although it can be cleared in the
 900                  * descriptor, the cached bit always remains at 1. Since
 901                  * Intel has a check on this, set it here to support
 902                  * cross-vendor migration.
 903                  */
 904                 if (!var->unusable)
 905                         var->type |= 0x1;
 906                 break;
 907         case VCPU_SREG_SS:
 908                 /* On AMD CPUs sometimes the DB bit in the segment
 909                  * descriptor is left as 1, although the whole segment has
 910                  * been made unusable. Clear it here to pass an Intel VMX
 911                  * entry check when cross vendor migrating.
 912                  */
 913                 if (var->unusable)
 914                         var->db = 0;
 915                 break;
 916         }
 917 }
 918
 919 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 920 {
 921         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 922
 923         return save->cpl;
 924 }
 925
 926 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 927 {
 928         struct vcpu_svm *svm = to_svm(vcpu);
 929
 930         dt->limit = svm->vmcb->save.idtr.limit;
 931         dt->base = svm->vmcb->save.idtr.base;
 932 }
 933
 934 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 935 {
 936         struct vcpu_svm *svm = to_svm(vcpu);
 937
 938         svm->vmcb->save.idtr.limit = dt->limit;
 939         svm->vmcb->save.idtr.base = dt->base ;
 940 }
 941
 942 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 943 {
 944         struct vcpu_svm *svm = to_svm(vcpu);
 945
 946         dt->limit = svm->vmcb->save.gdtr.limit;
 947         dt->base = svm->vmcb->save.gdtr.base;
 948 }
 949
 950 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 951 {
 952         struct vcpu_svm *svm = to_svm(vcpu);
 953
 954         svm->vmcb->save.gdtr.limit = dt->limit;
 955         svm->vmcb->save.gdtr.base = dt->base ;
 956 }
 957
 958 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 959 {
 960 }
 961
 962 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 963 {
 964         struct vcpu_svm *svm = to_svm(vcpu);
 965
 966 #ifdef CONFIG_X86_64
 967         if (vcpu->arch.shadow_efer & EFER_LME) {
 968                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 969                         vcpu->arch.shadow_efer |= EFER_LMA;
 970                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 971                 }
 972
 973                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 974                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 975                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 976                 }
 977         }
 978 #endif
 979         if (npt_enabled)
 980                 goto set;
 981
 982         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 983                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 984                 vcpu->fpu_active = 1;
 985         }
 986
 987         vcpu->arch.cr0 = cr0;
 988         cr0 |= X86_CR0_PG | X86_CR0_WP;
 989         if (!vcpu->fpu_active) {
 990                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 991                 cr0 |= X86_CR0_TS;
 992         }
 993 set:
 994         /*
 995          * re-enable caching here because the QEMU bios
 996          * does not do it - this results in some delay at
 997          * reboot
 998          */
 999         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1000         svm->vmcb->save.cr0 = cr0;
1001 }
1002
1003 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1004 {
1005         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1006         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1007
1008         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1009                 force_new_asid(vcpu);
1010
1011         vcpu->arch.cr4 = cr4;
1012         if (!npt_enabled)
1013                 cr4 |= X86_CR4_PAE;
1014         cr4 |= host_cr4_mce;
1015         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1016 }
1017
1018 static void svm_set_segment(struct kvm_vcpu *vcpu,
1019                             struct kvm_segment *var, int seg)
1020 {
1021         struct vcpu_svm *svm = to_svm(vcpu);
1022         struct vmcb_seg *s = svm_seg(vcpu, seg);
1023
1024         s->base = var->base;
1025         s->limit = var->limit;
1026         s->selector = var->selector;
1027         if (var->unusable)
1028                 s->attrib = 0;
1029         else {
1030                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1031                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1032                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1033                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1034                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1035                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1036                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1037                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1038         }
1039         if (seg == VCPU_SREG_CS)
1040                 svm->vmcb->save.cpl
1041                         = (svm->vmcb->save.cs.attrib
1042                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1043
1044 }
1045
1046 static void update_db_intercept(struct kvm_vcpu *vcpu)
1047 {
1048         struct vcpu_svm *svm = to_svm(vcpu);
1049
1050         svm->vmcb->control.intercept_exceptions &=
1051                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1052
1053         if (vcpu->arch.singlestep)
1054                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1055
1056         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1057                 if (vcpu->guest_debug &
1058                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1059                         svm->vmcb->control.intercept_exceptions |=
1060                                 1 << DB_VECTOR;
1061                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1062                         svm->vmcb->control.intercept_exceptions |=
1063                                 1 << BP_VECTOR;
1064         } else
1065                 vcpu->guest_debug = 0;
1066 }
1067
1068 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1069 {
1070         struct vcpu_svm *svm = to_svm(vcpu);
1071
1072         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1073                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1074         else
1075                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1076
1077         update_db_intercept(vcpu);
1078 }
1079
1080 static void load_host_msrs(struct kvm_vcpu *vcpu)
1081 {
1082 #ifdef CONFIG_X86_64
1083         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1084 #endif
1085 }
1086
1087 static void save_host_msrs(struct kvm_vcpu *vcpu)
1088 {
1089 #ifdef CONFIG_X86_64
1090         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1091 #endif
1092 }
1093
1094 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1095 {
1096         if (svm_data->next_asid > svm_data->max_asid) {
1097                 ++svm_data->asid_generation;
1098                 svm_data->next_asid = 1;
1099                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1100         }
1101
1102         svm->asid_generation = svm_data->asid_generation;
1103         svm->vmcb->control.asid = svm_data->next_asid++;
1104 }
1105
1106 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1107 {
1108         struct vcpu_svm *svm = to_svm(vcpu);
1109         unsigned long val;
1110
1111         switch (dr) {
1112         case 0 ... 3:
1113                 val = vcpu->arch.db[dr];
1114                 break;
1115         case 6:
1116                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1117                         val = vcpu->arch.dr6;
1118                 else
1119                         val = svm->vmcb->save.dr6;
1120                 break;
1121         case 7:
1122                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1123                         val = vcpu->arch.dr7;
1124                 else
1125                         val = svm->vmcb->save.dr7;
1126                 break;
1127         default:
1128                 val = 0;
1129         }
1130
1131         return val;
1132 }
1133
1134 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1135                        int *exception)
1136 {
1137         struct vcpu_svm *svm = to_svm(vcpu);
1138
1139         *exception = 0;
1140
1141         switch (dr) {
1142         case 0 ... 3:
1143                 vcpu->arch.db[dr] = value;
1144                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1145                         vcpu->arch.eff_db[dr] = value;
1146                 return;
1147         case 4 ... 5:
1148                 if (vcpu->arch.cr4 & X86_CR4_DE)
1149                         *exception = UD_VECTOR;
1150                 return;
1151         case 6:
1152                 if (value & 0xffffffff00000000ULL) {
1153                         *exception = GP_VECTOR;
1154                         return;
1155                 }
1156                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1157                 return;
1158         case 7:
1159                 if (value & 0xffffffff00000000ULL) {
1160                         *exception = GP_VECTOR;
1161                         return;
1162                 }
1163                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1164                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1165                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1166                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1167                 }
1168                 return;
1169         default:
1170                 /* FIXME: Possible case? */
1171                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1172                        __func__, dr);
1173                 *exception = UD_VECTOR;
1174                 return;
1175         }
1176 }
1177
1178 static int pf_interception(struct vcpu_svm *svm)
1179 {
1180         u64 fault_address;
1181         u32 error_code;
1182
1183         fault_address  = svm->vmcb->control.exit_info_2;
1184         error_code = svm->vmcb->control.exit_info_1;
1185
1186         trace_kvm_page_fault(fault_address, error_code);
1187         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1188                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1189         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1190 }
1191
1192 static int db_interception(struct vcpu_svm *svm)
1193 {
1194         struct kvm_run *kvm_run = svm->vcpu.run;
1195
1196         if (!(svm->vcpu.guest_debug &
1197               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1198                 !svm->vcpu.arch.singlestep) {
1199                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1200                 return 1;
1201         }
1202
1203         if (svm->vcpu.arch.singlestep) {
1204                 svm->vcpu.arch.singlestep = false;
1205                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1206                         svm->vmcb->save.rflags &=
1207                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1208                 update_db_intercept(&svm->vcpu);
1209         }
1210
1211         if (svm->vcpu.guest_debug &
1212             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1213                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1214                 kvm_run->debug.arch.pc =
1215                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1216                 kvm_run->debug.arch.exception = DB_VECTOR;
1217                 return 0;
1218         }
1219
1220         return 1;
1221 }
1222
1223 static int bp_interception(struct vcpu_svm *svm)
1224 {
1225         struct kvm_run *kvm_run = svm->vcpu.run;
1226
1227         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1228         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1229         kvm_run->debug.arch.exception = BP_VECTOR;
1230         return 0;
1231 }
1232
1233 static int ud_interception(struct vcpu_svm *svm)
1234 {
1235         int er;
1236
1237         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1238         if (er != EMULATE_DONE)
1239                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1240         return 1;
1241 }
1242
1243 static int nm_interception(struct vcpu_svm *svm)
1244 {
1245         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1246         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1247                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1248         svm->vcpu.fpu_active = 1;
1249
1250         return 1;
1251 }
1252
1253 static int mc_interception(struct vcpu_svm *svm)
1254 {
1255         /*
1256          * On an #MC intercept the MCE handler is not called automatically in
1257          * the host. So do it by hand here.
1258          */
1259         asm volatile (
1260                 "int $0x12\n");
1261         /* not sure if we ever come back to this point */
1262
1263         return 1;
1264 }
1265
1266 static int shutdown_interception(struct vcpu_svm *svm)
1267 {
1268         struct kvm_run *kvm_run = svm->vcpu.run;
1269
1270         /*
1271          * VMCB is undefined after a SHUTDOWN intercept
1272          * so reinitialize it.
1273          */
1274         clear_page(svm->vmcb);
1275         init_vmcb(svm);
1276
1277         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1278         return 0;
1279 }
1280
1281 static int io_interception(struct vcpu_svm *svm)
1282 {
1283         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1284         int size, in, string;
1285         unsigned port;
1286
1287         ++svm->vcpu.stat.io_exits;
1288
1289         svm->next_rip = svm->vmcb->control.exit_info_2;
1290
1291         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1292
1293         if (string) {
1294                 if (emulate_instruction(&svm->vcpu,
1295                                         0, 0, 0) == EMULATE_DO_MMIO)
1296                         return 0;
1297                 return 1;
1298         }
1299
1300         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1301         port = io_info >> 16;
1302         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1303
1304         skip_emulated_instruction(&svm->vcpu);
1305         return kvm_emulate_pio(&svm->vcpu, in, size, port);
1306 }
1307
1308 static int nmi_interception(struct vcpu_svm *svm)
1309 {
1310         return 1;
1311 }
1312
1313 static int intr_interception(struct vcpu_svm *svm)
1314 {
1315         ++svm->vcpu.stat.irq_exits;
1316         return 1;
1317 }
1318
1319 static int nop_on_interception(struct vcpu_svm *svm)
1320 {
1321         return 1;
1322 }
1323
1324 static int halt_interception(struct vcpu_svm *svm)
1325 {
1326         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1327         skip_emulated_instruction(&svm->vcpu);
1328         return kvm_emulate_halt(&svm->vcpu);
1329 }
1330
1331 static int vmmcall_interception(struct vcpu_svm *svm)
1332 {
1333         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1334         skip_emulated_instruction(&svm->vcpu);
1335         kvm_emulate_hypercall(&svm->vcpu);
1336         return 1;
1337 }
1338
1339 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1340 {
1341         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1342             || !is_paging(&svm->vcpu)) {
1343                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1344                 return 1;
1345         }
1346
1347         if (svm->vmcb->save.cpl) {
1348                 kvm_inject_gp(&svm->vcpu, 0);
1349                 return 1;
1350         }
1351
1352        return 0;
1353 }
1354
1355 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1356                                       bool has_error_code, u32 error_code)
1357 {
1358         if (!is_nested(svm))
1359                 return 0;
1360
1361         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1362         svm->vmcb->control.exit_code_hi = 0;
1363         svm->vmcb->control.exit_info_1 = error_code;
1364         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1365
1366         return nested_svm_exit_handled(svm);
1367 }
1368
1369 static inline int nested_svm_intr(struct vcpu_svm *svm)
1370 {
1371         if (!is_nested(svm))
1372                 return 0;
1373
1374         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1375                 return 0;
1376
1377         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1378                 return 0;
1379
1380         svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1381
1382         if (nested_svm_exit_handled(svm)) {
1383                 nsvm_printk("VMexit -> INTR\n");
1384                 return 1;
1385         }
1386
1387         return 0;
1388 }
1389
1390 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1391 {
1392         struct page *page;
1393
1394         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1395         if (is_error_page(page))
1396                 goto error;
1397
1398         return kmap_atomic(page, idx);
1399
1400 error:
1401         kvm_release_page_clean(page);
1402         kvm_inject_gp(&svm->vcpu, 0);
1403
1404         return NULL;
1405 }
1406
1407 static void nested_svm_unmap(void *addr, enum km_type idx)
1408 {
1409         struct page *page;
1410
1411         if (!addr)
1412                 return;
1413
1414         page = kmap_atomic_to_page(addr);
1415
1416         kunmap_atomic(addr, idx);
1417         kvm_release_page_dirty(page);
1418 }
1419
1420 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1421 {
1422         u32 param = svm->vmcb->control.exit_info_1 & 1;
1423         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1424         bool ret = false;
1425         u32 t0, t1;
1426         u8 *msrpm;
1427
1428         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1429                 return false;
1430
1431         msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1432
1433         if (!msrpm)
1434                 goto out;
1435
1436         switch (msr) {
1437         case 0 ... 0x1fff:
1438                 t0 = (msr * 2) % 8;
1439                 t1 = msr / 8;
1440                 break;
1441         case 0xc0000000 ... 0xc0001fff:
1442                 t0 = (8192 + msr - 0xc0000000) * 2;
1443                 t1 = (t0 / 8);
1444                 t0 %= 8;
1445                 break;
1446         case 0xc0010000 ... 0xc0011fff:
1447                 t0 = (16384 + msr - 0xc0010000) * 2;
1448                 t1 = (t0 / 8);
1449                 t0 %= 8;
1450                 break;
1451         default:
1452                 ret = true;
1453                 goto out;
1454         }
1455
1456         ret = msrpm[t1] & ((1 << param) << t0);
1457
1458 out:
1459         nested_svm_unmap(msrpm, KM_USER0);
1460
1461         return ret;
1462 }
1463
1464 static int nested_svm_exit_special(struct vcpu_svm *svm)
1465 {
1466         u32 exit_code = svm->vmcb->control.exit_code;
1467
1468         switch (exit_code) {
1469         case SVM_EXIT_INTR:
1470         case SVM_EXIT_NMI:
1471                 return NESTED_EXIT_HOST;
1472                 /* For now we are always handling NPFs when using them */
1473         case SVM_EXIT_NPF:
1474                 if (npt_enabled)
1475                         return NESTED_EXIT_HOST;
1476                 break;
1477         /* When we're shadowing, trap PFs */
1478         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1479                 if (!npt_enabled)
1480                         return NESTED_EXIT_HOST;
1481                 break;
1482         default:
1483                 break;
1484         }
1485
1486         return NESTED_EXIT_CONTINUE;
1487 }
1488
1489 /*
1490  * If this function returns true, this #vmexit was already handled
1491  */
1492 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1493 {
1494         u32 exit_code = svm->vmcb->control.exit_code;
1495         int vmexit = NESTED_EXIT_HOST;
1496
1497         switch (exit_code) {
1498         case SVM_EXIT_MSR:
1499                 vmexit = nested_svm_exit_handled_msr(svm);
1500                 break;
1501         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1502                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1503                 if (svm->nested.intercept_cr_read & cr_bits)
1504                         vmexit = NESTED_EXIT_DONE;
1505                 break;
1506         }
1507         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1508                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1509                 if (svm->nested.intercept_cr_write & cr_bits)
1510                         vmexit = NESTED_EXIT_DONE;
1511                 break;
1512         }
1513         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1514                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1515                 if (svm->nested.intercept_dr_read & dr_bits)
1516                         vmexit = NESTED_EXIT_DONE;
1517                 break;
1518         }
1519         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1520                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1521                 if (svm->nested.intercept_dr_write & dr_bits)
1522                         vmexit = NESTED_EXIT_DONE;
1523                 break;
1524         }
1525         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1526                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1527                 if (svm->nested.intercept_exceptions & excp_bits)
1528                         vmexit = NESTED_EXIT_DONE;
1529                 break;
1530         }
1531         default: {
1532                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1533                 nsvm_printk("exit code: 0x%x\n", exit_code);
1534                 if (svm->nested.intercept & exit_bits)
1535                         vmexit = NESTED_EXIT_DONE;
1536         }
1537         }
1538
1539         if (vmexit == NESTED_EXIT_DONE) {
1540                 nsvm_printk("#VMEXIT reason=%04x\n", exit_code);
1541                 nested_svm_vmexit(svm);
1542         }
1543
1544         return vmexit;
1545 }
1546
1547 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1548 {
1549         struct vmcb_control_area *dst  = &dst_vmcb->control;
1550         struct vmcb_control_area *from = &from_vmcb->control;
1551
1552         dst->intercept_cr_read    = from->intercept_cr_read;
1553         dst->intercept_cr_write   = from->intercept_cr_write;
1554         dst->intercept_dr_read    = from->intercept_dr_read;
1555         dst->intercept_dr_write   = from->intercept_dr_write;
1556         dst->intercept_exceptions = from->intercept_exceptions;
1557         dst->intercept            = from->intercept;
1558         dst->iopm_base_pa         = from->iopm_base_pa;
1559         dst->msrpm_base_pa        = from->msrpm_base_pa;
1560         dst->tsc_offset           = from->tsc_offset;
1561         dst->asid                 = from->asid;
1562         dst->tlb_ctl              = from->tlb_ctl;
1563         dst->int_ctl              = from->int_ctl;
1564         dst->int_vector           = from->int_vector;
1565         dst->int_state            = from->int_state;
1566         dst->exit_code            = from->exit_code;
1567         dst->exit_code_hi         = from->exit_code_hi;
1568         dst->exit_info_1          = from->exit_info_1;
1569         dst->exit_info_2          = from->exit_info_2;
1570         dst->exit_int_info        = from->exit_int_info;
1571         dst->exit_int_info_err    = from->exit_int_info_err;
1572         dst->nested_ctl           = from->nested_ctl;
1573         dst->event_inj            = from->event_inj;
1574         dst->event_inj_err        = from->event_inj_err;
1575         dst->nested_cr3           = from->nested_cr3;
1576         dst->lbr_ctl              = from->lbr_ctl;
1577 }
1578
1579 static int nested_svm_vmexit(struct vcpu_svm *svm)
1580 {
1581         struct vmcb *nested_vmcb;
1582         struct vmcb *hsave = svm->nested.hsave;
1583         struct vmcb *vmcb = svm->vmcb;
1584
1585         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1586         if (!nested_vmcb)
1587                 return 1;
1588
1589         /* Give the current vmcb to the guest */
1590         disable_gif(svm);
1591
1592         nested_vmcb->save.es     = vmcb->save.es;
1593         nested_vmcb->save.cs     = vmcb->save.cs;
1594         nested_vmcb->save.ss     = vmcb->save.ss;
1595         nested_vmcb->save.ds     = vmcb->save.ds;
1596         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1597         nested_vmcb->save.idtr   = vmcb->save.idtr;
1598         if (npt_enabled)
1599                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1600         nested_vmcb->save.cr2    = vmcb->save.cr2;
1601         nested_vmcb->save.rflags = vmcb->save.rflags;
1602         nested_vmcb->save.rip    = vmcb->save.rip;
1603         nested_vmcb->save.rsp    = vmcb->save.rsp;
1604         nested_vmcb->save.rax    = vmcb->save.rax;
1605         nested_vmcb->save.dr7    = vmcb->save.dr7;
1606         nested_vmcb->save.dr6    = vmcb->save.dr6;
1607         nested_vmcb->save.cpl    = vmcb->save.cpl;
1608
1609         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1610         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1611         nested_vmcb->control.int_state         = vmcb->control.int_state;
1612         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1613         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1614         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1615         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1616         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1617         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1618
1619         /*
1620          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1621          * to make sure that we do not lose injected events. So check event_inj
1622          * here and copy it to exit_int_info if it is valid.
1623          * Exit_int_info and event_inj can't be both valid because the case
1624          * below only happens on a VMRUN instruction intercept which has
1625          * no valid exit_int_info set.
1626          */
1627         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1628                 struct vmcb_control_area *nc = &nested_vmcb->control;
1629
1630                 nc->exit_int_info     = vmcb->control.event_inj;
1631                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1632         }
1633
1634         nested_vmcb->control.tlb_ctl           = 0;
1635         nested_vmcb->control.event_inj         = 0;
1636         nested_vmcb->control.event_inj_err     = 0;
1637
1638         /* We always set V_INTR_MASKING and remember the old value in hflags */
1639         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1640                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1641
1642         /* Restore the original control entries */
1643         copy_vmcb_control_area(vmcb, hsave);
1644
1645         /* Kill any pending exceptions */
1646         if (svm->vcpu.arch.exception.pending == true)
1647                 nsvm_printk("WARNING: Pending Exception\n");
1648
1649         kvm_clear_exception_queue(&svm->vcpu);
1650         kvm_clear_interrupt_queue(&svm->vcpu);
1651
1652         /* Restore selected save entries */
1653         svm->vmcb->save.es = hsave->save.es;
1654         svm->vmcb->save.cs = hsave->save.cs;
1655         svm->vmcb->save.ss = hsave->save.ss;
1656         svm->vmcb->save.ds = hsave->save.ds;
1657         svm->vmcb->save.gdtr = hsave->save.gdtr;
1658         svm->vmcb->save.idtr = hsave->save.idtr;
1659         svm->vmcb->save.rflags = hsave->save.rflags;
1660         svm_set_efer(&svm->vcpu, hsave->save.efer);
1661         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1662         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1663         if (npt_enabled) {
1664                 svm->vmcb->save.cr3 = hsave->save.cr3;
1665                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1666         } else {
1667                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1668         }
1669         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1670         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1671         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1672         svm->vmcb->save.dr7 = 0;
1673         svm->vmcb->save.cpl = 0;
1674         svm->vmcb->control.exit_int_info = 0;
1675
1676         /* Exit nested SVM mode */
1677         svm->nested.vmcb = 0;
1678
1679         nested_svm_unmap(nested_vmcb, KM_USER0);
1680
1681         kvm_mmu_reset_context(&svm->vcpu);
1682         kvm_mmu_load(&svm->vcpu);
1683
1684         return 0;
1685 }
1686
1687 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1688 {
1689         u32 *nested_msrpm;
1690         int i;
1691
1692         nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1693         if (!nested_msrpm)
1694                 return false;
1695
1696         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1697                 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1698
1699         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1700
1701         nested_svm_unmap(nested_msrpm, KM_USER0);
1702
1703         return true;
1704 }
1705
1706 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1707 {
1708         struct vmcb *nested_vmcb;
1709         struct vmcb *hsave = svm->nested.hsave;
1710         struct vmcb *vmcb = svm->vmcb;
1711
1712         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1713         if (!nested_vmcb)
1714                 return false;
1715
1716         /* nested_vmcb is our indicator if nested SVM is activated */
1717         svm->nested.vmcb = svm->vmcb->save.rax;
1718
1719         /* Clear internal status */
1720         kvm_clear_exception_queue(&svm->vcpu);
1721         kvm_clear_interrupt_queue(&svm->vcpu);
1722
1723         /* Save the old vmcb, so we don't need to pick what we save, but
1724            can restore everything when a VMEXIT occurs */
1725         hsave->save.es     = vmcb->save.es;
1726         hsave->save.cs     = vmcb->save.cs;
1727         hsave->save.ss     = vmcb->save.ss;
1728         hsave->save.ds     = vmcb->save.ds;
1729         hsave->save.gdtr   = vmcb->save.gdtr;
1730         hsave->save.idtr   = vmcb->save.idtr;
1731         hsave->save.efer   = svm->vcpu.arch.shadow_efer;
1732         hsave->save.cr0    = svm->vcpu.arch.cr0;
1733         hsave->save.cr4    = svm->vcpu.arch.cr4;
1734         hsave->save.rflags = vmcb->save.rflags;
1735         hsave->save.rip    = svm->next_rip;
1736         hsave->save.rsp    = vmcb->save.rsp;
1737         hsave->save.rax    = vmcb->save.rax;
1738         if (npt_enabled)
1739                 hsave->save.cr3    = vmcb->save.cr3;
1740         else
1741                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1742
1743         copy_vmcb_control_area(hsave, vmcb);
1744
1745         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1746                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1747         else
1748                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1749
1750         /* Load the nested guest state */
1751         svm->vmcb->save.es = nested_vmcb->save.es;
1752         svm->vmcb->save.cs = nested_vmcb->save.cs;
1753         svm->vmcb->save.ss = nested_vmcb->save.ss;
1754         svm->vmcb->save.ds = nested_vmcb->save.ds;
1755         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1756         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1757         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1758         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1759         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1760         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1761         if (npt_enabled) {
1762                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1763                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1764         } else {
1765                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1766                 kvm_mmu_reset_context(&svm->vcpu);
1767         }
1768         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1769         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1770         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1771         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1772         /* In case we don't even reach vcpu_run, the fields are not updated */
1773         svm->vmcb->save.rax = nested_vmcb->save.rax;
1774         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1775         svm->vmcb->save.rip = nested_vmcb->save.rip;
1776         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1777         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1778         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1779
1780         /* We don't want a nested guest to be more powerful than the guest,
1781            so all intercepts are ORed */
1782         svm->vmcb->control.intercept_cr_read |=
1783                 nested_vmcb->control.intercept_cr_read;
1784         svm->vmcb->control.intercept_cr_write |=
1785                 nested_vmcb->control.intercept_cr_write;
1786         svm->vmcb->control.intercept_dr_read |=
1787                 nested_vmcb->control.intercept_dr_read;
1788         svm->vmcb->control.intercept_dr_write |=
1789                 nested_vmcb->control.intercept_dr_write;
1790         svm->vmcb->control.intercept_exceptions |=
1791                 nested_vmcb->control.intercept_exceptions;
1792
1793         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1794
1795         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1796
1797         /* cache intercepts */
1798         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
1799         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
1800         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
1801         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
1802         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1803         svm->nested.intercept            = nested_vmcb->control.intercept;
1804
1805         force_new_asid(&svm->vcpu);
1806         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1807         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1808                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1809                                 nested_vmcb->control.int_ctl);
1810         }
1811         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1812                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1813         else
1814                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1815
1816         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1817                         nested_vmcb->control.exit_int_info,
1818                         nested_vmcb->control.int_state);
1819
1820         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1821         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1822         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1823         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1824                 nsvm_printk("Injecting Event: 0x%x\n",
1825                                 nested_vmcb->control.event_inj);
1826         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1827         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1828
1829         nested_svm_unmap(nested_vmcb, KM_USER0);
1830
1831         enable_gif(svm);
1832
1833         return true;
1834 }
1835
1836 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1837 {
1838         to_vmcb->save.fs = from_vmcb->save.fs;
1839         to_vmcb->save.gs = from_vmcb->save.gs;
1840         to_vmcb->save.tr = from_vmcb->save.tr;
1841         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1842         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1843         to_vmcb->save.star = from_vmcb->save.star;
1844         to_vmcb->save.lstar = from_vmcb->save.lstar;
1845         to_vmcb->save.cstar = from_vmcb->save.cstar;
1846         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1847         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1848         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1849         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1850 }
1851
1852 static int vmload_interception(struct vcpu_svm *svm)
1853 {
1854         struct vmcb *nested_vmcb;
1855
1856         if (nested_svm_check_permissions(svm))
1857                 return 1;
1858
1859         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1860         skip_emulated_instruction(&svm->vcpu);
1861
1862         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1863         if (!nested_vmcb)
1864                 return 1;
1865
1866         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1867         nested_svm_unmap(nested_vmcb, KM_USER0);
1868
1869         return 1;
1870 }
1871
1872 static int vmsave_interception(struct vcpu_svm *svm)
1873 {
1874         struct vmcb *nested_vmcb;
1875
1876         if (nested_svm_check_permissions(svm))
1877                 return 1;
1878
1879         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1880         skip_emulated_instruction(&svm->vcpu);
1881
1882         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1883         if (!nested_vmcb)
1884                 return 1;
1885
1886         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1887         nested_svm_unmap(nested_vmcb, KM_USER0);
1888
1889         return 1;
1890 }
1891
1892 static int vmrun_interception(struct vcpu_svm *svm)
1893 {
1894         nsvm_printk("VMrun\n");
1895
1896         if (nested_svm_check_permissions(svm))
1897                 return 1;
1898
1899         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1900         skip_emulated_instruction(&svm->vcpu);
1901
1902         if (!nested_svm_vmrun(svm))
1903                 return 1;
1904
1905         if (!nested_svm_vmrun_msrpm(svm))
1906                 goto failed;
1907
1908         return 1;
1909
1910 failed:
1911
1912         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
1913         svm->vmcb->control.exit_code_hi = 0;
1914         svm->vmcb->control.exit_info_1  = 0;
1915         svm->vmcb->control.exit_info_2  = 0;
1916
1917         nested_svm_vmexit(svm);
1918
1919         return 1;
1920 }
1921
1922 static int stgi_interception(struct vcpu_svm *svm)
1923 {
1924         if (nested_svm_check_permissions(svm))
1925                 return 1;
1926
1927         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1928         skip_emulated_instruction(&svm->vcpu);
1929
1930         enable_gif(svm);
1931
1932         return 1;
1933 }
1934
1935 static int clgi_interception(struct vcpu_svm *svm)
1936 {
1937         if (nested_svm_check_permissions(svm))
1938                 return 1;
1939
1940         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1941         skip_emulated_instruction(&svm->vcpu);
1942
1943         disable_gif(svm);
1944
1945         /* After a CLGI no interrupts should come */
1946         svm_clear_vintr(svm);
1947         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1948
1949         return 1;
1950 }
1951
1952 static int invlpga_interception(struct vcpu_svm *svm)
1953 {
1954         struct kvm_vcpu *vcpu = &svm->vcpu;
1955         nsvm_printk("INVLPGA\n");
1956
1957         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1958         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1959
1960         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1961         skip_emulated_instruction(&svm->vcpu);
1962         return 1;
1963 }
1964
1965 static int invalid_op_interception(struct vcpu_svm *svm)
1966 {
1967         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1968         return 1;
1969 }
1970
1971 static int task_switch_interception(struct vcpu_svm *svm)
1972 {
1973         u16 tss_selector;
1974         int reason;
1975         int int_type = svm->vmcb->control.exit_int_info &
1976                 SVM_EXITINTINFO_TYPE_MASK;
1977         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1978         uint32_t type =
1979                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1980         uint32_t idt_v =
1981                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1982
1983         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1984
1985         if (svm->vmcb->control.exit_info_2 &
1986             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1987                 reason = TASK_SWITCH_IRET;
1988         else if (svm->vmcb->control.exit_info_2 &
1989                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1990                 reason = TASK_SWITCH_JMP;
1991         else if (idt_v)
1992                 reason = TASK_SWITCH_GATE;
1993         else
1994                 reason = TASK_SWITCH_CALL;
1995
1996         if (reason == TASK_SWITCH_GATE) {
1997                 switch (type) {
1998                 case SVM_EXITINTINFO_TYPE_NMI:
1999                         svm->vcpu.arch.nmi_injected = false;
2000                         break;
2001                 case SVM_EXITINTINFO_TYPE_EXEPT:
2002                         kvm_clear_exception_queue(&svm->vcpu);
2003                         break;
2004                 case SVM_EXITINTINFO_TYPE_INTR:
2005                         kvm_clear_interrupt_queue(&svm->vcpu);
2006                         break;
2007                 default:
2008                         break;
2009                 }
2010         }
2011
2012         if (reason != TASK_SWITCH_GATE ||
2013             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2014             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2015              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2016                 skip_emulated_instruction(&svm->vcpu);
2017
2018         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2019 }
2020
2021 static int cpuid_interception(struct vcpu_svm *svm)
2022 {
2023         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2024         kvm_emulate_cpuid(&svm->vcpu);
2025         return 1;
2026 }
2027
2028 static int iret_interception(struct vcpu_svm *svm)
2029 {
2030         ++svm->vcpu.stat.nmi_window_exits;
2031         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2032         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2033         return 1;
2034 }
2035
2036 static int invlpg_interception(struct vcpu_svm *svm)
2037 {
2038         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2039                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2040         return 1;
2041 }
2042
2043 static int emulate_on_interception(struct vcpu_svm *svm)
2044 {
2045         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2046                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2047         return 1;
2048 }
2049
2050 static int cr8_write_interception(struct vcpu_svm *svm)
2051 {
2052         struct kvm_run *kvm_run = svm->vcpu.run;
2053
2054         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2055         /* instruction emulation calls kvm_set_cr8() */
2056         emulate_instruction(&svm->vcpu, 0, 0, 0);
2057         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2058                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2059                 return 1;
2060         }
2061         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2062                 return 1;
2063         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2064         return 0;
2065 }
2066
2067 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2068 {
2069         struct vcpu_svm *svm = to_svm(vcpu);
2070
2071         switch (ecx) {
2072         case MSR_IA32_TSC: {
2073                 u64 tsc_offset;
2074
2075                 if (is_nested(svm))
2076                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2077                 else
2078                         tsc_offset = svm->vmcb->control.tsc_offset;
2079
2080                 *data = tsc_offset + native_read_tsc();
2081                 break;
2082         }
2083         case MSR_K6_STAR:
2084                 *data = svm->vmcb->save.star;
2085                 break;
2086 #ifdef CONFIG_X86_64
2087         case MSR_LSTAR:
2088                 *data = svm->vmcb->save.lstar;
2089                 break;
2090         case MSR_CSTAR:
2091                 *data = svm->vmcb->save.cstar;
2092                 break;
2093         case MSR_KERNEL_GS_BASE:
2094                 *data = svm->vmcb->save.kernel_gs_base;
2095                 break;
2096         case MSR_SYSCALL_MASK:
2097                 *data = svm->vmcb->save.sfmask;
2098                 break;
2099 #endif
2100         case MSR_IA32_SYSENTER_CS:
2101                 *data = svm->vmcb->save.sysenter_cs;
2102                 break;
2103         case MSR_IA32_SYSENTER_EIP:
2104                 *data = svm->sysenter_eip;
2105                 break;
2106         case MSR_IA32_SYSENTER_ESP:
2107                 *data = svm->sysenter_esp;
2108                 break;
2109         /* Nobody will change the following 5 values in the VMCB so
2110            we can safely return them on rdmsr. They will always be 0
2111            until LBRV is implemented. */
2112         case MSR_IA32_DEBUGCTLMSR:
2113                 *data = svm->vmcb->save.dbgctl;
2114                 break;
2115         case MSR_IA32_LASTBRANCHFROMIP:
2116                 *data = svm->vmcb->save.br_from;
2117                 break;
2118         case MSR_IA32_LASTBRANCHTOIP:
2119                 *data = svm->vmcb->save.br_to;
2120                 break;
2121         case MSR_IA32_LASTINTFROMIP:
2122                 *data = svm->vmcb->save.last_excp_from;
2123                 break;
2124         case MSR_IA32_LASTINTTOIP:
2125                 *data = svm->vmcb->save.last_excp_to;
2126                 break;
2127         case MSR_VM_HSAVE_PA:
2128                 *data = svm->nested.hsave_msr;
2129                 break;
2130         case MSR_VM_CR:
2131                 *data = 0;
2132                 break;
2133         case MSR_IA32_UCODE_REV:
2134                 *data = 0x01000065;
2135                 break;
2136         default:
2137                 return kvm_get_msr_common(vcpu, ecx, data);
2138         }
2139         return 0;
2140 }
2141
2142 static int rdmsr_interception(struct vcpu_svm *svm)
2143 {
2144         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2145         u64 data;
2146
2147         if (svm_get_msr(&svm->vcpu, ecx, &data))
2148                 kvm_inject_gp(&svm->vcpu, 0);
2149         else {
2150                 trace_kvm_msr_read(ecx, data);
2151
2152                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2153                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2154                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2155                 skip_emulated_instruction(&svm->vcpu);
2156         }
2157         return 1;
2158 }
2159
2160 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2161 {
2162         struct vcpu_svm *svm = to_svm(vcpu);
2163
2164         switch (ecx) {
2165         case MSR_IA32_TSC: {
2166                 u64 tsc_offset = data - native_read_tsc();
2167                 u64 g_tsc_offset = 0;
2168
2169                 if (is_nested(svm)) {
2170                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2171                                        svm->nested.hsave->control.tsc_offset;
2172                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2173                 }
2174
2175                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2176
2177                 break;
2178         }
2179         case MSR_K6_STAR:
2180                 svm->vmcb->save.star = data;
2181                 break;
2182 #ifdef CONFIG_X86_64
2183         case MSR_LSTAR:
2184                 svm->vmcb->save.lstar = data;
2185                 break;
2186         case MSR_CSTAR:
2187                 svm->vmcb->save.cstar = data;
2188                 break;
2189         case MSR_KERNEL_GS_BASE:
2190                 svm->vmcb->save.kernel_gs_base = data;
2191                 break;
2192         case MSR_SYSCALL_MASK:
2193                 svm->vmcb->save.sfmask = data;
2194                 break;
2195 #endif
2196         case MSR_IA32_SYSENTER_CS:
2197                 svm->vmcb->save.sysenter_cs = data;
2198                 break;
2199         case MSR_IA32_SYSENTER_EIP:
2200                 svm->sysenter_eip = data;
2201                 svm->vmcb->save.sysenter_eip = data;
2202                 break;
2203         case MSR_IA32_SYSENTER_ESP:
2204                 svm->sysenter_esp = data;
2205                 svm->vmcb->save.sysenter_esp = data;
2206                 break;
2207         case MSR_IA32_DEBUGCTLMSR:
2208                 if (!svm_has(SVM_FEATURE_LBRV)) {
2209                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2210                                         __func__, data);
2211                         break;
2212                 }
2213                 if (data & DEBUGCTL_RESERVED_BITS)
2214                         return 1;
2215
2216                 svm->vmcb->save.dbgctl = data;
2217                 if (data & (1ULL<<0))
2218                         svm_enable_lbrv(svm);
2219                 else
2220                         svm_disable_lbrv(svm);
2221                 break;
2222         case MSR_VM_HSAVE_PA:
2223                 svm->nested.hsave_msr = data;
2224                 break;
2225         case MSR_VM_CR:
2226         case MSR_VM_IGNNE:
2227                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2228                 break;
2229         default:
2230                 return kvm_set_msr_common(vcpu, ecx, data);
2231         }
2232         return 0;
2233 }
2234
2235 static int wrmsr_interception(struct vcpu_svm *svm)
2236 {
2237         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2238         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2239                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2240
2241         trace_kvm_msr_write(ecx, data);
2242
2243         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2244         if (svm_set_msr(&svm->vcpu, ecx, data))
2245                 kvm_inject_gp(&svm->vcpu, 0);
2246         else
2247                 skip_emulated_instruction(&svm->vcpu);
2248         return 1;
2249 }
2250
2251 static int msr_interception(struct vcpu_svm *svm)
2252 {
2253         if (svm->vmcb->control.exit_info_1)
2254                 return wrmsr_interception(svm);
2255         else
2256                 return rdmsr_interception(svm);
2257 }
2258
2259 static int interrupt_window_interception(struct vcpu_svm *svm)
2260 {
2261         struct kvm_run *kvm_run = svm->vcpu.run;
2262
2263         svm_clear_vintr(svm);
2264         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2265         /*
2266          * If the user space waits to inject interrupts, exit as soon as
2267          * possible
2268          */
2269         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2270             kvm_run->request_interrupt_window &&
2271             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2272                 ++svm->vcpu.stat.irq_window_exits;
2273                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2274                 return 0;
2275         }
2276
2277         return 1;
2278 }
2279
2280 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2281         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2282         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2283         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2284         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2285         /* for now: */
2286         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2287         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2288         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2289         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2290         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2291         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2292         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2293         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2294         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2295         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2296         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2297         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2298         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2299         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2300         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2301         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2302         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2303         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2304         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2305         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2306         [SVM_EXIT_INTR]                         = intr_interception,
2307         [SVM_EXIT_NMI]                          = nmi_interception,
2308         [SVM_EXIT_SMI]                          = nop_on_interception,
2309         [SVM_EXIT_INIT]                         = nop_on_interception,
2310         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2311         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2312         [SVM_EXIT_CPUID]                        = cpuid_interception,
2313         [SVM_EXIT_IRET]                         = iret_interception,
2314         [SVM_EXIT_INVD]                         = emulate_on_interception,
2315         [SVM_EXIT_HLT]                          = halt_interception,
2316         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2317         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2318         [SVM_EXIT_IOIO]                         = io_interception,
2319         [SVM_EXIT_MSR]                          = msr_interception,
2320         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2321         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2322         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2323         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2324         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2325         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2326         [SVM_EXIT_STGI]                         = stgi_interception,
2327         [SVM_EXIT_CLGI]                         = clgi_interception,
2328         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
2329         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2330         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2331         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2332         [SVM_EXIT_NPF]                          = pf_interception,
2333 };
2334
2335 static int handle_exit(struct kvm_vcpu *vcpu)
2336 {
2337         struct vcpu_svm *svm = to_svm(vcpu);
2338         struct kvm_run *kvm_run = vcpu->run;
2339         u32 exit_code = svm->vmcb->control.exit_code;
2340
2341         trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2342
2343         if (is_nested(svm)) {
2344                 int vmexit;
2345
2346                 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2347                             exit_code, svm->vmcb->control.exit_info_1,
2348                             svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2349
2350                 vmexit = nested_svm_exit_special(svm);
2351
2352                 if (vmexit == NESTED_EXIT_CONTINUE)
2353                         vmexit = nested_svm_exit_handled(svm);
2354
2355                 if (vmexit == NESTED_EXIT_DONE)
2356                         return 1;
2357         }
2358
2359         svm_complete_interrupts(svm);
2360
2361         if (npt_enabled) {
2362                 int mmu_reload = 0;
2363                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2364                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2365                         mmu_reload = 1;
2366                 }
2367                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2368                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2369                 if (mmu_reload) {
2370                         kvm_mmu_reset_context(vcpu);
2371                         kvm_mmu_load(vcpu);
2372                 }
2373         }
2374
2375
2376         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2377                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2378                 kvm_run->fail_entry.hardware_entry_failure_reason
2379                         = svm->vmcb->control.exit_code;
2380                 return 0;
2381         }
2382
2383         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2384             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2385             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2386                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2387                        "exit_code 0x%x\n",
2388                        __func__, svm->vmcb->control.exit_int_info,
2389                        exit_code);
2390
2391         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2392             || !svm_exit_handlers[exit_code]) {
2393                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2394                 kvm_run->hw.hardware_exit_reason = exit_code;
2395                 return 0;
2396         }
2397
2398         return svm_exit_handlers[exit_code](svm);
2399 }
2400
2401 static void reload_tss(struct kvm_vcpu *vcpu)
2402 {
2403         int cpu = raw_smp_processor_id();
2404
2405         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2406         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2407         load_TR_desc();
2408 }
2409
2410 static void pre_svm_run(struct vcpu_svm *svm)
2411 {
2412         int cpu = raw_smp_processor_id();
2413
2414         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2415
2416         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2417         /* FIXME: handle wraparound of asid_generation */
2418         if (svm->asid_generation != svm_data->asid_generation)
2419                 new_asid(svm, svm_data);
2420 }
2421
2422 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2423 {
2424         struct vcpu_svm *svm = to_svm(vcpu);
2425
2426         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2427         vcpu->arch.hflags |= HF_NMI_MASK;
2428         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2429         ++vcpu->stat.nmi_injections;
2430 }
2431
2432 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2433 {
2434         struct vmcb_control_area *control;
2435
2436         trace_kvm_inj_virq(irq);
2437
2438         ++svm->vcpu.stat.irq_injections;
2439         control = &svm->vmcb->control;
2440         control->int_vector = irq;
2441         control->int_ctl &= ~V_INTR_PRIO_MASK;
2442         control->int_ctl |= V_IRQ_MASK |
2443                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2444 }
2445
2446 static void svm_set_irq(struct kvm_vcpu *vcpu)
2447 {
2448         struct vcpu_svm *svm = to_svm(vcpu);
2449
2450         BUG_ON(!(gif_set(svm)));
2451
2452         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2453                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2454 }
2455
2456 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2457 {
2458         struct vcpu_svm *svm = to_svm(vcpu);
2459
2460         if (irr == -1)
2461                 return;
2462
2463         if (tpr >= irr)
2464                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2465 }
2466
2467 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2468 {
2469         struct vcpu_svm *svm = to_svm(vcpu);
2470         struct vmcb *vmcb = svm->vmcb;
2471         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2472                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2473 }
2474
2475 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2476 {
2477         struct vcpu_svm *svm = to_svm(vcpu);
2478         struct vmcb *vmcb = svm->vmcb;
2479         int ret;
2480
2481         if (!gif_set(svm) ||
2482              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2483                 return 0;
2484
2485         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2486
2487         if (is_nested(svm))
2488                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2489
2490         return ret;
2491 }
2492
2493 static void enable_irq_window(struct kvm_vcpu *vcpu)
2494 {
2495         struct vcpu_svm *svm = to_svm(vcpu);
2496         nsvm_printk("Trying to open IRQ window\n");
2497
2498         nested_svm_intr(svm);
2499
2500         /* In case GIF=0 we can't rely on the CPU to tell us when
2501          * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2502          * The next time we get that intercept, this function will be
2503          * called again though and we'll get the vintr intercept. */
2504         if (gif_set(svm)) {
2505                 svm_set_vintr(svm);
2506                 svm_inject_irq(svm, 0x0);
2507         }
2508 }
2509
2510 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2511 {
2512         struct vcpu_svm *svm = to_svm(vcpu);
2513
2514         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2515             == HF_NMI_MASK)
2516                 return; /* IRET will cause a vm exit */
2517
2518         /* Something prevents NMI from been injected. Single step over
2519            possible problem (IRET or exception injection or interrupt
2520            shadow) */
2521         vcpu->arch.singlestep = true;
2522         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2523         update_db_intercept(vcpu);
2524 }
2525
2526 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2527 {
2528         return 0;
2529 }
2530
2531 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2532 {
2533         force_new_asid(vcpu);
2534 }
2535
2536 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2537 {
2538 }
2539
2540 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2541 {
2542         struct vcpu_svm *svm = to_svm(vcpu);
2543
2544         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2545                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2546                 kvm_set_cr8(vcpu, cr8);
2547         }
2548 }
2549
2550 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2551 {
2552         struct vcpu_svm *svm = to_svm(vcpu);
2553         u64 cr8;
2554
2555         cr8 = kvm_get_cr8(vcpu);
2556         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2557         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2558 }
2559
2560 static void svm_complete_interrupts(struct vcpu_svm *svm)
2561 {
2562         u8 vector;
2563         int type;
2564         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2565
2566         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2567                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2568
2569         svm->vcpu.arch.nmi_injected = false;
2570         kvm_clear_exception_queue(&svm->vcpu);
2571         kvm_clear_interrupt_queue(&svm->vcpu);
2572
2573         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2574                 return;
2575
2576         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2577         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2578
2579         switch (type) {
2580         case SVM_EXITINTINFO_TYPE_NMI:
2581                 svm->vcpu.arch.nmi_injected = true;
2582                 break;
2583         case SVM_EXITINTINFO_TYPE_EXEPT:
2584                 /* In case of software exception do not reinject an exception
2585                    vector, but re-execute and instruction instead */
2586                 if (is_nested(svm))
2587                         break;
2588                 if (kvm_exception_is_soft(vector))
2589                         break;
2590                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2591                         u32 err = svm->vmcb->control.exit_int_info_err;
2592                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2593
2594                 } else
2595                         kvm_queue_exception(&svm->vcpu, vector);
2596                 break;
2597         case SVM_EXITINTINFO_TYPE_INTR:
2598                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2599                 break;
2600         default:
2601                 break;
2602         }
2603 }
2604
2605 #ifdef CONFIG_X86_64
2606 #define R "r"
2607 #else
2608 #define R "e"
2609 #endif
2610
2611 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2612 {
2613         struct vcpu_svm *svm = to_svm(vcpu);
2614         u16 fs_selector;
2615         u16 gs_selector;
2616         u16 ldt_selector;
2617
2618         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2619         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2620         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2621
2622         pre_svm_run(svm);
2623
2624         sync_lapic_to_cr8(vcpu);
2625
2626         save_host_msrs(vcpu);
2627         fs_selector = kvm_read_fs();
2628         gs_selector = kvm_read_gs();
2629         ldt_selector = kvm_read_ldt();
2630         svm->vmcb->save.cr2 = vcpu->arch.cr2;
2631         /* required for live migration with NPT */
2632         if (npt_enabled)
2633                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2634
2635         clgi();
2636
2637         local_irq_enable();
2638
2639         asm volatile (
2640                 "push %%"R"bp; \n\t"
2641                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2642                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2643                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2644                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2645                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2646                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2647 #ifdef CONFIG_X86_64
2648                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2649                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2650                 "mov %c[r10](%[svm]), %%r10 \n\t"
2651                 "mov %c[r11](%[svm]), %%r11 \n\t"
2652                 "mov %c[r12](%[svm]), %%r12 \n\t"
2653                 "mov %c[r13](%[svm]), %%r13 \n\t"
2654                 "mov %c[r14](%[svm]), %%r14 \n\t"
2655                 "mov %c[r15](%[svm]), %%r15 \n\t"
2656 #endif
2657
2658                 /* Enter guest mode */
2659                 "push %%"R"ax \n\t"
2660                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2661                 __ex(SVM_VMLOAD) "\n\t"
2662                 __ex(SVM_VMRUN) "\n\t"
2663                 __ex(SVM_VMSAVE) "\n\t"
2664                 "pop %%"R"ax \n\t"
2665
2666                 /* Save guest registers, load host registers */
2667                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2668                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2669                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2670                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2671                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2672                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2673 #ifdef CONFIG_X86_64
2674                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2675                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2676                 "mov %%r10, %c[r10](%[svm]) \n\t"
2677                 "mov %%r11, %c[r11](%[svm]) \n\t"
2678                 "mov %%r12, %c[r12](%[svm]) \n\t"
2679                 "mov %%r13, %c[r13](%[svm]) \n\t"
2680                 "mov %%r14, %c[r14](%[svm]) \n\t"
2681                 "mov %%r15, %c[r15](%[svm]) \n\t"
2682 #endif
2683                 "pop %%"R"bp"
2684                 :
2685                 : [svm]"a"(svm),
2686                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2687                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2688                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2689                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2690                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2691                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2692                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2693 #ifdef CONFIG_X86_64
2694                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2695                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2696                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2697                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2698                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2699                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2700                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2701                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2702 #endif
2703                 : "cc", "memory"
2704                 , R"bx", R"cx", R"dx", R"si", R"di"
2705 #ifdef CONFIG_X86_64
2706                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2707 #endif
2708                 );
2709
2710         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2711         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2712         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2713         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2714
2715         kvm_load_fs(fs_selector);
2716         kvm_load_gs(gs_selector);
2717         kvm_load_ldt(ldt_selector);
2718         load_host_msrs(vcpu);
2719
2720         reload_tss(vcpu);
2721
2722         local_irq_disable();
2723
2724         stgi();
2725
2726         sync_cr8_to_lapic(vcpu);
2727
2728         svm->next_rip = 0;
2729
2730         if (npt_enabled) {
2731                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2732                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2733         }
2734 }
2735
2736 #undef R
2737
2738 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2739 {
2740         struct vcpu_svm *svm = to_svm(vcpu);
2741
2742         if (npt_enabled) {
2743                 svm->vmcb->control.nested_cr3 = root;
2744                 force_new_asid(vcpu);
2745                 return;
2746         }
2747
2748         svm->vmcb->save.cr3 = root;
2749         force_new_asid(vcpu);
2750
2751         if (vcpu->fpu_active) {
2752                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2753                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2754                 vcpu->fpu_active = 0;
2755         }
2756 }
2757
2758 static int is_disabled(void)
2759 {
2760         u64 vm_cr;
2761
2762         rdmsrl(MSR_VM_CR, vm_cr);
2763         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2764                 return 1;
2765
2766         return 0;
2767 }
2768
2769 static void
2770 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2771 {
2772         /*
2773          * Patch in the VMMCALL instruction:
2774          */
2775         hypercall[0] = 0x0f;
2776         hypercall[1] = 0x01;
2777         hypercall[2] = 0xd9;
2778 }
2779
2780 static void svm_check_processor_compat(void *rtn)
2781 {
2782         *(int *)rtn = 0;
2783 }
2784
2785 static bool svm_cpu_has_accelerated_tpr(void)
2786 {
2787         return false;
2788 }
2789
2790 static int get_npt_level(void)
2791 {
2792 #ifdef CONFIG_X86_64
2793         return PT64_ROOT_LEVEL;
2794 #else
2795         return PT32E_ROOT_LEVEL;
2796 #endif
2797 }
2798
2799 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2800 {
2801         return 0;
2802 }
2803
2804 static const struct trace_print_flags svm_exit_reasons_str[] = {
2805         { SVM_EXIT_READ_CR0,                    "read_cr0" },
2806         { SVM_EXIT_READ_CR3,                    "read_cr3" },
2807         { SVM_EXIT_READ_CR4,                    "read_cr4" },
2808         { SVM_EXIT_READ_CR8,                    "read_cr8" },
2809         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
2810         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
2811         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
2812         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
2813         { SVM_EXIT_READ_DR0,                    "read_dr0" },
2814         { SVM_EXIT_READ_DR1,                    "read_dr1" },
2815         { SVM_EXIT_READ_DR2,                    "read_dr2" },
2816         { SVM_EXIT_READ_DR3,                    "read_dr3" },
2817         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
2818         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
2819         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
2820         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
2821         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
2822         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
2823         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
2824         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
2825         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
2826         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
2827         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
2828         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
2829         { SVM_EXIT_INTR,                        "interrupt" },
2830         { SVM_EXIT_NMI,                         "nmi" },
2831         { SVM_EXIT_SMI,                         "smi" },
2832         { SVM_EXIT_INIT,                        "init" },
2833         { SVM_EXIT_VINTR,                       "vintr" },
2834         { SVM_EXIT_CPUID,                       "cpuid" },
2835         { SVM_EXIT_INVD,                        "invd" },
2836         { SVM_EXIT_HLT,                         "hlt" },
2837         { SVM_EXIT_INVLPG,                      "invlpg" },
2838         { SVM_EXIT_INVLPGA,                     "invlpga" },
2839         { SVM_EXIT_IOIO,                        "io" },
2840         { SVM_EXIT_MSR,                         "msr" },
2841         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
2842         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
2843         { SVM_EXIT_VMRUN,                       "vmrun" },
2844         { SVM_EXIT_VMMCALL,                     "hypercall" },
2845         { SVM_EXIT_VMLOAD,                      "vmload" },
2846         { SVM_EXIT_VMSAVE,                      "vmsave" },
2847         { SVM_EXIT_STGI,                        "stgi" },
2848         { SVM_EXIT_CLGI,                        "clgi" },
2849         { SVM_EXIT_SKINIT,                      "skinit" },
2850         { SVM_EXIT_WBINVD,                      "wbinvd" },
2851         { SVM_EXIT_MONITOR,                     "monitor" },
2852         { SVM_EXIT_MWAIT,                       "mwait" },
2853         { SVM_EXIT_NPF,                         "npf" },
2854         { -1, NULL }
2855 };
2856
2857 static bool svm_gb_page_enable(void)
2858 {
2859         return true;
2860 }
2861
2862 static struct kvm_x86_ops svm_x86_ops = {
2863         .cpu_has_kvm_support = has_svm,
2864         .disabled_by_bios = is_disabled,
2865         .hardware_setup = svm_hardware_setup,
2866         .hardware_unsetup = svm_hardware_unsetup,
2867         .check_processor_compatibility = svm_check_processor_compat,
2868         .hardware_enable = svm_hardware_enable,
2869         .hardware_disable = svm_hardware_disable,
2870         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2871
2872         .vcpu_create = svm_create_vcpu,
2873         .vcpu_free = svm_free_vcpu,
2874         .vcpu_reset = svm_vcpu_reset,
2875
2876         .prepare_guest_switch = svm_prepare_guest_switch,
2877         .vcpu_load = svm_vcpu_load,
2878         .vcpu_put = svm_vcpu_put,
2879
2880         .set_guest_debug = svm_guest_debug,
2881         .get_msr = svm_get_msr,
2882         .set_msr = svm_set_msr,
2883         .get_segment_base = svm_get_segment_base,
2884         .get_segment = svm_get_segment,
2885         .set_segment = svm_set_segment,
2886         .get_cpl = svm_get_cpl,
2887         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2888         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2889         .set_cr0 = svm_set_cr0,
2890         .set_cr3 = svm_set_cr3,
2891         .set_cr4 = svm_set_cr4,
2892         .set_efer = svm_set_efer,
2893         .get_idt = svm_get_idt,
2894         .set_idt = svm_set_idt,
2895         .get_gdt = svm_get_gdt,
2896         .set_gdt = svm_set_gdt,
2897         .get_dr = svm_get_dr,
2898         .set_dr = svm_set_dr,
2899         .cache_reg = svm_cache_reg,
2900         .get_rflags = svm_get_rflags,
2901         .set_rflags = svm_set_rflags,
2902
2903         .tlb_flush = svm_flush_tlb,
2904
2905         .run = svm_vcpu_run,
2906         .handle_exit = handle_exit,
2907         .skip_emulated_instruction = skip_emulated_instruction,
2908         .set_interrupt_shadow = svm_set_interrupt_shadow,
2909         .get_interrupt_shadow = svm_get_interrupt_shadow,
2910         .patch_hypercall = svm_patch_hypercall,
2911         .set_irq = svm_set_irq,
2912         .set_nmi = svm_inject_nmi,
2913         .queue_exception = svm_queue_exception,
2914         .interrupt_allowed = svm_interrupt_allowed,
2915         .nmi_allowed = svm_nmi_allowed,
2916         .enable_nmi_window = enable_nmi_window,
2917         .enable_irq_window = enable_irq_window,
2918         .update_cr8_intercept = update_cr8_intercept,
2919
2920         .set_tss_addr = svm_set_tss_addr,
2921         .get_tdp_level = get_npt_level,
2922         .get_mt_mask = svm_get_mt_mask,
2923
2924         .exit_reasons_str = svm_exit_reasons_str,
2925         .gb_page_enable = svm_gb_page_enable,
2926 };
2927
2928 static int __init svm_init(void)
2929 {
2930         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2931                               THIS_MODULE);
2932 }
2933
2934 static void __exit svm_exit(void)
2935 {
2936         kvm_exit();
2937 }
2938
2939 module_init(svm_init)
2940 module_exit(svm_exit)