arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33 #include "trace.h"
  34
  35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  36
  37 MODULE_AUTHOR("Qumranet");
  38 MODULE_LICENSE("GPL");
  39
  40 #define IOPM_ALLOC_ORDER 2
  41 #define MSRPM_ALLOC_ORDER 1
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_FEATURE_SVML (1 << 2)
  49
  50 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  51 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  52 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  53
  54 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  55
  56 /* Turn on to get debugging output*/
  57 /* #define NESTED_DEBUG */
  58
  59 #ifdef NESTED_DEBUG
  60 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  61 #else
  62 #define nsvm_printk(fmt, args...) do {} while(0)
  63 #endif
  64
  65 static const u32 host_save_user_msrs[] = {
  66 #ifdef CONFIG_X86_64
  67         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  68         MSR_FS_BASE,
  69 #endif
  70         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  71 };
  72
  73 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  74
  75 struct kvm_vcpu;
  76
  77 struct nested_state {
  78         struct vmcb *hsave;
  79         u64 hsave_msr;
  80         u64 vmcb;
  81
  82         /* These are the merged vectors */
  83         u32 *msrpm;
  84
  85         /* gpa pointers to the real vectors */
  86         u64 vmcb_msrpm;
  87
  88         /* cache for intercepts of the guest */
  89         u16 intercept_cr_read;
  90         u16 intercept_cr_write;
  91         u16 intercept_dr_read;
  92         u16 intercept_dr_write;
  93         u32 intercept_exceptions;
  94         u64 intercept;
  95
  96 };
  97
  98 struct vcpu_svm {
  99         struct kvm_vcpu vcpu;
 100         struct vmcb *vmcb;
 101         unsigned long vmcb_pa;
 102         struct svm_cpu_data *svm_data;
 103         uint64_t asid_generation;
 104         uint64_t sysenter_esp;
 105         uint64_t sysenter_eip;
 106
 107         u64 next_rip;
 108
 109         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 110         u64 host_gs_base;
 111
 112         u32 *msrpm;
 113
 114         struct nested_state nested;
 115 };
 116
 117 /* enable NPT for AMD64 and X86 with PAE */
 118 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 119 static bool npt_enabled = true;
 120 #else
 121 static bool npt_enabled = false;
 122 #endif
 123 static int npt = 1;
 124
 125 module_param(npt, int, S_IRUGO);
 126
 127 static int nested = 1;
 128 module_param(nested, int, S_IRUGO);
 129
 130 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 131 static void svm_complete_interrupts(struct vcpu_svm *svm);
 132
 133 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 134 static int nested_svm_vmexit(struct vcpu_svm *svm);
 135 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 136                                       bool has_error_code, u32 error_code);
 137
 138 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 139 {
 140         return container_of(vcpu, struct vcpu_svm, vcpu);
 141 }
 142
 143 static inline bool is_nested(struct vcpu_svm *svm)
 144 {
 145         return svm->nested.vmcb;
 146 }
 147
 148 static inline void enable_gif(struct vcpu_svm *svm)
 149 {
 150         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 151 }
 152
 153 static inline void disable_gif(struct vcpu_svm *svm)
 154 {
 155         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 156 }
 157
 158 static inline bool gif_set(struct vcpu_svm *svm)
 159 {
 160         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 161 }
 162
 163 static unsigned long iopm_base;
 164
 165 struct kvm_ldttss_desc {
 166         u16 limit0;
 167         u16 base0;
 168         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
 169         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
 170         u32 base3;
 171         u32 zero1;
 172 } __attribute__((packed));
 173
 174 struct svm_cpu_data {
 175         int cpu;
 176
 177         u64 asid_generation;
 178         u32 max_asid;
 179         u32 next_asid;
 180         struct kvm_ldttss_desc *tss_desc;
 181
 182         struct page *save_area;
 183 };
 184
 185 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 186 static uint32_t svm_features;
 187
 188 struct svm_init_data {
 189         int cpu;
 190         int r;
 191 };
 192
 193 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 194
 195 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 196 #define MSRS_RANGE_SIZE 2048
 197 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 198
 199 #define MAX_INST_SIZE 15
 200
 201 static inline u32 svm_has(u32 feat)
 202 {
 203         return svm_features & feat;
 204 }
 205
 206 static inline void clgi(void)
 207 {
 208         asm volatile (__ex(SVM_CLGI));
 209 }
 210
 211 static inline void stgi(void)
 212 {
 213         asm volatile (__ex(SVM_STGI));
 214 }
 215
 216 static inline void invlpga(unsigned long addr, u32 asid)
 217 {
 218         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 219 }
 220
 221 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 222 {
 223         to_svm(vcpu)->asid_generation--;
 224 }
 225
 226 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 227 {
 228         force_new_asid(vcpu);
 229 }
 230
 231 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 232 {
 233         if (!npt_enabled && !(efer & EFER_LMA))
 234                 efer &= ~EFER_LME;
 235
 236         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 237         vcpu->arch.shadow_efer = efer;
 238 }
 239
 240 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 241                                 bool has_error_code, u32 error_code)
 242 {
 243         struct vcpu_svm *svm = to_svm(vcpu);
 244
 245         /* If we are within a nested VM we'd better #VMEXIT and let the
 246            guest handle the exception */
 247         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 248                 return;
 249
 250         svm->vmcb->control.event_inj = nr
 251                 | SVM_EVTINJ_VALID
 252                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 253                 | SVM_EVTINJ_TYPE_EXEPT;
 254         svm->vmcb->control.event_inj_err = error_code;
 255 }
 256
 257 static int is_external_interrupt(u32 info)
 258 {
 259         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 260         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 261 }
 262
 263 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 264 {
 265         struct vcpu_svm *svm = to_svm(vcpu);
 266         u32 ret = 0;
 267
 268         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 269                 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
 270         return ret & mask;
 271 }
 272
 273 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 274 {
 275         struct vcpu_svm *svm = to_svm(vcpu);
 276
 277         if (mask == 0)
 278                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 279         else
 280                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 281
 282 }
 283
 284 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 285 {
 286         struct vcpu_svm *svm = to_svm(vcpu);
 287
 288         if (!svm->next_rip) {
 289                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 290                                 EMULATE_DONE)
 291                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 292                 return;
 293         }
 294         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 295                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 296                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 297
 298         kvm_rip_write(vcpu, svm->next_rip);
 299         svm_set_interrupt_shadow(vcpu, 0);
 300 }
 301
 302 static int has_svm(void)
 303 {
 304         const char *msg;
 305
 306         if (!cpu_has_svm(&msg)) {
 307                 printk(KERN_INFO "has_svm: %s\n", msg);
 308                 return 0;
 309         }
 310
 311         return 1;
 312 }
 313
 314 static void svm_hardware_disable(void *garbage)
 315 {
 316         cpu_svm_disable();
 317 }
 318
 319 static void svm_hardware_enable(void *garbage)
 320 {
 321
 322         struct svm_cpu_data *svm_data;
 323         uint64_t efer;
 324         struct descriptor_table gdt_descr;
 325         struct desc_struct *gdt;
 326         int me = raw_smp_processor_id();
 327
 328         if (!has_svm()) {
 329                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 330                 return;
 331         }
 332         svm_data = per_cpu(svm_data, me);
 333
 334         if (!svm_data) {
 335                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 336                        me);
 337                 return;
 338         }
 339
 340         svm_data->asid_generation = 1;
 341         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 342         svm_data->next_asid = svm_data->max_asid + 1;
 343
 344         kvm_get_gdt(&gdt_descr);
 345         gdt = (struct desc_struct *)gdt_descr.base;
 346         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 347
 348         rdmsrl(MSR_EFER, efer);
 349         wrmsrl(MSR_EFER, efer | EFER_SVME);
 350
 351         wrmsrl(MSR_VM_HSAVE_PA,
 352                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 353 }
 354
 355 static void svm_cpu_uninit(int cpu)
 356 {
 357         struct svm_cpu_data *svm_data
 358                 = per_cpu(svm_data, raw_smp_processor_id());
 359
 360         if (!svm_data)
 361                 return;
 362
 363         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 364         __free_page(svm_data->save_area);
 365         kfree(svm_data);
 366 }
 367
 368 static int svm_cpu_init(int cpu)
 369 {
 370         struct svm_cpu_data *svm_data;
 371         int r;
 372
 373         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 374         if (!svm_data)
 375                 return -ENOMEM;
 376         svm_data->cpu = cpu;
 377         svm_data->save_area = alloc_page(GFP_KERNEL);
 378         r = -ENOMEM;
 379         if (!svm_data->save_area)
 380                 goto err_1;
 381
 382         per_cpu(svm_data, cpu) = svm_data;
 383
 384         return 0;
 385
 386 err_1:
 387         kfree(svm_data);
 388         return r;
 389
 390 }
 391
 392 static void set_msr_interception(u32 *msrpm, unsigned msr,
 393                                  int read, int write)
 394 {
 395         int i;
 396
 397         for (i = 0; i < NUM_MSR_MAPS; i++) {
 398                 if (msr >= msrpm_ranges[i] &&
 399                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 400                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 401                                           msrpm_ranges[i]) * 2;
 402
 403                         u32 *base = msrpm + (msr_offset / 32);
 404                         u32 msr_shift = msr_offset % 32;
 405                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 406                         *base = (*base & ~(0x3 << msr_shift)) |
 407                                 (mask << msr_shift);
 408                         return;
 409                 }
 410         }
 411         BUG();
 412 }
 413
 414 static void svm_vcpu_init_msrpm(u32 *msrpm)
 415 {
 416         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 417
 418 #ifdef CONFIG_X86_64
 419         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 420         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 421         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 422         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 423         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 424         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 425 #endif
 426         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 427         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 428 }
 429
 430 static void svm_enable_lbrv(struct vcpu_svm *svm)
 431 {
 432         u32 *msrpm = svm->msrpm;
 433
 434         svm->vmcb->control.lbr_ctl = 1;
 435         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 436         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 437         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 438         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 439 }
 440
 441 static void svm_disable_lbrv(struct vcpu_svm *svm)
 442 {
 443         u32 *msrpm = svm->msrpm;
 444
 445         svm->vmcb->control.lbr_ctl = 0;
 446         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 447         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 448         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 449         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 450 }
 451
 452 static __init int svm_hardware_setup(void)
 453 {
 454         int cpu;
 455         struct page *iopm_pages;
 456         void *iopm_va;
 457         int r;
 458
 459         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 460
 461         if (!iopm_pages)
 462                 return -ENOMEM;
 463
 464         iopm_va = page_address(iopm_pages);
 465         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 466         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 467
 468         if (boot_cpu_has(X86_FEATURE_NX))
 469                 kvm_enable_efer_bits(EFER_NX);
 470
 471         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 472                 kvm_enable_efer_bits(EFER_FFXSR);
 473
 474         if (nested) {
 475                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 476                 kvm_enable_efer_bits(EFER_SVME);
 477         }
 478
 479         for_each_online_cpu(cpu) {
 480                 r = svm_cpu_init(cpu);
 481                 if (r)
 482                         goto err;
 483         }
 484
 485         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 486
 487         if (!svm_has(SVM_FEATURE_NPT))
 488                 npt_enabled = false;
 489
 490         if (npt_enabled && !npt) {
 491                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 492                 npt_enabled = false;
 493         }
 494
 495         if (npt_enabled) {
 496                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 497                 kvm_enable_tdp();
 498         } else
 499                 kvm_disable_tdp();
 500
 501         return 0;
 502
 503 err:
 504         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 505         iopm_base = 0;
 506         return r;
 507 }
 508
 509 static __exit void svm_hardware_unsetup(void)
 510 {
 511         int cpu;
 512
 513         for_each_online_cpu(cpu)
 514                 svm_cpu_uninit(cpu);
 515
 516         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 517         iopm_base = 0;
 518 }
 519
 520 static void init_seg(struct vmcb_seg *seg)
 521 {
 522         seg->selector = 0;
 523         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 524                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 525         seg->limit = 0xffff;
 526         seg->base = 0;
 527 }
 528
 529 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 530 {
 531         seg->selector = 0;
 532         seg->attrib = SVM_SELECTOR_P_MASK | type;
 533         seg->limit = 0xffff;
 534         seg->base = 0;
 535 }
 536
 537 static void init_vmcb(struct vcpu_svm *svm)
 538 {
 539         struct vmcb_control_area *control = &svm->vmcb->control;
 540         struct vmcb_save_area *save = &svm->vmcb->save;
 541
 542         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 543                                         INTERCEPT_CR3_MASK |
 544                                         INTERCEPT_CR4_MASK;
 545
 546         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 547                                         INTERCEPT_CR3_MASK |
 548                                         INTERCEPT_CR4_MASK |
 549                                         INTERCEPT_CR8_MASK;
 550
 551         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 552                                         INTERCEPT_DR1_MASK |
 553                                         INTERCEPT_DR2_MASK |
 554                                         INTERCEPT_DR3_MASK;
 555
 556         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 557                                         INTERCEPT_DR1_MASK |
 558                                         INTERCEPT_DR2_MASK |
 559                                         INTERCEPT_DR3_MASK |
 560                                         INTERCEPT_DR5_MASK |
 561                                         INTERCEPT_DR7_MASK;
 562
 563         control->intercept_exceptions = (1 << PF_VECTOR) |
 564                                         (1 << UD_VECTOR) |
 565                                         (1 << MC_VECTOR);
 566
 567
 568         control->intercept =    (1ULL << INTERCEPT_INTR) |
 569                                 (1ULL << INTERCEPT_NMI) |
 570                                 (1ULL << INTERCEPT_SMI) |
 571                                 (1ULL << INTERCEPT_CPUID) |
 572                                 (1ULL << INTERCEPT_INVD) |
 573                                 (1ULL << INTERCEPT_HLT) |
 574                                 (1ULL << INTERCEPT_INVLPG) |
 575                                 (1ULL << INTERCEPT_INVLPGA) |
 576                                 (1ULL << INTERCEPT_IOIO_PROT) |
 577                                 (1ULL << INTERCEPT_MSR_PROT) |
 578                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 579                                 (1ULL << INTERCEPT_SHUTDOWN) |
 580                                 (1ULL << INTERCEPT_VMRUN) |
 581                                 (1ULL << INTERCEPT_VMMCALL) |
 582                                 (1ULL << INTERCEPT_VMLOAD) |
 583                                 (1ULL << INTERCEPT_VMSAVE) |
 584                                 (1ULL << INTERCEPT_STGI) |
 585                                 (1ULL << INTERCEPT_CLGI) |
 586                                 (1ULL << INTERCEPT_SKINIT) |
 587                                 (1ULL << INTERCEPT_WBINVD) |
 588                                 (1ULL << INTERCEPT_MONITOR) |
 589                                 (1ULL << INTERCEPT_MWAIT);
 590
 591         control->iopm_base_pa = iopm_base;
 592         control->msrpm_base_pa = __pa(svm->msrpm);
 593         control->tsc_offset = 0;
 594         control->int_ctl = V_INTR_MASKING_MASK;
 595
 596         init_seg(&save->es);
 597         init_seg(&save->ss);
 598         init_seg(&save->ds);
 599         init_seg(&save->fs);
 600         init_seg(&save->gs);
 601
 602         save->cs.selector = 0xf000;
 603         /* Executable/Readable Code Segment */
 604         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 605                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 606         save->cs.limit = 0xffff;
 607         /*
 608          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 609          * be consistent with it.
 610          *
 611          * Replace when we have real mode working for vmx.
 612          */
 613         save->cs.base = 0xf0000;
 614
 615         save->gdtr.limit = 0xffff;
 616         save->idtr.limit = 0xffff;
 617
 618         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 619         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 620
 621         save->efer = EFER_SVME;
 622         save->dr6 = 0xffff0ff0;
 623         save->dr7 = 0x400;
 624         save->rflags = 2;
 625         save->rip = 0x0000fff0;
 626         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 627
 628         /*
 629          * cr0 val on cpu init should be 0x60000010, we enable cpu
 630          * cache by default. the orderly way is to enable cache in bios.
 631          */
 632         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 633         save->cr4 = X86_CR4_PAE;
 634         /* rdx = ?? */
 635
 636         if (npt_enabled) {
 637                 /* Setup VMCB for Nested Paging */
 638                 control->nested_ctl = 1;
 639                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 640                                         (1ULL << INTERCEPT_INVLPG));
 641                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 642                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 643                                                 INTERCEPT_CR3_MASK);
 644                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 645                                                  INTERCEPT_CR3_MASK);
 646                 save->g_pat = 0x0007040600070406ULL;
 647                 /* enable caching because the QEMU Bios doesn't enable it */
 648                 save->cr0 = X86_CR0_ET;
 649                 save->cr3 = 0;
 650                 save->cr4 = 0;
 651         }
 652         force_new_asid(&svm->vcpu);
 653
 654         svm->nested.vmcb = 0;
 655         svm->vcpu.arch.hflags = 0;
 656
 657         enable_gif(svm);
 658 }
 659
 660 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 661 {
 662         struct vcpu_svm *svm = to_svm(vcpu);
 663
 664         init_vmcb(svm);
 665
 666         if (!kvm_vcpu_is_bsp(vcpu)) {
 667                 kvm_rip_write(vcpu, 0);
 668                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 669                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 670         }
 671         vcpu->arch.regs_avail = ~0;
 672         vcpu->arch.regs_dirty = ~0;
 673
 674         return 0;
 675 }
 676
 677 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 678 {
 679         struct vcpu_svm *svm;
 680         struct page *page;
 681         struct page *msrpm_pages;
 682         struct page *hsave_page;
 683         struct page *nested_msrpm_pages;
 684         int err;
 685
 686         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 687         if (!svm) {
 688                 err = -ENOMEM;
 689                 goto out;
 690         }
 691
 692         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 693         if (err)
 694                 goto free_svm;
 695
 696         page = alloc_page(GFP_KERNEL);
 697         if (!page) {
 698                 err = -ENOMEM;
 699                 goto uninit;
 700         }
 701
 702         err = -ENOMEM;
 703         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 704         if (!msrpm_pages)
 705                 goto uninit;
 706
 707         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 708         if (!nested_msrpm_pages)
 709                 goto uninit;
 710
 711         svm->msrpm = page_address(msrpm_pages);
 712         svm_vcpu_init_msrpm(svm->msrpm);
 713
 714         hsave_page = alloc_page(GFP_KERNEL);
 715         if (!hsave_page)
 716                 goto uninit;
 717         svm->nested.hsave = page_address(hsave_page);
 718
 719         svm->nested.msrpm = page_address(nested_msrpm_pages);
 720
 721         svm->vmcb = page_address(page);
 722         clear_page(svm->vmcb);
 723         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 724         svm->asid_generation = 0;
 725         init_vmcb(svm);
 726
 727         fx_init(&svm->vcpu);
 728         svm->vcpu.fpu_active = 1;
 729         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 730         if (kvm_vcpu_is_bsp(&svm->vcpu))
 731                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 732
 733         return &svm->vcpu;
 734
 735 uninit:
 736         kvm_vcpu_uninit(&svm->vcpu);
 737 free_svm:
 738         kmem_cache_free(kvm_vcpu_cache, svm);
 739 out:
 740         return ERR_PTR(err);
 741 }
 742
 743 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 744 {
 745         struct vcpu_svm *svm = to_svm(vcpu);
 746
 747         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 748         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 749         __free_page(virt_to_page(svm->nested.hsave));
 750         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 751         kvm_vcpu_uninit(vcpu);
 752         kmem_cache_free(kvm_vcpu_cache, svm);
 753 }
 754
 755 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 756 {
 757         struct vcpu_svm *svm = to_svm(vcpu);
 758         int i;
 759
 760         if (unlikely(cpu != vcpu->cpu)) {
 761                 u64 tsc_this, delta;
 762
 763                 /*
 764                  * Make sure that the guest sees a monotonically
 765                  * increasing TSC.
 766                  */
 767                 rdtscll(tsc_this);
 768                 delta = vcpu->arch.host_tsc - tsc_this;
 769                 svm->vmcb->control.tsc_offset += delta;
 770                 if (is_nested(svm))
 771                         svm->nested.hsave->control.tsc_offset += delta;
 772                 vcpu->cpu = cpu;
 773                 kvm_migrate_timers(vcpu);
 774                 svm->asid_generation = 0;
 775         }
 776
 777         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 778                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 779 }
 780
 781 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 782 {
 783         struct vcpu_svm *svm = to_svm(vcpu);
 784         int i;
 785
 786         ++vcpu->stat.host_state_reload;
 787         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 788                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 789
 790         rdtscll(vcpu->arch.host_tsc);
 791 }
 792
 793 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 794 {
 795         return to_svm(vcpu)->vmcb->save.rflags;
 796 }
 797
 798 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 799 {
 800         to_svm(vcpu)->vmcb->save.rflags = rflags;
 801 }
 802
 803 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 804 {
 805         switch (reg) {
 806         case VCPU_EXREG_PDPTR:
 807                 BUG_ON(!npt_enabled);
 808                 load_pdptrs(vcpu, vcpu->arch.cr3);
 809                 break;
 810         default:
 811                 BUG();
 812         }
 813 }
 814
 815 static void svm_set_vintr(struct vcpu_svm *svm)
 816 {
 817         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 818 }
 819
 820 static void svm_clear_vintr(struct vcpu_svm *svm)
 821 {
 822         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 823 }
 824
 825 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 826 {
 827         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 828
 829         switch (seg) {
 830         case VCPU_SREG_CS: return &save->cs;
 831         case VCPU_SREG_DS: return &save->ds;
 832         case VCPU_SREG_ES: return &save->es;
 833         case VCPU_SREG_FS: return &save->fs;
 834         case VCPU_SREG_GS: return &save->gs;
 835         case VCPU_SREG_SS: return &save->ss;
 836         case VCPU_SREG_TR: return &save->tr;
 837         case VCPU_SREG_LDTR: return &save->ldtr;
 838         }
 839         BUG();
 840         return NULL;
 841 }
 842
 843 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 844 {
 845         struct vmcb_seg *s = svm_seg(vcpu, seg);
 846
 847         return s->base;
 848 }
 849
 850 static void svm_get_segment(struct kvm_vcpu *vcpu,
 851                             struct kvm_segment *var, int seg)
 852 {
 853         struct vmcb_seg *s = svm_seg(vcpu, seg);
 854
 855         var->base = s->base;
 856         var->limit = s->limit;
 857         var->selector = s->selector;
 858         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 859         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 860         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 861         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 862         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 863         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 864         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 865         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 866
 867         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 868          * for cross vendor migration purposes by "not present"
 869          */
 870         var->unusable = !var->present || (var->type == 0);
 871
 872         switch (seg) {
 873         case VCPU_SREG_CS:
 874                 /*
 875                  * SVM always stores 0 for the 'G' bit in the CS selector in
 876                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 877                  * Intel's VMENTRY has a check on the 'G' bit.
 878                  */
 879                 var->g = s->limit > 0xfffff;
 880                 break;
 881         case VCPU_SREG_TR:
 882                 /*
 883                  * Work around a bug where the busy flag in the tr selector
 884                  * isn't exposed
 885                  */
 886                 var->type |= 0x2;
 887                 break;
 888         case VCPU_SREG_DS:
 889         case VCPU_SREG_ES:
 890         case VCPU_SREG_FS:
 891         case VCPU_SREG_GS:
 892                 /*
 893                  * The accessed bit must always be set in the segment
 894                  * descriptor cache, although it can be cleared in the
 895                  * descriptor, the cached bit always remains at 1. Since
 896                  * Intel has a check on this, set it here to support
 897                  * cross-vendor migration.
 898                  */
 899                 if (!var->unusable)
 900                         var->type |= 0x1;
 901                 break;
 902         case VCPU_SREG_SS:
 903                 /* On AMD CPUs sometimes the DB bit in the segment
 904                  * descriptor is left as 1, although the whole segment has
 905                  * been made unusable. Clear it here to pass an Intel VMX
 906                  * entry check when cross vendor migrating.
 907                  */
 908                 if (var->unusable)
 909                         var->db = 0;
 910                 break;
 911         }
 912 }
 913
 914 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 915 {
 916         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 917
 918         return save->cpl;
 919 }
 920
 921 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 922 {
 923         struct vcpu_svm *svm = to_svm(vcpu);
 924
 925         dt->limit = svm->vmcb->save.idtr.limit;
 926         dt->base = svm->vmcb->save.idtr.base;
 927 }
 928
 929 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 930 {
 931         struct vcpu_svm *svm = to_svm(vcpu);
 932
 933         svm->vmcb->save.idtr.limit = dt->limit;
 934         svm->vmcb->save.idtr.base = dt->base ;
 935 }
 936
 937 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 938 {
 939         struct vcpu_svm *svm = to_svm(vcpu);
 940
 941         dt->limit = svm->vmcb->save.gdtr.limit;
 942         dt->base = svm->vmcb->save.gdtr.base;
 943 }
 944
 945 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 946 {
 947         struct vcpu_svm *svm = to_svm(vcpu);
 948
 949         svm->vmcb->save.gdtr.limit = dt->limit;
 950         svm->vmcb->save.gdtr.base = dt->base ;
 951 }
 952
 953 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 954 {
 955 }
 956
 957 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 958 {
 959         struct vcpu_svm *svm = to_svm(vcpu);
 960
 961 #ifdef CONFIG_X86_64
 962         if (vcpu->arch.shadow_efer & EFER_LME) {
 963                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 964                         vcpu->arch.shadow_efer |= EFER_LMA;
 965                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 966                 }
 967
 968                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 969                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 970                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 971                 }
 972         }
 973 #endif
 974         if (npt_enabled)
 975                 goto set;
 976
 977         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 978                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 979                 vcpu->fpu_active = 1;
 980         }
 981
 982         vcpu->arch.cr0 = cr0;
 983         cr0 |= X86_CR0_PG | X86_CR0_WP;
 984         if (!vcpu->fpu_active) {
 985                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 986                 cr0 |= X86_CR0_TS;
 987         }
 988 set:
 989         /*
 990          * re-enable caching here because the QEMU bios
 991          * does not do it - this results in some delay at
 992          * reboot
 993          */
 994         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 995         svm->vmcb->save.cr0 = cr0;
 996 }
 997
 998 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 999 {
1000         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1001         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1002
1003         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1004                 force_new_asid(vcpu);
1005
1006         vcpu->arch.cr4 = cr4;
1007         if (!npt_enabled)
1008                 cr4 |= X86_CR4_PAE;
1009         cr4 |= host_cr4_mce;
1010         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1011 }
1012
1013 static void svm_set_segment(struct kvm_vcpu *vcpu,
1014                             struct kvm_segment *var, int seg)
1015 {
1016         struct vcpu_svm *svm = to_svm(vcpu);
1017         struct vmcb_seg *s = svm_seg(vcpu, seg);
1018
1019         s->base = var->base;
1020         s->limit = var->limit;
1021         s->selector = var->selector;
1022         if (var->unusable)
1023                 s->attrib = 0;
1024         else {
1025                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1026                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1027                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1028                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1029                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1030                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1031                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1032                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1033         }
1034         if (seg == VCPU_SREG_CS)
1035                 svm->vmcb->save.cpl
1036                         = (svm->vmcb->save.cs.attrib
1037                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1038
1039 }
1040
1041 static void update_db_intercept(struct kvm_vcpu *vcpu)
1042 {
1043         struct vcpu_svm *svm = to_svm(vcpu);
1044
1045         svm->vmcb->control.intercept_exceptions &=
1046                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1047
1048         if (vcpu->arch.singlestep)
1049                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1050
1051         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1052                 if (vcpu->guest_debug &
1053                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1054                         svm->vmcb->control.intercept_exceptions |=
1055                                 1 << DB_VECTOR;
1056                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1057                         svm->vmcb->control.intercept_exceptions |=
1058                                 1 << BP_VECTOR;
1059         } else
1060                 vcpu->guest_debug = 0;
1061 }
1062
1063 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1064 {
1065         int old_debug = vcpu->guest_debug;
1066         struct vcpu_svm *svm = to_svm(vcpu);
1067
1068         vcpu->guest_debug = dbg->control;
1069
1070         update_db_intercept(vcpu);
1071
1072         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1073                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1074         else
1075                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1076
1077         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1078                 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1079         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1080                 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1081
1082         return 0;
1083 }
1084
1085 static void load_host_msrs(struct kvm_vcpu *vcpu)
1086 {
1087 #ifdef CONFIG_X86_64
1088         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1089 #endif
1090 }
1091
1092 static void save_host_msrs(struct kvm_vcpu *vcpu)
1093 {
1094 #ifdef CONFIG_X86_64
1095         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1096 #endif
1097 }
1098
1099 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1100 {
1101         if (svm_data->next_asid > svm_data->max_asid) {
1102                 ++svm_data->asid_generation;
1103                 svm_data->next_asid = 1;
1104                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1105         }
1106
1107         svm->asid_generation = svm_data->asid_generation;
1108         svm->vmcb->control.asid = svm_data->next_asid++;
1109 }
1110
1111 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1112 {
1113         struct vcpu_svm *svm = to_svm(vcpu);
1114         unsigned long val;
1115
1116         switch (dr) {
1117         case 0 ... 3:
1118                 val = vcpu->arch.db[dr];
1119                 break;
1120         case 6:
1121                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1122                         val = vcpu->arch.dr6;
1123                 else
1124                         val = svm->vmcb->save.dr6;
1125                 break;
1126         case 7:
1127                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1128                         val = vcpu->arch.dr7;
1129                 else
1130                         val = svm->vmcb->save.dr7;
1131                 break;
1132         default:
1133                 val = 0;
1134         }
1135
1136         return val;
1137 }
1138
1139 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1140                        int *exception)
1141 {
1142         struct vcpu_svm *svm = to_svm(vcpu);
1143
1144         *exception = 0;
1145
1146         switch (dr) {
1147         case 0 ... 3:
1148                 vcpu->arch.db[dr] = value;
1149                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1150                         vcpu->arch.eff_db[dr] = value;
1151                 return;
1152         case 4 ... 5:
1153                 if (vcpu->arch.cr4 & X86_CR4_DE)
1154                         *exception = UD_VECTOR;
1155                 return;
1156         case 6:
1157                 if (value & 0xffffffff00000000ULL) {
1158                         *exception = GP_VECTOR;
1159                         return;
1160                 }
1161                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1162                 return;
1163         case 7:
1164                 if (value & 0xffffffff00000000ULL) {
1165                         *exception = GP_VECTOR;
1166                         return;
1167                 }
1168                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1169                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1170                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1171                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1172                 }
1173                 return;
1174         default:
1175                 /* FIXME: Possible case? */
1176                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1177                        __func__, dr);
1178                 *exception = UD_VECTOR;
1179                 return;
1180         }
1181 }
1182
1183 static int pf_interception(struct vcpu_svm *svm)
1184 {
1185         u64 fault_address;
1186         u32 error_code;
1187
1188         fault_address  = svm->vmcb->control.exit_info_2;
1189         error_code = svm->vmcb->control.exit_info_1;
1190
1191         trace_kvm_page_fault(fault_address, error_code);
1192         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1193                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1194         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1195 }
1196
1197 static int db_interception(struct vcpu_svm *svm)
1198 {
1199         struct kvm_run *kvm_run = svm->vcpu.run;
1200
1201         if (!(svm->vcpu.guest_debug &
1202               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1203                 !svm->vcpu.arch.singlestep) {
1204                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1205                 return 1;
1206         }
1207
1208         if (svm->vcpu.arch.singlestep) {
1209                 svm->vcpu.arch.singlestep = false;
1210                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1211                         svm->vmcb->save.rflags &=
1212                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1213                 update_db_intercept(&svm->vcpu);
1214         }
1215
1216         if (svm->vcpu.guest_debug &
1217             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1218                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1219                 kvm_run->debug.arch.pc =
1220                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1221                 kvm_run->debug.arch.exception = DB_VECTOR;
1222                 return 0;
1223         }
1224
1225         return 1;
1226 }
1227
1228 static int bp_interception(struct vcpu_svm *svm)
1229 {
1230         struct kvm_run *kvm_run = svm->vcpu.run;
1231
1232         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1233         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1234         kvm_run->debug.arch.exception = BP_VECTOR;
1235         return 0;
1236 }
1237
1238 static int ud_interception(struct vcpu_svm *svm)
1239 {
1240         int er;
1241
1242         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1243         if (er != EMULATE_DONE)
1244                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1245         return 1;
1246 }
1247
1248 static int nm_interception(struct vcpu_svm *svm)
1249 {
1250         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1251         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1252                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1253         svm->vcpu.fpu_active = 1;
1254
1255         return 1;
1256 }
1257
1258 static int mc_interception(struct vcpu_svm *svm)
1259 {
1260         /*
1261          * On an #MC intercept the MCE handler is not called automatically in
1262          * the host. So do it by hand here.
1263          */
1264         asm volatile (
1265                 "int $0x12\n");
1266         /* not sure if we ever come back to this point */
1267
1268         return 1;
1269 }
1270
1271 static int shutdown_interception(struct vcpu_svm *svm)
1272 {
1273         struct kvm_run *kvm_run = svm->vcpu.run;
1274
1275         /*
1276          * VMCB is undefined after a SHUTDOWN intercept
1277          * so reinitialize it.
1278          */
1279         clear_page(svm->vmcb);
1280         init_vmcb(svm);
1281
1282         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1283         return 0;
1284 }
1285
1286 static int io_interception(struct vcpu_svm *svm)
1287 {
1288         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1289         int size, in, string;
1290         unsigned port;
1291
1292         ++svm->vcpu.stat.io_exits;
1293
1294         svm->next_rip = svm->vmcb->control.exit_info_2;
1295
1296         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1297
1298         if (string) {
1299                 if (emulate_instruction(&svm->vcpu,
1300                                         0, 0, 0) == EMULATE_DO_MMIO)
1301                         return 0;
1302                 return 1;
1303         }
1304
1305         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1306         port = io_info >> 16;
1307         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1308
1309         skip_emulated_instruction(&svm->vcpu);
1310         return kvm_emulate_pio(&svm->vcpu, in, size, port);
1311 }
1312
1313 static int nmi_interception(struct vcpu_svm *svm)
1314 {
1315         return 1;
1316 }
1317
1318 static int intr_interception(struct vcpu_svm *svm)
1319 {
1320         ++svm->vcpu.stat.irq_exits;
1321         return 1;
1322 }
1323
1324 static int nop_on_interception(struct vcpu_svm *svm)
1325 {
1326         return 1;
1327 }
1328
1329 static int halt_interception(struct vcpu_svm *svm)
1330 {
1331         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1332         skip_emulated_instruction(&svm->vcpu);
1333         return kvm_emulate_halt(&svm->vcpu);
1334 }
1335
1336 static int vmmcall_interception(struct vcpu_svm *svm)
1337 {
1338         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1339         skip_emulated_instruction(&svm->vcpu);
1340         kvm_emulate_hypercall(&svm->vcpu);
1341         return 1;
1342 }
1343
1344 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1345 {
1346         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1347             || !is_paging(&svm->vcpu)) {
1348                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1349                 return 1;
1350         }
1351
1352         if (svm->vmcb->save.cpl) {
1353                 kvm_inject_gp(&svm->vcpu, 0);
1354                 return 1;
1355         }
1356
1357        return 0;
1358 }
1359
1360 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1361                                       bool has_error_code, u32 error_code)
1362 {
1363         if (!is_nested(svm))
1364                 return 0;
1365
1366         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1367         svm->vmcb->control.exit_code_hi = 0;
1368         svm->vmcb->control.exit_info_1 = error_code;
1369         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1370
1371         return nested_svm_exit_handled(svm);
1372 }
1373
1374 static inline int nested_svm_intr(struct vcpu_svm *svm)
1375 {
1376         if (!is_nested(svm))
1377                 return 0;
1378
1379         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1380                 return 0;
1381
1382         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1383                 return 0;
1384
1385         svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1386
1387         if (nested_svm_exit_handled(svm)) {
1388                 nsvm_printk("VMexit -> INTR\n");
1389                 return 1;
1390         }
1391
1392         return 0;
1393 }
1394
1395 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1396 {
1397         struct page *page;
1398
1399         down_read(&current->mm->mmap_sem);
1400         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1401         up_read(&current->mm->mmap_sem);
1402
1403         if (is_error_page(page))
1404                 goto error;
1405
1406         return kmap_atomic(page, idx);
1407
1408 error:
1409         kvm_release_page_clean(page);
1410         kvm_inject_gp(&svm->vcpu, 0);
1411
1412         return NULL;
1413 }
1414
1415 static void nested_svm_unmap(void *addr, enum km_type idx)
1416 {
1417         struct page *page;
1418
1419         if (!addr)
1420                 return;
1421
1422         page = kmap_atomic_to_page(addr);
1423
1424         kunmap_atomic(addr, idx);
1425         kvm_release_page_dirty(page);
1426 }
1427
1428 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1429 {
1430         u32 param = svm->vmcb->control.exit_info_1 & 1;
1431         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1432         bool ret = false;
1433         u32 t0, t1;
1434         u8 *msrpm;
1435
1436         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1437                 return false;
1438
1439         msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1440
1441         if (!msrpm)
1442                 goto out;
1443
1444         switch (msr) {
1445         case 0 ... 0x1fff:
1446                 t0 = (msr * 2) % 8;
1447                 t1 = msr / 8;
1448                 break;
1449         case 0xc0000000 ... 0xc0001fff:
1450                 t0 = (8192 + msr - 0xc0000000) * 2;
1451                 t1 = (t0 / 8);
1452                 t0 %= 8;
1453                 break;
1454         case 0xc0010000 ... 0xc0011fff:
1455                 t0 = (16384 + msr - 0xc0010000) * 2;
1456                 t1 = (t0 / 8);
1457                 t0 %= 8;
1458                 break;
1459         default:
1460                 ret = true;
1461                 goto out;
1462         }
1463
1464         ret = msrpm[t1] & ((1 << param) << t0);
1465
1466 out:
1467         nested_svm_unmap(msrpm, KM_USER0);
1468
1469         return ret;
1470 }
1471
1472 static int nested_svm_exit_special(struct vcpu_svm *svm)
1473 {
1474         u32 exit_code = svm->vmcb->control.exit_code;
1475
1476         switch (exit_code) {
1477         case SVM_EXIT_INTR:
1478         case SVM_EXIT_NMI:
1479                 return NESTED_EXIT_HOST;
1480                 /* For now we are always handling NPFs when using them */
1481         case SVM_EXIT_NPF:
1482                 if (npt_enabled)
1483                         return NESTED_EXIT_HOST;
1484                 break;
1485         /* When we're shadowing, trap PFs */
1486         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1487                 if (!npt_enabled)
1488                         return NESTED_EXIT_HOST;
1489                 break;
1490         default:
1491                 break;
1492         }
1493
1494         return NESTED_EXIT_CONTINUE;
1495 }
1496
1497 /*
1498  * If this function returns true, this #vmexit was already handled
1499  */
1500 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1501 {
1502         u32 exit_code = svm->vmcb->control.exit_code;
1503         int vmexit = NESTED_EXIT_HOST;
1504
1505         switch (exit_code) {
1506         case SVM_EXIT_MSR:
1507                 vmexit = nested_svm_exit_handled_msr(svm);
1508                 break;
1509         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1510                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1511                 if (svm->nested.intercept_cr_read & cr_bits)
1512                         vmexit = NESTED_EXIT_DONE;
1513                 break;
1514         }
1515         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1516                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1517                 if (svm->nested.intercept_cr_write & cr_bits)
1518                         vmexit = NESTED_EXIT_DONE;
1519                 break;
1520         }
1521         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1522                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1523                 if (svm->nested.intercept_dr_read & dr_bits)
1524                         vmexit = NESTED_EXIT_DONE;
1525                 break;
1526         }
1527         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1528                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1529                 if (svm->nested.intercept_dr_write & dr_bits)
1530                         vmexit = NESTED_EXIT_DONE;
1531                 break;
1532         }
1533         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1534                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1535                 if (svm->nested.intercept_exceptions & excp_bits)
1536                         vmexit = NESTED_EXIT_DONE;
1537                 break;
1538         }
1539         default: {
1540                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1541                 nsvm_printk("exit code: 0x%x\n", exit_code);
1542                 if (svm->nested.intercept & exit_bits)
1543                         vmexit = NESTED_EXIT_DONE;
1544         }
1545         }
1546
1547         if (vmexit == NESTED_EXIT_DONE) {
1548                 nsvm_printk("#VMEXIT reason=%04x\n", exit_code);
1549                 nested_svm_vmexit(svm);
1550         }
1551
1552         return vmexit;
1553 }
1554
1555 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1556 {
1557         struct vmcb_control_area *dst  = &dst_vmcb->control;
1558         struct vmcb_control_area *from = &from_vmcb->control;
1559
1560         dst->intercept_cr_read    = from->intercept_cr_read;
1561         dst->intercept_cr_write   = from->intercept_cr_write;
1562         dst->intercept_dr_read    = from->intercept_dr_read;
1563         dst->intercept_dr_write   = from->intercept_dr_write;
1564         dst->intercept_exceptions = from->intercept_exceptions;
1565         dst->intercept            = from->intercept;
1566         dst->iopm_base_pa         = from->iopm_base_pa;
1567         dst->msrpm_base_pa        = from->msrpm_base_pa;
1568         dst->tsc_offset           = from->tsc_offset;
1569         dst->asid                 = from->asid;
1570         dst->tlb_ctl              = from->tlb_ctl;
1571         dst->int_ctl              = from->int_ctl;
1572         dst->int_vector           = from->int_vector;
1573         dst->int_state            = from->int_state;
1574         dst->exit_code            = from->exit_code;
1575         dst->exit_code_hi         = from->exit_code_hi;
1576         dst->exit_info_1          = from->exit_info_1;
1577         dst->exit_info_2          = from->exit_info_2;
1578         dst->exit_int_info        = from->exit_int_info;
1579         dst->exit_int_info_err    = from->exit_int_info_err;
1580         dst->nested_ctl           = from->nested_ctl;
1581         dst->event_inj            = from->event_inj;
1582         dst->event_inj_err        = from->event_inj_err;
1583         dst->nested_cr3           = from->nested_cr3;
1584         dst->lbr_ctl              = from->lbr_ctl;
1585 }
1586
1587 static int nested_svm_vmexit(struct vcpu_svm *svm)
1588 {
1589         struct vmcb *nested_vmcb;
1590         struct vmcb *hsave = svm->nested.hsave;
1591         struct vmcb *vmcb = svm->vmcb;
1592
1593         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1594         if (!nested_vmcb)
1595                 return 1;
1596
1597         /* Give the current vmcb to the guest */
1598         disable_gif(svm);
1599
1600         nested_vmcb->save.es     = vmcb->save.es;
1601         nested_vmcb->save.cs     = vmcb->save.cs;
1602         nested_vmcb->save.ss     = vmcb->save.ss;
1603         nested_vmcb->save.ds     = vmcb->save.ds;
1604         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1605         nested_vmcb->save.idtr   = vmcb->save.idtr;
1606         if (npt_enabled)
1607                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1608         nested_vmcb->save.cr2    = vmcb->save.cr2;
1609         nested_vmcb->save.rflags = vmcb->save.rflags;
1610         nested_vmcb->save.rip    = vmcb->save.rip;
1611         nested_vmcb->save.rsp    = vmcb->save.rsp;
1612         nested_vmcb->save.rax    = vmcb->save.rax;
1613         nested_vmcb->save.dr7    = vmcb->save.dr7;
1614         nested_vmcb->save.dr6    = vmcb->save.dr6;
1615         nested_vmcb->save.cpl    = vmcb->save.cpl;
1616
1617         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1618         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1619         nested_vmcb->control.int_state         = vmcb->control.int_state;
1620         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1621         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1622         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1623         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1624         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1625         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1626         nested_vmcb->control.tlb_ctl           = 0;
1627         nested_vmcb->control.event_inj         = 0;
1628         nested_vmcb->control.event_inj_err     = 0;
1629
1630         /* We always set V_INTR_MASKING and remember the old value in hflags */
1631         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1632                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1633
1634         /* Restore the original control entries */
1635         copy_vmcb_control_area(vmcb, hsave);
1636
1637         /* Kill any pending exceptions */
1638         if (svm->vcpu.arch.exception.pending == true)
1639                 nsvm_printk("WARNING: Pending Exception\n");
1640
1641         kvm_clear_exception_queue(&svm->vcpu);
1642         kvm_clear_interrupt_queue(&svm->vcpu);
1643
1644         /* Restore selected save entries */
1645         svm->vmcb->save.es = hsave->save.es;
1646         svm->vmcb->save.cs = hsave->save.cs;
1647         svm->vmcb->save.ss = hsave->save.ss;
1648         svm->vmcb->save.ds = hsave->save.ds;
1649         svm->vmcb->save.gdtr = hsave->save.gdtr;
1650         svm->vmcb->save.idtr = hsave->save.idtr;
1651         svm->vmcb->save.rflags = hsave->save.rflags;
1652         svm_set_efer(&svm->vcpu, hsave->save.efer);
1653         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1654         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1655         if (npt_enabled) {
1656                 svm->vmcb->save.cr3 = hsave->save.cr3;
1657                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1658         } else {
1659                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1660         }
1661         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1662         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1663         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1664         svm->vmcb->save.dr7 = 0;
1665         svm->vmcb->save.cpl = 0;
1666         svm->vmcb->control.exit_int_info = 0;
1667
1668         /* Exit nested SVM mode */
1669         svm->nested.vmcb = 0;
1670
1671         nested_svm_unmap(nested_vmcb, KM_USER0);
1672
1673         kvm_mmu_reset_context(&svm->vcpu);
1674         kvm_mmu_load(&svm->vcpu);
1675
1676         return 0;
1677 }
1678
1679 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1680 {
1681         u32 *nested_msrpm;
1682         int i;
1683
1684         nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1685         if (!nested_msrpm)
1686                 return false;
1687
1688         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1689                 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1690
1691         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1692
1693         nested_svm_unmap(nested_msrpm, KM_USER0);
1694
1695         return true;
1696 }
1697
1698 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1699 {
1700         struct vmcb *nested_vmcb;
1701         struct vmcb *hsave = svm->nested.hsave;
1702         struct vmcb *vmcb = svm->vmcb;
1703
1704         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1705         if (!nested_vmcb)
1706                 return false;
1707
1708         /* nested_vmcb is our indicator if nested SVM is activated */
1709         svm->nested.vmcb = svm->vmcb->save.rax;
1710
1711         /* Clear internal status */
1712         kvm_clear_exception_queue(&svm->vcpu);
1713         kvm_clear_interrupt_queue(&svm->vcpu);
1714
1715         /* Save the old vmcb, so we don't need to pick what we save, but
1716            can restore everything when a VMEXIT occurs */
1717         hsave->save.es     = vmcb->save.es;
1718         hsave->save.cs     = vmcb->save.cs;
1719         hsave->save.ss     = vmcb->save.ss;
1720         hsave->save.ds     = vmcb->save.ds;
1721         hsave->save.gdtr   = vmcb->save.gdtr;
1722         hsave->save.idtr   = vmcb->save.idtr;
1723         hsave->save.efer   = svm->vcpu.arch.shadow_efer;
1724         hsave->save.cr0    = svm->vcpu.arch.cr0;
1725         hsave->save.cr4    = svm->vcpu.arch.cr4;
1726         hsave->save.rflags = vmcb->save.rflags;
1727         hsave->save.rip    = svm->next_rip;
1728         hsave->save.rsp    = vmcb->save.rsp;
1729         hsave->save.rax    = vmcb->save.rax;
1730         if (npt_enabled)
1731                 hsave->save.cr3    = vmcb->save.cr3;
1732         else
1733                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1734
1735         copy_vmcb_control_area(hsave, vmcb);
1736
1737         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1738                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1739         else
1740                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1741
1742         /* Load the nested guest state */
1743         svm->vmcb->save.es = nested_vmcb->save.es;
1744         svm->vmcb->save.cs = nested_vmcb->save.cs;
1745         svm->vmcb->save.ss = nested_vmcb->save.ss;
1746         svm->vmcb->save.ds = nested_vmcb->save.ds;
1747         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1748         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1749         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1750         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1751         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1752         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1753         if (npt_enabled) {
1754                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1755                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1756         } else {
1757                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1758                 kvm_mmu_reset_context(&svm->vcpu);
1759         }
1760         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1761         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1762         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1763         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1764         /* In case we don't even reach vcpu_run, the fields are not updated */
1765         svm->vmcb->save.rax = nested_vmcb->save.rax;
1766         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1767         svm->vmcb->save.rip = nested_vmcb->save.rip;
1768         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1769         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1770         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1771
1772         /* We don't want a nested guest to be more powerful than the guest,
1773            so all intercepts are ORed */
1774         svm->vmcb->control.intercept_cr_read |=
1775                 nested_vmcb->control.intercept_cr_read;
1776         svm->vmcb->control.intercept_cr_write |=
1777                 nested_vmcb->control.intercept_cr_write;
1778         svm->vmcb->control.intercept_dr_read |=
1779                 nested_vmcb->control.intercept_dr_read;
1780         svm->vmcb->control.intercept_dr_write |=
1781                 nested_vmcb->control.intercept_dr_write;
1782         svm->vmcb->control.intercept_exceptions |=
1783                 nested_vmcb->control.intercept_exceptions;
1784
1785         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1786
1787         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1788
1789         /* cache intercepts */
1790         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
1791         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
1792         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
1793         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
1794         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1795         svm->nested.intercept            = nested_vmcb->control.intercept;
1796
1797         force_new_asid(&svm->vcpu);
1798         svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1799         svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1800         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1801         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1802                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1803                                 nested_vmcb->control.int_ctl);
1804         }
1805         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1806                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1807         else
1808                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1809
1810         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1811                         nested_vmcb->control.exit_int_info,
1812                         nested_vmcb->control.int_state);
1813
1814         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1815         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1816         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1817         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1818                 nsvm_printk("Injecting Event: 0x%x\n",
1819                                 nested_vmcb->control.event_inj);
1820         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1821         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1822
1823         nested_svm_unmap(nested_vmcb, KM_USER0);
1824
1825         enable_gif(svm);
1826
1827         return true;
1828 }
1829
1830 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1831 {
1832         to_vmcb->save.fs = from_vmcb->save.fs;
1833         to_vmcb->save.gs = from_vmcb->save.gs;
1834         to_vmcb->save.tr = from_vmcb->save.tr;
1835         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1836         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1837         to_vmcb->save.star = from_vmcb->save.star;
1838         to_vmcb->save.lstar = from_vmcb->save.lstar;
1839         to_vmcb->save.cstar = from_vmcb->save.cstar;
1840         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1841         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1842         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1843         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1844 }
1845
1846 static int vmload_interception(struct vcpu_svm *svm)
1847 {
1848         struct vmcb *nested_vmcb;
1849
1850         if (nested_svm_check_permissions(svm))
1851                 return 1;
1852
1853         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1854         skip_emulated_instruction(&svm->vcpu);
1855
1856         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1857         if (!nested_vmcb)
1858                 return 1;
1859
1860         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1861         nested_svm_unmap(nested_vmcb, KM_USER0);
1862
1863         return 1;
1864 }
1865
1866 static int vmsave_interception(struct vcpu_svm *svm)
1867 {
1868         struct vmcb *nested_vmcb;
1869
1870         if (nested_svm_check_permissions(svm))
1871                 return 1;
1872
1873         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1874         skip_emulated_instruction(&svm->vcpu);
1875
1876         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1877         if (!nested_vmcb)
1878                 return 1;
1879
1880         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1881         nested_svm_unmap(nested_vmcb, KM_USER0);
1882
1883         return 1;
1884 }
1885
1886 static int vmrun_interception(struct vcpu_svm *svm)
1887 {
1888         nsvm_printk("VMrun\n");
1889
1890         if (nested_svm_check_permissions(svm))
1891                 return 1;
1892
1893         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1894         skip_emulated_instruction(&svm->vcpu);
1895
1896         if (!nested_svm_vmrun(svm))
1897                 return 1;
1898
1899         if (!nested_svm_vmrun_msrpm(svm))
1900                 goto failed;
1901
1902         return 1;
1903
1904 failed:
1905
1906         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
1907         svm->vmcb->control.exit_code_hi = 0;
1908         svm->vmcb->control.exit_info_1  = 0;
1909         svm->vmcb->control.exit_info_2  = 0;
1910
1911         nested_svm_vmexit(svm);
1912
1913         return 1;
1914 }
1915
1916 static int stgi_interception(struct vcpu_svm *svm)
1917 {
1918         if (nested_svm_check_permissions(svm))
1919                 return 1;
1920
1921         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1922         skip_emulated_instruction(&svm->vcpu);
1923
1924         enable_gif(svm);
1925
1926         return 1;
1927 }
1928
1929 static int clgi_interception(struct vcpu_svm *svm)
1930 {
1931         if (nested_svm_check_permissions(svm))
1932                 return 1;
1933
1934         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1935         skip_emulated_instruction(&svm->vcpu);
1936
1937         disable_gif(svm);
1938
1939         /* After a CLGI no interrupts should come */
1940         svm_clear_vintr(svm);
1941         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1942
1943         return 1;
1944 }
1945
1946 static int invlpga_interception(struct vcpu_svm *svm)
1947 {
1948         struct kvm_vcpu *vcpu = &svm->vcpu;
1949         nsvm_printk("INVLPGA\n");
1950
1951         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1952         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1953
1954         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1955         skip_emulated_instruction(&svm->vcpu);
1956         return 1;
1957 }
1958
1959 static int invalid_op_interception(struct vcpu_svm *svm)
1960 {
1961         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1962         return 1;
1963 }
1964
1965 static int task_switch_interception(struct vcpu_svm *svm)
1966 {
1967         u16 tss_selector;
1968         int reason;
1969         int int_type = svm->vmcb->control.exit_int_info &
1970                 SVM_EXITINTINFO_TYPE_MASK;
1971         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1972         uint32_t type =
1973                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1974         uint32_t idt_v =
1975                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1976
1977         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1978
1979         if (svm->vmcb->control.exit_info_2 &
1980             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1981                 reason = TASK_SWITCH_IRET;
1982         else if (svm->vmcb->control.exit_info_2 &
1983                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1984                 reason = TASK_SWITCH_JMP;
1985         else if (idt_v)
1986                 reason = TASK_SWITCH_GATE;
1987         else
1988                 reason = TASK_SWITCH_CALL;
1989
1990         if (reason == TASK_SWITCH_GATE) {
1991                 switch (type) {
1992                 case SVM_EXITINTINFO_TYPE_NMI:
1993                         svm->vcpu.arch.nmi_injected = false;
1994                         break;
1995                 case SVM_EXITINTINFO_TYPE_EXEPT:
1996                         kvm_clear_exception_queue(&svm->vcpu);
1997                         break;
1998                 case SVM_EXITINTINFO_TYPE_INTR:
1999                         kvm_clear_interrupt_queue(&svm->vcpu);
2000                         break;
2001                 default:
2002                         break;
2003                 }
2004         }
2005
2006         if (reason != TASK_SWITCH_GATE ||
2007             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2008             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2009              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2010                 skip_emulated_instruction(&svm->vcpu);
2011
2012         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2013 }
2014
2015 static int cpuid_interception(struct vcpu_svm *svm)
2016 {
2017         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2018         kvm_emulate_cpuid(&svm->vcpu);
2019         return 1;
2020 }
2021
2022 static int iret_interception(struct vcpu_svm *svm)
2023 {
2024         ++svm->vcpu.stat.nmi_window_exits;
2025         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2026         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2027         return 1;
2028 }
2029
2030 static int invlpg_interception(struct vcpu_svm *svm)
2031 {
2032         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2033                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2034         return 1;
2035 }
2036
2037 static int emulate_on_interception(struct vcpu_svm *svm)
2038 {
2039         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2040                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2041         return 1;
2042 }
2043
2044 static int cr8_write_interception(struct vcpu_svm *svm)
2045 {
2046         struct kvm_run *kvm_run = svm->vcpu.run;
2047
2048         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2049         /* instruction emulation calls kvm_set_cr8() */
2050         emulate_instruction(&svm->vcpu, 0, 0, 0);
2051         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2052                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2053                 return 1;
2054         }
2055         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2056                 return 1;
2057         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2058         return 0;
2059 }
2060
2061 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2062 {
2063         struct vcpu_svm *svm = to_svm(vcpu);
2064
2065         switch (ecx) {
2066         case MSR_IA32_TSC: {
2067                 u64 tsc_offset;
2068
2069                 if (is_nested(svm))
2070                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2071                 else
2072                         tsc_offset = svm->vmcb->control.tsc_offset;
2073
2074                 *data = tsc_offset + native_read_tsc();
2075                 break;
2076         }
2077         case MSR_K6_STAR:
2078                 *data = svm->vmcb->save.star;
2079                 break;
2080 #ifdef CONFIG_X86_64
2081         case MSR_LSTAR:
2082                 *data = svm->vmcb->save.lstar;
2083                 break;
2084         case MSR_CSTAR:
2085                 *data = svm->vmcb->save.cstar;
2086                 break;
2087         case MSR_KERNEL_GS_BASE:
2088                 *data = svm->vmcb->save.kernel_gs_base;
2089                 break;
2090         case MSR_SYSCALL_MASK:
2091                 *data = svm->vmcb->save.sfmask;
2092                 break;
2093 #endif
2094         case MSR_IA32_SYSENTER_CS:
2095                 *data = svm->vmcb->save.sysenter_cs;
2096                 break;
2097         case MSR_IA32_SYSENTER_EIP:
2098                 *data = svm->sysenter_eip;
2099                 break;
2100         case MSR_IA32_SYSENTER_ESP:
2101                 *data = svm->sysenter_esp;
2102                 break;
2103         /* Nobody will change the following 5 values in the VMCB so
2104            we can safely return them on rdmsr. They will always be 0
2105            until LBRV is implemented. */
2106         case MSR_IA32_DEBUGCTLMSR:
2107                 *data = svm->vmcb->save.dbgctl;
2108                 break;
2109         case MSR_IA32_LASTBRANCHFROMIP:
2110                 *data = svm->vmcb->save.br_from;
2111                 break;
2112         case MSR_IA32_LASTBRANCHTOIP:
2113                 *data = svm->vmcb->save.br_to;
2114                 break;
2115         case MSR_IA32_LASTINTFROMIP:
2116                 *data = svm->vmcb->save.last_excp_from;
2117                 break;
2118         case MSR_IA32_LASTINTTOIP:
2119                 *data = svm->vmcb->save.last_excp_to;
2120                 break;
2121         case MSR_VM_HSAVE_PA:
2122                 *data = svm->nested.hsave_msr;
2123                 break;
2124         case MSR_VM_CR:
2125                 *data = 0;
2126                 break;
2127         case MSR_IA32_UCODE_REV:
2128                 *data = 0x01000065;
2129                 break;
2130         default:
2131                 return kvm_get_msr_common(vcpu, ecx, data);
2132         }
2133         return 0;
2134 }
2135
2136 static int rdmsr_interception(struct vcpu_svm *svm)
2137 {
2138         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2139         u64 data;
2140
2141         if (svm_get_msr(&svm->vcpu, ecx, &data))
2142                 kvm_inject_gp(&svm->vcpu, 0);
2143         else {
2144                 trace_kvm_msr_read(ecx, data);
2145
2146                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2147                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2148                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2149                 skip_emulated_instruction(&svm->vcpu);
2150         }
2151         return 1;
2152 }
2153
2154 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2155 {
2156         struct vcpu_svm *svm = to_svm(vcpu);
2157
2158         switch (ecx) {
2159         case MSR_IA32_TSC: {
2160                 u64 tsc_offset = data - native_read_tsc();
2161                 u64 g_tsc_offset = 0;
2162
2163                 if (is_nested(svm)) {
2164                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2165                                        svm->nested.hsave->control.tsc_offset;
2166                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2167                 }
2168
2169                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2170
2171                 break;
2172         }
2173         case MSR_K6_STAR:
2174                 svm->vmcb->save.star = data;
2175                 break;
2176 #ifdef CONFIG_X86_64
2177         case MSR_LSTAR:
2178                 svm->vmcb->save.lstar = data;
2179                 break;
2180         case MSR_CSTAR:
2181                 svm->vmcb->save.cstar = data;
2182                 break;
2183         case MSR_KERNEL_GS_BASE:
2184                 svm->vmcb->save.kernel_gs_base = data;
2185                 break;
2186         case MSR_SYSCALL_MASK:
2187                 svm->vmcb->save.sfmask = data;
2188                 break;
2189 #endif
2190         case MSR_IA32_SYSENTER_CS:
2191                 svm->vmcb->save.sysenter_cs = data;
2192                 break;
2193         case MSR_IA32_SYSENTER_EIP:
2194                 svm->sysenter_eip = data;
2195                 svm->vmcb->save.sysenter_eip = data;
2196                 break;
2197         case MSR_IA32_SYSENTER_ESP:
2198                 svm->sysenter_esp = data;
2199                 svm->vmcb->save.sysenter_esp = data;
2200                 break;
2201         case MSR_IA32_DEBUGCTLMSR:
2202                 if (!svm_has(SVM_FEATURE_LBRV)) {
2203                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2204                                         __func__, data);
2205                         break;
2206                 }
2207                 if (data & DEBUGCTL_RESERVED_BITS)
2208                         return 1;
2209
2210                 svm->vmcb->save.dbgctl = data;
2211                 if (data & (1ULL<<0))
2212                         svm_enable_lbrv(svm);
2213                 else
2214                         svm_disable_lbrv(svm);
2215                 break;
2216         case MSR_VM_HSAVE_PA:
2217                 svm->nested.hsave_msr = data;
2218                 break;
2219         case MSR_VM_CR:
2220         case MSR_VM_IGNNE:
2221                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2222                 break;
2223         default:
2224                 return kvm_set_msr_common(vcpu, ecx, data);
2225         }
2226         return 0;
2227 }
2228
2229 static int wrmsr_interception(struct vcpu_svm *svm)
2230 {
2231         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2232         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2233                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2234
2235         trace_kvm_msr_write(ecx, data);
2236
2237         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2238         if (svm_set_msr(&svm->vcpu, ecx, data))
2239                 kvm_inject_gp(&svm->vcpu, 0);
2240         else
2241                 skip_emulated_instruction(&svm->vcpu);
2242         return 1;
2243 }
2244
2245 static int msr_interception(struct vcpu_svm *svm)
2246 {
2247         if (svm->vmcb->control.exit_info_1)
2248                 return wrmsr_interception(svm);
2249         else
2250                 return rdmsr_interception(svm);
2251 }
2252
2253 static int interrupt_window_interception(struct vcpu_svm *svm)
2254 {
2255         struct kvm_run *kvm_run = svm->vcpu.run;
2256
2257         svm_clear_vintr(svm);
2258         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2259         /*
2260          * If the user space waits to inject interrupts, exit as soon as
2261          * possible
2262          */
2263         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2264             kvm_run->request_interrupt_window &&
2265             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2266                 ++svm->vcpu.stat.irq_window_exits;
2267                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2268                 return 0;
2269         }
2270
2271         return 1;
2272 }
2273
2274 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2275         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2276         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2277         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2278         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2279         /* for now: */
2280         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2281         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2282         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2283         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2284         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2285         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2286         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2287         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2288         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2289         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2290         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2291         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2292         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2293         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2294         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2295         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2296         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2297         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2298         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2299         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2300         [SVM_EXIT_INTR]                         = intr_interception,
2301         [SVM_EXIT_NMI]                          = nmi_interception,
2302         [SVM_EXIT_SMI]                          = nop_on_interception,
2303         [SVM_EXIT_INIT]                         = nop_on_interception,
2304         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2305         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2306         [SVM_EXIT_CPUID]                        = cpuid_interception,
2307         [SVM_EXIT_IRET]                         = iret_interception,
2308         [SVM_EXIT_INVD]                         = emulate_on_interception,
2309         [SVM_EXIT_HLT]                          = halt_interception,
2310         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2311         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2312         [SVM_EXIT_IOIO]                         = io_interception,
2313         [SVM_EXIT_MSR]                          = msr_interception,
2314         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2315         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2316         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2317         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2318         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2319         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2320         [SVM_EXIT_STGI]                         = stgi_interception,
2321         [SVM_EXIT_CLGI]                         = clgi_interception,
2322         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
2323         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2324         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2325         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2326         [SVM_EXIT_NPF]                          = pf_interception,
2327 };
2328
2329 static int handle_exit(struct kvm_vcpu *vcpu)
2330 {
2331         struct vcpu_svm *svm = to_svm(vcpu);
2332         struct kvm_run *kvm_run = vcpu->run;
2333         u32 exit_code = svm->vmcb->control.exit_code;
2334
2335         trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2336
2337         if (is_nested(svm)) {
2338                 int vmexit;
2339
2340                 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2341                             exit_code, svm->vmcb->control.exit_info_1,
2342                             svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2343
2344                 vmexit = nested_svm_exit_special(svm);
2345
2346                 if (vmexit == NESTED_EXIT_CONTINUE)
2347                         vmexit = nested_svm_exit_handled(svm);
2348
2349                 if (vmexit == NESTED_EXIT_DONE)
2350                         return 1;
2351         }
2352
2353         svm_complete_interrupts(svm);
2354
2355         if (npt_enabled) {
2356                 int mmu_reload = 0;
2357                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2358                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2359                         mmu_reload = 1;
2360                 }
2361                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2362                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2363                 if (mmu_reload) {
2364                         kvm_mmu_reset_context(vcpu);
2365                         kvm_mmu_load(vcpu);
2366                 }
2367         }
2368
2369
2370         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2371                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2372                 kvm_run->fail_entry.hardware_entry_failure_reason
2373                         = svm->vmcb->control.exit_code;
2374                 return 0;
2375         }
2376
2377         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2378             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2379             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2380                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2381                        "exit_code 0x%x\n",
2382                        __func__, svm->vmcb->control.exit_int_info,
2383                        exit_code);
2384
2385         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2386             || !svm_exit_handlers[exit_code]) {
2387                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2388                 kvm_run->hw.hardware_exit_reason = exit_code;
2389                 return 0;
2390         }
2391
2392         return svm_exit_handlers[exit_code](svm);
2393 }
2394
2395 static void reload_tss(struct kvm_vcpu *vcpu)
2396 {
2397         int cpu = raw_smp_processor_id();
2398
2399         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2400         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2401         load_TR_desc();
2402 }
2403
2404 static void pre_svm_run(struct vcpu_svm *svm)
2405 {
2406         int cpu = raw_smp_processor_id();
2407
2408         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2409
2410         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2411         /* FIXME: handle wraparound of asid_generation */
2412         if (svm->asid_generation != svm_data->asid_generation)
2413                 new_asid(svm, svm_data);
2414 }
2415
2416 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2417 {
2418         struct vcpu_svm *svm = to_svm(vcpu);
2419
2420         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2421         vcpu->arch.hflags |= HF_NMI_MASK;
2422         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2423         ++vcpu->stat.nmi_injections;
2424 }
2425
2426 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2427 {
2428         struct vmcb_control_area *control;
2429
2430         trace_kvm_inj_virq(irq);
2431
2432         ++svm->vcpu.stat.irq_injections;
2433         control = &svm->vmcb->control;
2434         control->int_vector = irq;
2435         control->int_ctl &= ~V_INTR_PRIO_MASK;
2436         control->int_ctl |= V_IRQ_MASK |
2437                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2438 }
2439
2440 static void svm_set_irq(struct kvm_vcpu *vcpu)
2441 {
2442         struct vcpu_svm *svm = to_svm(vcpu);
2443
2444         BUG_ON(!(gif_set(svm)));
2445
2446         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2447                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2448 }
2449
2450 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2451 {
2452         struct vcpu_svm *svm = to_svm(vcpu);
2453
2454         if (irr == -1)
2455                 return;
2456
2457         if (tpr >= irr)
2458                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2459 }
2460
2461 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2462 {
2463         struct vcpu_svm *svm = to_svm(vcpu);
2464         struct vmcb *vmcb = svm->vmcb;
2465         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2466                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2467 }
2468
2469 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2470 {
2471         struct vcpu_svm *svm = to_svm(vcpu);
2472         struct vmcb *vmcb = svm->vmcb;
2473         return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2474                 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2475                 gif_set(svm) &&
2476                 !(is_nested(svm) && (svm->vcpu.arch.hflags & HF_VINTR_MASK));
2477 }
2478
2479 static void enable_irq_window(struct kvm_vcpu *vcpu)
2480 {
2481         struct vcpu_svm *svm = to_svm(vcpu);
2482         nsvm_printk("Trying to open IRQ window\n");
2483
2484         nested_svm_intr(svm);
2485
2486         /* In case GIF=0 we can't rely on the CPU to tell us when
2487          * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2488          * The next time we get that intercept, this function will be
2489          * called again though and we'll get the vintr intercept. */
2490         if (gif_set(svm)) {
2491                 svm_set_vintr(svm);
2492                 svm_inject_irq(svm, 0x0);
2493         }
2494 }
2495
2496 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2497 {
2498         struct vcpu_svm *svm = to_svm(vcpu);
2499
2500         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2501             == HF_NMI_MASK)
2502                 return; /* IRET will cause a vm exit */
2503
2504         /* Something prevents NMI from been injected. Single step over
2505            possible problem (IRET or exception injection or interrupt
2506            shadow) */
2507         vcpu->arch.singlestep = true;
2508         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2509         update_db_intercept(vcpu);
2510 }
2511
2512 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2513 {
2514         return 0;
2515 }
2516
2517 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2518 {
2519         force_new_asid(vcpu);
2520 }
2521
2522 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2523 {
2524 }
2525
2526 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2527 {
2528         struct vcpu_svm *svm = to_svm(vcpu);
2529
2530         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2531                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2532                 kvm_set_cr8(vcpu, cr8);
2533         }
2534 }
2535
2536 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2537 {
2538         struct vcpu_svm *svm = to_svm(vcpu);
2539         u64 cr8;
2540
2541         cr8 = kvm_get_cr8(vcpu);
2542         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2543         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2544 }
2545
2546 static void svm_complete_interrupts(struct vcpu_svm *svm)
2547 {
2548         u8 vector;
2549         int type;
2550         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2551
2552         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2553                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2554
2555         svm->vcpu.arch.nmi_injected = false;
2556         kvm_clear_exception_queue(&svm->vcpu);
2557         kvm_clear_interrupt_queue(&svm->vcpu);
2558
2559         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2560                 return;
2561
2562         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2563         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2564
2565         switch (type) {
2566         case SVM_EXITINTINFO_TYPE_NMI:
2567                 svm->vcpu.arch.nmi_injected = true;
2568                 break;
2569         case SVM_EXITINTINFO_TYPE_EXEPT:
2570                 /* In case of software exception do not reinject an exception
2571                    vector, but re-execute and instruction instead */
2572                 if (is_nested(svm))
2573                         break;
2574                 if (kvm_exception_is_soft(vector))
2575                         break;
2576                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2577                         u32 err = svm->vmcb->control.exit_int_info_err;
2578                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2579
2580                 } else
2581                         kvm_queue_exception(&svm->vcpu, vector);
2582                 break;
2583         case SVM_EXITINTINFO_TYPE_INTR:
2584                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2585                 break;
2586         default:
2587                 break;
2588         }
2589 }
2590
2591 #ifdef CONFIG_X86_64
2592 #define R "r"
2593 #else
2594 #define R "e"
2595 #endif
2596
2597 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2598 {
2599         struct vcpu_svm *svm = to_svm(vcpu);
2600         u16 fs_selector;
2601         u16 gs_selector;
2602         u16 ldt_selector;
2603
2604         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2605         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2606         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2607
2608         pre_svm_run(svm);
2609
2610         sync_lapic_to_cr8(vcpu);
2611
2612         save_host_msrs(vcpu);
2613         fs_selector = kvm_read_fs();
2614         gs_selector = kvm_read_gs();
2615         ldt_selector = kvm_read_ldt();
2616         svm->vmcb->save.cr2 = vcpu->arch.cr2;
2617         /* required for live migration with NPT */
2618         if (npt_enabled)
2619                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2620
2621         clgi();
2622
2623         local_irq_enable();
2624
2625         asm volatile (
2626                 "push %%"R"bp; \n\t"
2627                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2628                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2629                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2630                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2631                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2632                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2633 #ifdef CONFIG_X86_64
2634                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2635                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2636                 "mov %c[r10](%[svm]), %%r10 \n\t"
2637                 "mov %c[r11](%[svm]), %%r11 \n\t"
2638                 "mov %c[r12](%[svm]), %%r12 \n\t"
2639                 "mov %c[r13](%[svm]), %%r13 \n\t"
2640                 "mov %c[r14](%[svm]), %%r14 \n\t"
2641                 "mov %c[r15](%[svm]), %%r15 \n\t"
2642 #endif
2643
2644                 /* Enter guest mode */
2645                 "push %%"R"ax \n\t"
2646                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2647                 __ex(SVM_VMLOAD) "\n\t"
2648                 __ex(SVM_VMRUN) "\n\t"
2649                 __ex(SVM_VMSAVE) "\n\t"
2650                 "pop %%"R"ax \n\t"
2651
2652                 /* Save guest registers, load host registers */
2653                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2654                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2655                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2656                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2657                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2658                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2659 #ifdef CONFIG_X86_64
2660                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2661                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2662                 "mov %%r10, %c[r10](%[svm]) \n\t"
2663                 "mov %%r11, %c[r11](%[svm]) \n\t"
2664                 "mov %%r12, %c[r12](%[svm]) \n\t"
2665                 "mov %%r13, %c[r13](%[svm]) \n\t"
2666                 "mov %%r14, %c[r14](%[svm]) \n\t"
2667                 "mov %%r15, %c[r15](%[svm]) \n\t"
2668 #endif
2669                 "pop %%"R"bp"
2670                 :
2671                 : [svm]"a"(svm),
2672                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2673                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2674                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2675                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2676                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2677                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2678                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2679 #ifdef CONFIG_X86_64
2680                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2681                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2682                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2683                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2684                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2685                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2686                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2687                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2688 #endif
2689                 : "cc", "memory"
2690                 , R"bx", R"cx", R"dx", R"si", R"di"
2691 #ifdef CONFIG_X86_64
2692                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2693 #endif
2694                 );
2695
2696         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2697         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2698         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2699         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2700
2701         kvm_load_fs(fs_selector);
2702         kvm_load_gs(gs_selector);
2703         kvm_load_ldt(ldt_selector);
2704         load_host_msrs(vcpu);
2705
2706         reload_tss(vcpu);
2707
2708         local_irq_disable();
2709
2710         stgi();
2711
2712         sync_cr8_to_lapic(vcpu);
2713
2714         svm->next_rip = 0;
2715
2716         if (npt_enabled) {
2717                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2718                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2719         }
2720 }
2721
2722 #undef R
2723
2724 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2725 {
2726         struct vcpu_svm *svm = to_svm(vcpu);
2727
2728         if (npt_enabled) {
2729                 svm->vmcb->control.nested_cr3 = root;
2730                 force_new_asid(vcpu);
2731                 return;
2732         }
2733
2734         svm->vmcb->save.cr3 = root;
2735         force_new_asid(vcpu);
2736
2737         if (vcpu->fpu_active) {
2738                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2739                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2740                 vcpu->fpu_active = 0;
2741         }
2742 }
2743
2744 static int is_disabled(void)
2745 {
2746         u64 vm_cr;
2747
2748         rdmsrl(MSR_VM_CR, vm_cr);
2749         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2750                 return 1;
2751
2752         return 0;
2753 }
2754
2755 static void
2756 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2757 {
2758         /*
2759          * Patch in the VMMCALL instruction:
2760          */
2761         hypercall[0] = 0x0f;
2762         hypercall[1] = 0x01;
2763         hypercall[2] = 0xd9;
2764 }
2765
2766 static void svm_check_processor_compat(void *rtn)
2767 {
2768         *(int *)rtn = 0;
2769 }
2770
2771 static bool svm_cpu_has_accelerated_tpr(void)
2772 {
2773         return false;
2774 }
2775
2776 static int get_npt_level(void)
2777 {
2778 #ifdef CONFIG_X86_64
2779         return PT64_ROOT_LEVEL;
2780 #else
2781         return PT32E_ROOT_LEVEL;
2782 #endif
2783 }
2784
2785 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2786 {
2787         return 0;
2788 }
2789
2790 static const struct trace_print_flags svm_exit_reasons_str[] = {
2791         { SVM_EXIT_READ_CR0,                    "read_cr0" },
2792         { SVM_EXIT_READ_CR3,                    "read_cr3" },
2793         { SVM_EXIT_READ_CR4,                    "read_cr4" },
2794         { SVM_EXIT_READ_CR8,                    "read_cr8" },
2795         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
2796         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
2797         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
2798         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
2799         { SVM_EXIT_READ_DR0,                    "read_dr0" },
2800         { SVM_EXIT_READ_DR1,                    "read_dr1" },
2801         { SVM_EXIT_READ_DR2,                    "read_dr2" },
2802         { SVM_EXIT_READ_DR3,                    "read_dr3" },
2803         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
2804         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
2805         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
2806         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
2807         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
2808         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
2809         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
2810         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
2811         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
2812         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
2813         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
2814         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
2815         { SVM_EXIT_INTR,                        "interrupt" },
2816         { SVM_EXIT_NMI,                         "nmi" },
2817         { SVM_EXIT_SMI,                         "smi" },
2818         { SVM_EXIT_INIT,                        "init" },
2819         { SVM_EXIT_VINTR,                       "vintr" },
2820         { SVM_EXIT_CPUID,                       "cpuid" },
2821         { SVM_EXIT_INVD,                        "invd" },
2822         { SVM_EXIT_HLT,                         "hlt" },
2823         { SVM_EXIT_INVLPG,                      "invlpg" },
2824         { SVM_EXIT_INVLPGA,                     "invlpga" },
2825         { SVM_EXIT_IOIO,                        "io" },
2826         { SVM_EXIT_MSR,                         "msr" },
2827         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
2828         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
2829         { SVM_EXIT_VMRUN,                       "vmrun" },
2830         { SVM_EXIT_VMMCALL,                     "hypercall" },
2831         { SVM_EXIT_VMLOAD,                      "vmload" },
2832         { SVM_EXIT_VMSAVE,                      "vmsave" },
2833         { SVM_EXIT_STGI,                        "stgi" },
2834         { SVM_EXIT_CLGI,                        "clgi" },
2835         { SVM_EXIT_SKINIT,                      "skinit" },
2836         { SVM_EXIT_WBINVD,                      "wbinvd" },
2837         { SVM_EXIT_MONITOR,                     "monitor" },
2838         { SVM_EXIT_MWAIT,                       "mwait" },
2839         { SVM_EXIT_NPF,                         "npf" },
2840         { -1, NULL }
2841 };
2842
2843 static bool svm_gb_page_enable(void)
2844 {
2845         return true;
2846 }
2847
2848 static struct kvm_x86_ops svm_x86_ops = {
2849         .cpu_has_kvm_support = has_svm,
2850         .disabled_by_bios = is_disabled,
2851         .hardware_setup = svm_hardware_setup,
2852         .hardware_unsetup = svm_hardware_unsetup,
2853         .check_processor_compatibility = svm_check_processor_compat,
2854         .hardware_enable = svm_hardware_enable,
2855         .hardware_disable = svm_hardware_disable,
2856         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2857
2858         .vcpu_create = svm_create_vcpu,
2859         .vcpu_free = svm_free_vcpu,
2860         .vcpu_reset = svm_vcpu_reset,
2861
2862         .prepare_guest_switch = svm_prepare_guest_switch,
2863         .vcpu_load = svm_vcpu_load,
2864         .vcpu_put = svm_vcpu_put,
2865
2866         .set_guest_debug = svm_guest_debug,
2867         .get_msr = svm_get_msr,
2868         .set_msr = svm_set_msr,
2869         .get_segment_base = svm_get_segment_base,
2870         .get_segment = svm_get_segment,
2871         .set_segment = svm_set_segment,
2872         .get_cpl = svm_get_cpl,
2873         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2874         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2875         .set_cr0 = svm_set_cr0,
2876         .set_cr3 = svm_set_cr3,
2877         .set_cr4 = svm_set_cr4,
2878         .set_efer = svm_set_efer,
2879         .get_idt = svm_get_idt,
2880         .set_idt = svm_set_idt,
2881         .get_gdt = svm_get_gdt,
2882         .set_gdt = svm_set_gdt,
2883         .get_dr = svm_get_dr,
2884         .set_dr = svm_set_dr,
2885         .cache_reg = svm_cache_reg,
2886         .get_rflags = svm_get_rflags,
2887         .set_rflags = svm_set_rflags,
2888
2889         .tlb_flush = svm_flush_tlb,
2890
2891         .run = svm_vcpu_run,
2892         .handle_exit = handle_exit,
2893         .skip_emulated_instruction = skip_emulated_instruction,
2894         .set_interrupt_shadow = svm_set_interrupt_shadow,
2895         .get_interrupt_shadow = svm_get_interrupt_shadow,
2896         .patch_hypercall = svm_patch_hypercall,
2897         .set_irq = svm_set_irq,
2898         .set_nmi = svm_inject_nmi,
2899         .queue_exception = svm_queue_exception,
2900         .interrupt_allowed = svm_interrupt_allowed,
2901         .nmi_allowed = svm_nmi_allowed,
2902         .enable_nmi_window = enable_nmi_window,
2903         .enable_irq_window = enable_irq_window,
2904         .update_cr8_intercept = update_cr8_intercept,
2905
2906         .set_tss_addr = svm_set_tss_addr,
2907         .get_tdp_level = get_npt_level,
2908         .get_mt_mask = svm_get_mt_mask,
2909
2910         .exit_reasons_str = svm_exit_reasons_str,
2911         .gb_page_enable = svm_gb_page_enable,
2912 };
2913
2914 static int __init svm_init(void)
2915 {
2916         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2917                               THIS_MODULE);
2918 }
2919
2920 static void __exit svm_exit(void)
2921 {
2922         kvm_exit();
2923 }
2924
2925 module_init(svm_init)
2926 module_exit(svm_exit)