2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
25 #include <linux/module.h>
26 #include <linux/mod_devicetable.h>
27 #include <linux/kernel.h>
28 #include <linux/vmalloc.h>
29 #include <linux/highmem.h>
30 #include <linux/sched.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
34 #include <asm/perf_event.h>
35 #include <asm/tlbflush.h>
37 #include <asm/debugreg.h>
38 #include <asm/kvm_para.h>
40 #include <asm/virtext.h>
43 #define __ex(x) __kvm_handle_fault_on_reboot(x)
45 MODULE_AUTHOR("Qumranet");
46 MODULE_LICENSE("GPL");
48 static const struct x86_cpu_id svm_cpu_id[] = {
49 X86_FEATURE_MATCH(X86_FEATURE_SVM),
52 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
54 #define IOPM_ALLOC_ORDER 2
55 #define MSRPM_ALLOC_ORDER 1
57 #define SEG_TYPE_LDT 2
58 #define SEG_TYPE_BUSY_TSS16 3
60 #define SVM_FEATURE_NPT (1 << 0)
61 #define SVM_FEATURE_LBRV (1 << 1)
62 #define SVM_FEATURE_SVML (1 << 2)
63 #define SVM_FEATURE_NRIP (1 << 3)
64 #define SVM_FEATURE_TSC_RATE (1 << 4)
65 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
66 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
67 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
68 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
70 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
71 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
72 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
74 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
76 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
77 #define TSC_RATIO_MIN 0x0000000000000001ULL
78 #define TSC_RATIO_MAX 0x000000ffffffffffULL
80 static bool erratum_383_found __read_mostly;
82 static const u32 host_save_user_msrs[] = {
84 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
87 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
90 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
100 /* These are the merged vectors */
103 /* gpa pointers to the real vectors */
107 /* A VMEXIT is required but not yet emulated */
110 /* cache for intercepts of the guest */
113 u32 intercept_exceptions;
116 /* Nested Paging related state */
120 #define MSRPM_OFFSETS 16
121 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
124 * Set osvw_len to higher value when updated Revision Guides
125 * are published and we know what the new status bits are
127 static uint64_t osvw_len = 4, osvw_status;
130 struct kvm_vcpu vcpu;
132 unsigned long vmcb_pa;
133 struct svm_cpu_data *svm_data;
134 uint64_t asid_generation;
135 uint64_t sysenter_esp;
136 uint64_t sysenter_eip;
140 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
152 struct nested_state nested;
156 unsigned int3_injected;
157 unsigned long int3_rip;
163 static DEFINE_PER_CPU(u64, current_tsc_ratio);
164 #define TSC_RATIO_DEFAULT 0x0100000000ULL
166 #define MSR_INVALID 0xffffffffU
168 static const struct svm_direct_access_msrs {
169 u32 index; /* Index of the MSR */
170 bool always; /* True if intercept is always on */
171 } direct_access_msrs[] = {
172 { .index = MSR_STAR, .always = true },
173 { .index = MSR_IA32_SYSENTER_CS, .always = true },
175 { .index = MSR_GS_BASE, .always = true },
176 { .index = MSR_FS_BASE, .always = true },
177 { .index = MSR_KERNEL_GS_BASE, .always = true },
178 { .index = MSR_LSTAR, .always = true },
179 { .index = MSR_CSTAR, .always = true },
180 { .index = MSR_SYSCALL_MASK, .always = true },
182 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
183 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
184 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
185 { .index = MSR_IA32_LASTINTTOIP, .always = false },
186 { .index = MSR_INVALID, .always = false },
189 /* enable NPT for AMD64 and X86 with PAE */
190 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
191 static bool npt_enabled = true;
193 static bool npt_enabled;
196 /* allow nested paging (virtualized MMU) for all guests */
197 static int npt = true;
198 module_param(npt, int, S_IRUGO);
200 /* allow nested virtualization in KVM/SVM */
201 static int nested = true;
202 module_param(nested, int, S_IRUGO);
204 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
205 static void svm_complete_interrupts(struct vcpu_svm *svm);
207 static int nested_svm_exit_handled(struct vcpu_svm *svm);
208 static int nested_svm_intercept(struct vcpu_svm *svm);
209 static int nested_svm_vmexit(struct vcpu_svm *svm);
210 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
211 bool has_error_code, u32 error_code);
212 static u64 __scale_tsc(u64 ratio, u64 tsc);
215 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
216 pause filter count */
217 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
218 VMCB_ASID, /* ASID */
219 VMCB_INTR, /* int_ctl, int_vector */
220 VMCB_NPT, /* npt_en, nCR3, gPAT */
221 VMCB_CR, /* CR0, CR3, CR4, EFER */
222 VMCB_DR, /* DR6, DR7 */
223 VMCB_DT, /* GDT, IDT */
224 VMCB_SEG, /* CS, DS, SS, ES, CPL */
225 VMCB_CR2, /* CR2 only */
226 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
230 /* TPR and CR2 are always written before VMRUN */
231 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
233 static inline void mark_all_dirty(struct vmcb *vmcb)
235 vmcb->control.clean = 0;
238 static inline void mark_all_clean(struct vmcb *vmcb)
240 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
241 & ~VMCB_ALWAYS_DIRTY_MASK;
244 static inline void mark_dirty(struct vmcb *vmcb, int bit)
246 vmcb->control.clean &= ~(1 << bit);
249 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
251 return container_of(vcpu, struct vcpu_svm, vcpu);
254 static void recalc_intercepts(struct vcpu_svm *svm)
256 struct vmcb_control_area *c, *h;
257 struct nested_state *g;
259 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
261 if (!is_guest_mode(&svm->vcpu))
264 c = &svm->vmcb->control;
265 h = &svm->nested.hsave->control;
268 c->intercept_cr = h->intercept_cr | g->intercept_cr;
269 c->intercept_dr = h->intercept_dr | g->intercept_dr;
270 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
271 c->intercept = h->intercept | g->intercept;
274 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
276 if (is_guest_mode(&svm->vcpu))
277 return svm->nested.hsave;
282 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
284 struct vmcb *vmcb = get_host_vmcb(svm);
286 vmcb->control.intercept_cr |= (1U << bit);
288 recalc_intercepts(svm);
291 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
293 struct vmcb *vmcb = get_host_vmcb(svm);
295 vmcb->control.intercept_cr &= ~(1U << bit);
297 recalc_intercepts(svm);
300 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
302 struct vmcb *vmcb = get_host_vmcb(svm);
304 return vmcb->control.intercept_cr & (1U << bit);
307 static inline void set_dr_intercepts(struct vcpu_svm *svm)
309 struct vmcb *vmcb = get_host_vmcb(svm);
311 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
312 | (1 << INTERCEPT_DR1_READ)
313 | (1 << INTERCEPT_DR2_READ)
314 | (1 << INTERCEPT_DR3_READ)
315 | (1 << INTERCEPT_DR4_READ)
316 | (1 << INTERCEPT_DR5_READ)
317 | (1 << INTERCEPT_DR6_READ)
318 | (1 << INTERCEPT_DR7_READ)
319 | (1 << INTERCEPT_DR0_WRITE)
320 | (1 << INTERCEPT_DR1_WRITE)
321 | (1 << INTERCEPT_DR2_WRITE)
322 | (1 << INTERCEPT_DR3_WRITE)
323 | (1 << INTERCEPT_DR4_WRITE)
324 | (1 << INTERCEPT_DR5_WRITE)
325 | (1 << INTERCEPT_DR6_WRITE)
326 | (1 << INTERCEPT_DR7_WRITE);
328 recalc_intercepts(svm);
331 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
333 struct vmcb *vmcb = get_host_vmcb(svm);
335 vmcb->control.intercept_dr = 0;
337 recalc_intercepts(svm);
340 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
342 struct vmcb *vmcb = get_host_vmcb(svm);
344 vmcb->control.intercept_exceptions |= (1U << bit);
346 recalc_intercepts(svm);
349 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
351 struct vmcb *vmcb = get_host_vmcb(svm);
353 vmcb->control.intercept_exceptions &= ~(1U << bit);
355 recalc_intercepts(svm);
358 static inline void set_intercept(struct vcpu_svm *svm, int bit)
360 struct vmcb *vmcb = get_host_vmcb(svm);
362 vmcb->control.intercept |= (1ULL << bit);
364 recalc_intercepts(svm);
367 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
369 struct vmcb *vmcb = get_host_vmcb(svm);
371 vmcb->control.intercept &= ~(1ULL << bit);
373 recalc_intercepts(svm);
376 static inline void enable_gif(struct vcpu_svm *svm)
378 svm->vcpu.arch.hflags |= HF_GIF_MASK;
381 static inline void disable_gif(struct vcpu_svm *svm)
383 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
386 static inline bool gif_set(struct vcpu_svm *svm)
388 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
391 static unsigned long iopm_base;
393 struct kvm_ldttss_desc {
396 unsigned base1:8, type:5, dpl:2, p:1;
397 unsigned limit1:4, zero0:3, g:1, base2:8;
400 } __attribute__((packed));
402 struct svm_cpu_data {
408 struct kvm_ldttss_desc *tss_desc;
410 struct page *save_area;
413 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
415 struct svm_init_data {
420 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
422 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
423 #define MSRS_RANGE_SIZE 2048
424 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
426 static u32 svm_msrpm_offset(u32 msr)
431 for (i = 0; i < NUM_MSR_MAPS; i++) {
432 if (msr < msrpm_ranges[i] ||
433 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
436 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
437 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
439 /* Now we have the u8 offset - but need the u32 offset */
443 /* MSR not in any range */
447 #define MAX_INST_SIZE 15
449 static inline void clgi(void)
451 asm volatile (__ex(SVM_CLGI));
454 static inline void stgi(void)
456 asm volatile (__ex(SVM_STGI));
459 static inline void invlpga(unsigned long addr, u32 asid)
461 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
464 static int get_npt_level(void)
467 return PT64_ROOT_LEVEL;
469 return PT32E_ROOT_LEVEL;
473 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
475 vcpu->arch.efer = efer;
476 if (!npt_enabled && !(efer & EFER_LMA))
479 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
480 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
483 static int is_external_interrupt(u32 info)
485 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
486 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
489 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
491 struct vcpu_svm *svm = to_svm(vcpu);
494 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
495 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
499 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
501 struct vcpu_svm *svm = to_svm(vcpu);
504 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
506 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
510 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
512 struct vcpu_svm *svm = to_svm(vcpu);
514 if (svm->vmcb->control.next_rip != 0)
515 svm->next_rip = svm->vmcb->control.next_rip;
517 if (!svm->next_rip) {
518 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
520 printk(KERN_DEBUG "%s: NOP\n", __func__);
523 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
524 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
525 __func__, kvm_rip_read(vcpu), svm->next_rip);
527 kvm_rip_write(vcpu, svm->next_rip);
528 svm_set_interrupt_shadow(vcpu, 0);
531 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
532 bool has_error_code, u32 error_code,
535 struct vcpu_svm *svm = to_svm(vcpu);
538 * If we are within a nested VM we'd better #VMEXIT and let the guest
539 * handle the exception
542 nested_svm_check_exception(svm, nr, has_error_code, error_code))
545 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
546 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
549 * For guest debugging where we have to reinject #BP if some
550 * INT3 is guest-owned:
551 * Emulate nRIP by moving RIP forward. Will fail if injection
552 * raises a fault that is not intercepted. Still better than
553 * failing in all cases.
555 skip_emulated_instruction(&svm->vcpu);
556 rip = kvm_rip_read(&svm->vcpu);
557 svm->int3_rip = rip + svm->vmcb->save.cs.base;
558 svm->int3_injected = rip - old_rip;
561 svm->vmcb->control.event_inj = nr
563 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
564 | SVM_EVTINJ_TYPE_EXEPT;
565 svm->vmcb->control.event_inj_err = error_code;
568 static void svm_init_erratum_383(void)
574 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
577 /* Use _safe variants to not break nested virtualization */
578 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
584 low = lower_32_bits(val);
585 high = upper_32_bits(val);
587 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
589 erratum_383_found = true;
592 static void svm_init_osvw(struct kvm_vcpu *vcpu)
595 * Guests should see errata 400 and 415 as fixed (assuming that
596 * HLT and IO instructions are intercepted).
598 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
599 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
602 * By increasing VCPU's osvw.length to 3 we are telling the guest that
603 * all osvw.status bits inside that length, including bit 0 (which is
604 * reserved for erratum 298), are valid. However, if host processor's
605 * osvw_len is 0 then osvw_status[0] carries no information. We need to
606 * be conservative here and therefore we tell the guest that erratum 298
607 * is present (because we really don't know).
609 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
610 vcpu->arch.osvw.status |= 1;
613 static int has_svm(void)
617 if (!cpu_has_svm(&msg)) {
618 printk(KERN_INFO "has_svm: %s\n", msg);
625 static void svm_hardware_disable(void)
627 /* Make sure we clean up behind us */
628 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
629 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
633 amd_pmu_disable_virt();
636 static int svm_hardware_enable(void)
639 struct svm_cpu_data *sd;
641 struct desc_ptr gdt_descr;
642 struct desc_struct *gdt;
643 int me = raw_smp_processor_id();
645 rdmsrl(MSR_EFER, efer);
646 if (efer & EFER_SVME)
650 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
653 sd = per_cpu(svm_data, me);
655 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
659 sd->asid_generation = 1;
660 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
661 sd->next_asid = sd->max_asid + 1;
663 native_store_gdt(&gdt_descr);
664 gdt = (struct desc_struct *)gdt_descr.address;
665 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
667 wrmsrl(MSR_EFER, efer | EFER_SVME);
669 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
671 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
672 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
673 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
680 * Note that it is possible to have a system with mixed processor
681 * revisions and therefore different OSVW bits. If bits are not the same
682 * on different processors then choose the worst case (i.e. if erratum
683 * is present on one processor and not on another then assume that the
684 * erratum is present everywhere).
686 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
687 uint64_t len, status = 0;
690 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
692 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
696 osvw_status = osvw_len = 0;
700 osvw_status |= status;
701 osvw_status &= (1ULL << osvw_len) - 1;
704 osvw_status = osvw_len = 0;
706 svm_init_erratum_383();
708 amd_pmu_enable_virt();
713 static void svm_cpu_uninit(int cpu)
715 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
720 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
721 __free_page(sd->save_area);
725 static int svm_cpu_init(int cpu)
727 struct svm_cpu_data *sd;
730 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
734 sd->save_area = alloc_page(GFP_KERNEL);
739 per_cpu(svm_data, cpu) = sd;
749 static bool valid_msr_intercept(u32 index)
753 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
754 if (direct_access_msrs[i].index == index)
760 static void set_msr_interception(u32 *msrpm, unsigned msr,
763 u8 bit_read, bit_write;
768 * If this warning triggers extend the direct_access_msrs list at the
769 * beginning of the file
771 WARN_ON(!valid_msr_intercept(msr));
773 offset = svm_msrpm_offset(msr);
774 bit_read = 2 * (msr & 0x0f);
775 bit_write = 2 * (msr & 0x0f) + 1;
778 BUG_ON(offset == MSR_INVALID);
780 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
781 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
786 static void svm_vcpu_init_msrpm(u32 *msrpm)
790 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
792 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
793 if (!direct_access_msrs[i].always)
796 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
800 static void add_msr_offset(u32 offset)
804 for (i = 0; i < MSRPM_OFFSETS; ++i) {
806 /* Offset already in list? */
807 if (msrpm_offsets[i] == offset)
810 /* Slot used by another offset? */
811 if (msrpm_offsets[i] != MSR_INVALID)
814 /* Add offset to list */
815 msrpm_offsets[i] = offset;
821 * If this BUG triggers the msrpm_offsets table has an overflow. Just
822 * increase MSRPM_OFFSETS in this case.
827 static void init_msrpm_offsets(void)
831 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
833 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
836 offset = svm_msrpm_offset(direct_access_msrs[i].index);
837 BUG_ON(offset == MSR_INVALID);
839 add_msr_offset(offset);
843 static void svm_enable_lbrv(struct vcpu_svm *svm)
845 u32 *msrpm = svm->msrpm;
847 svm->vmcb->control.lbr_ctl = 1;
848 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
849 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
850 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
851 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
854 static void svm_disable_lbrv(struct vcpu_svm *svm)
856 u32 *msrpm = svm->msrpm;
858 svm->vmcb->control.lbr_ctl = 0;
859 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
860 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
861 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
862 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
865 static __init int svm_hardware_setup(void)
868 struct page *iopm_pages;
872 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
877 iopm_va = page_address(iopm_pages);
878 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
879 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
881 init_msrpm_offsets();
883 if (boot_cpu_has(X86_FEATURE_NX))
884 kvm_enable_efer_bits(EFER_NX);
886 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
887 kvm_enable_efer_bits(EFER_FFXSR);
889 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
892 kvm_has_tsc_control = true;
895 * Make sure the user can only configure tsc_khz values that
896 * fit into a signed integer.
897 * A min value is not calculated needed because it will always
898 * be 1 on all machines and a value of 0 is used to disable
899 * tsc-scaling for the vcpu.
901 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
903 kvm_max_guest_tsc_khz = max;
907 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
908 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
911 for_each_possible_cpu(cpu) {
912 r = svm_cpu_init(cpu);
917 if (!boot_cpu_has(X86_FEATURE_NPT))
920 if (npt_enabled && !npt) {
921 printk(KERN_INFO "kvm: Nested Paging disabled\n");
926 printk(KERN_INFO "kvm: Nested Paging enabled\n");
934 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
939 static __exit void svm_hardware_unsetup(void)
943 for_each_possible_cpu(cpu)
946 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
950 static void init_seg(struct vmcb_seg *seg)
953 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
954 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
959 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
962 seg->attrib = SVM_SELECTOR_P_MASK | type;
967 static u64 __scale_tsc(u64 ratio, u64 tsc)
969 u64 mult, frac, _tsc;
972 frac = ratio & ((1ULL << 32) - 1);
976 _tsc += (tsc >> 32) * frac;
977 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
982 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
984 struct vcpu_svm *svm = to_svm(vcpu);
987 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
988 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
993 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
995 struct vcpu_svm *svm = to_svm(vcpu);
999 /* Guest TSC same frequency as host TSC? */
1001 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1005 /* TSC scaling supported? */
1006 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1007 if (user_tsc_khz > tsc_khz) {
1008 vcpu->arch.tsc_catchup = 1;
1009 vcpu->arch.tsc_always_catchup = 1;
1011 WARN(1, "user requested TSC rate below hardware speed\n");
1017 /* TSC scaling required - calculate ratio */
1019 do_div(ratio, tsc_khz);
1021 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1022 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1026 svm->tsc_ratio = ratio;
1029 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1031 struct vcpu_svm *svm = to_svm(vcpu);
1033 return svm->vmcb->control.tsc_offset;
1036 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1038 struct vcpu_svm *svm = to_svm(vcpu);
1039 u64 g_tsc_offset = 0;
1041 if (is_guest_mode(vcpu)) {
1042 g_tsc_offset = svm->vmcb->control.tsc_offset -
1043 svm->nested.hsave->control.tsc_offset;
1044 svm->nested.hsave->control.tsc_offset = offset;
1046 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1047 svm->vmcb->control.tsc_offset,
1050 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1052 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1055 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1057 struct vcpu_svm *svm = to_svm(vcpu);
1059 WARN_ON(adjustment < 0);
1061 adjustment = svm_scale_tsc(vcpu, adjustment);
1063 svm->vmcb->control.tsc_offset += adjustment;
1064 if (is_guest_mode(vcpu))
1065 svm->nested.hsave->control.tsc_offset += adjustment;
1067 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1068 svm->vmcb->control.tsc_offset - adjustment,
1069 svm->vmcb->control.tsc_offset);
1071 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1074 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1078 tsc = svm_scale_tsc(vcpu, native_read_tsc());
1080 return target_tsc - tsc;
1083 static void init_vmcb(struct vcpu_svm *svm)
1085 struct vmcb_control_area *control = &svm->vmcb->control;
1086 struct vmcb_save_area *save = &svm->vmcb->save;
1088 svm->vcpu.fpu_active = 1;
1089 svm->vcpu.arch.hflags = 0;
1091 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1092 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1093 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1094 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1095 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1096 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1097 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1099 set_dr_intercepts(svm);
1101 set_exception_intercept(svm, PF_VECTOR);
1102 set_exception_intercept(svm, UD_VECTOR);
1103 set_exception_intercept(svm, MC_VECTOR);
1105 set_intercept(svm, INTERCEPT_INTR);
1106 set_intercept(svm, INTERCEPT_NMI);
1107 set_intercept(svm, INTERCEPT_SMI);
1108 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1109 set_intercept(svm, INTERCEPT_RDPMC);
1110 set_intercept(svm, INTERCEPT_CPUID);
1111 set_intercept(svm, INTERCEPT_INVD);
1112 set_intercept(svm, INTERCEPT_HLT);
1113 set_intercept(svm, INTERCEPT_INVLPG);
1114 set_intercept(svm, INTERCEPT_INVLPGA);
1115 set_intercept(svm, INTERCEPT_IOIO_PROT);
1116 set_intercept(svm, INTERCEPT_MSR_PROT);
1117 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1118 set_intercept(svm, INTERCEPT_SHUTDOWN);
1119 set_intercept(svm, INTERCEPT_VMRUN);
1120 set_intercept(svm, INTERCEPT_VMMCALL);
1121 set_intercept(svm, INTERCEPT_VMLOAD);
1122 set_intercept(svm, INTERCEPT_VMSAVE);
1123 set_intercept(svm, INTERCEPT_STGI);
1124 set_intercept(svm, INTERCEPT_CLGI);
1125 set_intercept(svm, INTERCEPT_SKINIT);
1126 set_intercept(svm, INTERCEPT_WBINVD);
1127 set_intercept(svm, INTERCEPT_MONITOR);
1128 set_intercept(svm, INTERCEPT_MWAIT);
1129 set_intercept(svm, INTERCEPT_XSETBV);
1131 control->iopm_base_pa = iopm_base;
1132 control->msrpm_base_pa = __pa(svm->msrpm);
1133 control->int_ctl = V_INTR_MASKING_MASK;
1135 init_seg(&save->es);
1136 init_seg(&save->ss);
1137 init_seg(&save->ds);
1138 init_seg(&save->fs);
1139 init_seg(&save->gs);
1141 save->cs.selector = 0xf000;
1142 save->cs.base = 0xffff0000;
1143 /* Executable/Readable Code Segment */
1144 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1145 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1146 save->cs.limit = 0xffff;
1148 save->gdtr.limit = 0xffff;
1149 save->idtr.limit = 0xffff;
1151 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1152 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1154 svm_set_efer(&svm->vcpu, 0);
1155 save->dr6 = 0xffff0ff0;
1156 kvm_set_rflags(&svm->vcpu, 2);
1157 save->rip = 0x0000fff0;
1158 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1161 * This is the guest-visible cr0 value.
1162 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1164 svm->vcpu.arch.cr0 = 0;
1165 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1167 save->cr4 = X86_CR4_PAE;
1171 /* Setup VMCB for Nested Paging */
1172 control->nested_ctl = 1;
1173 clr_intercept(svm, INTERCEPT_INVLPG);
1174 clr_exception_intercept(svm, PF_VECTOR);
1175 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1176 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1177 save->g_pat = 0x0007040600070406ULL;
1181 svm->asid_generation = 0;
1183 svm->nested.vmcb = 0;
1184 svm->vcpu.arch.hflags = 0;
1186 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1187 control->pause_filter_count = 3000;
1188 set_intercept(svm, INTERCEPT_PAUSE);
1191 mark_all_dirty(svm->vmcb);
1196 static void svm_vcpu_reset(struct kvm_vcpu *vcpu)
1198 struct vcpu_svm *svm = to_svm(vcpu);
1204 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1205 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1208 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1210 struct vcpu_svm *svm;
1212 struct page *msrpm_pages;
1213 struct page *hsave_page;
1214 struct page *nested_msrpm_pages;
1217 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1223 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1225 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1230 page = alloc_page(GFP_KERNEL);
1234 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1238 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1239 if (!nested_msrpm_pages)
1242 hsave_page = alloc_page(GFP_KERNEL);
1246 svm->nested.hsave = page_address(hsave_page);
1248 svm->msrpm = page_address(msrpm_pages);
1249 svm_vcpu_init_msrpm(svm->msrpm);
1251 svm->nested.msrpm = page_address(nested_msrpm_pages);
1252 svm_vcpu_init_msrpm(svm->nested.msrpm);
1254 svm->vmcb = page_address(page);
1255 clear_page(svm->vmcb);
1256 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1257 svm->asid_generation = 0;
1260 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1261 if (kvm_vcpu_is_bsp(&svm->vcpu))
1262 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1264 svm_init_osvw(&svm->vcpu);
1269 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1271 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1275 kvm_vcpu_uninit(&svm->vcpu);
1277 kmem_cache_free(kvm_vcpu_cache, svm);
1279 return ERR_PTR(err);
1282 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1284 struct vcpu_svm *svm = to_svm(vcpu);
1286 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1287 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1288 __free_page(virt_to_page(svm->nested.hsave));
1289 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1290 kvm_vcpu_uninit(vcpu);
1291 kmem_cache_free(kvm_vcpu_cache, svm);
1294 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1296 struct vcpu_svm *svm = to_svm(vcpu);
1299 if (unlikely(cpu != vcpu->cpu)) {
1300 svm->asid_generation = 0;
1301 mark_all_dirty(svm->vmcb);
1304 #ifdef CONFIG_X86_64
1305 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1307 savesegment(fs, svm->host.fs);
1308 savesegment(gs, svm->host.gs);
1309 svm->host.ldt = kvm_read_ldt();
1311 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1312 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1314 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1315 svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1316 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1317 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1321 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1323 struct vcpu_svm *svm = to_svm(vcpu);
1326 ++vcpu->stat.host_state_reload;
1327 kvm_load_ldt(svm->host.ldt);
1328 #ifdef CONFIG_X86_64
1329 loadsegment(fs, svm->host.fs);
1330 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1331 load_gs_index(svm->host.gs);
1333 #ifdef CONFIG_X86_32_LAZY_GS
1334 loadsegment(gs, svm->host.gs);
1337 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1338 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1341 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1343 return to_svm(vcpu)->vmcb->save.rflags;
1346 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1349 * Any change of EFLAGS.VM is accompained by a reload of SS
1350 * (caused by either a task switch or an inter-privilege IRET),
1351 * so we do not need to update the CPL here.
1353 to_svm(vcpu)->vmcb->save.rflags = rflags;
1356 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1359 case VCPU_EXREG_PDPTR:
1360 BUG_ON(!npt_enabled);
1361 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1368 static void svm_set_vintr(struct vcpu_svm *svm)
1370 set_intercept(svm, INTERCEPT_VINTR);
1373 static void svm_clear_vintr(struct vcpu_svm *svm)
1375 clr_intercept(svm, INTERCEPT_VINTR);
1378 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1380 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1383 case VCPU_SREG_CS: return &save->cs;
1384 case VCPU_SREG_DS: return &save->ds;
1385 case VCPU_SREG_ES: return &save->es;
1386 case VCPU_SREG_FS: return &save->fs;
1387 case VCPU_SREG_GS: return &save->gs;
1388 case VCPU_SREG_SS: return &save->ss;
1389 case VCPU_SREG_TR: return &save->tr;
1390 case VCPU_SREG_LDTR: return &save->ldtr;
1396 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1398 struct vmcb_seg *s = svm_seg(vcpu, seg);
1403 static void svm_get_segment(struct kvm_vcpu *vcpu,
1404 struct kvm_segment *var, int seg)
1406 struct vmcb_seg *s = svm_seg(vcpu, seg);
1408 var->base = s->base;
1409 var->limit = s->limit;
1410 var->selector = s->selector;
1411 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1412 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1413 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1414 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1415 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1416 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1417 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1420 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1421 * However, the SVM spec states that the G bit is not observed by the
1422 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1423 * So let's synthesize a legal G bit for all segments, this helps
1424 * running KVM nested. It also helps cross-vendor migration, because
1425 * Intel's vmentry has a check on the 'G' bit.
1427 var->g = s->limit > 0xfffff;
1430 * AMD's VMCB does not have an explicit unusable field, so emulate it
1431 * for cross vendor migration purposes by "not present"
1433 var->unusable = !var->present || (var->type == 0);
1438 * Work around a bug where the busy flag in the tr selector
1448 * The accessed bit must always be set in the segment
1449 * descriptor cache, although it can be cleared in the
1450 * descriptor, the cached bit always remains at 1. Since
1451 * Intel has a check on this, set it here to support
1452 * cross-vendor migration.
1459 * On AMD CPUs sometimes the DB bit in the segment
1460 * descriptor is left as 1, although the whole segment has
1461 * been made unusable. Clear it here to pass an Intel VMX
1462 * entry check when cross vendor migrating.
1466 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1471 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1473 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1478 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1480 struct vcpu_svm *svm = to_svm(vcpu);
1482 dt->size = svm->vmcb->save.idtr.limit;
1483 dt->address = svm->vmcb->save.idtr.base;
1486 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1488 struct vcpu_svm *svm = to_svm(vcpu);
1490 svm->vmcb->save.idtr.limit = dt->size;
1491 svm->vmcb->save.idtr.base = dt->address ;
1492 mark_dirty(svm->vmcb, VMCB_DT);
1495 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1497 struct vcpu_svm *svm = to_svm(vcpu);
1499 dt->size = svm->vmcb->save.gdtr.limit;
1500 dt->address = svm->vmcb->save.gdtr.base;
1503 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1505 struct vcpu_svm *svm = to_svm(vcpu);
1507 svm->vmcb->save.gdtr.limit = dt->size;
1508 svm->vmcb->save.gdtr.base = dt->address ;
1509 mark_dirty(svm->vmcb, VMCB_DT);
1512 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1516 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1520 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1524 static void update_cr0_intercept(struct vcpu_svm *svm)
1526 ulong gcr0 = svm->vcpu.arch.cr0;
1527 u64 *hcr0 = &svm->vmcb->save.cr0;
1529 if (!svm->vcpu.fpu_active)
1530 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1532 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1533 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1535 mark_dirty(svm->vmcb, VMCB_CR);
1537 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1538 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1539 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1541 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1542 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1546 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1548 struct vcpu_svm *svm = to_svm(vcpu);
1550 #ifdef CONFIG_X86_64
1551 if (vcpu->arch.efer & EFER_LME) {
1552 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1553 vcpu->arch.efer |= EFER_LMA;
1554 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1557 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1558 vcpu->arch.efer &= ~EFER_LMA;
1559 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1563 vcpu->arch.cr0 = cr0;
1566 cr0 |= X86_CR0_PG | X86_CR0_WP;
1568 if (!vcpu->fpu_active)
1571 * re-enable caching here because the QEMU bios
1572 * does not do it - this results in some delay at
1575 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1576 svm->vmcb->save.cr0 = cr0;
1577 mark_dirty(svm->vmcb, VMCB_CR);
1578 update_cr0_intercept(svm);
1581 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1583 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1584 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1586 if (cr4 & X86_CR4_VMXE)
1589 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1590 svm_flush_tlb(vcpu);
1592 vcpu->arch.cr4 = cr4;
1595 cr4 |= host_cr4_mce;
1596 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1597 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1601 static void svm_set_segment(struct kvm_vcpu *vcpu,
1602 struct kvm_segment *var, int seg)
1604 struct vcpu_svm *svm = to_svm(vcpu);
1605 struct vmcb_seg *s = svm_seg(vcpu, seg);
1607 s->base = var->base;
1608 s->limit = var->limit;
1609 s->selector = var->selector;
1613 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1614 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1615 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1616 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1617 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1618 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1619 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1620 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1624 * This is always accurate, except if SYSRET returned to a segment
1625 * with SS.DPL != 3. Intel does not have this quirk, and always
1626 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1627 * would entail passing the CPL to userspace and back.
1629 if (seg == VCPU_SREG_SS)
1630 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1632 mark_dirty(svm->vmcb, VMCB_SEG);
1635 static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1637 struct vcpu_svm *svm = to_svm(vcpu);
1639 clr_exception_intercept(svm, DB_VECTOR);
1640 clr_exception_intercept(svm, BP_VECTOR);
1642 if (svm->nmi_singlestep)
1643 set_exception_intercept(svm, DB_VECTOR);
1645 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1646 if (vcpu->guest_debug &
1647 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1648 set_exception_intercept(svm, DB_VECTOR);
1649 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1650 set_exception_intercept(svm, BP_VECTOR);
1652 vcpu->guest_debug = 0;
1655 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1657 if (sd->next_asid > sd->max_asid) {
1658 ++sd->asid_generation;
1660 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1663 svm->asid_generation = sd->asid_generation;
1664 svm->vmcb->control.asid = sd->next_asid++;
1666 mark_dirty(svm->vmcb, VMCB_ASID);
1669 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1671 return to_svm(vcpu)->vmcb->save.dr6;
1674 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1676 struct vcpu_svm *svm = to_svm(vcpu);
1678 svm->vmcb->save.dr6 = value;
1679 mark_dirty(svm->vmcb, VMCB_DR);
1682 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1684 struct vcpu_svm *svm = to_svm(vcpu);
1686 get_debugreg(vcpu->arch.db[0], 0);
1687 get_debugreg(vcpu->arch.db[1], 1);
1688 get_debugreg(vcpu->arch.db[2], 2);
1689 get_debugreg(vcpu->arch.db[3], 3);
1690 vcpu->arch.dr6 = svm_get_dr6(vcpu);
1691 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1693 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1694 set_dr_intercepts(svm);
1697 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1699 struct vcpu_svm *svm = to_svm(vcpu);
1701 svm->vmcb->save.dr7 = value;
1702 mark_dirty(svm->vmcb, VMCB_DR);
1705 static int pf_interception(struct vcpu_svm *svm)
1707 u64 fault_address = svm->vmcb->control.exit_info_2;
1711 switch (svm->apf_reason) {
1713 error_code = svm->vmcb->control.exit_info_1;
1715 trace_kvm_page_fault(fault_address, error_code);
1716 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1717 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1718 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1719 svm->vmcb->control.insn_bytes,
1720 svm->vmcb->control.insn_len);
1722 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1723 svm->apf_reason = 0;
1724 local_irq_disable();
1725 kvm_async_pf_task_wait(fault_address);
1728 case KVM_PV_REASON_PAGE_READY:
1729 svm->apf_reason = 0;
1730 local_irq_disable();
1731 kvm_async_pf_task_wake(fault_address);
1738 static int db_interception(struct vcpu_svm *svm)
1740 struct kvm_run *kvm_run = svm->vcpu.run;
1742 if (!(svm->vcpu.guest_debug &
1743 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1744 !svm->nmi_singlestep) {
1745 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1749 if (svm->nmi_singlestep) {
1750 svm->nmi_singlestep = false;
1751 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1752 svm->vmcb->save.rflags &=
1753 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1754 update_db_bp_intercept(&svm->vcpu);
1757 if (svm->vcpu.guest_debug &
1758 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1759 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1760 kvm_run->debug.arch.pc =
1761 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1762 kvm_run->debug.arch.exception = DB_VECTOR;
1769 static int bp_interception(struct vcpu_svm *svm)
1771 struct kvm_run *kvm_run = svm->vcpu.run;
1773 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1774 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1775 kvm_run->debug.arch.exception = BP_VECTOR;
1779 static int ud_interception(struct vcpu_svm *svm)
1783 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1784 if (er != EMULATE_DONE)
1785 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1789 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1791 struct vcpu_svm *svm = to_svm(vcpu);
1793 clr_exception_intercept(svm, NM_VECTOR);
1795 svm->vcpu.fpu_active = 1;
1796 update_cr0_intercept(svm);
1799 static int nm_interception(struct vcpu_svm *svm)
1801 svm_fpu_activate(&svm->vcpu);
1805 static bool is_erratum_383(void)
1810 if (!erratum_383_found)
1813 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1817 /* Bit 62 may or may not be set for this mce */
1818 value &= ~(1ULL << 62);
1820 if (value != 0xb600000000010015ULL)
1823 /* Clear MCi_STATUS registers */
1824 for (i = 0; i < 6; ++i)
1825 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1827 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1831 value &= ~(1ULL << 2);
1832 low = lower_32_bits(value);
1833 high = upper_32_bits(value);
1835 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1838 /* Flush tlb to evict multi-match entries */
1844 static void svm_handle_mce(struct vcpu_svm *svm)
1846 if (is_erratum_383()) {
1848 * Erratum 383 triggered. Guest state is corrupt so kill the
1851 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1853 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1859 * On an #MC intercept the MCE handler is not called automatically in
1860 * the host. So do it by hand here.
1864 /* not sure if we ever come back to this point */
1869 static int mc_interception(struct vcpu_svm *svm)
1874 static int shutdown_interception(struct vcpu_svm *svm)
1876 struct kvm_run *kvm_run = svm->vcpu.run;
1879 * VMCB is undefined after a SHUTDOWN intercept
1880 * so reinitialize it.
1882 clear_page(svm->vmcb);
1885 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1889 static int io_interception(struct vcpu_svm *svm)
1891 struct kvm_vcpu *vcpu = &svm->vcpu;
1892 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1893 int size, in, string;
1896 ++svm->vcpu.stat.io_exits;
1897 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1898 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1900 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1902 port = io_info >> 16;
1903 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1904 svm->next_rip = svm->vmcb->control.exit_info_2;
1905 skip_emulated_instruction(&svm->vcpu);
1907 return kvm_fast_pio_out(vcpu, size, port);
1910 static int nmi_interception(struct vcpu_svm *svm)
1915 static int intr_interception(struct vcpu_svm *svm)
1917 ++svm->vcpu.stat.irq_exits;
1921 static int nop_on_interception(struct vcpu_svm *svm)
1926 static int halt_interception(struct vcpu_svm *svm)
1928 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1929 skip_emulated_instruction(&svm->vcpu);
1930 return kvm_emulate_halt(&svm->vcpu);
1933 static int vmmcall_interception(struct vcpu_svm *svm)
1935 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1936 skip_emulated_instruction(&svm->vcpu);
1937 kvm_emulate_hypercall(&svm->vcpu);
1941 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1943 struct vcpu_svm *svm = to_svm(vcpu);
1945 return svm->nested.nested_cr3;
1948 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1950 struct vcpu_svm *svm = to_svm(vcpu);
1951 u64 cr3 = svm->nested.nested_cr3;
1955 ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1956 offset_in_page(cr3) + index * 8, 8);
1962 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1965 struct vcpu_svm *svm = to_svm(vcpu);
1967 svm->vmcb->control.nested_cr3 = root;
1968 mark_dirty(svm->vmcb, VMCB_NPT);
1969 svm_flush_tlb(vcpu);
1972 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1973 struct x86_exception *fault)
1975 struct vcpu_svm *svm = to_svm(vcpu);
1977 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1978 svm->vmcb->control.exit_code_hi = 0;
1979 svm->vmcb->control.exit_info_1 = fault->error_code;
1980 svm->vmcb->control.exit_info_2 = fault->address;
1982 nested_svm_vmexit(svm);
1985 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1987 kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1989 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1990 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1991 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
1992 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1993 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1994 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1997 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1999 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2002 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2004 if (!(svm->vcpu.arch.efer & EFER_SVME)
2005 || !is_paging(&svm->vcpu)) {
2006 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2010 if (svm->vmcb->save.cpl) {
2011 kvm_inject_gp(&svm->vcpu, 0);
2018 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2019 bool has_error_code, u32 error_code)
2023 if (!is_guest_mode(&svm->vcpu))
2026 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2027 svm->vmcb->control.exit_code_hi = 0;
2028 svm->vmcb->control.exit_info_1 = error_code;
2029 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2031 vmexit = nested_svm_intercept(svm);
2032 if (vmexit == NESTED_EXIT_DONE)
2033 svm->nested.exit_required = true;
2038 /* This function returns true if it is save to enable the irq window */
2039 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2041 if (!is_guest_mode(&svm->vcpu))
2044 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2047 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2051 * if vmexit was already requested (by intercepted exception
2052 * for instance) do not overwrite it with "external interrupt"
2055 if (svm->nested.exit_required)
2058 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2059 svm->vmcb->control.exit_info_1 = 0;
2060 svm->vmcb->control.exit_info_2 = 0;
2062 if (svm->nested.intercept & 1ULL) {
2064 * The #vmexit can't be emulated here directly because this
2065 * code path runs with irqs and preemption disabled. A
2066 * #vmexit emulation might sleep. Only signal request for
2069 svm->nested.exit_required = true;
2070 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2077 /* This function returns true if it is save to enable the nmi window */
2078 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2080 if (!is_guest_mode(&svm->vcpu))
2083 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2086 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2087 svm->nested.exit_required = true;
2092 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2098 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2099 if (is_error_page(page))
2107 kvm_inject_gp(&svm->vcpu, 0);
2112 static void nested_svm_unmap(struct page *page)
2115 kvm_release_page_dirty(page);
2118 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2120 unsigned port, size, iopm_len;
2125 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2126 return NESTED_EXIT_HOST;
2128 port = svm->vmcb->control.exit_info_1 >> 16;
2129 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2130 SVM_IOIO_SIZE_SHIFT;
2131 gpa = svm->nested.vmcb_iopm + (port / 8);
2132 start_bit = port % 8;
2133 iopm_len = (start_bit + size > 8) ? 2 : 1;
2134 mask = (0xf >> (4 - size)) << start_bit;
2137 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, iopm_len))
2138 return NESTED_EXIT_DONE;
2140 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2143 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2145 u32 offset, msr, value;
2148 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2149 return NESTED_EXIT_HOST;
2151 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2152 offset = svm_msrpm_offset(msr);
2153 write = svm->vmcb->control.exit_info_1 & 1;
2154 mask = 1 << ((2 * (msr & 0xf)) + write);
2156 if (offset == MSR_INVALID)
2157 return NESTED_EXIT_DONE;
2159 /* Offset is in 32 bit units but need in 8 bit units */
2162 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2163 return NESTED_EXIT_DONE;
2165 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2168 static int nested_svm_exit_special(struct vcpu_svm *svm)
2170 u32 exit_code = svm->vmcb->control.exit_code;
2172 switch (exit_code) {
2175 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2176 return NESTED_EXIT_HOST;
2178 /* For now we are always handling NPFs when using them */
2180 return NESTED_EXIT_HOST;
2182 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2183 /* When we're shadowing, trap PFs, but not async PF */
2184 if (!npt_enabled && svm->apf_reason == 0)
2185 return NESTED_EXIT_HOST;
2187 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2188 nm_interception(svm);
2194 return NESTED_EXIT_CONTINUE;
2198 * If this function returns true, this #vmexit was already handled
2200 static int nested_svm_intercept(struct vcpu_svm *svm)
2202 u32 exit_code = svm->vmcb->control.exit_code;
2203 int vmexit = NESTED_EXIT_HOST;
2205 switch (exit_code) {
2207 vmexit = nested_svm_exit_handled_msr(svm);
2210 vmexit = nested_svm_intercept_ioio(svm);
2212 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2213 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2214 if (svm->nested.intercept_cr & bit)
2215 vmexit = NESTED_EXIT_DONE;
2218 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2219 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2220 if (svm->nested.intercept_dr & bit)
2221 vmexit = NESTED_EXIT_DONE;
2224 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2225 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2226 if (svm->nested.intercept_exceptions & excp_bits)
2227 vmexit = NESTED_EXIT_DONE;
2228 /* async page fault always cause vmexit */
2229 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2230 svm->apf_reason != 0)
2231 vmexit = NESTED_EXIT_DONE;
2234 case SVM_EXIT_ERR: {
2235 vmexit = NESTED_EXIT_DONE;
2239 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2240 if (svm->nested.intercept & exit_bits)
2241 vmexit = NESTED_EXIT_DONE;
2248 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2252 vmexit = nested_svm_intercept(svm);
2254 if (vmexit == NESTED_EXIT_DONE)
2255 nested_svm_vmexit(svm);
2260 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2262 struct vmcb_control_area *dst = &dst_vmcb->control;
2263 struct vmcb_control_area *from = &from_vmcb->control;
2265 dst->intercept_cr = from->intercept_cr;
2266 dst->intercept_dr = from->intercept_dr;
2267 dst->intercept_exceptions = from->intercept_exceptions;
2268 dst->intercept = from->intercept;
2269 dst->iopm_base_pa = from->iopm_base_pa;
2270 dst->msrpm_base_pa = from->msrpm_base_pa;
2271 dst->tsc_offset = from->tsc_offset;
2272 dst->asid = from->asid;
2273 dst->tlb_ctl = from->tlb_ctl;
2274 dst->int_ctl = from->int_ctl;
2275 dst->int_vector = from->int_vector;
2276 dst->int_state = from->int_state;
2277 dst->exit_code = from->exit_code;
2278 dst->exit_code_hi = from->exit_code_hi;
2279 dst->exit_info_1 = from->exit_info_1;
2280 dst->exit_info_2 = from->exit_info_2;
2281 dst->exit_int_info = from->exit_int_info;
2282 dst->exit_int_info_err = from->exit_int_info_err;
2283 dst->nested_ctl = from->nested_ctl;
2284 dst->event_inj = from->event_inj;
2285 dst->event_inj_err = from->event_inj_err;
2286 dst->nested_cr3 = from->nested_cr3;
2287 dst->lbr_ctl = from->lbr_ctl;
2290 static int nested_svm_vmexit(struct vcpu_svm *svm)
2292 struct vmcb *nested_vmcb;
2293 struct vmcb *hsave = svm->nested.hsave;
2294 struct vmcb *vmcb = svm->vmcb;
2297 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2298 vmcb->control.exit_info_1,
2299 vmcb->control.exit_info_2,
2300 vmcb->control.exit_int_info,
2301 vmcb->control.exit_int_info_err,
2304 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2308 /* Exit Guest-Mode */
2309 leave_guest_mode(&svm->vcpu);
2310 svm->nested.vmcb = 0;
2312 /* Give the current vmcb to the guest */
2315 nested_vmcb->save.es = vmcb->save.es;
2316 nested_vmcb->save.cs = vmcb->save.cs;
2317 nested_vmcb->save.ss = vmcb->save.ss;
2318 nested_vmcb->save.ds = vmcb->save.ds;
2319 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2320 nested_vmcb->save.idtr = vmcb->save.idtr;
2321 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2322 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2323 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2324 nested_vmcb->save.cr2 = vmcb->save.cr2;
2325 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2326 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2327 nested_vmcb->save.rip = vmcb->save.rip;
2328 nested_vmcb->save.rsp = vmcb->save.rsp;
2329 nested_vmcb->save.rax = vmcb->save.rax;
2330 nested_vmcb->save.dr7 = vmcb->save.dr7;
2331 nested_vmcb->save.dr6 = vmcb->save.dr6;
2332 nested_vmcb->save.cpl = vmcb->save.cpl;
2334 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2335 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2336 nested_vmcb->control.int_state = vmcb->control.int_state;
2337 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2338 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2339 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2340 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2341 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2342 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2343 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2346 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2347 * to make sure that we do not lose injected events. So check event_inj
2348 * here and copy it to exit_int_info if it is valid.
2349 * Exit_int_info and event_inj can't be both valid because the case
2350 * below only happens on a VMRUN instruction intercept which has
2351 * no valid exit_int_info set.
2353 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2354 struct vmcb_control_area *nc = &nested_vmcb->control;
2356 nc->exit_int_info = vmcb->control.event_inj;
2357 nc->exit_int_info_err = vmcb->control.event_inj_err;
2360 nested_vmcb->control.tlb_ctl = 0;
2361 nested_vmcb->control.event_inj = 0;
2362 nested_vmcb->control.event_inj_err = 0;
2364 /* We always set V_INTR_MASKING and remember the old value in hflags */
2365 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2366 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2368 /* Restore the original control entries */
2369 copy_vmcb_control_area(vmcb, hsave);
2371 kvm_clear_exception_queue(&svm->vcpu);
2372 kvm_clear_interrupt_queue(&svm->vcpu);
2374 svm->nested.nested_cr3 = 0;
2376 /* Restore selected save entries */
2377 svm->vmcb->save.es = hsave->save.es;
2378 svm->vmcb->save.cs = hsave->save.cs;
2379 svm->vmcb->save.ss = hsave->save.ss;
2380 svm->vmcb->save.ds = hsave->save.ds;
2381 svm->vmcb->save.gdtr = hsave->save.gdtr;
2382 svm->vmcb->save.idtr = hsave->save.idtr;
2383 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2384 svm_set_efer(&svm->vcpu, hsave->save.efer);
2385 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2386 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2388 svm->vmcb->save.cr3 = hsave->save.cr3;
2389 svm->vcpu.arch.cr3 = hsave->save.cr3;
2391 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2393 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2394 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2395 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2396 svm->vmcb->save.dr7 = 0;
2397 svm->vmcb->save.cpl = 0;
2398 svm->vmcb->control.exit_int_info = 0;
2400 mark_all_dirty(svm->vmcb);
2402 nested_svm_unmap(page);
2404 nested_svm_uninit_mmu_context(&svm->vcpu);
2405 kvm_mmu_reset_context(&svm->vcpu);
2406 kvm_mmu_load(&svm->vcpu);
2411 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2414 * This function merges the msr permission bitmaps of kvm and the
2415 * nested vmcb. It is optimized in that it only merges the parts where
2416 * the kvm msr permission bitmap may contain zero bits
2420 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2423 for (i = 0; i < MSRPM_OFFSETS; i++) {
2427 if (msrpm_offsets[i] == 0xffffffff)
2430 p = msrpm_offsets[i];
2431 offset = svm->nested.vmcb_msrpm + (p * 4);
2433 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2436 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2439 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2444 static bool nested_vmcb_checks(struct vmcb *vmcb)
2446 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2449 if (vmcb->control.asid == 0)
2452 if (vmcb->control.nested_ctl && !npt_enabled)
2458 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2460 struct vmcb *nested_vmcb;
2461 struct vmcb *hsave = svm->nested.hsave;
2462 struct vmcb *vmcb = svm->vmcb;
2466 vmcb_gpa = svm->vmcb->save.rax;
2468 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2472 if (!nested_vmcb_checks(nested_vmcb)) {
2473 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2474 nested_vmcb->control.exit_code_hi = 0;
2475 nested_vmcb->control.exit_info_1 = 0;
2476 nested_vmcb->control.exit_info_2 = 0;
2478 nested_svm_unmap(page);
2483 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2484 nested_vmcb->save.rip,
2485 nested_vmcb->control.int_ctl,
2486 nested_vmcb->control.event_inj,
2487 nested_vmcb->control.nested_ctl);
2489 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2490 nested_vmcb->control.intercept_cr >> 16,
2491 nested_vmcb->control.intercept_exceptions,
2492 nested_vmcb->control.intercept);
2494 /* Clear internal status */
2495 kvm_clear_exception_queue(&svm->vcpu);
2496 kvm_clear_interrupt_queue(&svm->vcpu);
2499 * Save the old vmcb, so we don't need to pick what we save, but can
2500 * restore everything when a VMEXIT occurs
2502 hsave->save.es = vmcb->save.es;
2503 hsave->save.cs = vmcb->save.cs;
2504 hsave->save.ss = vmcb->save.ss;
2505 hsave->save.ds = vmcb->save.ds;
2506 hsave->save.gdtr = vmcb->save.gdtr;
2507 hsave->save.idtr = vmcb->save.idtr;
2508 hsave->save.efer = svm->vcpu.arch.efer;
2509 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2510 hsave->save.cr4 = svm->vcpu.arch.cr4;
2511 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2512 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2513 hsave->save.rsp = vmcb->save.rsp;
2514 hsave->save.rax = vmcb->save.rax;
2516 hsave->save.cr3 = vmcb->save.cr3;
2518 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2520 copy_vmcb_control_area(hsave, vmcb);
2522 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2523 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2525 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2527 if (nested_vmcb->control.nested_ctl) {
2528 kvm_mmu_unload(&svm->vcpu);
2529 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2530 nested_svm_init_mmu_context(&svm->vcpu);
2533 /* Load the nested guest state */
2534 svm->vmcb->save.es = nested_vmcb->save.es;
2535 svm->vmcb->save.cs = nested_vmcb->save.cs;
2536 svm->vmcb->save.ss = nested_vmcb->save.ss;
2537 svm->vmcb->save.ds = nested_vmcb->save.ds;
2538 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2539 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2540 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2541 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2542 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2543 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2545 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2546 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2548 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2550 /* Guest paging mode is active - reset mmu */
2551 kvm_mmu_reset_context(&svm->vcpu);
2553 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2554 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2555 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2556 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2558 /* In case we don't even reach vcpu_run, the fields are not updated */
2559 svm->vmcb->save.rax = nested_vmcb->save.rax;
2560 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2561 svm->vmcb->save.rip = nested_vmcb->save.rip;
2562 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2563 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2564 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2566 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2567 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2569 /* cache intercepts */
2570 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2571 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2572 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2573 svm->nested.intercept = nested_vmcb->control.intercept;
2575 svm_flush_tlb(&svm->vcpu);
2576 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2577 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2578 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2580 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2582 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2583 /* We only want the cr8 intercept bits of the guest */
2584 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2585 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2588 /* We don't want to see VMMCALLs from a nested guest */
2589 clr_intercept(svm, INTERCEPT_VMMCALL);
2591 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2592 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2593 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2594 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2595 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2596 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2598 nested_svm_unmap(page);
2600 /* Enter Guest-Mode */
2601 enter_guest_mode(&svm->vcpu);
2604 * Merge guest and host intercepts - must be called with vcpu in
2605 * guest-mode to take affect here
2607 recalc_intercepts(svm);
2609 svm->nested.vmcb = vmcb_gpa;
2613 mark_all_dirty(svm->vmcb);
2618 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2620 to_vmcb->save.fs = from_vmcb->save.fs;
2621 to_vmcb->save.gs = from_vmcb->save.gs;
2622 to_vmcb->save.tr = from_vmcb->save.tr;
2623 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2624 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2625 to_vmcb->save.star = from_vmcb->save.star;
2626 to_vmcb->save.lstar = from_vmcb->save.lstar;
2627 to_vmcb->save.cstar = from_vmcb->save.cstar;
2628 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2629 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2630 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2631 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2634 static int vmload_interception(struct vcpu_svm *svm)
2636 struct vmcb *nested_vmcb;
2639 if (nested_svm_check_permissions(svm))
2642 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2646 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2647 skip_emulated_instruction(&svm->vcpu);
2649 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2650 nested_svm_unmap(page);
2655 static int vmsave_interception(struct vcpu_svm *svm)
2657 struct vmcb *nested_vmcb;
2660 if (nested_svm_check_permissions(svm))
2663 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2667 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2668 skip_emulated_instruction(&svm->vcpu);
2670 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2671 nested_svm_unmap(page);
2676 static int vmrun_interception(struct vcpu_svm *svm)
2678 if (nested_svm_check_permissions(svm))
2681 /* Save rip after vmrun instruction */
2682 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2684 if (!nested_svm_vmrun(svm))
2687 if (!nested_svm_vmrun_msrpm(svm))
2694 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2695 svm->vmcb->control.exit_code_hi = 0;
2696 svm->vmcb->control.exit_info_1 = 0;
2697 svm->vmcb->control.exit_info_2 = 0;
2699 nested_svm_vmexit(svm);
2704 static int stgi_interception(struct vcpu_svm *svm)
2706 if (nested_svm_check_permissions(svm))
2709 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2710 skip_emulated_instruction(&svm->vcpu);
2711 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2718 static int clgi_interception(struct vcpu_svm *svm)
2720 if (nested_svm_check_permissions(svm))
2723 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2724 skip_emulated_instruction(&svm->vcpu);
2728 /* After a CLGI no interrupts should come */
2729 svm_clear_vintr(svm);
2730 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2732 mark_dirty(svm->vmcb, VMCB_INTR);
2737 static int invlpga_interception(struct vcpu_svm *svm)
2739 struct kvm_vcpu *vcpu = &svm->vcpu;
2741 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2742 vcpu->arch.regs[VCPU_REGS_RAX]);
2744 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2745 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2747 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2748 skip_emulated_instruction(&svm->vcpu);
2752 static int skinit_interception(struct vcpu_svm *svm)
2754 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2756 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2760 static int xsetbv_interception(struct vcpu_svm *svm)
2762 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2763 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2765 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2766 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2767 skip_emulated_instruction(&svm->vcpu);
2773 static int task_switch_interception(struct vcpu_svm *svm)
2777 int int_type = svm->vmcb->control.exit_int_info &
2778 SVM_EXITINTINFO_TYPE_MASK;
2779 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2781 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2783 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2784 bool has_error_code = false;
2787 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2789 if (svm->vmcb->control.exit_info_2 &
2790 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2791 reason = TASK_SWITCH_IRET;
2792 else if (svm->vmcb->control.exit_info_2 &
2793 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2794 reason = TASK_SWITCH_JMP;
2796 reason = TASK_SWITCH_GATE;
2798 reason = TASK_SWITCH_CALL;
2800 if (reason == TASK_SWITCH_GATE) {
2802 case SVM_EXITINTINFO_TYPE_NMI:
2803 svm->vcpu.arch.nmi_injected = false;
2805 case SVM_EXITINTINFO_TYPE_EXEPT:
2806 if (svm->vmcb->control.exit_info_2 &
2807 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2808 has_error_code = true;
2810 (u32)svm->vmcb->control.exit_info_2;
2812 kvm_clear_exception_queue(&svm->vcpu);
2814 case SVM_EXITINTINFO_TYPE_INTR:
2815 kvm_clear_interrupt_queue(&svm->vcpu);
2822 if (reason != TASK_SWITCH_GATE ||
2823 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2824 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2825 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2826 skip_emulated_instruction(&svm->vcpu);
2828 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2831 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2832 has_error_code, error_code) == EMULATE_FAIL) {
2833 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2834 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2835 svm->vcpu.run->internal.ndata = 0;
2841 static int cpuid_interception(struct vcpu_svm *svm)
2843 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2844 kvm_emulate_cpuid(&svm->vcpu);
2848 static int iret_interception(struct vcpu_svm *svm)
2850 ++svm->vcpu.stat.nmi_window_exits;
2851 clr_intercept(svm, INTERCEPT_IRET);
2852 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2853 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2854 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2858 static int invlpg_interception(struct vcpu_svm *svm)
2860 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2861 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2863 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2864 skip_emulated_instruction(&svm->vcpu);
2868 static int emulate_on_interception(struct vcpu_svm *svm)
2870 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2873 static int rdpmc_interception(struct vcpu_svm *svm)
2877 if (!static_cpu_has(X86_FEATURE_NRIPS))
2878 return emulate_on_interception(svm);
2880 err = kvm_rdpmc(&svm->vcpu);
2881 kvm_complete_insn_gp(&svm->vcpu, err);
2886 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2888 unsigned long cr0 = svm->vcpu.arch.cr0;
2892 intercept = svm->nested.intercept;
2894 if (!is_guest_mode(&svm->vcpu) ||
2895 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2898 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2899 val &= ~SVM_CR0_SELECTIVE_MASK;
2902 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2903 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2909 #define CR_VALID (1ULL << 63)
2911 static int cr_interception(struct vcpu_svm *svm)
2917 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2918 return emulate_on_interception(svm);
2920 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2921 return emulate_on_interception(svm);
2923 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2924 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2927 if (cr >= 16) { /* mov to cr */
2929 val = kvm_register_read(&svm->vcpu, reg);
2932 if (!check_selective_cr0_intercepted(svm, val))
2933 err = kvm_set_cr0(&svm->vcpu, val);
2939 err = kvm_set_cr3(&svm->vcpu, val);
2942 err = kvm_set_cr4(&svm->vcpu, val);
2945 err = kvm_set_cr8(&svm->vcpu, val);
2948 WARN(1, "unhandled write to CR%d", cr);
2949 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2952 } else { /* mov from cr */
2955 val = kvm_read_cr0(&svm->vcpu);
2958 val = svm->vcpu.arch.cr2;
2961 val = kvm_read_cr3(&svm->vcpu);
2964 val = kvm_read_cr4(&svm->vcpu);
2967 val = kvm_get_cr8(&svm->vcpu);
2970 WARN(1, "unhandled read from CR%d", cr);
2971 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2974 kvm_register_write(&svm->vcpu, reg, val);
2976 kvm_complete_insn_gp(&svm->vcpu, err);
2981 static int dr_interception(struct vcpu_svm *svm)
2987 if (svm->vcpu.guest_debug == 0) {
2989 * No more DR vmexits; force a reload of the debug registers
2990 * and reenter on this instruction. The next vmexit will
2991 * retrieve the full state of the debug registers.
2993 clr_dr_intercepts(svm);
2994 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2998 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2999 return emulate_on_interception(svm);
3001 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3002 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3004 if (dr >= 16) { /* mov to DRn */
3005 val = kvm_register_read(&svm->vcpu, reg);
3006 kvm_set_dr(&svm->vcpu, dr - 16, val);
3008 err = kvm_get_dr(&svm->vcpu, dr, &val);
3010 kvm_register_write(&svm->vcpu, reg, val);
3013 skip_emulated_instruction(&svm->vcpu);
3018 static int cr8_write_interception(struct vcpu_svm *svm)
3020 struct kvm_run *kvm_run = svm->vcpu.run;
3023 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3024 /* instruction emulation calls kvm_set_cr8() */
3025 r = cr_interception(svm);
3026 if (irqchip_in_kernel(svm->vcpu.kvm))
3028 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3030 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3034 static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3036 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3037 return vmcb->control.tsc_offset +
3038 svm_scale_tsc(vcpu, host_tsc);
3041 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
3043 struct vcpu_svm *svm = to_svm(vcpu);
3046 case MSR_IA32_TSC: {
3047 *data = svm->vmcb->control.tsc_offset +
3048 svm_scale_tsc(vcpu, native_read_tsc());
3053 *data = svm->vmcb->save.star;
3055 #ifdef CONFIG_X86_64
3057 *data = svm->vmcb->save.lstar;
3060 *data = svm->vmcb->save.cstar;
3062 case MSR_KERNEL_GS_BASE:
3063 *data = svm->vmcb->save.kernel_gs_base;
3065 case MSR_SYSCALL_MASK:
3066 *data = svm->vmcb->save.sfmask;
3069 case MSR_IA32_SYSENTER_CS:
3070 *data = svm->vmcb->save.sysenter_cs;
3072 case MSR_IA32_SYSENTER_EIP:
3073 *data = svm->sysenter_eip;
3075 case MSR_IA32_SYSENTER_ESP:
3076 *data = svm->sysenter_esp;
3079 * Nobody will change the following 5 values in the VMCB so we can
3080 * safely return them on rdmsr. They will always be 0 until LBRV is
3083 case MSR_IA32_DEBUGCTLMSR:
3084 *data = svm->vmcb->save.dbgctl;
3086 case MSR_IA32_LASTBRANCHFROMIP:
3087 *data = svm->vmcb->save.br_from;
3089 case MSR_IA32_LASTBRANCHTOIP:
3090 *data = svm->vmcb->save.br_to;
3092 case MSR_IA32_LASTINTFROMIP:
3093 *data = svm->vmcb->save.last_excp_from;
3095 case MSR_IA32_LASTINTTOIP:
3096 *data = svm->vmcb->save.last_excp_to;
3098 case MSR_VM_HSAVE_PA:
3099 *data = svm->nested.hsave_msr;
3102 *data = svm->nested.vm_cr_msr;
3104 case MSR_IA32_UCODE_REV:
3108 return kvm_get_msr_common(vcpu, ecx, data);
3113 static int rdmsr_interception(struct vcpu_svm *svm)
3115 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3118 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3119 trace_kvm_msr_read_ex(ecx);
3120 kvm_inject_gp(&svm->vcpu, 0);
3122 trace_kvm_msr_read(ecx, data);
3124 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3125 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3126 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3127 skip_emulated_instruction(&svm->vcpu);
3132 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3134 struct vcpu_svm *svm = to_svm(vcpu);
3135 int svm_dis, chg_mask;
3137 if (data & ~SVM_VM_CR_VALID_MASK)
3140 chg_mask = SVM_VM_CR_VALID_MASK;
3142 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3143 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3145 svm->nested.vm_cr_msr &= ~chg_mask;
3146 svm->nested.vm_cr_msr |= (data & chg_mask);
3148 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3150 /* check for svm_disable while efer.svme is set */
3151 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3157 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3159 struct vcpu_svm *svm = to_svm(vcpu);
3161 u32 ecx = msr->index;
3162 u64 data = msr->data;
3165 kvm_write_tsc(vcpu, msr);
3168 svm->vmcb->save.star = data;
3170 #ifdef CONFIG_X86_64
3172 svm->vmcb->save.lstar = data;
3175 svm->vmcb->save.cstar = data;
3177 case MSR_KERNEL_GS_BASE:
3178 svm->vmcb->save.kernel_gs_base = data;
3180 case MSR_SYSCALL_MASK:
3181 svm->vmcb->save.sfmask = data;
3184 case MSR_IA32_SYSENTER_CS:
3185 svm->vmcb->save.sysenter_cs = data;
3187 case MSR_IA32_SYSENTER_EIP:
3188 svm->sysenter_eip = data;
3189 svm->vmcb->save.sysenter_eip = data;
3191 case MSR_IA32_SYSENTER_ESP:
3192 svm->sysenter_esp = data;
3193 svm->vmcb->save.sysenter_esp = data;
3195 case MSR_IA32_DEBUGCTLMSR:
3196 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3197 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3201 if (data & DEBUGCTL_RESERVED_BITS)
3204 svm->vmcb->save.dbgctl = data;
3205 mark_dirty(svm->vmcb, VMCB_LBR);
3206 if (data & (1ULL<<0))
3207 svm_enable_lbrv(svm);
3209 svm_disable_lbrv(svm);
3211 case MSR_VM_HSAVE_PA:
3212 svm->nested.hsave_msr = data;
3215 return svm_set_vm_cr(vcpu, data);
3217 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3220 return kvm_set_msr_common(vcpu, msr);
3225 static int wrmsr_interception(struct vcpu_svm *svm)
3227 struct msr_data msr;
3228 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3229 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3230 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3234 msr.host_initiated = false;
3236 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3237 if (svm_set_msr(&svm->vcpu, &msr)) {
3238 trace_kvm_msr_write_ex(ecx, data);
3239 kvm_inject_gp(&svm->vcpu, 0);
3241 trace_kvm_msr_write(ecx, data);
3242 skip_emulated_instruction(&svm->vcpu);
3247 static int msr_interception(struct vcpu_svm *svm)
3249 if (svm->vmcb->control.exit_info_1)
3250 return wrmsr_interception(svm);
3252 return rdmsr_interception(svm);
3255 static int interrupt_window_interception(struct vcpu_svm *svm)
3257 struct kvm_run *kvm_run = svm->vcpu.run;
3259 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3260 svm_clear_vintr(svm);
3261 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3262 mark_dirty(svm->vmcb, VMCB_INTR);
3263 ++svm->vcpu.stat.irq_window_exits;
3265 * If the user space waits to inject interrupts, exit as soon as
3268 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3269 kvm_run->request_interrupt_window &&
3270 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3271 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3278 static int pause_interception(struct vcpu_svm *svm)
3280 kvm_vcpu_on_spin(&(svm->vcpu));
3284 static int nop_interception(struct vcpu_svm *svm)
3286 skip_emulated_instruction(&(svm->vcpu));
3290 static int monitor_interception(struct vcpu_svm *svm)
3292 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3293 return nop_interception(svm);
3296 static int mwait_interception(struct vcpu_svm *svm)
3298 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3299 return nop_interception(svm);
3302 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3303 [SVM_EXIT_READ_CR0] = cr_interception,
3304 [SVM_EXIT_READ_CR3] = cr_interception,
3305 [SVM_EXIT_READ_CR4] = cr_interception,
3306 [SVM_EXIT_READ_CR8] = cr_interception,
3307 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
3308 [SVM_EXIT_WRITE_CR0] = cr_interception,
3309 [SVM_EXIT_WRITE_CR3] = cr_interception,
3310 [SVM_EXIT_WRITE_CR4] = cr_interception,
3311 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3312 [SVM_EXIT_READ_DR0] = dr_interception,
3313 [SVM_EXIT_READ_DR1] = dr_interception,
3314 [SVM_EXIT_READ_DR2] = dr_interception,
3315 [SVM_EXIT_READ_DR3] = dr_interception,
3316 [SVM_EXIT_READ_DR4] = dr_interception,
3317 [SVM_EXIT_READ_DR5] = dr_interception,
3318 [SVM_EXIT_READ_DR6] = dr_interception,
3319 [SVM_EXIT_READ_DR7] = dr_interception,
3320 [SVM_EXIT_WRITE_DR0] = dr_interception,
3321 [SVM_EXIT_WRITE_DR1] = dr_interception,
3322 [SVM_EXIT_WRITE_DR2] = dr_interception,
3323 [SVM_EXIT_WRITE_DR3] = dr_interception,
3324 [SVM_EXIT_WRITE_DR4] = dr_interception,
3325 [SVM_EXIT_WRITE_DR5] = dr_interception,
3326 [SVM_EXIT_WRITE_DR6] = dr_interception,
3327 [SVM_EXIT_WRITE_DR7] = dr_interception,
3328 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3329 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3330 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3331 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3332 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3333 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3334 [SVM_EXIT_INTR] = intr_interception,
3335 [SVM_EXIT_NMI] = nmi_interception,
3336 [SVM_EXIT_SMI] = nop_on_interception,
3337 [SVM_EXIT_INIT] = nop_on_interception,
3338 [SVM_EXIT_VINTR] = interrupt_window_interception,
3339 [SVM_EXIT_RDPMC] = rdpmc_interception,
3340 [SVM_EXIT_CPUID] = cpuid_interception,
3341 [SVM_EXIT_IRET] = iret_interception,
3342 [SVM_EXIT_INVD] = emulate_on_interception,
3343 [SVM_EXIT_PAUSE] = pause_interception,
3344 [SVM_EXIT_HLT] = halt_interception,
3345 [SVM_EXIT_INVLPG] = invlpg_interception,
3346 [SVM_EXIT_INVLPGA] = invlpga_interception,
3347 [SVM_EXIT_IOIO] = io_interception,
3348 [SVM_EXIT_MSR] = msr_interception,
3349 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3350 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3351 [SVM_EXIT_VMRUN] = vmrun_interception,
3352 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3353 [SVM_EXIT_VMLOAD] = vmload_interception,
3354 [SVM_EXIT_VMSAVE] = vmsave_interception,
3355 [SVM_EXIT_STGI] = stgi_interception,
3356 [SVM_EXIT_CLGI] = clgi_interception,
3357 [SVM_EXIT_SKINIT] = skinit_interception,
3358 [SVM_EXIT_WBINVD] = emulate_on_interception,
3359 [SVM_EXIT_MONITOR] = monitor_interception,
3360 [SVM_EXIT_MWAIT] = mwait_interception,
3361 [SVM_EXIT_XSETBV] = xsetbv_interception,
3362 [SVM_EXIT_NPF] = pf_interception,
3365 static void dump_vmcb(struct kvm_vcpu *vcpu)
3367 struct vcpu_svm *svm = to_svm(vcpu);
3368 struct vmcb_control_area *control = &svm->vmcb->control;
3369 struct vmcb_save_area *save = &svm->vmcb->save;
3371 pr_err("VMCB Control Area:\n");
3372 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3373 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3374 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3375 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3376 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3377 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3378 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3379 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3380 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3381 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3382 pr_err("%-20s%d\n", "asid:", control->asid);
3383 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3384 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3385 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3386 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3387 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3388 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3389 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3390 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3391 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3392 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3393 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3394 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3395 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3396 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3397 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3398 pr_err("VMCB State Save Area:\n");
3399 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3401 save->es.selector, save->es.attrib,
3402 save->es.limit, save->es.base);
3403 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3405 save->cs.selector, save->cs.attrib,
3406 save->cs.limit, save->cs.base);
3407 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3409 save->ss.selector, save->ss.attrib,
3410 save->ss.limit, save->ss.base);
3411 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3413 save->ds.selector, save->ds.attrib,
3414 save->ds.limit, save->ds.base);
3415 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3417 save->fs.selector, save->fs.attrib,
3418 save->fs.limit, save->fs.base);
3419 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3421 save->gs.selector, save->gs.attrib,
3422 save->gs.limit, save->gs.base);
3423 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3425 save->gdtr.selector, save->gdtr.attrib,
3426 save->gdtr.limit, save->gdtr.base);
3427 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3429 save->ldtr.selector, save->ldtr.attrib,
3430 save->ldtr.limit, save->ldtr.base);
3431 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3433 save->idtr.selector, save->idtr.attrib,
3434 save->idtr.limit, save->idtr.base);
3435 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3437 save->tr.selector, save->tr.attrib,
3438 save->tr.limit, save->tr.base);
3439 pr_err("cpl: %d efer: %016llx\n",
3440 save->cpl, save->efer);
3441 pr_err("%-15s %016llx %-13s %016llx\n",
3442 "cr0:", save->cr0, "cr2:", save->cr2);
3443 pr_err("%-15s %016llx %-13s %016llx\n",
3444 "cr3:", save->cr3, "cr4:", save->cr4);
3445 pr_err("%-15s %016llx %-13s %016llx\n",
3446 "dr6:", save->dr6, "dr7:", save->dr7);
3447 pr_err("%-15s %016llx %-13s %016llx\n",
3448 "rip:", save->rip, "rflags:", save->rflags);
3449 pr_err("%-15s %016llx %-13s %016llx\n",
3450 "rsp:", save->rsp, "rax:", save->rax);
3451 pr_err("%-15s %016llx %-13s %016llx\n",
3452 "star:", save->star, "lstar:", save->lstar);
3453 pr_err("%-15s %016llx %-13s %016llx\n",
3454 "cstar:", save->cstar, "sfmask:", save->sfmask);
3455 pr_err("%-15s %016llx %-13s %016llx\n",
3456 "kernel_gs_base:", save->kernel_gs_base,
3457 "sysenter_cs:", save->sysenter_cs);
3458 pr_err("%-15s %016llx %-13s %016llx\n",
3459 "sysenter_esp:", save->sysenter_esp,
3460 "sysenter_eip:", save->sysenter_eip);
3461 pr_err("%-15s %016llx %-13s %016llx\n",
3462 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3463 pr_err("%-15s %016llx %-13s %016llx\n",
3464 "br_from:", save->br_from, "br_to:", save->br_to);
3465 pr_err("%-15s %016llx %-13s %016llx\n",
3466 "excp_from:", save->last_excp_from,
3467 "excp_to:", save->last_excp_to);
3470 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3472 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3474 *info1 = control->exit_info_1;
3475 *info2 = control->exit_info_2;
3478 static int handle_exit(struct kvm_vcpu *vcpu)
3480 struct vcpu_svm *svm = to_svm(vcpu);
3481 struct kvm_run *kvm_run = vcpu->run;
3482 u32 exit_code = svm->vmcb->control.exit_code;
3484 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3485 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3487 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3489 if (unlikely(svm->nested.exit_required)) {
3490 nested_svm_vmexit(svm);
3491 svm->nested.exit_required = false;
3496 if (is_guest_mode(vcpu)) {
3499 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3500 svm->vmcb->control.exit_info_1,
3501 svm->vmcb->control.exit_info_2,
3502 svm->vmcb->control.exit_int_info,
3503 svm->vmcb->control.exit_int_info_err,
3506 vmexit = nested_svm_exit_special(svm);
3508 if (vmexit == NESTED_EXIT_CONTINUE)
3509 vmexit = nested_svm_exit_handled(svm);
3511 if (vmexit == NESTED_EXIT_DONE)
3515 svm_complete_interrupts(svm);
3517 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3518 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3519 kvm_run->fail_entry.hardware_entry_failure_reason
3520 = svm->vmcb->control.exit_code;
3521 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3526 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3527 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3528 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3529 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3530 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3532 __func__, svm->vmcb->control.exit_int_info,
3535 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3536 || !svm_exit_handlers[exit_code]) {
3537 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3538 kvm_run->hw.hardware_exit_reason = exit_code;
3542 return svm_exit_handlers[exit_code](svm);
3545 static void reload_tss(struct kvm_vcpu *vcpu)
3547 int cpu = raw_smp_processor_id();
3549 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3550 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3554 static void pre_svm_run(struct vcpu_svm *svm)
3556 int cpu = raw_smp_processor_id();
3558 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3560 /* FIXME: handle wraparound of asid_generation */
3561 if (svm->asid_generation != sd->asid_generation)
3565 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3567 struct vcpu_svm *svm = to_svm(vcpu);
3569 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3570 vcpu->arch.hflags |= HF_NMI_MASK;
3571 set_intercept(svm, INTERCEPT_IRET);
3572 ++vcpu->stat.nmi_injections;
3575 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3577 struct vmcb_control_area *control;
3579 control = &svm->vmcb->control;
3580 control->int_vector = irq;
3581 control->int_ctl &= ~V_INTR_PRIO_MASK;
3582 control->int_ctl |= V_IRQ_MASK |
3583 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3584 mark_dirty(svm->vmcb, VMCB_INTR);
3587 static void svm_set_irq(struct kvm_vcpu *vcpu)
3589 struct vcpu_svm *svm = to_svm(vcpu);
3591 BUG_ON(!(gif_set(svm)));
3593 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3594 ++vcpu->stat.irq_injections;
3596 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3597 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3600 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3602 struct vcpu_svm *svm = to_svm(vcpu);
3604 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3607 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3613 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3616 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3621 static int svm_vm_has_apicv(struct kvm *kvm)
3626 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3631 static void svm_hwapic_isr_update(struct kvm *kvm, int isr)
3636 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3641 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3643 struct vcpu_svm *svm = to_svm(vcpu);
3644 struct vmcb *vmcb = svm->vmcb;
3646 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3647 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3648 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3653 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3655 struct vcpu_svm *svm = to_svm(vcpu);
3657 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3660 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3662 struct vcpu_svm *svm = to_svm(vcpu);
3665 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3666 set_intercept(svm, INTERCEPT_IRET);
3668 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3669 clr_intercept(svm, INTERCEPT_IRET);
3673 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3675 struct vcpu_svm *svm = to_svm(vcpu);
3676 struct vmcb *vmcb = svm->vmcb;
3679 if (!gif_set(svm) ||
3680 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3683 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3685 if (is_guest_mode(vcpu))
3686 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3691 static void enable_irq_window(struct kvm_vcpu *vcpu)
3693 struct vcpu_svm *svm = to_svm(vcpu);
3696 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3697 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3698 * get that intercept, this function will be called again though and
3699 * we'll get the vintr intercept.
3701 if (gif_set(svm) && nested_svm_intr(svm)) {
3703 svm_inject_irq(svm, 0x0);
3707 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3709 struct vcpu_svm *svm = to_svm(vcpu);
3711 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3713 return; /* IRET will cause a vm exit */
3716 * Something prevents NMI from been injected. Single step over possible
3717 * problem (IRET or exception injection or interrupt shadow)
3719 svm->nmi_singlestep = true;
3720 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3721 update_db_bp_intercept(vcpu);
3724 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3729 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3731 struct vcpu_svm *svm = to_svm(vcpu);
3733 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3734 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3736 svm->asid_generation--;
3739 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3743 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3745 struct vcpu_svm *svm = to_svm(vcpu);
3747 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3750 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3751 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3752 kvm_set_cr8(vcpu, cr8);
3756 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3758 struct vcpu_svm *svm = to_svm(vcpu);
3761 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3764 cr8 = kvm_get_cr8(vcpu);
3765 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3766 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3769 static void svm_complete_interrupts(struct vcpu_svm *svm)
3773 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3774 unsigned int3_injected = svm->int3_injected;
3776 svm->int3_injected = 0;
3779 * If we've made progress since setting HF_IRET_MASK, we've
3780 * executed an IRET and can allow NMI injection.
3782 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3783 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3784 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3785 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3788 svm->vcpu.arch.nmi_injected = false;
3789 kvm_clear_exception_queue(&svm->vcpu);
3790 kvm_clear_interrupt_queue(&svm->vcpu);
3792 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3795 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3797 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3798 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3801 case SVM_EXITINTINFO_TYPE_NMI:
3802 svm->vcpu.arch.nmi_injected = true;
3804 case SVM_EXITINTINFO_TYPE_EXEPT:
3806 * In case of software exceptions, do not reinject the vector,
3807 * but re-execute the instruction instead. Rewind RIP first
3808 * if we emulated INT3 before.
3810 if (kvm_exception_is_soft(vector)) {
3811 if (vector == BP_VECTOR && int3_injected &&
3812 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3813 kvm_rip_write(&svm->vcpu,
3814 kvm_rip_read(&svm->vcpu) -
3818 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3819 u32 err = svm->vmcb->control.exit_int_info_err;
3820 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3823 kvm_requeue_exception(&svm->vcpu, vector);
3825 case SVM_EXITINTINFO_TYPE_INTR:
3826 kvm_queue_interrupt(&svm->vcpu, vector, false);
3833 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3835 struct vcpu_svm *svm = to_svm(vcpu);
3836 struct vmcb_control_area *control = &svm->vmcb->control;
3838 control->exit_int_info = control->event_inj;
3839 control->exit_int_info_err = control->event_inj_err;
3840 control->event_inj = 0;
3841 svm_complete_interrupts(svm);
3844 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3846 struct vcpu_svm *svm = to_svm(vcpu);
3848 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3849 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3850 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3853 * A vmexit emulation is required before the vcpu can be executed
3856 if (unlikely(svm->nested.exit_required))
3861 sync_lapic_to_cr8(vcpu);
3863 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3870 "push %%" _ASM_BP "; \n\t"
3871 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
3872 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
3873 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
3874 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
3875 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
3876 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
3877 #ifdef CONFIG_X86_64
3878 "mov %c[r8](%[svm]), %%r8 \n\t"
3879 "mov %c[r9](%[svm]), %%r9 \n\t"
3880 "mov %c[r10](%[svm]), %%r10 \n\t"
3881 "mov %c[r11](%[svm]), %%r11 \n\t"
3882 "mov %c[r12](%[svm]), %%r12 \n\t"
3883 "mov %c[r13](%[svm]), %%r13 \n\t"
3884 "mov %c[r14](%[svm]), %%r14 \n\t"
3885 "mov %c[r15](%[svm]), %%r15 \n\t"
3888 /* Enter guest mode */
3889 "push %%" _ASM_AX " \n\t"
3890 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
3891 __ex(SVM_VMLOAD) "\n\t"
3892 __ex(SVM_VMRUN) "\n\t"
3893 __ex(SVM_VMSAVE) "\n\t"
3894 "pop %%" _ASM_AX " \n\t"
3896 /* Save guest registers, load host registers */
3897 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
3898 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
3899 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
3900 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
3901 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
3902 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
3903 #ifdef CONFIG_X86_64
3904 "mov %%r8, %c[r8](%[svm]) \n\t"
3905 "mov %%r9, %c[r9](%[svm]) \n\t"
3906 "mov %%r10, %c[r10](%[svm]) \n\t"
3907 "mov %%r11, %c[r11](%[svm]) \n\t"
3908 "mov %%r12, %c[r12](%[svm]) \n\t"
3909 "mov %%r13, %c[r13](%[svm]) \n\t"
3910 "mov %%r14, %c[r14](%[svm]) \n\t"
3911 "mov %%r15, %c[r15](%[svm]) \n\t"
3916 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3917 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3918 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3919 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3920 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3921 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3922 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3923 #ifdef CONFIG_X86_64
3924 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3925 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3926 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3927 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3928 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3929 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3930 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3931 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3934 #ifdef CONFIG_X86_64
3935 , "rbx", "rcx", "rdx", "rsi", "rdi"
3936 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3938 , "ebx", "ecx", "edx", "esi", "edi"
3942 #ifdef CONFIG_X86_64
3943 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3945 loadsegment(fs, svm->host.fs);
3946 #ifndef CONFIG_X86_32_LAZY_GS
3947 loadsegment(gs, svm->host.gs);
3953 local_irq_disable();
3955 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3956 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3957 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3958 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3960 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3962 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3963 kvm_before_handle_nmi(&svm->vcpu);
3967 /* Any pending NMI will happen here */
3969 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3970 kvm_after_handle_nmi(&svm->vcpu);
3972 sync_cr8_to_lapic(vcpu);
3976 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3978 /* if exit due to PF check for async PF */
3979 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3980 svm->apf_reason = kvm_read_and_reset_pf_reason();
3983 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3984 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3988 * We need to handle MC intercepts here before the vcpu has a chance to
3989 * change the physical cpu
3991 if (unlikely(svm->vmcb->control.exit_code ==
3992 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3993 svm_handle_mce(svm);
3995 mark_all_clean(svm->vmcb);
3998 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4000 struct vcpu_svm *svm = to_svm(vcpu);
4002 svm->vmcb->save.cr3 = root;
4003 mark_dirty(svm->vmcb, VMCB_CR);
4004 svm_flush_tlb(vcpu);
4007 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4009 struct vcpu_svm *svm = to_svm(vcpu);
4011 svm->vmcb->control.nested_cr3 = root;
4012 mark_dirty(svm->vmcb, VMCB_NPT);
4014 /* Also sync guest cr3 here in case we live migrate */
4015 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4016 mark_dirty(svm->vmcb, VMCB_CR);
4018 svm_flush_tlb(vcpu);
4021 static int is_disabled(void)
4025 rdmsrl(MSR_VM_CR, vm_cr);
4026 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4033 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4036 * Patch in the VMMCALL instruction:
4038 hypercall[0] = 0x0f;
4039 hypercall[1] = 0x01;
4040 hypercall[2] = 0xd9;
4043 static void svm_check_processor_compat(void *rtn)
4048 static bool svm_cpu_has_accelerated_tpr(void)
4053 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4058 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4062 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4067 entry->ecx |= (1 << 2); /* Set SVM bit */
4070 entry->eax = 1; /* SVM revision 1 */
4071 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4072 ASID emulation to nested SVM */
4073 entry->ecx = 0; /* Reserved */
4074 entry->edx = 0; /* Per default do not support any
4075 additional features */
4077 /* Support next_rip if host supports it */
4078 if (boot_cpu_has(X86_FEATURE_NRIPS))
4079 entry->edx |= SVM_FEATURE_NRIP;
4081 /* Support NPT for the guest if enabled */
4083 entry->edx |= SVM_FEATURE_NPT;
4089 static int svm_get_lpage_level(void)
4091 return PT_PDPE_LEVEL;
4094 static bool svm_rdtscp_supported(void)
4099 static bool svm_invpcid_supported(void)
4104 static bool svm_mpx_supported(void)
4109 static bool svm_has_wbinvd_exit(void)
4114 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4116 struct vcpu_svm *svm = to_svm(vcpu);
4118 set_exception_intercept(svm, NM_VECTOR);
4119 update_cr0_intercept(svm);
4122 #define PRE_EX(exit) { .exit_code = (exit), \
4123 .stage = X86_ICPT_PRE_EXCEPT, }
4124 #define POST_EX(exit) { .exit_code = (exit), \
4125 .stage = X86_ICPT_POST_EXCEPT, }
4126 #define POST_MEM(exit) { .exit_code = (exit), \
4127 .stage = X86_ICPT_POST_MEMACCESS, }
4129 static const struct __x86_intercept {
4131 enum x86_intercept_stage stage;
4132 } x86_intercept_map[] = {
4133 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4134 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4135 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4136 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4137 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4138 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4139 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4140 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4141 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4142 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4143 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4144 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4145 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4146 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4147 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4148 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4149 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4150 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4151 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4152 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4153 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4154 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4155 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4156 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4157 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4158 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4159 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4160 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4161 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4162 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4163 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4164 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4165 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4166 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4167 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4168 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4169 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4170 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4171 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4172 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4173 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4174 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4175 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4176 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4177 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4178 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4185 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4186 struct x86_instruction_info *info,
4187 enum x86_intercept_stage stage)
4189 struct vcpu_svm *svm = to_svm(vcpu);
4190 int vmexit, ret = X86EMUL_CONTINUE;
4191 struct __x86_intercept icpt_info;
4192 struct vmcb *vmcb = svm->vmcb;
4194 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4197 icpt_info = x86_intercept_map[info->intercept];
4199 if (stage != icpt_info.stage)
4202 switch (icpt_info.exit_code) {
4203 case SVM_EXIT_READ_CR0:
4204 if (info->intercept == x86_intercept_cr_read)
4205 icpt_info.exit_code += info->modrm_reg;
4207 case SVM_EXIT_WRITE_CR0: {
4208 unsigned long cr0, val;
4211 if (info->intercept == x86_intercept_cr_write)
4212 icpt_info.exit_code += info->modrm_reg;
4214 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4215 info->intercept == x86_intercept_clts)
4218 intercept = svm->nested.intercept;
4220 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4223 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4224 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4226 if (info->intercept == x86_intercept_lmsw) {
4229 /* lmsw can't clear PE - catch this here */
4230 if (cr0 & X86_CR0_PE)
4235 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4239 case SVM_EXIT_READ_DR0:
4240 case SVM_EXIT_WRITE_DR0:
4241 icpt_info.exit_code += info->modrm_reg;
4244 if (info->intercept == x86_intercept_wrmsr)
4245 vmcb->control.exit_info_1 = 1;
4247 vmcb->control.exit_info_1 = 0;
4249 case SVM_EXIT_PAUSE:
4251 * We get this for NOP only, but pause
4252 * is rep not, check this here
4254 if (info->rep_prefix != REPE_PREFIX)
4256 case SVM_EXIT_IOIO: {
4260 if (info->intercept == x86_intercept_in ||
4261 info->intercept == x86_intercept_ins) {
4262 exit_info = ((info->src_val & 0xffff) << 16) |
4264 bytes = info->dst_bytes;
4266 exit_info = (info->dst_val & 0xffff) << 16;
4267 bytes = info->src_bytes;
4270 if (info->intercept == x86_intercept_outs ||
4271 info->intercept == x86_intercept_ins)
4272 exit_info |= SVM_IOIO_STR_MASK;
4274 if (info->rep_prefix)
4275 exit_info |= SVM_IOIO_REP_MASK;
4277 bytes = min(bytes, 4u);
4279 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4281 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4283 vmcb->control.exit_info_1 = exit_info;
4284 vmcb->control.exit_info_2 = info->next_rip;
4292 vmcb->control.next_rip = info->next_rip;
4293 vmcb->control.exit_code = icpt_info.exit_code;
4294 vmexit = nested_svm_exit_handled(svm);
4296 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4303 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4308 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4312 static struct kvm_x86_ops svm_x86_ops = {
4313 .cpu_has_kvm_support = has_svm,
4314 .disabled_by_bios = is_disabled,
4315 .hardware_setup = svm_hardware_setup,
4316 .hardware_unsetup = svm_hardware_unsetup,
4317 .check_processor_compatibility = svm_check_processor_compat,
4318 .hardware_enable = svm_hardware_enable,
4319 .hardware_disable = svm_hardware_disable,
4320 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4322 .vcpu_create = svm_create_vcpu,
4323 .vcpu_free = svm_free_vcpu,
4324 .vcpu_reset = svm_vcpu_reset,
4326 .prepare_guest_switch = svm_prepare_guest_switch,
4327 .vcpu_load = svm_vcpu_load,
4328 .vcpu_put = svm_vcpu_put,
4330 .update_db_bp_intercept = update_db_bp_intercept,
4331 .get_msr = svm_get_msr,
4332 .set_msr = svm_set_msr,
4333 .get_segment_base = svm_get_segment_base,
4334 .get_segment = svm_get_segment,
4335 .set_segment = svm_set_segment,
4336 .get_cpl = svm_get_cpl,
4337 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4338 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4339 .decache_cr3 = svm_decache_cr3,
4340 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4341 .set_cr0 = svm_set_cr0,
4342 .set_cr3 = svm_set_cr3,
4343 .set_cr4 = svm_set_cr4,
4344 .set_efer = svm_set_efer,
4345 .get_idt = svm_get_idt,
4346 .set_idt = svm_set_idt,
4347 .get_gdt = svm_get_gdt,
4348 .set_gdt = svm_set_gdt,
4349 .get_dr6 = svm_get_dr6,
4350 .set_dr6 = svm_set_dr6,
4351 .set_dr7 = svm_set_dr7,
4352 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4353 .cache_reg = svm_cache_reg,
4354 .get_rflags = svm_get_rflags,
4355 .set_rflags = svm_set_rflags,
4356 .fpu_deactivate = svm_fpu_deactivate,
4358 .tlb_flush = svm_flush_tlb,
4360 .run = svm_vcpu_run,
4361 .handle_exit = handle_exit,
4362 .skip_emulated_instruction = skip_emulated_instruction,
4363 .set_interrupt_shadow = svm_set_interrupt_shadow,
4364 .get_interrupt_shadow = svm_get_interrupt_shadow,
4365 .patch_hypercall = svm_patch_hypercall,
4366 .set_irq = svm_set_irq,
4367 .set_nmi = svm_inject_nmi,
4368 .queue_exception = svm_queue_exception,
4369 .cancel_injection = svm_cancel_injection,
4370 .interrupt_allowed = svm_interrupt_allowed,
4371 .nmi_allowed = svm_nmi_allowed,
4372 .get_nmi_mask = svm_get_nmi_mask,
4373 .set_nmi_mask = svm_set_nmi_mask,
4374 .enable_nmi_window = enable_nmi_window,
4375 .enable_irq_window = enable_irq_window,
4376 .update_cr8_intercept = update_cr8_intercept,
4377 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4378 .vm_has_apicv = svm_vm_has_apicv,
4379 .load_eoi_exitmap = svm_load_eoi_exitmap,
4380 .hwapic_isr_update = svm_hwapic_isr_update,
4381 .sync_pir_to_irr = svm_sync_pir_to_irr,
4383 .set_tss_addr = svm_set_tss_addr,
4384 .get_tdp_level = get_npt_level,
4385 .get_mt_mask = svm_get_mt_mask,
4387 .get_exit_info = svm_get_exit_info,
4389 .get_lpage_level = svm_get_lpage_level,
4391 .cpuid_update = svm_cpuid_update,
4393 .rdtscp_supported = svm_rdtscp_supported,
4394 .invpcid_supported = svm_invpcid_supported,
4395 .mpx_supported = svm_mpx_supported,
4397 .set_supported_cpuid = svm_set_supported_cpuid,
4399 .has_wbinvd_exit = svm_has_wbinvd_exit,
4401 .set_tsc_khz = svm_set_tsc_khz,
4402 .read_tsc_offset = svm_read_tsc_offset,
4403 .write_tsc_offset = svm_write_tsc_offset,
4404 .adjust_tsc_offset = svm_adjust_tsc_offset,
4405 .compute_tsc_offset = svm_compute_tsc_offset,
4406 .read_l1_tsc = svm_read_l1_tsc,
4408 .set_tdp_cr3 = set_tdp_cr3,
4410 .check_intercept = svm_check_intercept,
4411 .handle_external_intr = svm_handle_external_intr,
4413 .sched_in = svm_sched_in,
4416 static int __init svm_init(void)
4418 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4419 __alignof__(struct vcpu_svm), THIS_MODULE);
4422 static void __exit svm_exit(void)
4427 module_init(svm_init)
4428 module_exit(svm_exit)