1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Yaniv Kamay <yaniv@qumranet.com>
12 * Avi Kivity <avi@qumranet.com>
15 #define pr_fmt(fmt) "SVM: " fmt
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
26 #include <linux/module.h>
27 #include <linux/mod_devicetable.h>
28 #include <linux/kernel.h>
29 #include <linux/vmalloc.h>
30 #include <linux/highmem.h>
31 #include <linux/sched.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/hashtable.h>
36 #include <linux/frame.h>
37 #include <linux/psp-sev.h>
38 #include <linux/file.h>
39 #include <linux/pagemap.h>
40 #include <linux/swap.h>
41 #include <linux/rwsem.h>
44 #include <asm/perf_event.h>
45 #include <asm/tlbflush.h>
47 #include <asm/debugreg.h>
48 #include <asm/kvm_para.h>
49 #include <asm/irq_remapping.h>
50 #include <asm/spec-ctrl.h>
51 #include <asm/cpu_device_id.h>
53 #include <asm/virtext.h>
56 #define __ex(x) __kvm_handle_fault_on_reboot(x)
58 MODULE_AUTHOR("Qumranet");
59 MODULE_LICENSE("GPL");
61 static const struct x86_cpu_id svm_cpu_id[] = {
62 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
65 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
67 #define IOPM_ALLOC_ORDER 2
68 #define MSRPM_ALLOC_ORDER 1
70 #define SEG_TYPE_LDT 2
71 #define SEG_TYPE_BUSY_TSS16 3
73 #define SVM_FEATURE_LBRV (1 << 1)
74 #define SVM_FEATURE_SVML (1 << 2)
75 #define SVM_FEATURE_TSC_RATE (1 << 4)
76 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
77 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
78 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
79 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
81 #define SVM_AVIC_DOORBELL 0xc001011b
83 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
84 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
85 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
87 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
89 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
90 #define TSC_RATIO_MIN 0x0000000000000001ULL
91 #define TSC_RATIO_MAX 0x000000ffffffffffULL
93 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
96 * 0xff is broadcast, so the max index allowed for physical APIC ID
97 * table is 0xfe. APIC IDs above 0xff are reserved.
99 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
101 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
102 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
103 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
105 /* AVIC GATAG is encoded using VM and VCPU IDs */
106 #define AVIC_VCPU_ID_BITS 8
107 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
109 #define AVIC_VM_ID_BITS 24
110 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
111 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
113 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
114 (y & AVIC_VCPU_ID_MASK))
115 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
116 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
118 static bool erratum_383_found __read_mostly;
120 static const u32 host_save_user_msrs[] = {
122 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
125 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
129 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
131 struct kvm_sev_info {
132 bool active; /* SEV enabled guest */
133 unsigned int asid; /* ASID used for this guest */
134 unsigned int handle; /* SEV firmware handle */
135 int fd; /* SEV device fd */
136 unsigned long pages_locked; /* Number of pages locked */
137 struct list_head regions_list; /* List of registered regions */
143 /* Struct members for AVIC */
145 struct page *avic_logical_id_table_page;
146 struct page *avic_physical_id_table_page;
147 struct hlist_node hnode;
149 struct kvm_sev_info sev_info;
154 struct nested_state {
160 /* These are the merged vectors */
163 /* gpa pointers to the real vectors */
167 /* A VMEXIT is required but not yet emulated */
170 /* cache for intercepts of the guest */
173 u32 intercept_exceptions;
176 /* Nested Paging related state */
180 #define MSRPM_OFFSETS 16
181 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
184 * Set osvw_len to higher value when updated Revision Guides
185 * are published and we know what the new status bits are
187 static uint64_t osvw_len = 4, osvw_status;
190 struct kvm_vcpu vcpu;
192 unsigned long vmcb_pa;
193 struct svm_cpu_data *svm_data;
194 uint64_t asid_generation;
195 uint64_t sysenter_esp;
196 uint64_t sysenter_eip;
203 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
213 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
214 * translated into the appropriate L2_CFG bits on the host to
215 * perform speculative control.
223 struct nested_state nested;
226 u64 nmi_singlestep_guest_rflags;
228 unsigned int3_injected;
229 unsigned long int3_rip;
231 /* cached guest cpuid flags for faster access */
232 bool nrips_enabled : 1;
236 struct page *avic_backing_page;
237 u64 *avic_physical_id_cache;
238 bool avic_is_running;
241 * Per-vcpu list of struct amd_svm_iommu_ir:
242 * This is used mainly to store interrupt remapping information used
243 * when update the vcpu affinity. This avoids the need to scan for
244 * IRTE and try to match ga_tag in the IOMMU driver.
246 struct list_head ir_list;
247 spinlock_t ir_list_lock;
249 /* which host CPU was used for running this vcpu */
250 unsigned int last_cpu;
254 * This is a wrapper of struct amd_iommu_ir_data.
256 struct amd_svm_iommu_ir {
257 struct list_head node; /* Used by SVM for per-vcpu ir_list */
258 void *data; /* Storing pointer to struct amd_ir_data */
261 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
262 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
263 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
265 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
266 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
267 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
268 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
270 static DEFINE_PER_CPU(u64, current_tsc_ratio);
271 #define TSC_RATIO_DEFAULT 0x0100000000ULL
273 #define MSR_INVALID 0xffffffffU
275 static const struct svm_direct_access_msrs {
276 u32 index; /* Index of the MSR */
277 bool always; /* True if intercept is always on */
278 } direct_access_msrs[] = {
279 { .index = MSR_STAR, .always = true },
280 { .index = MSR_IA32_SYSENTER_CS, .always = true },
282 { .index = MSR_GS_BASE, .always = true },
283 { .index = MSR_FS_BASE, .always = true },
284 { .index = MSR_KERNEL_GS_BASE, .always = true },
285 { .index = MSR_LSTAR, .always = true },
286 { .index = MSR_CSTAR, .always = true },
287 { .index = MSR_SYSCALL_MASK, .always = true },
289 { .index = MSR_IA32_SPEC_CTRL, .always = false },
290 { .index = MSR_IA32_PRED_CMD, .always = false },
291 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
292 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
293 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
294 { .index = MSR_IA32_LASTINTTOIP, .always = false },
295 { .index = MSR_INVALID, .always = false },
298 /* enable NPT for AMD64 and X86 with PAE */
299 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
300 static bool npt_enabled = true;
302 static bool npt_enabled;
306 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
307 * pause_filter_count: On processors that support Pause filtering(indicated
308 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
309 * count value. On VMRUN this value is loaded into an internal counter.
310 * Each time a pause instruction is executed, this counter is decremented
311 * until it reaches zero at which time a #VMEXIT is generated if pause
312 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
313 * Intercept Filtering for more details.
314 * This also indicate if ple logic enabled.
316 * pause_filter_thresh: In addition, some processor families support advanced
317 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
318 * the amount of time a guest is allowed to execute in a pause loop.
319 * In this mode, a 16-bit pause filter threshold field is added in the
320 * VMCB. The threshold value is a cycle count that is used to reset the
321 * pause counter. As with simple pause filtering, VMRUN loads the pause
322 * count value from VMCB into an internal counter. Then, on each pause
323 * instruction the hardware checks the elapsed number of cycles since
324 * the most recent pause instruction against the pause filter threshold.
325 * If the elapsed cycle count is greater than the pause filter threshold,
326 * then the internal pause count is reloaded from the VMCB and execution
327 * continues. If the elapsed cycle count is less than the pause filter
328 * threshold, then the internal pause count is decremented. If the count
329 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
330 * triggered. If advanced pause filtering is supported and pause filter
331 * threshold field is set to zero, the filter will operate in the simpler,
335 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
336 module_param(pause_filter_thresh, ushort, 0444);
338 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
339 module_param(pause_filter_count, ushort, 0444);
341 /* Default doubles per-vcpu window every exit. */
342 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
343 module_param(pause_filter_count_grow, ushort, 0444);
345 /* Default resets per-vcpu window every exit to pause_filter_count. */
346 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
347 module_param(pause_filter_count_shrink, ushort, 0444);
349 /* Default is to compute the maximum so we can never overflow. */
350 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
351 module_param(pause_filter_count_max, ushort, 0444);
353 /* allow nested paging (virtualized MMU) for all guests */
354 static int npt = true;
355 module_param(npt, int, S_IRUGO);
357 /* allow nested virtualization in KVM/SVM */
358 static int nested = true;
359 module_param(nested, int, S_IRUGO);
361 /* enable / disable AVIC */
363 #ifdef CONFIG_X86_LOCAL_APIC
364 module_param(avic, int, S_IRUGO);
367 /* enable/disable Next RIP Save */
368 static int nrips = true;
369 module_param(nrips, int, 0444);
371 /* enable/disable Virtual VMLOAD VMSAVE */
372 static int vls = true;
373 module_param(vls, int, 0444);
375 /* enable/disable Virtual GIF */
376 static int vgif = true;
377 module_param(vgif, int, 0444);
379 /* enable/disable SEV support */
380 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
381 module_param(sev, int, 0444);
383 static bool __read_mostly dump_invalid_vmcb = 0;
384 module_param(dump_invalid_vmcb, bool, 0644);
386 static u8 rsm_ins_bytes[] = "\x0f\xaa";
388 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
389 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
390 static void svm_complete_interrupts(struct vcpu_svm *svm);
391 static void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate);
392 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu);
394 static int nested_svm_exit_handled(struct vcpu_svm *svm);
395 static int nested_svm_intercept(struct vcpu_svm *svm);
396 static int nested_svm_vmexit(struct vcpu_svm *svm);
397 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
398 bool has_error_code, u32 error_code);
401 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
402 pause filter count */
403 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
404 VMCB_ASID, /* ASID */
405 VMCB_INTR, /* int_ctl, int_vector */
406 VMCB_NPT, /* npt_en, nCR3, gPAT */
407 VMCB_CR, /* CR0, CR3, CR4, EFER */
408 VMCB_DR, /* DR6, DR7 */
409 VMCB_DT, /* GDT, IDT */
410 VMCB_SEG, /* CS, DS, SS, ES, CPL */
411 VMCB_CR2, /* CR2 only */
412 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
413 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
414 * AVIC PHYSICAL_TABLE pointer,
415 * AVIC LOGICAL_TABLE pointer
420 /* TPR and CR2 are always written before VMRUN */
421 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
423 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
425 static int sev_flush_asids(void);
426 static DECLARE_RWSEM(sev_deactivate_lock);
427 static DEFINE_MUTEX(sev_bitmap_lock);
428 static unsigned int max_sev_asid;
429 static unsigned int min_sev_asid;
430 static unsigned long *sev_asid_bitmap;
431 static unsigned long *sev_reclaim_asid_bitmap;
432 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
435 struct list_head list;
436 unsigned long npages;
443 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
445 return container_of(kvm, struct kvm_svm, kvm);
448 static inline bool svm_sev_enabled(void)
450 return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
453 static inline bool sev_guest(struct kvm *kvm)
455 #ifdef CONFIG_KVM_AMD_SEV
456 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
464 static inline int sev_get_asid(struct kvm *kvm)
466 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
471 static inline void mark_all_dirty(struct vmcb *vmcb)
473 vmcb->control.clean = 0;
476 static inline void mark_all_clean(struct vmcb *vmcb)
478 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
479 & ~VMCB_ALWAYS_DIRTY_MASK;
482 static inline void mark_dirty(struct vmcb *vmcb, int bit)
484 vmcb->control.clean &= ~(1 << bit);
487 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
489 return container_of(vcpu, struct vcpu_svm, vcpu);
492 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
494 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
495 mark_dirty(svm->vmcb, VMCB_AVIC);
498 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
500 struct vcpu_svm *svm = to_svm(vcpu);
501 u64 *entry = svm->avic_physical_id_cache;
506 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
509 static void recalc_intercepts(struct vcpu_svm *svm)
511 struct vmcb_control_area *c, *h;
512 struct nested_state *g;
514 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
516 if (!is_guest_mode(&svm->vcpu))
519 c = &svm->vmcb->control;
520 h = &svm->nested.hsave->control;
523 c->intercept_cr = h->intercept_cr | g->intercept_cr;
524 c->intercept_dr = h->intercept_dr | g->intercept_dr;
525 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
526 c->intercept = h->intercept | g->intercept;
529 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
531 if (is_guest_mode(&svm->vcpu))
532 return svm->nested.hsave;
537 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
539 struct vmcb *vmcb = get_host_vmcb(svm);
541 vmcb->control.intercept_cr |= (1U << bit);
543 recalc_intercepts(svm);
546 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
548 struct vmcb *vmcb = get_host_vmcb(svm);
550 vmcb->control.intercept_cr &= ~(1U << bit);
552 recalc_intercepts(svm);
555 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
557 struct vmcb *vmcb = get_host_vmcb(svm);
559 return vmcb->control.intercept_cr & (1U << bit);
562 static inline void set_dr_intercepts(struct vcpu_svm *svm)
564 struct vmcb *vmcb = get_host_vmcb(svm);
566 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
567 | (1 << INTERCEPT_DR1_READ)
568 | (1 << INTERCEPT_DR2_READ)
569 | (1 << INTERCEPT_DR3_READ)
570 | (1 << INTERCEPT_DR4_READ)
571 | (1 << INTERCEPT_DR5_READ)
572 | (1 << INTERCEPT_DR6_READ)
573 | (1 << INTERCEPT_DR7_READ)
574 | (1 << INTERCEPT_DR0_WRITE)
575 | (1 << INTERCEPT_DR1_WRITE)
576 | (1 << INTERCEPT_DR2_WRITE)
577 | (1 << INTERCEPT_DR3_WRITE)
578 | (1 << INTERCEPT_DR4_WRITE)
579 | (1 << INTERCEPT_DR5_WRITE)
580 | (1 << INTERCEPT_DR6_WRITE)
581 | (1 << INTERCEPT_DR7_WRITE);
583 recalc_intercepts(svm);
586 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
588 struct vmcb *vmcb = get_host_vmcb(svm);
590 vmcb->control.intercept_dr = 0;
592 recalc_intercepts(svm);
595 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
597 struct vmcb *vmcb = get_host_vmcb(svm);
599 vmcb->control.intercept_exceptions |= (1U << bit);
601 recalc_intercepts(svm);
604 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
606 struct vmcb *vmcb = get_host_vmcb(svm);
608 vmcb->control.intercept_exceptions &= ~(1U << bit);
610 recalc_intercepts(svm);
613 static inline void set_intercept(struct vcpu_svm *svm, int bit)
615 struct vmcb *vmcb = get_host_vmcb(svm);
617 vmcb->control.intercept |= (1ULL << bit);
619 recalc_intercepts(svm);
622 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
624 struct vmcb *vmcb = get_host_vmcb(svm);
626 vmcb->control.intercept &= ~(1ULL << bit);
628 recalc_intercepts(svm);
631 static inline bool vgif_enabled(struct vcpu_svm *svm)
633 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
636 static inline void enable_gif(struct vcpu_svm *svm)
638 if (vgif_enabled(svm))
639 svm->vmcb->control.int_ctl |= V_GIF_MASK;
641 svm->vcpu.arch.hflags |= HF_GIF_MASK;
644 static inline void disable_gif(struct vcpu_svm *svm)
646 if (vgif_enabled(svm))
647 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
649 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
652 static inline bool gif_set(struct vcpu_svm *svm)
654 if (vgif_enabled(svm))
655 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
657 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
660 static unsigned long iopm_base;
662 struct kvm_ldttss_desc {
665 unsigned base1:8, type:5, dpl:2, p:1;
666 unsigned limit1:4, zero0:3, g:1, base2:8;
669 } __attribute__((packed));
671 struct svm_cpu_data {
678 struct kvm_ldttss_desc *tss_desc;
680 struct page *save_area;
681 struct vmcb *current_vmcb;
683 /* index = sev_asid, value = vmcb pointer */
684 struct vmcb **sev_vmcbs;
687 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
689 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
691 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
692 #define MSRS_RANGE_SIZE 2048
693 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
695 static u32 svm_msrpm_offset(u32 msr)
700 for (i = 0; i < NUM_MSR_MAPS; i++) {
701 if (msr < msrpm_ranges[i] ||
702 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
705 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
706 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
708 /* Now we have the u8 offset - but need the u32 offset */
712 /* MSR not in any range */
716 #define MAX_INST_SIZE 15
718 static inline void clgi(void)
720 asm volatile (__ex("clgi"));
723 static inline void stgi(void)
725 asm volatile (__ex("stgi"));
728 static inline void invlpga(unsigned long addr, u32 asid)
730 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
733 static int get_npt_level(struct kvm_vcpu *vcpu)
736 return PT64_ROOT_4LEVEL;
738 return PT32E_ROOT_LEVEL;
742 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
744 vcpu->arch.efer = efer;
747 /* Shadow paging assumes NX to be available. */
750 if (!(efer & EFER_LMA))
754 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
755 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
758 static int is_external_interrupt(u32 info)
760 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
761 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
764 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
766 struct vcpu_svm *svm = to_svm(vcpu);
769 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
770 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
774 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
776 struct vcpu_svm *svm = to_svm(vcpu);
779 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
781 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
785 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
787 struct vcpu_svm *svm = to_svm(vcpu);
789 if (nrips && svm->vmcb->control.next_rip != 0) {
790 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
791 svm->next_rip = svm->vmcb->control.next_rip;
794 if (!svm->next_rip) {
795 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
798 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
799 pr_err("%s: ip 0x%lx next 0x%llx\n",
800 __func__, kvm_rip_read(vcpu), svm->next_rip);
801 kvm_rip_write(vcpu, svm->next_rip);
803 svm_set_interrupt_shadow(vcpu, 0);
808 static void svm_queue_exception(struct kvm_vcpu *vcpu)
810 struct vcpu_svm *svm = to_svm(vcpu);
811 unsigned nr = vcpu->arch.exception.nr;
812 bool has_error_code = vcpu->arch.exception.has_error_code;
813 bool reinject = vcpu->arch.exception.injected;
814 u32 error_code = vcpu->arch.exception.error_code;
817 * If we are within a nested VM we'd better #VMEXIT and let the guest
818 * handle the exception
821 nested_svm_check_exception(svm, nr, has_error_code, error_code))
824 kvm_deliver_exception_payload(&svm->vcpu);
826 if (nr == BP_VECTOR && !nrips) {
827 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
830 * For guest debugging where we have to reinject #BP if some
831 * INT3 is guest-owned:
832 * Emulate nRIP by moving RIP forward. Will fail if injection
833 * raises a fault that is not intercepted. Still better than
834 * failing in all cases.
836 (void)skip_emulated_instruction(&svm->vcpu);
837 rip = kvm_rip_read(&svm->vcpu);
838 svm->int3_rip = rip + svm->vmcb->save.cs.base;
839 svm->int3_injected = rip - old_rip;
842 svm->vmcb->control.event_inj = nr
844 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
845 | SVM_EVTINJ_TYPE_EXEPT;
846 svm->vmcb->control.event_inj_err = error_code;
849 static void svm_init_erratum_383(void)
855 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
858 /* Use _safe variants to not break nested virtualization */
859 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
865 low = lower_32_bits(val);
866 high = upper_32_bits(val);
868 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
870 erratum_383_found = true;
873 static void svm_init_osvw(struct kvm_vcpu *vcpu)
876 * Guests should see errata 400 and 415 as fixed (assuming that
877 * HLT and IO instructions are intercepted).
879 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
880 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
883 * By increasing VCPU's osvw.length to 3 we are telling the guest that
884 * all osvw.status bits inside that length, including bit 0 (which is
885 * reserved for erratum 298), are valid. However, if host processor's
886 * osvw_len is 0 then osvw_status[0] carries no information. We need to
887 * be conservative here and therefore we tell the guest that erratum 298
888 * is present (because we really don't know).
890 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
891 vcpu->arch.osvw.status |= 1;
894 static int has_svm(void)
898 if (!cpu_has_svm(&msg)) {
899 printk(KERN_INFO "has_svm: %s\n", msg);
906 static void svm_hardware_disable(void)
908 /* Make sure we clean up behind us */
909 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
910 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
914 amd_pmu_disable_virt();
917 static int svm_hardware_enable(void)
920 struct svm_cpu_data *sd;
922 struct desc_struct *gdt;
923 int me = raw_smp_processor_id();
925 rdmsrl(MSR_EFER, efer);
926 if (efer & EFER_SVME)
930 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
933 sd = per_cpu(svm_data, me);
935 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
939 sd->asid_generation = 1;
940 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
941 sd->next_asid = sd->max_asid + 1;
942 sd->min_asid = max_sev_asid + 1;
944 gdt = get_current_gdt_rw();
945 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
947 wrmsrl(MSR_EFER, efer | EFER_SVME);
949 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
951 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
952 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
953 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
960 * Note that it is possible to have a system with mixed processor
961 * revisions and therefore different OSVW bits. If bits are not the same
962 * on different processors then choose the worst case (i.e. if erratum
963 * is present on one processor and not on another then assume that the
964 * erratum is present everywhere).
966 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
967 uint64_t len, status = 0;
970 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
972 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
976 osvw_status = osvw_len = 0;
980 osvw_status |= status;
981 osvw_status &= (1ULL << osvw_len) - 1;
984 osvw_status = osvw_len = 0;
986 svm_init_erratum_383();
988 amd_pmu_enable_virt();
993 static void svm_cpu_uninit(int cpu)
995 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
1000 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
1001 kfree(sd->sev_vmcbs);
1002 __free_page(sd->save_area);
1006 static int svm_cpu_init(int cpu)
1008 struct svm_cpu_data *sd;
1011 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
1016 sd->save_area = alloc_page(GFP_KERNEL);
1020 if (svm_sev_enabled()) {
1022 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1029 per_cpu(svm_data, cpu) = sd;
1039 static bool valid_msr_intercept(u32 index)
1043 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1044 if (direct_access_msrs[i].index == index)
1050 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1057 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1058 to_svm(vcpu)->msrpm;
1060 offset = svm_msrpm_offset(msr);
1061 bit_write = 2 * (msr & 0x0f) + 1;
1062 tmp = msrpm[offset];
1064 BUG_ON(offset == MSR_INVALID);
1066 return !!test_bit(bit_write, &tmp);
1069 static void set_msr_interception(u32 *msrpm, unsigned msr,
1070 int read, int write)
1072 u8 bit_read, bit_write;
1077 * If this warning triggers extend the direct_access_msrs list at the
1078 * beginning of the file
1080 WARN_ON(!valid_msr_intercept(msr));
1082 offset = svm_msrpm_offset(msr);
1083 bit_read = 2 * (msr & 0x0f);
1084 bit_write = 2 * (msr & 0x0f) + 1;
1085 tmp = msrpm[offset];
1087 BUG_ON(offset == MSR_INVALID);
1089 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
1090 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1092 msrpm[offset] = tmp;
1095 static void svm_vcpu_init_msrpm(u32 *msrpm)
1099 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1101 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1102 if (!direct_access_msrs[i].always)
1105 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1109 static void add_msr_offset(u32 offset)
1113 for (i = 0; i < MSRPM_OFFSETS; ++i) {
1115 /* Offset already in list? */
1116 if (msrpm_offsets[i] == offset)
1119 /* Slot used by another offset? */
1120 if (msrpm_offsets[i] != MSR_INVALID)
1123 /* Add offset to list */
1124 msrpm_offsets[i] = offset;
1130 * If this BUG triggers the msrpm_offsets table has an overflow. Just
1131 * increase MSRPM_OFFSETS in this case.
1136 static void init_msrpm_offsets(void)
1140 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1142 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1145 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1146 BUG_ON(offset == MSR_INVALID);
1148 add_msr_offset(offset);
1152 static void svm_enable_lbrv(struct vcpu_svm *svm)
1154 u32 *msrpm = svm->msrpm;
1156 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1157 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1158 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1159 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1160 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1163 static void svm_disable_lbrv(struct vcpu_svm *svm)
1165 u32 *msrpm = svm->msrpm;
1167 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1168 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1169 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1170 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1171 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1174 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1176 svm->nmi_singlestep = false;
1178 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1179 /* Clear our flags if they were not set by the guest */
1180 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1181 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1182 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1183 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1188 * This hash table is used to map VM_ID to a struct kvm_svm,
1189 * when handling AMD IOMMU GALOG notification to schedule in
1190 * a particular vCPU.
1192 #define SVM_VM_DATA_HASH_BITS 8
1193 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1194 static u32 next_vm_id = 0;
1195 static bool next_vm_id_wrapped = 0;
1196 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1199 * This function is called from IOMMU driver to notify
1200 * SVM to schedule in a particular vCPU of a particular VM.
1202 static int avic_ga_log_notifier(u32 ga_tag)
1204 unsigned long flags;
1205 struct kvm_svm *kvm_svm;
1206 struct kvm_vcpu *vcpu = NULL;
1207 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1208 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1210 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1212 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1213 hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1214 if (kvm_svm->avic_vm_id != vm_id)
1216 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1219 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1222 * At this point, the IOMMU should have already set the pending
1223 * bit in the vAPIC backing page. So, we just need to schedule
1227 kvm_vcpu_wake_up(vcpu);
1232 static __init int sev_hardware_setup(void)
1234 struct sev_user_data_status *status;
1237 /* Maximum number of encrypted guests supported simultaneously */
1238 max_sev_asid = cpuid_ecx(0x8000001F);
1243 /* Minimum ASID value that should be used for SEV guest */
1244 min_sev_asid = cpuid_edx(0x8000001F);
1246 /* Initialize SEV ASID bitmaps */
1247 sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1248 if (!sev_asid_bitmap)
1251 sev_reclaim_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1252 if (!sev_reclaim_asid_bitmap)
1255 status = kmalloc(sizeof(*status), GFP_KERNEL);
1260 * Check SEV platform status.
1262 * PLATFORM_STATUS can be called in any state, if we failed to query
1263 * the PLATFORM status then either PSP firmware does not support SEV
1264 * feature or SEV firmware is dead.
1266 rc = sev_platform_status(status, NULL);
1270 pr_info("SEV supported\n");
1277 static void grow_ple_window(struct kvm_vcpu *vcpu)
1279 struct vcpu_svm *svm = to_svm(vcpu);
1280 struct vmcb_control_area *control = &svm->vmcb->control;
1281 int old = control->pause_filter_count;
1283 control->pause_filter_count = __grow_ple_window(old,
1285 pause_filter_count_grow,
1286 pause_filter_count_max);
1288 if (control->pause_filter_count != old) {
1289 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1290 trace_kvm_ple_window_update(vcpu->vcpu_id,
1291 control->pause_filter_count, old);
1295 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1297 struct vcpu_svm *svm = to_svm(vcpu);
1298 struct vmcb_control_area *control = &svm->vmcb->control;
1299 int old = control->pause_filter_count;
1301 control->pause_filter_count =
1302 __shrink_ple_window(old,
1304 pause_filter_count_shrink,
1305 pause_filter_count);
1306 if (control->pause_filter_count != old) {
1307 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1308 trace_kvm_ple_window_update(vcpu->vcpu_id,
1309 control->pause_filter_count, old);
1314 * The default MMIO mask is a single bit (excluding the present bit),
1315 * which could conflict with the memory encryption bit. Check for
1316 * memory encryption support and override the default MMIO mask if
1317 * memory encryption is enabled.
1319 static __init void svm_adjust_mmio_mask(void)
1321 unsigned int enc_bit, mask_bit;
1324 /* If there is no memory encryption support, use existing mask */
1325 if (cpuid_eax(0x80000000) < 0x8000001f)
1328 /* If memory encryption is not enabled, use existing mask */
1329 rdmsrl(MSR_K8_SYSCFG, msr);
1330 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
1333 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
1334 mask_bit = boot_cpu_data.x86_phys_bits;
1336 /* Increment the mask bit if it is the same as the encryption bit */
1337 if (enc_bit == mask_bit)
1341 * If the mask bit location is below 52, then some bits above the
1342 * physical addressing limit will always be reserved, so use the
1343 * rsvd_bits() function to generate the mask. This mask, along with
1344 * the present bit, will be used to generate a page fault with
1347 * If the mask bit location is 52 (or above), then clear the mask.
1349 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
1351 kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
1354 static __init int svm_hardware_setup(void)
1357 struct page *iopm_pages;
1361 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1366 iopm_va = page_address(iopm_pages);
1367 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1368 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1370 init_msrpm_offsets();
1372 if (boot_cpu_has(X86_FEATURE_NX))
1373 kvm_enable_efer_bits(EFER_NX);
1375 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1376 kvm_enable_efer_bits(EFER_FFXSR);
1378 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1379 kvm_has_tsc_control = true;
1380 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1381 kvm_tsc_scaling_ratio_frac_bits = 32;
1384 /* Check for pause filtering support */
1385 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1386 pause_filter_count = 0;
1387 pause_filter_thresh = 0;
1388 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1389 pause_filter_thresh = 0;
1393 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1394 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1398 if (boot_cpu_has(X86_FEATURE_SEV) &&
1399 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1400 r = sev_hardware_setup();
1408 svm_adjust_mmio_mask();
1410 for_each_possible_cpu(cpu) {
1411 r = svm_cpu_init(cpu);
1416 if (!boot_cpu_has(X86_FEATURE_NPT))
1417 npt_enabled = false;
1419 if (npt_enabled && !npt) {
1420 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1421 npt_enabled = false;
1425 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1431 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1437 !boot_cpu_has(X86_FEATURE_AVIC) ||
1438 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1441 pr_info("AVIC enabled\n");
1443 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1449 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1450 !IS_ENABLED(CONFIG_X86_64)) {
1453 pr_info("Virtual VMLOAD VMSAVE supported\n");
1458 if (!boot_cpu_has(X86_FEATURE_VGIF))
1461 pr_info("Virtual GIF supported\n");
1467 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1472 static __exit void svm_hardware_unsetup(void)
1476 if (svm_sev_enabled()) {
1477 bitmap_free(sev_asid_bitmap);
1478 bitmap_free(sev_reclaim_asid_bitmap);
1483 for_each_possible_cpu(cpu)
1484 svm_cpu_uninit(cpu);
1486 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1490 static void init_seg(struct vmcb_seg *seg)
1493 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1494 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1495 seg->limit = 0xffff;
1499 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1502 seg->attrib = SVM_SELECTOR_P_MASK | type;
1503 seg->limit = 0xffff;
1507 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1509 struct vcpu_svm *svm = to_svm(vcpu);
1511 if (is_guest_mode(vcpu))
1512 return svm->nested.hsave->control.tsc_offset;
1514 return vcpu->arch.tsc_offset;
1517 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1519 struct vcpu_svm *svm = to_svm(vcpu);
1520 u64 g_tsc_offset = 0;
1522 if (is_guest_mode(vcpu)) {
1523 /* Write L1's TSC offset. */
1524 g_tsc_offset = svm->vmcb->control.tsc_offset -
1525 svm->nested.hsave->control.tsc_offset;
1526 svm->nested.hsave->control.tsc_offset = offset;
1529 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1530 svm->vmcb->control.tsc_offset - g_tsc_offset,
1533 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1535 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1536 return svm->vmcb->control.tsc_offset;
1539 static void avic_init_vmcb(struct vcpu_svm *svm)
1541 struct vmcb *vmcb = svm->vmcb;
1542 struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1543 phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1544 phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1545 phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1547 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1548 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1549 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1550 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1551 if (kvm_apicv_activated(svm->vcpu.kvm))
1552 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1554 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
1557 static void init_vmcb(struct vcpu_svm *svm)
1559 struct vmcb_control_area *control = &svm->vmcb->control;
1560 struct vmcb_save_area *save = &svm->vmcb->save;
1562 svm->vcpu.arch.hflags = 0;
1564 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1565 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1566 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1567 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1568 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1569 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1570 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1571 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1573 set_dr_intercepts(svm);
1575 set_exception_intercept(svm, PF_VECTOR);
1576 set_exception_intercept(svm, UD_VECTOR);
1577 set_exception_intercept(svm, MC_VECTOR);
1578 set_exception_intercept(svm, AC_VECTOR);
1579 set_exception_intercept(svm, DB_VECTOR);
1581 * Guest access to VMware backdoor ports could legitimately
1582 * trigger #GP because of TSS I/O permission bitmap.
1583 * We intercept those #GP and allow access to them anyway
1586 if (enable_vmware_backdoor)
1587 set_exception_intercept(svm, GP_VECTOR);
1589 set_intercept(svm, INTERCEPT_INTR);
1590 set_intercept(svm, INTERCEPT_NMI);
1591 set_intercept(svm, INTERCEPT_SMI);
1592 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1593 set_intercept(svm, INTERCEPT_RDPMC);
1594 set_intercept(svm, INTERCEPT_CPUID);
1595 set_intercept(svm, INTERCEPT_INVD);
1596 set_intercept(svm, INTERCEPT_INVLPG);
1597 set_intercept(svm, INTERCEPT_INVLPGA);
1598 set_intercept(svm, INTERCEPT_IOIO_PROT);
1599 set_intercept(svm, INTERCEPT_MSR_PROT);
1600 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1601 set_intercept(svm, INTERCEPT_SHUTDOWN);
1602 set_intercept(svm, INTERCEPT_VMRUN);
1603 set_intercept(svm, INTERCEPT_VMMCALL);
1604 set_intercept(svm, INTERCEPT_VMLOAD);
1605 set_intercept(svm, INTERCEPT_VMSAVE);
1606 set_intercept(svm, INTERCEPT_STGI);
1607 set_intercept(svm, INTERCEPT_CLGI);
1608 set_intercept(svm, INTERCEPT_SKINIT);
1609 set_intercept(svm, INTERCEPT_WBINVD);
1610 set_intercept(svm, INTERCEPT_XSETBV);
1611 set_intercept(svm, INTERCEPT_RDPRU);
1612 set_intercept(svm, INTERCEPT_RSM);
1614 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1615 set_intercept(svm, INTERCEPT_MONITOR);
1616 set_intercept(svm, INTERCEPT_MWAIT);
1619 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1620 set_intercept(svm, INTERCEPT_HLT);
1622 control->iopm_base_pa = __sme_set(iopm_base);
1623 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1624 control->int_ctl = V_INTR_MASKING_MASK;
1626 init_seg(&save->es);
1627 init_seg(&save->ss);
1628 init_seg(&save->ds);
1629 init_seg(&save->fs);
1630 init_seg(&save->gs);
1632 save->cs.selector = 0xf000;
1633 save->cs.base = 0xffff0000;
1634 /* Executable/Readable Code Segment */
1635 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1636 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1637 save->cs.limit = 0xffff;
1639 save->gdtr.limit = 0xffff;
1640 save->idtr.limit = 0xffff;
1642 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1643 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1645 svm_set_efer(&svm->vcpu, 0);
1646 save->dr6 = 0xffff0ff0;
1647 kvm_set_rflags(&svm->vcpu, 2);
1648 save->rip = 0x0000fff0;
1649 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1652 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1653 * It also updates the guest-visible cr0 value.
1655 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1656 kvm_mmu_reset_context(&svm->vcpu);
1658 save->cr4 = X86_CR4_PAE;
1662 /* Setup VMCB for Nested Paging */
1663 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1664 clr_intercept(svm, INTERCEPT_INVLPG);
1665 clr_exception_intercept(svm, PF_VECTOR);
1666 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1667 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1668 save->g_pat = svm->vcpu.arch.pat;
1672 svm->asid_generation = 0;
1674 svm->nested.vmcb = 0;
1675 svm->vcpu.arch.hflags = 0;
1677 if (pause_filter_count) {
1678 control->pause_filter_count = pause_filter_count;
1679 if (pause_filter_thresh)
1680 control->pause_filter_thresh = pause_filter_thresh;
1681 set_intercept(svm, INTERCEPT_PAUSE);
1683 clr_intercept(svm, INTERCEPT_PAUSE);
1686 if (kvm_vcpu_apicv_active(&svm->vcpu))
1687 avic_init_vmcb(svm);
1690 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1691 * in VMCB and clear intercepts to avoid #VMEXIT.
1694 clr_intercept(svm, INTERCEPT_VMLOAD);
1695 clr_intercept(svm, INTERCEPT_VMSAVE);
1696 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1700 clr_intercept(svm, INTERCEPT_STGI);
1701 clr_intercept(svm, INTERCEPT_CLGI);
1702 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1705 if (sev_guest(svm->vcpu.kvm)) {
1706 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1707 clr_exception_intercept(svm, UD_VECTOR);
1710 mark_all_dirty(svm->vmcb);
1716 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1719 u64 *avic_physical_id_table;
1720 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1722 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1725 avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1727 return &avic_physical_id_table[index];
1732 * AVIC hardware walks the nested page table to check permissions,
1733 * but does not use the SPA address specified in the leaf page
1734 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1735 * field of the VMCB. Therefore, we set up the
1736 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1738 static int avic_update_access_page(struct kvm *kvm, bool activate)
1742 mutex_lock(&kvm->slots_lock);
1744 * During kvm_destroy_vm(), kvm_pit_set_reinject() could trigger
1745 * APICv mode change, which update APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
1746 * memory region. So, we need to ensure that kvm->mm == current->mm.
1748 if ((kvm->arch.apic_access_page_done == activate) ||
1749 (kvm->mm != current->mm))
1752 ret = __x86_set_memory_region(kvm,
1753 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1754 APIC_DEFAULT_PHYS_BASE,
1755 activate ? PAGE_SIZE : 0);
1759 kvm->arch.apic_access_page_done = activate;
1761 mutex_unlock(&kvm->slots_lock);
1765 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1767 u64 *entry, new_entry;
1768 int id = vcpu->vcpu_id;
1769 struct vcpu_svm *svm = to_svm(vcpu);
1771 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1774 if (!svm->vcpu.arch.apic->regs)
1777 if (kvm_apicv_activated(vcpu->kvm)) {
1780 ret = avic_update_access_page(vcpu->kvm, true);
1785 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1787 /* Setting AVIC backing page address in the phy APIC ID table */
1788 entry = avic_get_physical_id_entry(vcpu, id);
1792 new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1793 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1794 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1795 WRITE_ONCE(*entry, new_entry);
1797 svm->avic_physical_id_cache = entry;
1802 static void sev_asid_free(int asid)
1804 struct svm_cpu_data *sd;
1807 mutex_lock(&sev_bitmap_lock);
1810 __set_bit(pos, sev_reclaim_asid_bitmap);
1812 for_each_possible_cpu(cpu) {
1813 sd = per_cpu(svm_data, cpu);
1814 sd->sev_vmcbs[pos] = NULL;
1817 mutex_unlock(&sev_bitmap_lock);
1820 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1822 struct sev_data_decommission *decommission;
1823 struct sev_data_deactivate *data;
1828 data = kzalloc(sizeof(*data), GFP_KERNEL);
1832 /* deactivate handle */
1833 data->handle = handle;
1835 /* Guard DEACTIVATE against WBINVD/DF_FLUSH used in ASID recycling */
1836 down_read(&sev_deactivate_lock);
1837 sev_guest_deactivate(data, NULL);
1838 up_read(&sev_deactivate_lock);
1842 decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1846 /* decommission handle */
1847 decommission->handle = handle;
1848 sev_guest_decommission(decommission, NULL);
1850 kfree(decommission);
1853 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1854 unsigned long ulen, unsigned long *n,
1857 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1858 unsigned long npages, npinned, size;
1859 unsigned long locked, lock_limit;
1860 struct page **pages;
1861 unsigned long first, last;
1863 if (ulen == 0 || uaddr + ulen < uaddr)
1866 /* Calculate number of pages. */
1867 first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1868 last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1869 npages = (last - first + 1);
1871 locked = sev->pages_locked + npages;
1872 lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1873 if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1874 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1878 /* Avoid using vmalloc for smaller buffers. */
1879 size = npages * sizeof(struct page *);
1880 if (size > PAGE_SIZE)
1881 pages = __vmalloc(size, GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1884 pages = kmalloc(size, GFP_KERNEL_ACCOUNT);
1889 /* Pin the user virtual address. */
1890 npinned = get_user_pages_fast(uaddr, npages, FOLL_WRITE, pages);
1891 if (npinned != npages) {
1892 pr_err("SEV: Failure locking %lu pages.\n", npages);
1897 sev->pages_locked = locked;
1903 release_pages(pages, npinned);
1909 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1910 unsigned long npages)
1912 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1914 release_pages(pages, npages);
1916 sev->pages_locked -= npages;
1919 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1921 uint8_t *page_virtual;
1924 if (npages == 0 || pages == NULL)
1927 for (i = 0; i < npages; i++) {
1928 page_virtual = kmap_atomic(pages[i]);
1929 clflush_cache_range(page_virtual, PAGE_SIZE);
1930 kunmap_atomic(page_virtual);
1934 static void __unregister_enc_region_locked(struct kvm *kvm,
1935 struct enc_region *region)
1938 * The guest may change the memory encryption attribute from C=0 -> C=1
1939 * or vice versa for this memory range. Lets make sure caches are
1940 * flushed to ensure that guest data gets written into memory with
1943 sev_clflush_pages(region->pages, region->npages);
1945 sev_unpin_memory(kvm, region->pages, region->npages);
1946 list_del(®ion->list);
1950 static struct kvm *svm_vm_alloc(void)
1952 struct kvm_svm *kvm_svm = __vmalloc(sizeof(struct kvm_svm),
1953 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1955 return &kvm_svm->kvm;
1958 static void svm_vm_free(struct kvm *kvm)
1960 vfree(to_kvm_svm(kvm));
1963 static void sev_vm_destroy(struct kvm *kvm)
1965 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1966 struct list_head *head = &sev->regions_list;
1967 struct list_head *pos, *q;
1969 if (!sev_guest(kvm))
1972 mutex_lock(&kvm->lock);
1975 * if userspace was terminated before unregistering the memory regions
1976 * then lets unpin all the registered memory.
1978 if (!list_empty(head)) {
1979 list_for_each_safe(pos, q, head) {
1980 __unregister_enc_region_locked(kvm,
1981 list_entry(pos, struct enc_region, list));
1985 mutex_unlock(&kvm->lock);
1987 sev_unbind_asid(kvm, sev->handle);
1988 sev_asid_free(sev->asid);
1991 static void avic_vm_destroy(struct kvm *kvm)
1993 unsigned long flags;
1994 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1999 if (kvm_svm->avic_logical_id_table_page)
2000 __free_page(kvm_svm->avic_logical_id_table_page);
2001 if (kvm_svm->avic_physical_id_table_page)
2002 __free_page(kvm_svm->avic_physical_id_table_page);
2004 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
2005 hash_del(&kvm_svm->hnode);
2006 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
2009 static void svm_vm_destroy(struct kvm *kvm)
2011 avic_vm_destroy(kvm);
2012 sev_vm_destroy(kvm);
2015 static int avic_vm_init(struct kvm *kvm)
2017 unsigned long flags;
2019 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
2021 struct page *p_page;
2022 struct page *l_page;
2028 /* Allocating physical APIC ID table (4KB) */
2029 p_page = alloc_page(GFP_KERNEL_ACCOUNT);
2033 kvm_svm->avic_physical_id_table_page = p_page;
2034 clear_page(page_address(p_page));
2036 /* Allocating logical APIC ID table (4KB) */
2037 l_page = alloc_page(GFP_KERNEL_ACCOUNT);
2041 kvm_svm->avic_logical_id_table_page = l_page;
2042 clear_page(page_address(l_page));
2044 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
2046 vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
2047 if (vm_id == 0) { /* id is 1-based, zero is not okay */
2048 next_vm_id_wrapped = 1;
2051 /* Is it still in use? Only possible if wrapped at least once */
2052 if (next_vm_id_wrapped) {
2053 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
2054 if (k2->avic_vm_id == vm_id)
2058 kvm_svm->avic_vm_id = vm_id;
2059 hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
2060 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
2065 avic_vm_destroy(kvm);
2069 static int svm_vm_init(struct kvm *kvm)
2072 int ret = avic_vm_init(kvm);
2077 kvm_apicv_init(kvm, avic);
2082 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
2085 unsigned long flags;
2086 struct amd_svm_iommu_ir *ir;
2087 struct vcpu_svm *svm = to_svm(vcpu);
2089 if (!kvm_arch_has_assigned_device(vcpu->kvm))
2093 * Here, we go through the per-vcpu ir_list to update all existing
2094 * interrupt remapping table entry targeting this vcpu.
2096 spin_lock_irqsave(&svm->ir_list_lock, flags);
2098 if (list_empty(&svm->ir_list))
2101 list_for_each_entry(ir, &svm->ir_list, node) {
2102 ret = amd_iommu_update_ga(cpu, r, ir->data);
2107 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2111 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2114 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2115 int h_physical_id = kvm_cpu_get_apicid(cpu);
2116 struct vcpu_svm *svm = to_svm(vcpu);
2118 if (!kvm_vcpu_apicv_active(vcpu))
2122 * Since the host physical APIC id is 8 bits,
2123 * we can support host APIC ID upto 255.
2125 if (WARN_ON(h_physical_id > AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK))
2128 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2129 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2131 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2132 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2134 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2135 if (svm->avic_is_running)
2136 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2138 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2139 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2140 svm->avic_is_running);
2143 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2146 struct vcpu_svm *svm = to_svm(vcpu);
2148 if (!kvm_vcpu_apicv_active(vcpu))
2151 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2152 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2153 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2155 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2156 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2160 * This function is called during VCPU halt/unhalt.
2162 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2164 struct vcpu_svm *svm = to_svm(vcpu);
2166 svm->avic_is_running = is_run;
2168 avic_vcpu_load(vcpu, vcpu->cpu);
2170 avic_vcpu_put(vcpu);
2173 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2175 struct vcpu_svm *svm = to_svm(vcpu);
2180 svm->virt_spec_ctrl = 0;
2183 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2184 MSR_IA32_APICBASE_ENABLE;
2185 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2186 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2190 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2191 kvm_rdx_write(vcpu, eax);
2193 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2194 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2197 static int avic_init_vcpu(struct vcpu_svm *svm)
2201 if (!kvm_vcpu_apicv_active(&svm->vcpu))
2204 ret = avic_init_backing_page(&svm->vcpu);
2208 INIT_LIST_HEAD(&svm->ir_list);
2209 spin_lock_init(&svm->ir_list_lock);
2210 svm->dfr_reg = APIC_DFR_FLAT;
2215 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
2217 struct vcpu_svm *svm;
2219 struct page *msrpm_pages;
2220 struct page *hsave_page;
2221 struct page *nested_msrpm_pages;
2224 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
2228 page = alloc_page(GFP_KERNEL_ACCOUNT);
2232 msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2236 nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2237 if (!nested_msrpm_pages)
2240 hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
2244 err = avic_init_vcpu(svm);
2248 /* We initialize this flag to true to make sure that the is_running
2249 * bit would be set the first time the vcpu is loaded.
2251 if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
2252 svm->avic_is_running = true;
2254 svm->nested.hsave = page_address(hsave_page);
2256 svm->msrpm = page_address(msrpm_pages);
2257 svm_vcpu_init_msrpm(svm->msrpm);
2259 svm->nested.msrpm = page_address(nested_msrpm_pages);
2260 svm_vcpu_init_msrpm(svm->nested.msrpm);
2262 svm->vmcb = page_address(page);
2263 clear_page(svm->vmcb);
2264 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2265 svm->asid_generation = 0;
2268 svm_init_osvw(vcpu);
2269 vcpu->arch.microcode_version = 0x01000065;
2274 __free_page(hsave_page);
2276 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2278 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2285 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2289 for_each_online_cpu(i)
2290 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2293 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2295 struct vcpu_svm *svm = to_svm(vcpu);
2298 * The vmcb page can be recycled, causing a false negative in
2299 * svm_vcpu_load(). So, ensure that no logical CPU has this
2300 * vmcb page recorded as its current vmcb.
2302 svm_clear_current_vmcb(svm->vmcb);
2304 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2305 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2306 __free_page(virt_to_page(svm->nested.hsave));
2307 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2310 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2312 struct vcpu_svm *svm = to_svm(vcpu);
2313 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2316 if (unlikely(cpu != vcpu->cpu)) {
2317 svm->asid_generation = 0;
2318 mark_all_dirty(svm->vmcb);
2321 #ifdef CONFIG_X86_64
2322 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2324 savesegment(fs, svm->host.fs);
2325 savesegment(gs, svm->host.gs);
2326 svm->host.ldt = kvm_read_ldt();
2328 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2329 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2331 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2332 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2333 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2334 __this_cpu_write(current_tsc_ratio, tsc_ratio);
2335 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2338 /* This assumes that the kernel never uses MSR_TSC_AUX */
2339 if (static_cpu_has(X86_FEATURE_RDTSCP))
2340 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2342 if (sd->current_vmcb != svm->vmcb) {
2343 sd->current_vmcb = svm->vmcb;
2344 indirect_branch_prediction_barrier();
2346 avic_vcpu_load(vcpu, cpu);
2349 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2351 struct vcpu_svm *svm = to_svm(vcpu);
2354 avic_vcpu_put(vcpu);
2356 ++vcpu->stat.host_state_reload;
2357 kvm_load_ldt(svm->host.ldt);
2358 #ifdef CONFIG_X86_64
2359 loadsegment(fs, svm->host.fs);
2360 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2361 load_gs_index(svm->host.gs);
2363 #ifdef CONFIG_X86_32_LAZY_GS
2364 loadsegment(gs, svm->host.gs);
2367 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2368 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2371 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2373 avic_set_running(vcpu, false);
2376 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2378 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
2379 kvm_vcpu_update_apicv(vcpu);
2380 avic_set_running(vcpu, true);
2383 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2385 struct vcpu_svm *svm = to_svm(vcpu);
2386 unsigned long rflags = svm->vmcb->save.rflags;
2388 if (svm->nmi_singlestep) {
2389 /* Hide our flags if they were not set by the guest */
2390 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2391 rflags &= ~X86_EFLAGS_TF;
2392 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2393 rflags &= ~X86_EFLAGS_RF;
2398 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2400 if (to_svm(vcpu)->nmi_singlestep)
2401 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2404 * Any change of EFLAGS.VM is accompanied by a reload of SS
2405 * (caused by either a task switch or an inter-privilege IRET),
2406 * so we do not need to update the CPL here.
2408 to_svm(vcpu)->vmcb->save.rflags = rflags;
2411 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2414 case VCPU_EXREG_PDPTR:
2415 BUG_ON(!npt_enabled);
2416 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2423 static void svm_set_vintr(struct vcpu_svm *svm)
2425 set_intercept(svm, INTERCEPT_VINTR);
2428 static void svm_clear_vintr(struct vcpu_svm *svm)
2430 clr_intercept(svm, INTERCEPT_VINTR);
2433 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2435 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2438 case VCPU_SREG_CS: return &save->cs;
2439 case VCPU_SREG_DS: return &save->ds;
2440 case VCPU_SREG_ES: return &save->es;
2441 case VCPU_SREG_FS: return &save->fs;
2442 case VCPU_SREG_GS: return &save->gs;
2443 case VCPU_SREG_SS: return &save->ss;
2444 case VCPU_SREG_TR: return &save->tr;
2445 case VCPU_SREG_LDTR: return &save->ldtr;
2451 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2453 struct vmcb_seg *s = svm_seg(vcpu, seg);
2458 static void svm_get_segment(struct kvm_vcpu *vcpu,
2459 struct kvm_segment *var, int seg)
2461 struct vmcb_seg *s = svm_seg(vcpu, seg);
2463 var->base = s->base;
2464 var->limit = s->limit;
2465 var->selector = s->selector;
2466 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2467 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2468 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2469 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2470 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2471 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2472 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2475 * AMD CPUs circa 2014 track the G bit for all segments except CS.
2476 * However, the SVM spec states that the G bit is not observed by the
2477 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2478 * So let's synthesize a legal G bit for all segments, this helps
2479 * running KVM nested. It also helps cross-vendor migration, because
2480 * Intel's vmentry has a check on the 'G' bit.
2482 var->g = s->limit > 0xfffff;
2485 * AMD's VMCB does not have an explicit unusable field, so emulate it
2486 * for cross vendor migration purposes by "not present"
2488 var->unusable = !var->present;
2493 * Work around a bug where the busy flag in the tr selector
2503 * The accessed bit must always be set in the segment
2504 * descriptor cache, although it can be cleared in the
2505 * descriptor, the cached bit always remains at 1. Since
2506 * Intel has a check on this, set it here to support
2507 * cross-vendor migration.
2514 * On AMD CPUs sometimes the DB bit in the segment
2515 * descriptor is left as 1, although the whole segment has
2516 * been made unusable. Clear it here to pass an Intel VMX
2517 * entry check when cross vendor migrating.
2521 /* This is symmetric with svm_set_segment() */
2522 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2527 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2529 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2534 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2536 struct vcpu_svm *svm = to_svm(vcpu);
2538 dt->size = svm->vmcb->save.idtr.limit;
2539 dt->address = svm->vmcb->save.idtr.base;
2542 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2544 struct vcpu_svm *svm = to_svm(vcpu);
2546 svm->vmcb->save.idtr.limit = dt->size;
2547 svm->vmcb->save.idtr.base = dt->address ;
2548 mark_dirty(svm->vmcb, VMCB_DT);
2551 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2553 struct vcpu_svm *svm = to_svm(vcpu);
2555 dt->size = svm->vmcb->save.gdtr.limit;
2556 dt->address = svm->vmcb->save.gdtr.base;
2559 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2561 struct vcpu_svm *svm = to_svm(vcpu);
2563 svm->vmcb->save.gdtr.limit = dt->size;
2564 svm->vmcb->save.gdtr.base = dt->address ;
2565 mark_dirty(svm->vmcb, VMCB_DT);
2568 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2572 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2576 static void update_cr0_intercept(struct vcpu_svm *svm)
2578 ulong gcr0 = svm->vcpu.arch.cr0;
2579 u64 *hcr0 = &svm->vmcb->save.cr0;
2581 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2582 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2584 mark_dirty(svm->vmcb, VMCB_CR);
2586 if (gcr0 == *hcr0) {
2587 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2588 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2590 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2591 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2595 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2597 struct vcpu_svm *svm = to_svm(vcpu);
2599 #ifdef CONFIG_X86_64
2600 if (vcpu->arch.efer & EFER_LME) {
2601 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2602 vcpu->arch.efer |= EFER_LMA;
2603 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2606 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2607 vcpu->arch.efer &= ~EFER_LMA;
2608 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2612 vcpu->arch.cr0 = cr0;
2615 cr0 |= X86_CR0_PG | X86_CR0_WP;
2618 * re-enable caching here because the QEMU bios
2619 * does not do it - this results in some delay at
2622 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2623 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2624 svm->vmcb->save.cr0 = cr0;
2625 mark_dirty(svm->vmcb, VMCB_CR);
2626 update_cr0_intercept(svm);
2629 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2631 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2632 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2634 if (cr4 & X86_CR4_VMXE)
2637 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2638 svm_flush_tlb(vcpu, true);
2640 vcpu->arch.cr4 = cr4;
2643 cr4 |= host_cr4_mce;
2644 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2645 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2649 static void svm_set_segment(struct kvm_vcpu *vcpu,
2650 struct kvm_segment *var, int seg)
2652 struct vcpu_svm *svm = to_svm(vcpu);
2653 struct vmcb_seg *s = svm_seg(vcpu, seg);
2655 s->base = var->base;
2656 s->limit = var->limit;
2657 s->selector = var->selector;
2658 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2659 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2660 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2661 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2662 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2663 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2664 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2665 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2668 * This is always accurate, except if SYSRET returned to a segment
2669 * with SS.DPL != 3. Intel does not have this quirk, and always
2670 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2671 * would entail passing the CPL to userspace and back.
2673 if (seg == VCPU_SREG_SS)
2674 /* This is symmetric with svm_get_segment() */
2675 svm->vmcb->save.cpl = (var->dpl & 3);
2677 mark_dirty(svm->vmcb, VMCB_SEG);
2680 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2682 struct vcpu_svm *svm = to_svm(vcpu);
2684 clr_exception_intercept(svm, BP_VECTOR);
2686 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2687 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2688 set_exception_intercept(svm, BP_VECTOR);
2690 vcpu->guest_debug = 0;
2693 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2695 if (sd->next_asid > sd->max_asid) {
2696 ++sd->asid_generation;
2697 sd->next_asid = sd->min_asid;
2698 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2701 svm->asid_generation = sd->asid_generation;
2702 svm->vmcb->control.asid = sd->next_asid++;
2704 mark_dirty(svm->vmcb, VMCB_ASID);
2707 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2709 return to_svm(vcpu)->vmcb->save.dr6;
2712 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2714 struct vcpu_svm *svm = to_svm(vcpu);
2716 svm->vmcb->save.dr6 = value;
2717 mark_dirty(svm->vmcb, VMCB_DR);
2720 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2722 struct vcpu_svm *svm = to_svm(vcpu);
2724 get_debugreg(vcpu->arch.db[0], 0);
2725 get_debugreg(vcpu->arch.db[1], 1);
2726 get_debugreg(vcpu->arch.db[2], 2);
2727 get_debugreg(vcpu->arch.db[3], 3);
2728 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2729 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2731 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2732 set_dr_intercepts(svm);
2735 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2737 struct vcpu_svm *svm = to_svm(vcpu);
2739 svm->vmcb->save.dr7 = value;
2740 mark_dirty(svm->vmcb, VMCB_DR);
2743 static int pf_interception(struct vcpu_svm *svm)
2745 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2746 u64 error_code = svm->vmcb->control.exit_info_1;
2748 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2749 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2750 svm->vmcb->control.insn_bytes : NULL,
2751 svm->vmcb->control.insn_len);
2754 static int npf_interception(struct vcpu_svm *svm)
2756 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2757 u64 error_code = svm->vmcb->control.exit_info_1;
2759 trace_kvm_page_fault(fault_address, error_code);
2760 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2761 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2762 svm->vmcb->control.insn_bytes : NULL,
2763 svm->vmcb->control.insn_len);
2766 static int db_interception(struct vcpu_svm *svm)
2768 struct kvm_run *kvm_run = svm->vcpu.run;
2769 struct kvm_vcpu *vcpu = &svm->vcpu;
2771 if (!(svm->vcpu.guest_debug &
2772 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2773 !svm->nmi_singlestep) {
2774 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2778 if (svm->nmi_singlestep) {
2779 disable_nmi_singlestep(svm);
2780 /* Make sure we check for pending NMIs upon entry */
2781 kvm_make_request(KVM_REQ_EVENT, vcpu);
2784 if (svm->vcpu.guest_debug &
2785 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2786 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2787 kvm_run->debug.arch.pc =
2788 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2789 kvm_run->debug.arch.exception = DB_VECTOR;
2796 static int bp_interception(struct vcpu_svm *svm)
2798 struct kvm_run *kvm_run = svm->vcpu.run;
2800 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2801 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2802 kvm_run->debug.arch.exception = BP_VECTOR;
2806 static int ud_interception(struct vcpu_svm *svm)
2808 return handle_ud(&svm->vcpu);
2811 static int ac_interception(struct vcpu_svm *svm)
2813 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2817 static int gp_interception(struct vcpu_svm *svm)
2819 struct kvm_vcpu *vcpu = &svm->vcpu;
2820 u32 error_code = svm->vmcb->control.exit_info_1;
2822 WARN_ON_ONCE(!enable_vmware_backdoor);
2825 * VMware backdoor emulation on #GP interception only handles IN{S},
2826 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
2829 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2832 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
2835 static bool is_erratum_383(void)
2840 if (!erratum_383_found)
2843 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2847 /* Bit 62 may or may not be set for this mce */
2848 value &= ~(1ULL << 62);
2850 if (value != 0xb600000000010015ULL)
2853 /* Clear MCi_STATUS registers */
2854 for (i = 0; i < 6; ++i)
2855 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2857 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2861 value &= ~(1ULL << 2);
2862 low = lower_32_bits(value);
2863 high = upper_32_bits(value);
2865 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2868 /* Flush tlb to evict multi-match entries */
2874 static void svm_handle_mce(struct vcpu_svm *svm)
2876 if (is_erratum_383()) {
2878 * Erratum 383 triggered. Guest state is corrupt so kill the
2881 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2883 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2889 * On an #MC intercept the MCE handler is not called automatically in
2890 * the host. So do it by hand here.
2894 /* not sure if we ever come back to this point */
2899 static int mc_interception(struct vcpu_svm *svm)
2904 static int shutdown_interception(struct vcpu_svm *svm)
2906 struct kvm_run *kvm_run = svm->vcpu.run;
2909 * VMCB is undefined after a SHUTDOWN intercept
2910 * so reinitialize it.
2912 clear_page(svm->vmcb);
2915 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2919 static int io_interception(struct vcpu_svm *svm)
2921 struct kvm_vcpu *vcpu = &svm->vcpu;
2922 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2923 int size, in, string;
2926 ++svm->vcpu.stat.io_exits;
2927 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2928 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2930 return kvm_emulate_instruction(vcpu, 0);
2932 port = io_info >> 16;
2933 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2934 svm->next_rip = svm->vmcb->control.exit_info_2;
2936 return kvm_fast_pio(&svm->vcpu, size, port, in);
2939 static int nmi_interception(struct vcpu_svm *svm)
2944 static int intr_interception(struct vcpu_svm *svm)
2946 ++svm->vcpu.stat.irq_exits;
2950 static int nop_on_interception(struct vcpu_svm *svm)
2955 static int halt_interception(struct vcpu_svm *svm)
2957 return kvm_emulate_halt(&svm->vcpu);
2960 static int vmmcall_interception(struct vcpu_svm *svm)
2962 return kvm_emulate_hypercall(&svm->vcpu);
2965 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2967 struct vcpu_svm *svm = to_svm(vcpu);
2969 return svm->nested.nested_cr3;
2972 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2974 struct vcpu_svm *svm = to_svm(vcpu);
2975 u64 cr3 = svm->nested.nested_cr3;
2979 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2980 offset_in_page(cr3) + index * 8, 8);
2986 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2989 struct vcpu_svm *svm = to_svm(vcpu);
2991 svm->vmcb->control.nested_cr3 = __sme_set(root);
2992 mark_dirty(svm->vmcb, VMCB_NPT);
2995 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2996 struct x86_exception *fault)
2998 struct vcpu_svm *svm = to_svm(vcpu);
3000 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
3002 * TODO: track the cause of the nested page fault, and
3003 * correctly fill in the high bits of exit_info_1.
3005 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
3006 svm->vmcb->control.exit_code_hi = 0;
3007 svm->vmcb->control.exit_info_1 = (1ULL << 32);
3008 svm->vmcb->control.exit_info_2 = fault->address;
3011 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
3012 svm->vmcb->control.exit_info_1 |= fault->error_code;
3015 * The present bit is always zero for page structure faults on real
3018 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
3019 svm->vmcb->control.exit_info_1 &= ~1;
3021 nested_svm_vmexit(svm);
3024 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
3026 WARN_ON(mmu_is_nested(vcpu));
3028 vcpu->arch.mmu = &vcpu->arch.guest_mmu;
3029 kvm_init_shadow_mmu(vcpu);
3030 vcpu->arch.mmu->set_cr3 = nested_svm_set_tdp_cr3;
3031 vcpu->arch.mmu->get_cr3 = nested_svm_get_tdp_cr3;
3032 vcpu->arch.mmu->get_pdptr = nested_svm_get_tdp_pdptr;
3033 vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
3034 vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu);
3035 reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
3036 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
3039 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
3041 vcpu->arch.mmu = &vcpu->arch.root_mmu;
3042 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
3045 static int nested_svm_check_permissions(struct vcpu_svm *svm)
3047 if (!(svm->vcpu.arch.efer & EFER_SVME) ||
3048 !is_paging(&svm->vcpu)) {
3049 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3053 if (svm->vmcb->save.cpl) {
3054 kvm_inject_gp(&svm->vcpu, 0);
3061 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
3062 bool has_error_code, u32 error_code)
3066 if (!is_guest_mode(&svm->vcpu))
3069 vmexit = nested_svm_intercept(svm);
3070 if (vmexit != NESTED_EXIT_DONE)
3073 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
3074 svm->vmcb->control.exit_code_hi = 0;
3075 svm->vmcb->control.exit_info_1 = error_code;
3078 * EXITINFO2 is undefined for all exception intercepts other
3081 if (svm->vcpu.arch.exception.nested_apf)
3082 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
3083 else if (svm->vcpu.arch.exception.has_payload)
3084 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
3086 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
3088 svm->nested.exit_required = true;
3092 /* This function returns true if it is save to enable the irq window */
3093 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3095 if (!is_guest_mode(&svm->vcpu))
3098 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3101 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3105 * if vmexit was already requested (by intercepted exception
3106 * for instance) do not overwrite it with "external interrupt"
3109 if (svm->nested.exit_required)
3112 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
3113 svm->vmcb->control.exit_info_1 = 0;
3114 svm->vmcb->control.exit_info_2 = 0;
3116 if (svm->nested.intercept & 1ULL) {
3118 * The #vmexit can't be emulated here directly because this
3119 * code path runs with irqs and preemption disabled. A
3120 * #vmexit emulation might sleep. Only signal request for
3123 svm->nested.exit_required = true;
3124 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3131 /* This function returns true if it is save to enable the nmi window */
3132 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3134 if (!is_guest_mode(&svm->vcpu))
3137 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3140 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3141 svm->nested.exit_required = true;
3146 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3148 unsigned port, size, iopm_len;
3153 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3154 return NESTED_EXIT_HOST;
3156 port = svm->vmcb->control.exit_info_1 >> 16;
3157 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3158 SVM_IOIO_SIZE_SHIFT;
3159 gpa = svm->nested.vmcb_iopm + (port / 8);
3160 start_bit = port % 8;
3161 iopm_len = (start_bit + size > 8) ? 2 : 1;
3162 mask = (0xf >> (4 - size)) << start_bit;
3165 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3166 return NESTED_EXIT_DONE;
3168 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3171 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3173 u32 offset, msr, value;
3176 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3177 return NESTED_EXIT_HOST;
3179 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3180 offset = svm_msrpm_offset(msr);
3181 write = svm->vmcb->control.exit_info_1 & 1;
3182 mask = 1 << ((2 * (msr & 0xf)) + write);
3184 if (offset == MSR_INVALID)
3185 return NESTED_EXIT_DONE;
3187 /* Offset is in 32 bit units but need in 8 bit units */
3190 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3191 return NESTED_EXIT_DONE;
3193 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3196 /* DB exceptions for our internal use must not cause vmexit */
3197 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3201 /* if we're not singlestepping, it's not ours */
3202 if (!svm->nmi_singlestep)
3203 return NESTED_EXIT_DONE;
3205 /* if it's not a singlestep exception, it's not ours */
3206 if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3207 return NESTED_EXIT_DONE;
3208 if (!(dr6 & DR6_BS))
3209 return NESTED_EXIT_DONE;
3211 /* if the guest is singlestepping, it should get the vmexit */
3212 if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3213 disable_nmi_singlestep(svm);
3214 return NESTED_EXIT_DONE;
3217 /* it's ours, the nested hypervisor must not see this one */
3218 return NESTED_EXIT_HOST;
3221 static int nested_svm_exit_special(struct vcpu_svm *svm)
3223 u32 exit_code = svm->vmcb->control.exit_code;
3225 switch (exit_code) {
3228 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3229 return NESTED_EXIT_HOST;
3231 /* For now we are always handling NPFs when using them */
3233 return NESTED_EXIT_HOST;
3235 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3236 /* When we're shadowing, trap PFs, but not async PF */
3237 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3238 return NESTED_EXIT_HOST;
3244 return NESTED_EXIT_CONTINUE;
3248 * If this function returns true, this #vmexit was already handled
3250 static int nested_svm_intercept(struct vcpu_svm *svm)
3252 u32 exit_code = svm->vmcb->control.exit_code;
3253 int vmexit = NESTED_EXIT_HOST;
3255 switch (exit_code) {
3257 vmexit = nested_svm_exit_handled_msr(svm);
3260 vmexit = nested_svm_intercept_ioio(svm);
3262 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3263 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3264 if (svm->nested.intercept_cr & bit)
3265 vmexit = NESTED_EXIT_DONE;
3268 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3269 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3270 if (svm->nested.intercept_dr & bit)
3271 vmexit = NESTED_EXIT_DONE;
3274 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3275 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3276 if (svm->nested.intercept_exceptions & excp_bits) {
3277 if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3278 vmexit = nested_svm_intercept_db(svm);
3280 vmexit = NESTED_EXIT_DONE;
3282 /* async page fault always cause vmexit */
3283 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3284 svm->vcpu.arch.exception.nested_apf != 0)
3285 vmexit = NESTED_EXIT_DONE;
3288 case SVM_EXIT_ERR: {
3289 vmexit = NESTED_EXIT_DONE;
3293 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3294 if (svm->nested.intercept & exit_bits)
3295 vmexit = NESTED_EXIT_DONE;
3302 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3306 vmexit = nested_svm_intercept(svm);
3308 if (vmexit == NESTED_EXIT_DONE)
3309 nested_svm_vmexit(svm);
3314 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3316 struct vmcb_control_area *dst = &dst_vmcb->control;
3317 struct vmcb_control_area *from = &from_vmcb->control;
3319 dst->intercept_cr = from->intercept_cr;
3320 dst->intercept_dr = from->intercept_dr;
3321 dst->intercept_exceptions = from->intercept_exceptions;
3322 dst->intercept = from->intercept;
3323 dst->iopm_base_pa = from->iopm_base_pa;
3324 dst->msrpm_base_pa = from->msrpm_base_pa;
3325 dst->tsc_offset = from->tsc_offset;
3326 dst->asid = from->asid;
3327 dst->tlb_ctl = from->tlb_ctl;
3328 dst->int_ctl = from->int_ctl;
3329 dst->int_vector = from->int_vector;
3330 dst->int_state = from->int_state;
3331 dst->exit_code = from->exit_code;
3332 dst->exit_code_hi = from->exit_code_hi;
3333 dst->exit_info_1 = from->exit_info_1;
3334 dst->exit_info_2 = from->exit_info_2;
3335 dst->exit_int_info = from->exit_int_info;
3336 dst->exit_int_info_err = from->exit_int_info_err;
3337 dst->nested_ctl = from->nested_ctl;
3338 dst->event_inj = from->event_inj;
3339 dst->event_inj_err = from->event_inj_err;
3340 dst->nested_cr3 = from->nested_cr3;
3341 dst->virt_ext = from->virt_ext;
3342 dst->pause_filter_count = from->pause_filter_count;
3343 dst->pause_filter_thresh = from->pause_filter_thresh;
3346 static int nested_svm_vmexit(struct vcpu_svm *svm)
3349 struct vmcb *nested_vmcb;
3350 struct vmcb *hsave = svm->nested.hsave;
3351 struct vmcb *vmcb = svm->vmcb;
3352 struct kvm_host_map map;
3354 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3355 vmcb->control.exit_info_1,
3356 vmcb->control.exit_info_2,
3357 vmcb->control.exit_int_info,
3358 vmcb->control.exit_int_info_err,
3361 rc = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->nested.vmcb), &map);
3364 kvm_inject_gp(&svm->vcpu, 0);
3368 nested_vmcb = map.hva;
3370 /* Exit Guest-Mode */
3371 leave_guest_mode(&svm->vcpu);
3372 svm->nested.vmcb = 0;
3374 /* Give the current vmcb to the guest */
3377 nested_vmcb->save.es = vmcb->save.es;
3378 nested_vmcb->save.cs = vmcb->save.cs;
3379 nested_vmcb->save.ss = vmcb->save.ss;
3380 nested_vmcb->save.ds = vmcb->save.ds;
3381 nested_vmcb->save.gdtr = vmcb->save.gdtr;
3382 nested_vmcb->save.idtr = vmcb->save.idtr;
3383 nested_vmcb->save.efer = svm->vcpu.arch.efer;
3384 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
3385 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
3386 nested_vmcb->save.cr2 = vmcb->save.cr2;
3387 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
3388 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3389 nested_vmcb->save.rip = vmcb->save.rip;
3390 nested_vmcb->save.rsp = vmcb->save.rsp;
3391 nested_vmcb->save.rax = vmcb->save.rax;
3392 nested_vmcb->save.dr7 = vmcb->save.dr7;
3393 nested_vmcb->save.dr6 = vmcb->save.dr6;
3394 nested_vmcb->save.cpl = vmcb->save.cpl;
3396 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
3397 nested_vmcb->control.int_vector = vmcb->control.int_vector;
3398 nested_vmcb->control.int_state = vmcb->control.int_state;
3399 nested_vmcb->control.exit_code = vmcb->control.exit_code;
3400 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
3401 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
3402 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
3403 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
3404 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3406 if (svm->nrips_enabled)
3407 nested_vmcb->control.next_rip = vmcb->control.next_rip;
3410 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3411 * to make sure that we do not lose injected events. So check event_inj
3412 * here and copy it to exit_int_info if it is valid.
3413 * Exit_int_info and event_inj can't be both valid because the case
3414 * below only happens on a VMRUN instruction intercept which has
3415 * no valid exit_int_info set.
3417 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3418 struct vmcb_control_area *nc = &nested_vmcb->control;
3420 nc->exit_int_info = vmcb->control.event_inj;
3421 nc->exit_int_info_err = vmcb->control.event_inj_err;
3424 nested_vmcb->control.tlb_ctl = 0;
3425 nested_vmcb->control.event_inj = 0;
3426 nested_vmcb->control.event_inj_err = 0;
3428 nested_vmcb->control.pause_filter_count =
3429 svm->vmcb->control.pause_filter_count;
3430 nested_vmcb->control.pause_filter_thresh =
3431 svm->vmcb->control.pause_filter_thresh;
3433 /* We always set V_INTR_MASKING and remember the old value in hflags */
3434 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3435 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3437 /* Restore the original control entries */
3438 copy_vmcb_control_area(vmcb, hsave);
3440 svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3441 kvm_clear_exception_queue(&svm->vcpu);
3442 kvm_clear_interrupt_queue(&svm->vcpu);
3444 svm->nested.nested_cr3 = 0;
3446 /* Restore selected save entries */
3447 svm->vmcb->save.es = hsave->save.es;
3448 svm->vmcb->save.cs = hsave->save.cs;
3449 svm->vmcb->save.ss = hsave->save.ss;
3450 svm->vmcb->save.ds = hsave->save.ds;
3451 svm->vmcb->save.gdtr = hsave->save.gdtr;
3452 svm->vmcb->save.idtr = hsave->save.idtr;
3453 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3454 svm_set_efer(&svm->vcpu, hsave->save.efer);
3455 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3456 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3458 svm->vmcb->save.cr3 = hsave->save.cr3;
3459 svm->vcpu.arch.cr3 = hsave->save.cr3;
3461 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3463 kvm_rax_write(&svm->vcpu, hsave->save.rax);
3464 kvm_rsp_write(&svm->vcpu, hsave->save.rsp);
3465 kvm_rip_write(&svm->vcpu, hsave->save.rip);
3466 svm->vmcb->save.dr7 = 0;
3467 svm->vmcb->save.cpl = 0;
3468 svm->vmcb->control.exit_int_info = 0;
3470 mark_all_dirty(svm->vmcb);
3472 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3474 nested_svm_uninit_mmu_context(&svm->vcpu);
3475 kvm_mmu_reset_context(&svm->vcpu);
3476 kvm_mmu_load(&svm->vcpu);
3479 * Drop what we picked up for L2 via svm_complete_interrupts() so it
3480 * doesn't end up in L1.
3482 svm->vcpu.arch.nmi_injected = false;
3483 kvm_clear_exception_queue(&svm->vcpu);
3484 kvm_clear_interrupt_queue(&svm->vcpu);
3489 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3492 * This function merges the msr permission bitmaps of kvm and the
3493 * nested vmcb. It is optimized in that it only merges the parts where
3494 * the kvm msr permission bitmap may contain zero bits
3498 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3501 for (i = 0; i < MSRPM_OFFSETS; i++) {
3505 if (msrpm_offsets[i] == 0xffffffff)
3508 p = msrpm_offsets[i];
3509 offset = svm->nested.vmcb_msrpm + (p * 4);
3511 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3514 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3517 svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3522 static bool nested_vmcb_checks(struct vmcb *vmcb)
3524 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3527 if (vmcb->control.asid == 0)
3530 if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3537 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3538 struct vmcb *nested_vmcb, struct kvm_host_map *map)
3540 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3541 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3543 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3545 if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3546 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3547 nested_svm_init_mmu_context(&svm->vcpu);
3550 /* Load the nested guest state */
3551 svm->vmcb->save.es = nested_vmcb->save.es;
3552 svm->vmcb->save.cs = nested_vmcb->save.cs;
3553 svm->vmcb->save.ss = nested_vmcb->save.ss;
3554 svm->vmcb->save.ds = nested_vmcb->save.ds;
3555 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3556 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3557 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3558 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3559 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3560 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3562 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3563 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3565 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3567 /* Guest paging mode is active - reset mmu */
3568 kvm_mmu_reset_context(&svm->vcpu);
3570 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3571 kvm_rax_write(&svm->vcpu, nested_vmcb->save.rax);
3572 kvm_rsp_write(&svm->vcpu, nested_vmcb->save.rsp);
3573 kvm_rip_write(&svm->vcpu, nested_vmcb->save.rip);
3575 /* In case we don't even reach vcpu_run, the fields are not updated */
3576 svm->vmcb->save.rax = nested_vmcb->save.rax;
3577 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3578 svm->vmcb->save.rip = nested_vmcb->save.rip;
3579 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3580 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3581 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3583 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3584 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3586 /* cache intercepts */
3587 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3588 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3589 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3590 svm->nested.intercept = nested_vmcb->control.intercept;
3592 svm_flush_tlb(&svm->vcpu, true);
3593 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3594 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3595 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3597 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3599 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3600 /* We only want the cr8 intercept bits of the guest */
3601 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3602 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3605 /* We don't want to see VMMCALLs from a nested guest */
3606 clr_intercept(svm, INTERCEPT_VMMCALL);
3608 svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3609 svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3611 svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3612 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3613 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3614 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3615 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3617 svm->vmcb->control.pause_filter_count =
3618 nested_vmcb->control.pause_filter_count;
3619 svm->vmcb->control.pause_filter_thresh =
3620 nested_vmcb->control.pause_filter_thresh;
3622 kvm_vcpu_unmap(&svm->vcpu, map, true);
3624 /* Enter Guest-Mode */
3625 enter_guest_mode(&svm->vcpu);
3628 * Merge guest and host intercepts - must be called with vcpu in
3629 * guest-mode to take affect here
3631 recalc_intercepts(svm);
3633 svm->nested.vmcb = vmcb_gpa;
3637 mark_all_dirty(svm->vmcb);
3640 static int nested_svm_vmrun(struct vcpu_svm *svm)
3643 struct vmcb *nested_vmcb;
3644 struct vmcb *hsave = svm->nested.hsave;
3645 struct vmcb *vmcb = svm->vmcb;
3646 struct kvm_host_map map;
3649 vmcb_gpa = svm->vmcb->save.rax;
3651 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb_gpa), &map);
3652 if (ret == -EINVAL) {
3653 kvm_inject_gp(&svm->vcpu, 0);
3656 return kvm_skip_emulated_instruction(&svm->vcpu);
3659 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3661 nested_vmcb = map.hva;
3663 if (!nested_vmcb_checks(nested_vmcb)) {
3664 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
3665 nested_vmcb->control.exit_code_hi = 0;
3666 nested_vmcb->control.exit_info_1 = 0;
3667 nested_vmcb->control.exit_info_2 = 0;
3669 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3674 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3675 nested_vmcb->save.rip,
3676 nested_vmcb->control.int_ctl,
3677 nested_vmcb->control.event_inj,
3678 nested_vmcb->control.nested_ctl);
3680 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3681 nested_vmcb->control.intercept_cr >> 16,
3682 nested_vmcb->control.intercept_exceptions,
3683 nested_vmcb->control.intercept);
3685 /* Clear internal status */
3686 kvm_clear_exception_queue(&svm->vcpu);
3687 kvm_clear_interrupt_queue(&svm->vcpu);
3690 * Save the old vmcb, so we don't need to pick what we save, but can
3691 * restore everything when a VMEXIT occurs
3693 hsave->save.es = vmcb->save.es;
3694 hsave->save.cs = vmcb->save.cs;
3695 hsave->save.ss = vmcb->save.ss;
3696 hsave->save.ds = vmcb->save.ds;
3697 hsave->save.gdtr = vmcb->save.gdtr;
3698 hsave->save.idtr = vmcb->save.idtr;
3699 hsave->save.efer = svm->vcpu.arch.efer;
3700 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
3701 hsave->save.cr4 = svm->vcpu.arch.cr4;
3702 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3703 hsave->save.rip = kvm_rip_read(&svm->vcpu);
3704 hsave->save.rsp = vmcb->save.rsp;
3705 hsave->save.rax = vmcb->save.rax;
3707 hsave->save.cr3 = vmcb->save.cr3;
3709 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
3711 copy_vmcb_control_area(hsave, vmcb);
3713 enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, &map);
3715 if (!nested_svm_vmrun_msrpm(svm)) {
3716 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3717 svm->vmcb->control.exit_code_hi = 0;
3718 svm->vmcb->control.exit_info_1 = 0;
3719 svm->vmcb->control.exit_info_2 = 0;
3721 nested_svm_vmexit(svm);
3727 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3729 to_vmcb->save.fs = from_vmcb->save.fs;
3730 to_vmcb->save.gs = from_vmcb->save.gs;
3731 to_vmcb->save.tr = from_vmcb->save.tr;
3732 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3733 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3734 to_vmcb->save.star = from_vmcb->save.star;
3735 to_vmcb->save.lstar = from_vmcb->save.lstar;
3736 to_vmcb->save.cstar = from_vmcb->save.cstar;
3737 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3738 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3739 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3740 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3743 static int vmload_interception(struct vcpu_svm *svm)
3745 struct vmcb *nested_vmcb;
3746 struct kvm_host_map map;
3749 if (nested_svm_check_permissions(svm))
3752 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3755 kvm_inject_gp(&svm->vcpu, 0);
3759 nested_vmcb = map.hva;
3761 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3763 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3764 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3769 static int vmsave_interception(struct vcpu_svm *svm)
3771 struct vmcb *nested_vmcb;
3772 struct kvm_host_map map;
3775 if (nested_svm_check_permissions(svm))
3778 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3781 kvm_inject_gp(&svm->vcpu, 0);
3785 nested_vmcb = map.hva;
3787 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3789 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3790 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3795 static int vmrun_interception(struct vcpu_svm *svm)
3797 if (nested_svm_check_permissions(svm))
3800 return nested_svm_vmrun(svm);
3803 static int stgi_interception(struct vcpu_svm *svm)
3807 if (nested_svm_check_permissions(svm))
3811 * If VGIF is enabled, the STGI intercept is only added to
3812 * detect the opening of the SMI/NMI window; remove it now.
3814 if (vgif_enabled(svm))
3815 clr_intercept(svm, INTERCEPT_STGI);
3817 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3818 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3825 static int clgi_interception(struct vcpu_svm *svm)
3829 if (nested_svm_check_permissions(svm))
3832 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3836 /* After a CLGI no interrupts should come */
3837 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3838 svm_clear_vintr(svm);
3839 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3840 mark_dirty(svm->vmcb, VMCB_INTR);
3846 static int invlpga_interception(struct vcpu_svm *svm)
3848 struct kvm_vcpu *vcpu = &svm->vcpu;
3850 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
3851 kvm_rax_read(&svm->vcpu));
3853 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3854 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
3856 return kvm_skip_emulated_instruction(&svm->vcpu);
3859 static int skinit_interception(struct vcpu_svm *svm)
3861 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
3863 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3867 static int wbinvd_interception(struct vcpu_svm *svm)
3869 return kvm_emulate_wbinvd(&svm->vcpu);
3872 static int xsetbv_interception(struct vcpu_svm *svm)
3874 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3875 u32 index = kvm_rcx_read(&svm->vcpu);
3877 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3878 return kvm_skip_emulated_instruction(&svm->vcpu);
3884 static int rdpru_interception(struct vcpu_svm *svm)
3886 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3890 static int task_switch_interception(struct vcpu_svm *svm)
3894 int int_type = svm->vmcb->control.exit_int_info &
3895 SVM_EXITINTINFO_TYPE_MASK;
3896 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3898 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3900 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3901 bool has_error_code = false;
3904 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3906 if (svm->vmcb->control.exit_info_2 &
3907 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3908 reason = TASK_SWITCH_IRET;
3909 else if (svm->vmcb->control.exit_info_2 &
3910 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3911 reason = TASK_SWITCH_JMP;
3913 reason = TASK_SWITCH_GATE;
3915 reason = TASK_SWITCH_CALL;
3917 if (reason == TASK_SWITCH_GATE) {
3919 case SVM_EXITINTINFO_TYPE_NMI:
3920 svm->vcpu.arch.nmi_injected = false;
3922 case SVM_EXITINTINFO_TYPE_EXEPT:
3923 if (svm->vmcb->control.exit_info_2 &
3924 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3925 has_error_code = true;
3927 (u32)svm->vmcb->control.exit_info_2;
3929 kvm_clear_exception_queue(&svm->vcpu);
3931 case SVM_EXITINTINFO_TYPE_INTR:
3932 kvm_clear_interrupt_queue(&svm->vcpu);
3939 if (reason != TASK_SWITCH_GATE ||
3940 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3941 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3942 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
3943 if (!skip_emulated_instruction(&svm->vcpu))
3947 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3950 return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3951 has_error_code, error_code);
3954 static int cpuid_interception(struct vcpu_svm *svm)
3956 return kvm_emulate_cpuid(&svm->vcpu);
3959 static int iret_interception(struct vcpu_svm *svm)
3961 ++svm->vcpu.stat.nmi_window_exits;
3962 clr_intercept(svm, INTERCEPT_IRET);
3963 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3964 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3965 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3969 static int invlpg_interception(struct vcpu_svm *svm)
3971 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3972 return kvm_emulate_instruction(&svm->vcpu, 0);
3974 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3975 return kvm_skip_emulated_instruction(&svm->vcpu);
3978 static int emulate_on_interception(struct vcpu_svm *svm)
3980 return kvm_emulate_instruction(&svm->vcpu, 0);
3983 static int rsm_interception(struct vcpu_svm *svm)
3985 return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
3988 static int rdpmc_interception(struct vcpu_svm *svm)
3993 return emulate_on_interception(svm);
3995 err = kvm_rdpmc(&svm->vcpu);
3996 return kvm_complete_insn_gp(&svm->vcpu, err);
3999 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
4002 unsigned long cr0 = svm->vcpu.arch.cr0;
4006 intercept = svm->nested.intercept;
4008 if (!is_guest_mode(&svm->vcpu) ||
4009 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
4012 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
4013 val &= ~SVM_CR0_SELECTIVE_MASK;
4016 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4017 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
4023 #define CR_VALID (1ULL << 63)
4025 static int cr_interception(struct vcpu_svm *svm)
4031 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
4032 return emulate_on_interception(svm);
4034 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
4035 return emulate_on_interception(svm);
4037 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4038 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
4039 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
4041 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
4044 if (cr >= 16) { /* mov to cr */
4046 val = kvm_register_read(&svm->vcpu, reg);
4049 if (!check_selective_cr0_intercepted(svm, val))
4050 err = kvm_set_cr0(&svm->vcpu, val);
4056 err = kvm_set_cr3(&svm->vcpu, val);
4059 err = kvm_set_cr4(&svm->vcpu, val);
4062 err = kvm_set_cr8(&svm->vcpu, val);
4065 WARN(1, "unhandled write to CR%d", cr);
4066 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4069 } else { /* mov from cr */
4072 val = kvm_read_cr0(&svm->vcpu);
4075 val = svm->vcpu.arch.cr2;
4078 val = kvm_read_cr3(&svm->vcpu);
4081 val = kvm_read_cr4(&svm->vcpu);
4084 val = kvm_get_cr8(&svm->vcpu);
4087 WARN(1, "unhandled read from CR%d", cr);
4088 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4091 kvm_register_write(&svm->vcpu, reg, val);
4093 return kvm_complete_insn_gp(&svm->vcpu, err);
4096 static int dr_interception(struct vcpu_svm *svm)
4101 if (svm->vcpu.guest_debug == 0) {
4103 * No more DR vmexits; force a reload of the debug registers
4104 * and reenter on this instruction. The next vmexit will
4105 * retrieve the full state of the debug registers.
4107 clr_dr_intercepts(svm);
4108 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4112 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4113 return emulate_on_interception(svm);
4115 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4116 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4118 if (dr >= 16) { /* mov to DRn */
4119 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4121 val = kvm_register_read(&svm->vcpu, reg);
4122 kvm_set_dr(&svm->vcpu, dr - 16, val);
4124 if (!kvm_require_dr(&svm->vcpu, dr))
4126 kvm_get_dr(&svm->vcpu, dr, &val);
4127 kvm_register_write(&svm->vcpu, reg, val);
4130 return kvm_skip_emulated_instruction(&svm->vcpu);
4133 static int cr8_write_interception(struct vcpu_svm *svm)
4135 struct kvm_run *kvm_run = svm->vcpu.run;
4138 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4139 /* instruction emulation calls kvm_set_cr8() */
4140 r = cr_interception(svm);
4141 if (lapic_in_kernel(&svm->vcpu))
4143 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4145 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4149 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4153 switch (msr->index) {
4154 case MSR_F10H_DECFG:
4155 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4156 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4165 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4167 struct vcpu_svm *svm = to_svm(vcpu);
4169 switch (msr_info->index) {
4171 msr_info->data = svm->vmcb->save.star;
4173 #ifdef CONFIG_X86_64
4175 msr_info->data = svm->vmcb->save.lstar;
4178 msr_info->data = svm->vmcb->save.cstar;
4180 case MSR_KERNEL_GS_BASE:
4181 msr_info->data = svm->vmcb->save.kernel_gs_base;
4183 case MSR_SYSCALL_MASK:
4184 msr_info->data = svm->vmcb->save.sfmask;
4187 case MSR_IA32_SYSENTER_CS:
4188 msr_info->data = svm->vmcb->save.sysenter_cs;
4190 case MSR_IA32_SYSENTER_EIP:
4191 msr_info->data = svm->sysenter_eip;
4193 case MSR_IA32_SYSENTER_ESP:
4194 msr_info->data = svm->sysenter_esp;
4197 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4199 msr_info->data = svm->tsc_aux;
4202 * Nobody will change the following 5 values in the VMCB so we can
4203 * safely return them on rdmsr. They will always be 0 until LBRV is
4206 case MSR_IA32_DEBUGCTLMSR:
4207 msr_info->data = svm->vmcb->save.dbgctl;
4209 case MSR_IA32_LASTBRANCHFROMIP:
4210 msr_info->data = svm->vmcb->save.br_from;
4212 case MSR_IA32_LASTBRANCHTOIP:
4213 msr_info->data = svm->vmcb->save.br_to;
4215 case MSR_IA32_LASTINTFROMIP:
4216 msr_info->data = svm->vmcb->save.last_excp_from;
4218 case MSR_IA32_LASTINTTOIP:
4219 msr_info->data = svm->vmcb->save.last_excp_to;
4221 case MSR_VM_HSAVE_PA:
4222 msr_info->data = svm->nested.hsave_msr;
4225 msr_info->data = svm->nested.vm_cr_msr;
4227 case MSR_IA32_SPEC_CTRL:
4228 if (!msr_info->host_initiated &&
4229 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
4230 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
4231 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4232 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4235 msr_info->data = svm->spec_ctrl;
4237 case MSR_AMD64_VIRT_SPEC_CTRL:
4238 if (!msr_info->host_initiated &&
4239 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4242 msr_info->data = svm->virt_spec_ctrl;
4244 case MSR_F15H_IC_CFG: {
4248 family = guest_cpuid_family(vcpu);
4249 model = guest_cpuid_model(vcpu);
4251 if (family < 0 || model < 0)
4252 return kvm_get_msr_common(vcpu, msr_info);
4256 if (family == 0x15 &&
4257 (model >= 0x2 && model < 0x20))
4258 msr_info->data = 0x1E;
4261 case MSR_F10H_DECFG:
4262 msr_info->data = svm->msr_decfg;
4265 return kvm_get_msr_common(vcpu, msr_info);
4270 static int rdmsr_interception(struct vcpu_svm *svm)
4272 return kvm_emulate_rdmsr(&svm->vcpu);
4275 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4277 struct vcpu_svm *svm = to_svm(vcpu);
4278 int svm_dis, chg_mask;
4280 if (data & ~SVM_VM_CR_VALID_MASK)
4283 chg_mask = SVM_VM_CR_VALID_MASK;
4285 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4286 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4288 svm->nested.vm_cr_msr &= ~chg_mask;
4289 svm->nested.vm_cr_msr |= (data & chg_mask);
4291 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4293 /* check for svm_disable while efer.svme is set */
4294 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4300 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4302 struct vcpu_svm *svm = to_svm(vcpu);
4304 u32 ecx = msr->index;
4305 u64 data = msr->data;
4307 case MSR_IA32_CR_PAT:
4308 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4310 vcpu->arch.pat = data;
4311 svm->vmcb->save.g_pat = data;
4312 mark_dirty(svm->vmcb, VMCB_NPT);
4314 case MSR_IA32_SPEC_CTRL:
4315 if (!msr->host_initiated &&
4316 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
4317 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
4318 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4319 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4322 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
4325 svm->spec_ctrl = data;
4331 * When it's written (to non-zero) for the first time, pass
4335 * The handling of the MSR bitmap for L2 guests is done in
4336 * nested_svm_vmrun_msrpm.
4337 * We update the L1 MSR bit as well since it will end up
4338 * touching the MSR anyway now.
4340 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4342 case MSR_IA32_PRED_CMD:
4343 if (!msr->host_initiated &&
4344 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4347 if (data & ~PRED_CMD_IBPB)
4349 if (!boot_cpu_has(X86_FEATURE_AMD_IBPB))
4354 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4355 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4357 case MSR_AMD64_VIRT_SPEC_CTRL:
4358 if (!msr->host_initiated &&
4359 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4362 if (data & ~SPEC_CTRL_SSBD)
4365 svm->virt_spec_ctrl = data;
4368 svm->vmcb->save.star = data;
4370 #ifdef CONFIG_X86_64
4372 svm->vmcb->save.lstar = data;
4375 svm->vmcb->save.cstar = data;
4377 case MSR_KERNEL_GS_BASE:
4378 svm->vmcb->save.kernel_gs_base = data;
4380 case MSR_SYSCALL_MASK:
4381 svm->vmcb->save.sfmask = data;
4384 case MSR_IA32_SYSENTER_CS:
4385 svm->vmcb->save.sysenter_cs = data;
4387 case MSR_IA32_SYSENTER_EIP:
4388 svm->sysenter_eip = data;
4389 svm->vmcb->save.sysenter_eip = data;
4391 case MSR_IA32_SYSENTER_ESP:
4392 svm->sysenter_esp = data;
4393 svm->vmcb->save.sysenter_esp = data;
4396 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4400 * This is rare, so we update the MSR here instead of using
4401 * direct_access_msrs. Doing that would require a rdmsr in
4404 svm->tsc_aux = data;
4405 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4407 case MSR_IA32_DEBUGCTLMSR:
4408 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4409 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4413 if (data & DEBUGCTL_RESERVED_BITS)
4416 svm->vmcb->save.dbgctl = data;
4417 mark_dirty(svm->vmcb, VMCB_LBR);
4418 if (data & (1ULL<<0))
4419 svm_enable_lbrv(svm);
4421 svm_disable_lbrv(svm);
4423 case MSR_VM_HSAVE_PA:
4424 svm->nested.hsave_msr = data;
4427 return svm_set_vm_cr(vcpu, data);
4429 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4431 case MSR_F10H_DECFG: {
4432 struct kvm_msr_entry msr_entry;
4434 msr_entry.index = msr->index;
4435 if (svm_get_msr_feature(&msr_entry))
4438 /* Check the supported bits */
4439 if (data & ~msr_entry.data)
4442 /* Don't allow the guest to change a bit, #GP */
4443 if (!msr->host_initiated && (data ^ msr_entry.data))
4446 svm->msr_decfg = data;
4449 case MSR_IA32_APICBASE:
4450 if (kvm_vcpu_apicv_active(vcpu))
4451 avic_update_vapic_bar(to_svm(vcpu), data);
4454 return kvm_set_msr_common(vcpu, msr);
4459 static int wrmsr_interception(struct vcpu_svm *svm)
4461 return kvm_emulate_wrmsr(&svm->vcpu);
4464 static int msr_interception(struct vcpu_svm *svm)
4466 if (svm->vmcb->control.exit_info_1)
4467 return wrmsr_interception(svm);
4469 return rdmsr_interception(svm);
4472 static int interrupt_window_interception(struct vcpu_svm *svm)
4474 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4475 svm_clear_vintr(svm);
4478 * For AVIC, the only reason to end up here is ExtINTs.
4479 * In this case AVIC was temporarily disabled for
4480 * requesting the IRQ window and we have to re-enable it.
4482 svm_toggle_avic_for_irq_window(&svm->vcpu, true);
4484 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4485 mark_dirty(svm->vmcb, VMCB_INTR);
4486 ++svm->vcpu.stat.irq_window_exits;
4490 static int pause_interception(struct vcpu_svm *svm)
4492 struct kvm_vcpu *vcpu = &svm->vcpu;
4493 bool in_kernel = (svm_get_cpl(vcpu) == 0);
4495 if (pause_filter_thresh)
4496 grow_ple_window(vcpu);
4498 kvm_vcpu_on_spin(vcpu, in_kernel);
4502 static int nop_interception(struct vcpu_svm *svm)
4504 return kvm_skip_emulated_instruction(&(svm->vcpu));
4507 static int monitor_interception(struct vcpu_svm *svm)
4509 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4510 return nop_interception(svm);
4513 static int mwait_interception(struct vcpu_svm *svm)
4515 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4516 return nop_interception(svm);
4519 enum avic_ipi_failure_cause {
4520 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4521 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4522 AVIC_IPI_FAILURE_INVALID_TARGET,
4523 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4526 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4528 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4529 u32 icrl = svm->vmcb->control.exit_info_1;
4530 u32 id = svm->vmcb->control.exit_info_2 >> 32;
4531 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4532 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4534 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4537 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4539 * AVIC hardware handles the generation of
4540 * IPIs when the specified Message Type is Fixed
4541 * (also known as fixed delivery mode) and
4542 * the Trigger Mode is edge-triggered. The hardware
4543 * also supports self and broadcast delivery modes
4544 * specified via the Destination Shorthand(DSH)
4545 * field of the ICRL. Logical and physical APIC ID
4546 * formats are supported. All other IPI types cause
4547 * a #VMEXIT, which needs to emulated.
4549 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4550 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4552 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4554 struct kvm_vcpu *vcpu;
4555 struct kvm *kvm = svm->vcpu.kvm;
4556 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4559 * At this point, we expect that the AVIC HW has already
4560 * set the appropriate IRR bits on the valid target
4561 * vcpus. So, we just need to kick the appropriate vcpu.
4563 kvm_for_each_vcpu(i, vcpu, kvm) {
4564 bool m = kvm_apic_match_dest(vcpu, apic,
4565 icrl & APIC_SHORT_MASK,
4566 GET_APIC_DEST_FIELD(icrh),
4567 icrl & APIC_DEST_MASK);
4569 if (m && !avic_vcpu_is_running(vcpu))
4570 kvm_vcpu_wake_up(vcpu);
4574 case AVIC_IPI_FAILURE_INVALID_TARGET:
4575 WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n",
4576 index, svm->vcpu.vcpu_id, icrh, icrl);
4578 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4579 WARN_ONCE(1, "Invalid backing page\n");
4582 pr_err("Unknown IPI interception\n");
4588 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4590 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4592 u32 *logical_apic_id_table;
4593 int dlid = GET_APIC_LOGICAL_ID(ldr);
4598 if (flat) { /* flat */
4599 index = ffs(dlid) - 1;
4602 } else { /* cluster */
4603 int cluster = (dlid & 0xf0) >> 4;
4604 int apic = ffs(dlid & 0x0f) - 1;
4606 if ((apic < 0) || (apic > 7) ||
4609 index = (cluster << 2) + apic;
4612 logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4614 return &logical_apic_id_table[index];
4617 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr)
4620 u32 *entry, new_entry;
4622 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4623 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4627 new_entry = READ_ONCE(*entry);
4628 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4629 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4630 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4631 WRITE_ONCE(*entry, new_entry);
4636 static void avic_invalidate_logical_id_entry(struct kvm_vcpu *vcpu)
4638 struct vcpu_svm *svm = to_svm(vcpu);
4639 bool flat = svm->dfr_reg == APIC_DFR_FLAT;
4640 u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat);
4643 clear_bit(AVIC_LOGICAL_ID_ENTRY_VALID_BIT, (unsigned long *)entry);
4646 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4649 struct vcpu_svm *svm = to_svm(vcpu);
4650 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4651 u32 id = kvm_xapic_id(vcpu->arch.apic);
4653 if (ldr == svm->ldr_reg)
4656 avic_invalidate_logical_id_entry(vcpu);
4659 ret = avic_ldr_write(vcpu, id, ldr);
4667 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4670 struct vcpu_svm *svm = to_svm(vcpu);
4671 u32 id = kvm_xapic_id(vcpu->arch.apic);
4673 if (vcpu->vcpu_id == id)
4676 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4677 new = avic_get_physical_id_entry(vcpu, id);
4681 /* We need to move physical_id_entry to new offset */
4684 to_svm(vcpu)->avic_physical_id_cache = new;
4687 * Also update the guest physical APIC ID in the logical
4688 * APIC ID table entry if already setup the LDR.
4691 avic_handle_ldr_update(vcpu);
4696 static void avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4698 struct vcpu_svm *svm = to_svm(vcpu);
4699 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4701 if (svm->dfr_reg == dfr)
4704 avic_invalidate_logical_id_entry(vcpu);
4708 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4710 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4711 u32 offset = svm->vmcb->control.exit_info_1 &
4712 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4716 if (avic_handle_apic_id_update(&svm->vcpu))
4720 if (avic_handle_ldr_update(&svm->vcpu))
4724 avic_handle_dfr_update(&svm->vcpu);
4730 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4735 static bool is_avic_unaccelerated_access_trap(u32 offset)
4764 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4767 u32 offset = svm->vmcb->control.exit_info_1 &
4768 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4769 u32 vector = svm->vmcb->control.exit_info_2 &
4770 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4771 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4772 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4773 bool trap = is_avic_unaccelerated_access_trap(offset);
4775 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4776 trap, write, vector);
4779 WARN_ONCE(!write, "svm: Handling trap read.\n");
4780 ret = avic_unaccel_trap_write(svm);
4782 /* Handling Fault */
4783 ret = kvm_emulate_instruction(&svm->vcpu, 0);
4789 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4790 [SVM_EXIT_READ_CR0] = cr_interception,
4791 [SVM_EXIT_READ_CR3] = cr_interception,
4792 [SVM_EXIT_READ_CR4] = cr_interception,
4793 [SVM_EXIT_READ_CR8] = cr_interception,
4794 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4795 [SVM_EXIT_WRITE_CR0] = cr_interception,
4796 [SVM_EXIT_WRITE_CR3] = cr_interception,
4797 [SVM_EXIT_WRITE_CR4] = cr_interception,
4798 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4799 [SVM_EXIT_READ_DR0] = dr_interception,
4800 [SVM_EXIT_READ_DR1] = dr_interception,
4801 [SVM_EXIT_READ_DR2] = dr_interception,
4802 [SVM_EXIT_READ_DR3] = dr_interception,
4803 [SVM_EXIT_READ_DR4] = dr_interception,
4804 [SVM_EXIT_READ_DR5] = dr_interception,
4805 [SVM_EXIT_READ_DR6] = dr_interception,
4806 [SVM_EXIT_READ_DR7] = dr_interception,
4807 [SVM_EXIT_WRITE_DR0] = dr_interception,
4808 [SVM_EXIT_WRITE_DR1] = dr_interception,
4809 [SVM_EXIT_WRITE_DR2] = dr_interception,
4810 [SVM_EXIT_WRITE_DR3] = dr_interception,
4811 [SVM_EXIT_WRITE_DR4] = dr_interception,
4812 [SVM_EXIT_WRITE_DR5] = dr_interception,
4813 [SVM_EXIT_WRITE_DR6] = dr_interception,
4814 [SVM_EXIT_WRITE_DR7] = dr_interception,
4815 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4816 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4817 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4818 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4819 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4820 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4821 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
4822 [SVM_EXIT_INTR] = intr_interception,
4823 [SVM_EXIT_NMI] = nmi_interception,
4824 [SVM_EXIT_SMI] = nop_on_interception,
4825 [SVM_EXIT_INIT] = nop_on_interception,
4826 [SVM_EXIT_VINTR] = interrupt_window_interception,
4827 [SVM_EXIT_RDPMC] = rdpmc_interception,
4828 [SVM_EXIT_CPUID] = cpuid_interception,
4829 [SVM_EXIT_IRET] = iret_interception,
4830 [SVM_EXIT_INVD] = emulate_on_interception,
4831 [SVM_EXIT_PAUSE] = pause_interception,
4832 [SVM_EXIT_HLT] = halt_interception,
4833 [SVM_EXIT_INVLPG] = invlpg_interception,
4834 [SVM_EXIT_INVLPGA] = invlpga_interception,
4835 [SVM_EXIT_IOIO] = io_interception,
4836 [SVM_EXIT_MSR] = msr_interception,
4837 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4838 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4839 [SVM_EXIT_VMRUN] = vmrun_interception,
4840 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4841 [SVM_EXIT_VMLOAD] = vmload_interception,
4842 [SVM_EXIT_VMSAVE] = vmsave_interception,
4843 [SVM_EXIT_STGI] = stgi_interception,
4844 [SVM_EXIT_CLGI] = clgi_interception,
4845 [SVM_EXIT_SKINIT] = skinit_interception,
4846 [SVM_EXIT_WBINVD] = wbinvd_interception,
4847 [SVM_EXIT_MONITOR] = monitor_interception,
4848 [SVM_EXIT_MWAIT] = mwait_interception,
4849 [SVM_EXIT_XSETBV] = xsetbv_interception,
4850 [SVM_EXIT_RDPRU] = rdpru_interception,
4851 [SVM_EXIT_NPF] = npf_interception,
4852 [SVM_EXIT_RSM] = rsm_interception,
4853 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4854 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4857 static void dump_vmcb(struct kvm_vcpu *vcpu)
4859 struct vcpu_svm *svm = to_svm(vcpu);
4860 struct vmcb_control_area *control = &svm->vmcb->control;
4861 struct vmcb_save_area *save = &svm->vmcb->save;
4863 if (!dump_invalid_vmcb) {
4864 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
4868 pr_err("VMCB Control Area:\n");
4869 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4870 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4871 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4872 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4873 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4874 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4875 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4876 pr_err("%-20s%d\n", "pause filter threshold:",
4877 control->pause_filter_thresh);
4878 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4879 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4880 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4881 pr_err("%-20s%d\n", "asid:", control->asid);
4882 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4883 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4884 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4885 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4886 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4887 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4888 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4889 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4890 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4891 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4892 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4893 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4894 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4895 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4896 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4897 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4898 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4899 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4900 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4901 pr_err("VMCB State Save Area:\n");
4902 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4904 save->es.selector, save->es.attrib,
4905 save->es.limit, save->es.base);
4906 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4908 save->cs.selector, save->cs.attrib,
4909 save->cs.limit, save->cs.base);
4910 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4912 save->ss.selector, save->ss.attrib,
4913 save->ss.limit, save->ss.base);
4914 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4916 save->ds.selector, save->ds.attrib,
4917 save->ds.limit, save->ds.base);
4918 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4920 save->fs.selector, save->fs.attrib,
4921 save->fs.limit, save->fs.base);
4922 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4924 save->gs.selector, save->gs.attrib,
4925 save->gs.limit, save->gs.base);
4926 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4928 save->gdtr.selector, save->gdtr.attrib,
4929 save->gdtr.limit, save->gdtr.base);
4930 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4932 save->ldtr.selector, save->ldtr.attrib,
4933 save->ldtr.limit, save->ldtr.base);
4934 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4936 save->idtr.selector, save->idtr.attrib,
4937 save->idtr.limit, save->idtr.base);
4938 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4940 save->tr.selector, save->tr.attrib,
4941 save->tr.limit, save->tr.base);
4942 pr_err("cpl: %d efer: %016llx\n",
4943 save->cpl, save->efer);
4944 pr_err("%-15s %016llx %-13s %016llx\n",
4945 "cr0:", save->cr0, "cr2:", save->cr2);
4946 pr_err("%-15s %016llx %-13s %016llx\n",
4947 "cr3:", save->cr3, "cr4:", save->cr4);
4948 pr_err("%-15s %016llx %-13s %016llx\n",
4949 "dr6:", save->dr6, "dr7:", save->dr7);
4950 pr_err("%-15s %016llx %-13s %016llx\n",
4951 "rip:", save->rip, "rflags:", save->rflags);
4952 pr_err("%-15s %016llx %-13s %016llx\n",
4953 "rsp:", save->rsp, "rax:", save->rax);
4954 pr_err("%-15s %016llx %-13s %016llx\n",
4955 "star:", save->star, "lstar:", save->lstar);
4956 pr_err("%-15s %016llx %-13s %016llx\n",
4957 "cstar:", save->cstar, "sfmask:", save->sfmask);
4958 pr_err("%-15s %016llx %-13s %016llx\n",
4959 "kernel_gs_base:", save->kernel_gs_base,
4960 "sysenter_cs:", save->sysenter_cs);
4961 pr_err("%-15s %016llx %-13s %016llx\n",
4962 "sysenter_esp:", save->sysenter_esp,
4963 "sysenter_eip:", save->sysenter_eip);
4964 pr_err("%-15s %016llx %-13s %016llx\n",
4965 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4966 pr_err("%-15s %016llx %-13s %016llx\n",
4967 "br_from:", save->br_from, "br_to:", save->br_to);
4968 pr_err("%-15s %016llx %-13s %016llx\n",
4969 "excp_from:", save->last_excp_from,
4970 "excp_to:", save->last_excp_to);
4973 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4975 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4977 *info1 = control->exit_info_1;
4978 *info2 = control->exit_info_2;
4981 static int handle_exit(struct kvm_vcpu *vcpu,
4982 enum exit_fastpath_completion exit_fastpath)
4984 struct vcpu_svm *svm = to_svm(vcpu);
4985 struct kvm_run *kvm_run = vcpu->run;
4986 u32 exit_code = svm->vmcb->control.exit_code;
4988 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4990 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4991 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4993 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4995 if (unlikely(svm->nested.exit_required)) {
4996 nested_svm_vmexit(svm);
4997 svm->nested.exit_required = false;
5002 if (is_guest_mode(vcpu)) {
5005 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
5006 svm->vmcb->control.exit_info_1,
5007 svm->vmcb->control.exit_info_2,
5008 svm->vmcb->control.exit_int_info,
5009 svm->vmcb->control.exit_int_info_err,
5012 vmexit = nested_svm_exit_special(svm);
5014 if (vmexit == NESTED_EXIT_CONTINUE)
5015 vmexit = nested_svm_exit_handled(svm);
5017 if (vmexit == NESTED_EXIT_DONE)
5021 svm_complete_interrupts(svm);
5023 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
5024 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5025 kvm_run->fail_entry.hardware_entry_failure_reason
5026 = svm->vmcb->control.exit_code;
5031 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
5032 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
5033 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
5034 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
5035 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
5037 __func__, svm->vmcb->control.exit_int_info,
5040 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
5041 kvm_skip_emulated_instruction(vcpu);
5043 } else if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
5044 || !svm_exit_handlers[exit_code]) {
5045 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
5047 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5048 vcpu->run->internal.suberror =
5049 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5050 vcpu->run->internal.ndata = 1;
5051 vcpu->run->internal.data[0] = exit_code;
5055 #ifdef CONFIG_RETPOLINE
5056 if (exit_code == SVM_EXIT_MSR)
5057 return msr_interception(svm);
5058 else if (exit_code == SVM_EXIT_VINTR)
5059 return interrupt_window_interception(svm);
5060 else if (exit_code == SVM_EXIT_INTR)
5061 return intr_interception(svm);
5062 else if (exit_code == SVM_EXIT_HLT)
5063 return halt_interception(svm);
5064 else if (exit_code == SVM_EXIT_NPF)
5065 return npf_interception(svm);
5067 return svm_exit_handlers[exit_code](svm);
5070 static void reload_tss(struct kvm_vcpu *vcpu)
5072 int cpu = raw_smp_processor_id();
5074 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5075 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
5079 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
5081 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5082 int asid = sev_get_asid(svm->vcpu.kvm);
5084 /* Assign the asid allocated with this SEV guest */
5085 svm->vmcb->control.asid = asid;
5090 * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5091 * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5093 if (sd->sev_vmcbs[asid] == svm->vmcb &&
5094 svm->last_cpu == cpu)
5097 svm->last_cpu = cpu;
5098 sd->sev_vmcbs[asid] = svm->vmcb;
5099 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5100 mark_dirty(svm->vmcb, VMCB_ASID);
5103 static void pre_svm_run(struct vcpu_svm *svm)
5105 int cpu = raw_smp_processor_id();
5107 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5109 if (sev_guest(svm->vcpu.kvm))
5110 return pre_sev_run(svm, cpu);
5112 /* FIXME: handle wraparound of asid_generation */
5113 if (svm->asid_generation != sd->asid_generation)
5117 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5119 struct vcpu_svm *svm = to_svm(vcpu);
5121 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5122 vcpu->arch.hflags |= HF_NMI_MASK;
5123 set_intercept(svm, INTERCEPT_IRET);
5124 ++vcpu->stat.nmi_injections;
5127 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5129 struct vmcb_control_area *control;
5131 /* The following fields are ignored when AVIC is enabled */
5132 control = &svm->vmcb->control;
5133 control->int_vector = irq;
5134 control->int_ctl &= ~V_INTR_PRIO_MASK;
5135 control->int_ctl |= V_IRQ_MASK |
5136 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5137 mark_dirty(svm->vmcb, VMCB_INTR);
5140 static void svm_set_irq(struct kvm_vcpu *vcpu)
5142 struct vcpu_svm *svm = to_svm(vcpu);
5144 BUG_ON(!(gif_set(svm)));
5146 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5147 ++vcpu->stat.irq_injections;
5149 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5150 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5153 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5155 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5158 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5160 struct vcpu_svm *svm = to_svm(vcpu);
5162 if (svm_nested_virtualize_tpr(vcpu))
5165 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5171 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5174 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5179 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5183 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5187 static void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate)
5189 if (!avic || !lapic_in_kernel(vcpu))
5192 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5193 kvm_request_apicv_update(vcpu->kvm, activate,
5194 APICV_INHIBIT_REASON_IRQWIN);
5195 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5198 static int svm_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate)
5201 unsigned long flags;
5202 struct amd_svm_iommu_ir *ir;
5203 struct vcpu_svm *svm = to_svm(vcpu);
5205 if (!kvm_arch_has_assigned_device(vcpu->kvm))
5209 * Here, we go through the per-vcpu ir_list to update all existing
5210 * interrupt remapping table entry targeting this vcpu.
5212 spin_lock_irqsave(&svm->ir_list_lock, flags);
5214 if (list_empty(&svm->ir_list))
5217 list_for_each_entry(ir, &svm->ir_list, node) {
5219 ret = amd_iommu_activate_guest_mode(ir->data);
5221 ret = amd_iommu_deactivate_guest_mode(ir->data);
5226 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5230 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5232 struct vcpu_svm *svm = to_svm(vcpu);
5233 struct vmcb *vmcb = svm->vmcb;
5234 bool activated = kvm_vcpu_apicv_active(vcpu);
5238 * During AVIC temporary deactivation, guest could update
5239 * APIC ID, DFR and LDR registers, which would not be trapped
5240 * by avic_unaccelerated_access_interception(). In this case,
5241 * we need to check and update the AVIC logical APIC ID table
5242 * accordingly before re-activating.
5244 avic_post_state_restore(vcpu);
5245 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
5247 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5249 mark_dirty(vmcb, VMCB_AVIC);
5251 svm_set_pi_irte_mode(vcpu, activated);
5254 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5259 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5261 kvm_lapic_set_irr(vec, vcpu->arch.apic);
5262 smp_mb__after_atomic();
5264 if (avic_vcpu_is_running(vcpu)) {
5265 int cpuid = vcpu->cpu;
5267 if (cpuid != get_cpu())
5268 wrmsrl(SVM_AVIC_DOORBELL, kvm_cpu_get_apicid(cpuid));
5271 kvm_vcpu_wake_up(vcpu);
5274 static bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
5279 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5281 unsigned long flags;
5282 struct amd_svm_iommu_ir *cur;
5284 spin_lock_irqsave(&svm->ir_list_lock, flags);
5285 list_for_each_entry(cur, &svm->ir_list, node) {
5286 if (cur->data != pi->ir_data)
5288 list_del(&cur->node);
5292 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5295 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5298 unsigned long flags;
5299 struct amd_svm_iommu_ir *ir;
5302 * In some cases, the existing irte is updaed and re-set,
5303 * so we need to check here if it's already been * added
5306 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5307 struct kvm *kvm = svm->vcpu.kvm;
5308 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5309 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5310 struct vcpu_svm *prev_svm;
5317 prev_svm = to_svm(prev_vcpu);
5318 svm_ir_list_del(prev_svm, pi);
5322 * Allocating new amd_iommu_pi_data, which will get
5323 * add to the per-vcpu ir_list.
5325 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT);
5330 ir->data = pi->ir_data;
5332 spin_lock_irqsave(&svm->ir_list_lock, flags);
5333 list_add(&ir->node, &svm->ir_list);
5334 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5341 * The HW cannot support posting multicast/broadcast
5342 * interrupts to a vCPU. So, we still use legacy interrupt
5343 * remapping for these kind of interrupts.
5345 * For lowest-priority interrupts, we only support
5346 * those with single CPU as the destination, e.g. user
5347 * configures the interrupts via /proc/irq or uses
5348 * irqbalance to make the interrupts single-CPU.
5351 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5352 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5354 struct kvm_lapic_irq irq;
5355 struct kvm_vcpu *vcpu = NULL;
5357 kvm_set_msi_irq(kvm, e, &irq);
5359 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
5360 !kvm_irq_is_postable(&irq)) {
5361 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5362 __func__, irq.vector);
5366 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5368 *svm = to_svm(vcpu);
5369 vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5370 vcpu_info->vector = irq.vector;
5376 * svm_update_pi_irte - set IRTE for Posted-Interrupts
5379 * @host_irq: host irq of the interrupt
5380 * @guest_irq: gsi of the interrupt
5381 * @set: set or unset PI
5382 * returns 0 on success, < 0 on failure
5384 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5385 uint32_t guest_irq, bool set)
5387 struct kvm_kernel_irq_routing_entry *e;
5388 struct kvm_irq_routing_table *irq_rt;
5389 int idx, ret = -EINVAL;
5391 if (!kvm_arch_has_assigned_device(kvm) ||
5392 !irq_remapping_cap(IRQ_POSTING_CAP))
5395 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5396 __func__, host_irq, guest_irq, set);
5398 idx = srcu_read_lock(&kvm->irq_srcu);
5399 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5400 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5402 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5403 struct vcpu_data vcpu_info;
5404 struct vcpu_svm *svm = NULL;
5406 if (e->type != KVM_IRQ_ROUTING_MSI)
5410 * Here, we setup with legacy mode in the following cases:
5411 * 1. When cannot target interrupt to a specific vcpu.
5412 * 2. Unsetting posted interrupt.
5413 * 3. APIC virtialization is disabled for the vcpu.
5414 * 4. IRQ has incompatible delivery mode (SMI, INIT, etc)
5416 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5417 kvm_vcpu_apicv_active(&svm->vcpu)) {
5418 struct amd_iommu_pi_data pi;
5420 /* Try to enable guest_mode in IRTE */
5421 pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5423 pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5425 pi.is_guest_mode = true;
5426 pi.vcpu_data = &vcpu_info;
5427 ret = irq_set_vcpu_affinity(host_irq, &pi);
5430 * Here, we successfully setting up vcpu affinity in
5431 * IOMMU guest mode. Now, we need to store the posted
5432 * interrupt information in a per-vcpu ir_list so that
5433 * we can reference to them directly when we update vcpu
5434 * scheduling information in IOMMU irte.
5436 if (!ret && pi.is_guest_mode)
5437 svm_ir_list_add(svm, &pi);
5439 /* Use legacy mode in IRTE */
5440 struct amd_iommu_pi_data pi;
5443 * Here, pi is used to:
5444 * - Tell IOMMU to use legacy mode for this interrupt.
5445 * - Retrieve ga_tag of prior interrupt remapping data.
5447 pi.is_guest_mode = false;
5448 ret = irq_set_vcpu_affinity(host_irq, &pi);
5451 * Check if the posted interrupt was previously
5452 * setup with the guest_mode by checking if the ga_tag
5453 * was cached. If so, we need to clean up the per-vcpu
5456 if (!ret && pi.prev_ga_tag) {
5457 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5458 struct kvm_vcpu *vcpu;
5460 vcpu = kvm_get_vcpu_by_id(kvm, id);
5462 svm_ir_list_del(to_svm(vcpu), &pi);
5467 trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5468 e->gsi, vcpu_info.vector,
5469 vcpu_info.pi_desc_addr, set);
5473 pr_err("%s: failed to update PI IRTE\n", __func__);
5480 srcu_read_unlock(&kvm->irq_srcu, idx);
5484 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5486 struct vcpu_svm *svm = to_svm(vcpu);
5487 struct vmcb *vmcb = svm->vmcb;
5489 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5490 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5491 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5496 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5498 struct vcpu_svm *svm = to_svm(vcpu);
5500 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5503 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5505 struct vcpu_svm *svm = to_svm(vcpu);
5508 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5509 set_intercept(svm, INTERCEPT_IRET);
5511 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5512 clr_intercept(svm, INTERCEPT_IRET);
5516 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5518 struct vcpu_svm *svm = to_svm(vcpu);
5519 struct vmcb *vmcb = svm->vmcb;
5522 if (!gif_set(svm) ||
5523 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5526 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5528 if (is_guest_mode(vcpu))
5529 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5534 static void enable_irq_window(struct kvm_vcpu *vcpu)
5536 struct vcpu_svm *svm = to_svm(vcpu);
5539 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5540 * 1, because that's a separate STGI/VMRUN intercept. The next time we
5541 * get that intercept, this function will be called again though and
5542 * we'll get the vintr intercept. However, if the vGIF feature is
5543 * enabled, the STGI interception will not occur. Enable the irq
5544 * window under the assumption that the hardware will set the GIF.
5546 if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5548 * IRQ window is not needed when AVIC is enabled,
5549 * unless we have pending ExtINT since it cannot be injected
5550 * via AVIC. In such case, we need to temporarily disable AVIC,
5551 * and fallback to injecting IRQ via V_IRQ.
5553 svm_toggle_avic_for_irq_window(vcpu, false);
5555 svm_inject_irq(svm, 0x0);
5559 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5561 struct vcpu_svm *svm = to_svm(vcpu);
5563 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5565 return; /* IRET will cause a vm exit */
5567 if (!gif_set(svm)) {
5568 if (vgif_enabled(svm))
5569 set_intercept(svm, INTERCEPT_STGI);
5570 return; /* STGI will cause a vm exit */
5573 if (svm->nested.exit_required)
5574 return; /* we're not going to run the guest yet */
5577 * Something prevents NMI from been injected. Single step over possible
5578 * problem (IRET or exception injection or interrupt shadow)
5580 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5581 svm->nmi_singlestep = true;
5582 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5585 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5590 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5595 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5597 struct vcpu_svm *svm = to_svm(vcpu);
5599 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5600 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5602 svm->asid_generation--;
5605 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5607 struct vcpu_svm *svm = to_svm(vcpu);
5609 invlpga(gva, svm->vmcb->control.asid);
5612 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5616 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5618 struct vcpu_svm *svm = to_svm(vcpu);
5620 if (svm_nested_virtualize_tpr(vcpu))
5623 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5624 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5625 kvm_set_cr8(vcpu, cr8);
5629 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5631 struct vcpu_svm *svm = to_svm(vcpu);
5634 if (svm_nested_virtualize_tpr(vcpu) ||
5635 kvm_vcpu_apicv_active(vcpu))
5638 cr8 = kvm_get_cr8(vcpu);
5639 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5640 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5643 static void svm_complete_interrupts(struct vcpu_svm *svm)
5647 u32 exitintinfo = svm->vmcb->control.exit_int_info;
5648 unsigned int3_injected = svm->int3_injected;
5650 svm->int3_injected = 0;
5653 * If we've made progress since setting HF_IRET_MASK, we've
5654 * executed an IRET and can allow NMI injection.
5656 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5657 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5658 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5659 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5662 svm->vcpu.arch.nmi_injected = false;
5663 kvm_clear_exception_queue(&svm->vcpu);
5664 kvm_clear_interrupt_queue(&svm->vcpu);
5666 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5669 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5671 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5672 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5675 case SVM_EXITINTINFO_TYPE_NMI:
5676 svm->vcpu.arch.nmi_injected = true;
5678 case SVM_EXITINTINFO_TYPE_EXEPT:
5680 * In case of software exceptions, do not reinject the vector,
5681 * but re-execute the instruction instead. Rewind RIP first
5682 * if we emulated INT3 before.
5684 if (kvm_exception_is_soft(vector)) {
5685 if (vector == BP_VECTOR && int3_injected &&
5686 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5687 kvm_rip_write(&svm->vcpu,
5688 kvm_rip_read(&svm->vcpu) -
5692 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5693 u32 err = svm->vmcb->control.exit_int_info_err;
5694 kvm_requeue_exception_e(&svm->vcpu, vector, err);
5697 kvm_requeue_exception(&svm->vcpu, vector);
5699 case SVM_EXITINTINFO_TYPE_INTR:
5700 kvm_queue_interrupt(&svm->vcpu, vector, false);
5707 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5709 struct vcpu_svm *svm = to_svm(vcpu);
5710 struct vmcb_control_area *control = &svm->vmcb->control;
5712 control->exit_int_info = control->event_inj;
5713 control->exit_int_info_err = control->event_inj_err;
5714 control->event_inj = 0;
5715 svm_complete_interrupts(svm);
5718 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5720 struct vcpu_svm *svm = to_svm(vcpu);
5722 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5723 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5724 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5727 * A vmexit emulation is required before the vcpu can be executed
5730 if (unlikely(svm->nested.exit_required))
5734 * Disable singlestep if we're injecting an interrupt/exception.
5735 * We don't want our modified rflags to be pushed on the stack where
5736 * we might not be able to easily reset them if we disabled NMI
5739 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5741 * Event injection happens before external interrupts cause a
5742 * vmexit and interrupts are disabled here, so smp_send_reschedule
5743 * is enough to force an immediate vmexit.
5745 disable_nmi_singlestep(svm);
5746 smp_send_reschedule(vcpu->cpu);
5751 sync_lapic_to_cr8(vcpu);
5753 svm->vmcb->save.cr2 = vcpu->arch.cr2;
5756 kvm_load_guest_xsave_state(vcpu);
5758 if (lapic_in_kernel(vcpu) &&
5759 vcpu->arch.apic->lapic_timer.timer_advance_ns)
5760 kvm_wait_lapic_expire(vcpu);
5763 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5764 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5765 * is no need to worry about the conditional branch over the wrmsr
5766 * being speculatively taken.
5768 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5773 "push %%" _ASM_BP "; \n\t"
5774 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5775 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5776 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5777 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5778 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5779 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5780 #ifdef CONFIG_X86_64
5781 "mov %c[r8](%[svm]), %%r8 \n\t"
5782 "mov %c[r9](%[svm]), %%r9 \n\t"
5783 "mov %c[r10](%[svm]), %%r10 \n\t"
5784 "mov %c[r11](%[svm]), %%r11 \n\t"
5785 "mov %c[r12](%[svm]), %%r12 \n\t"
5786 "mov %c[r13](%[svm]), %%r13 \n\t"
5787 "mov %c[r14](%[svm]), %%r14 \n\t"
5788 "mov %c[r15](%[svm]), %%r15 \n\t"
5791 /* Enter guest mode */
5792 "push %%" _ASM_AX " \n\t"
5793 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5794 __ex("vmload %%" _ASM_AX) "\n\t"
5795 __ex("vmrun %%" _ASM_AX) "\n\t"
5796 __ex("vmsave %%" _ASM_AX) "\n\t"
5797 "pop %%" _ASM_AX " \n\t"
5799 /* Save guest registers, load host registers */
5800 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5801 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5802 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5803 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5804 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5805 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5806 #ifdef CONFIG_X86_64
5807 "mov %%r8, %c[r8](%[svm]) \n\t"
5808 "mov %%r9, %c[r9](%[svm]) \n\t"
5809 "mov %%r10, %c[r10](%[svm]) \n\t"
5810 "mov %%r11, %c[r11](%[svm]) \n\t"
5811 "mov %%r12, %c[r12](%[svm]) \n\t"
5812 "mov %%r13, %c[r13](%[svm]) \n\t"
5813 "mov %%r14, %c[r14](%[svm]) \n\t"
5814 "mov %%r15, %c[r15](%[svm]) \n\t"
5816 * Clear host registers marked as clobbered to prevent
5819 "xor %%r8d, %%r8d \n\t"
5820 "xor %%r9d, %%r9d \n\t"
5821 "xor %%r10d, %%r10d \n\t"
5822 "xor %%r11d, %%r11d \n\t"
5823 "xor %%r12d, %%r12d \n\t"
5824 "xor %%r13d, %%r13d \n\t"
5825 "xor %%r14d, %%r14d \n\t"
5826 "xor %%r15d, %%r15d \n\t"
5828 "xor %%ebx, %%ebx \n\t"
5829 "xor %%ecx, %%ecx \n\t"
5830 "xor %%edx, %%edx \n\t"
5831 "xor %%esi, %%esi \n\t"
5832 "xor %%edi, %%edi \n\t"
5836 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5837 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5838 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5839 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5840 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5841 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5842 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5843 #ifdef CONFIG_X86_64
5844 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5845 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5846 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5847 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5848 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5849 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5850 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5851 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5854 #ifdef CONFIG_X86_64
5855 , "rbx", "rcx", "rdx", "rsi", "rdi"
5856 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5858 , "ebx", "ecx", "edx", "esi", "edi"
5862 /* Eliminate branch target predictions from guest mode */
5865 #ifdef CONFIG_X86_64
5866 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5868 loadsegment(fs, svm->host.fs);
5869 #ifndef CONFIG_X86_32_LAZY_GS
5870 loadsegment(gs, svm->host.gs);
5875 * We do not use IBRS in the kernel. If this vCPU has used the
5876 * SPEC_CTRL MSR it may have left it on; save the value and
5877 * turn it off. This is much more efficient than blindly adding
5878 * it to the atomic save/restore list. Especially as the former
5879 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5881 * For non-nested case:
5882 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5886 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5889 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5890 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5894 local_irq_disable();
5896 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5898 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5899 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5900 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5901 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5903 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5904 kvm_before_interrupt(&svm->vcpu);
5906 kvm_load_host_xsave_state(vcpu);
5909 /* Any pending NMI will happen here */
5911 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5912 kvm_after_interrupt(&svm->vcpu);
5914 sync_cr8_to_lapic(vcpu);
5918 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5920 /* if exit due to PF check for async PF */
5921 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5922 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5925 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5926 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5930 * We need to handle MC intercepts here before the vcpu has a chance to
5931 * change the physical cpu
5933 if (unlikely(svm->vmcb->control.exit_code ==
5934 SVM_EXIT_EXCP_BASE + MC_VECTOR))
5935 svm_handle_mce(svm);
5937 mark_all_clean(svm->vmcb);
5939 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5941 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5943 struct vcpu_svm *svm = to_svm(vcpu);
5945 svm->vmcb->save.cr3 = __sme_set(root);
5946 mark_dirty(svm->vmcb, VMCB_CR);
5949 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5951 struct vcpu_svm *svm = to_svm(vcpu);
5953 svm->vmcb->control.nested_cr3 = __sme_set(root);
5954 mark_dirty(svm->vmcb, VMCB_NPT);
5956 /* Also sync guest cr3 here in case we live migrate */
5957 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5958 mark_dirty(svm->vmcb, VMCB_CR);
5961 static int is_disabled(void)
5965 rdmsrl(MSR_VM_CR, vm_cr);
5966 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5973 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5976 * Patch in the VMMCALL instruction:
5978 hypercall[0] = 0x0f;
5979 hypercall[1] = 0x01;
5980 hypercall[2] = 0xd9;
5983 static int __init svm_check_processor_compat(void)
5988 static bool svm_cpu_has_accelerated_tpr(void)
5993 static bool svm_has_emulated_msr(int index)
5996 case MSR_IA32_MCG_EXT_CTL:
5997 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6006 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6011 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
6013 struct vcpu_svm *svm = to_svm(vcpu);
6015 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
6016 boot_cpu_has(X86_FEATURE_XSAVE) &&
6017 boot_cpu_has(X86_FEATURE_XSAVES);
6019 /* Update nrips enabled cache */
6020 svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
6022 if (!kvm_vcpu_apicv_active(vcpu))
6025 guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
6028 * Currently, AVIC does not work with nested virtualization.
6029 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
6031 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
6032 kvm_request_apicv_update(vcpu->kvm, false,
6033 APICV_INHIBIT_REASON_NESTED);
6036 #define F feature_bit
6038 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6043 entry->ecx &= ~F(X2APIC);
6047 entry->ecx |= (1 << 2); /* Set SVM bit */
6050 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
6051 boot_cpu_has(X86_FEATURE_AMD_SSBD))
6052 entry->ebx |= F(VIRT_SSBD);
6055 entry->eax = 1; /* SVM revision 1 */
6056 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
6057 ASID emulation to nested SVM */
6058 entry->ecx = 0; /* Reserved */
6059 entry->edx = 0; /* Per default do not support any
6060 additional features */
6062 /* Support next_rip if host supports it */
6063 if (boot_cpu_has(X86_FEATURE_NRIPS))
6064 entry->edx |= F(NRIPS);
6066 /* Support NPT for the guest if enabled */
6068 entry->edx |= F(NPT);
6073 static int svm_get_lpage_level(void)
6075 return PT_PDPE_LEVEL;
6078 static bool svm_rdtscp_supported(void)
6080 return boot_cpu_has(X86_FEATURE_RDTSCP);
6083 static bool svm_invpcid_supported(void)
6088 static bool svm_mpx_supported(void)
6093 static bool svm_xsaves_supported(void)
6095 return boot_cpu_has(X86_FEATURE_XSAVES);
6098 static bool svm_umip_emulated(void)
6103 static bool svm_pt_supported(void)
6108 static bool svm_has_wbinvd_exit(void)
6113 static bool svm_pku_supported(void)
6118 #define PRE_EX(exit) { .exit_code = (exit), \
6119 .stage = X86_ICPT_PRE_EXCEPT, }
6120 #define POST_EX(exit) { .exit_code = (exit), \
6121 .stage = X86_ICPT_POST_EXCEPT, }
6122 #define POST_MEM(exit) { .exit_code = (exit), \
6123 .stage = X86_ICPT_POST_MEMACCESS, }
6125 static const struct __x86_intercept {
6127 enum x86_intercept_stage stage;
6128 } x86_intercept_map[] = {
6129 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
6130 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
6131 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
6132 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
6133 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
6134 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
6135 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
6136 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
6137 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
6138 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
6139 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
6140 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
6141 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
6142 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
6143 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
6144 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
6145 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
6146 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
6147 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
6148 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
6149 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
6150 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
6151 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
6152 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
6153 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
6154 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
6155 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
6156 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
6157 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
6158 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
6159 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
6160 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
6161 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
6162 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
6163 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
6164 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
6165 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
6166 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
6167 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
6168 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
6169 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
6170 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
6171 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
6172 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
6173 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
6174 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
6175 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
6182 static int svm_check_intercept(struct kvm_vcpu *vcpu,
6183 struct x86_instruction_info *info,
6184 enum x86_intercept_stage stage)
6186 struct vcpu_svm *svm = to_svm(vcpu);
6187 int vmexit, ret = X86EMUL_CONTINUE;
6188 struct __x86_intercept icpt_info;
6189 struct vmcb *vmcb = svm->vmcb;
6191 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6194 icpt_info = x86_intercept_map[info->intercept];
6196 if (stage != icpt_info.stage)
6199 switch (icpt_info.exit_code) {
6200 case SVM_EXIT_READ_CR0:
6201 if (info->intercept == x86_intercept_cr_read)
6202 icpt_info.exit_code += info->modrm_reg;
6204 case SVM_EXIT_WRITE_CR0: {
6205 unsigned long cr0, val;
6208 if (info->intercept == x86_intercept_cr_write)
6209 icpt_info.exit_code += info->modrm_reg;
6211 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6212 info->intercept == x86_intercept_clts)
6215 intercept = svm->nested.intercept;
6217 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6220 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6221 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
6223 if (info->intercept == x86_intercept_lmsw) {
6226 /* lmsw can't clear PE - catch this here */
6227 if (cr0 & X86_CR0_PE)
6232 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6236 case SVM_EXIT_READ_DR0:
6237 case SVM_EXIT_WRITE_DR0:
6238 icpt_info.exit_code += info->modrm_reg;
6241 if (info->intercept == x86_intercept_wrmsr)
6242 vmcb->control.exit_info_1 = 1;
6244 vmcb->control.exit_info_1 = 0;
6246 case SVM_EXIT_PAUSE:
6248 * We get this for NOP only, but pause
6249 * is rep not, check this here
6251 if (info->rep_prefix != REPE_PREFIX)
6254 case SVM_EXIT_IOIO: {
6258 if (info->intercept == x86_intercept_in ||
6259 info->intercept == x86_intercept_ins) {
6260 exit_info = ((info->src_val & 0xffff) << 16) |
6262 bytes = info->dst_bytes;
6264 exit_info = (info->dst_val & 0xffff) << 16;
6265 bytes = info->src_bytes;
6268 if (info->intercept == x86_intercept_outs ||
6269 info->intercept == x86_intercept_ins)
6270 exit_info |= SVM_IOIO_STR_MASK;
6272 if (info->rep_prefix)
6273 exit_info |= SVM_IOIO_REP_MASK;
6275 bytes = min(bytes, 4u);
6277 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6279 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6281 vmcb->control.exit_info_1 = exit_info;
6282 vmcb->control.exit_info_2 = info->next_rip;
6290 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6291 if (static_cpu_has(X86_FEATURE_NRIPS))
6292 vmcb->control.next_rip = info->next_rip;
6293 vmcb->control.exit_code = icpt_info.exit_code;
6294 vmexit = nested_svm_exit_handled(svm);
6296 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6303 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6304 enum exit_fastpath_completion *exit_fastpath)
6306 if (!is_guest_mode(vcpu) &&
6307 to_svm(vcpu)->vmcb->control.exit_code == EXIT_REASON_MSR_WRITE)
6308 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
6311 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6313 if (pause_filter_thresh)
6314 shrink_ple_window(vcpu);
6317 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6319 if (avic_handle_apic_id_update(vcpu) != 0)
6321 avic_handle_dfr_update(vcpu);
6322 avic_handle_ldr_update(vcpu);
6325 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6327 /* [63:9] are reserved. */
6328 vcpu->arch.mcg_cap &= 0x1ff;
6331 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6333 struct vcpu_svm *svm = to_svm(vcpu);
6335 /* Per APM Vol.2 15.22.2 "Response to SMI" */
6339 if (is_guest_mode(&svm->vcpu) &&
6340 svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6341 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6342 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6343 svm->nested.exit_required = true;
6350 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6352 struct vcpu_svm *svm = to_svm(vcpu);
6355 if (is_guest_mode(vcpu)) {
6356 /* FED8h - SVM Guest */
6357 put_smstate(u64, smstate, 0x7ed8, 1);
6358 /* FEE0h - SVM Guest VMCB Physical Address */
6359 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6361 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6362 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6363 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6365 ret = nested_svm_vmexit(svm);
6372 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
6374 struct vcpu_svm *svm = to_svm(vcpu);
6375 struct vmcb *nested_vmcb;
6376 struct kvm_host_map map;
6380 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
6381 vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
6384 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
6386 nested_vmcb = map.hva;
6387 enter_svm_guest_mode(svm, vmcb, nested_vmcb, &map);
6392 static int enable_smi_window(struct kvm_vcpu *vcpu)
6394 struct vcpu_svm *svm = to_svm(vcpu);
6396 if (!gif_set(svm)) {
6397 if (vgif_enabled(svm))
6398 set_intercept(svm, INTERCEPT_STGI);
6399 /* STGI will cause a vm exit */
6405 static int sev_flush_asids(void)
6410 * DEACTIVATE will clear the WBINVD indicator causing DF_FLUSH to fail,
6411 * so it must be guarded.
6413 down_write(&sev_deactivate_lock);
6415 wbinvd_on_all_cpus();
6416 ret = sev_guest_df_flush(&error);
6418 up_write(&sev_deactivate_lock);
6421 pr_err("SEV: DF_FLUSH failed, ret=%d, error=%#x\n", ret, error);
6426 /* Must be called with the sev_bitmap_lock held */
6427 static bool __sev_recycle_asids(void)
6431 /* Check if there are any ASIDs to reclaim before performing a flush */
6432 pos = find_next_bit(sev_reclaim_asid_bitmap,
6433 max_sev_asid, min_sev_asid - 1);
6434 if (pos >= max_sev_asid)
6437 if (sev_flush_asids())
6440 bitmap_xor(sev_asid_bitmap, sev_asid_bitmap, sev_reclaim_asid_bitmap,
6442 bitmap_zero(sev_reclaim_asid_bitmap, max_sev_asid);
6447 static int sev_asid_new(void)
6452 mutex_lock(&sev_bitmap_lock);
6455 * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6458 pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6459 if (pos >= max_sev_asid) {
6460 if (retry && __sev_recycle_asids()) {
6464 mutex_unlock(&sev_bitmap_lock);
6468 __set_bit(pos, sev_asid_bitmap);
6470 mutex_unlock(&sev_bitmap_lock);
6475 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6477 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6481 if (unlikely(sev->active))
6484 asid = sev_asid_new();
6488 ret = sev_platform_init(&argp->error);
6494 INIT_LIST_HEAD(&sev->regions_list);
6499 sev_asid_free(asid);
6503 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6505 struct sev_data_activate *data;
6506 int asid = sev_get_asid(kvm);
6509 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6513 /* activate ASID on the given handle */
6514 data->handle = handle;
6516 ret = sev_guest_activate(data, error);
6522 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6531 ret = sev_issue_cmd_external_user(f.file, id, data, error);
6537 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6539 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6541 return __sev_issue_cmd(sev->fd, id, data, error);
6544 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6546 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6547 struct sev_data_launch_start *start;
6548 struct kvm_sev_launch_start params;
6549 void *dh_blob, *session_blob;
6550 int *error = &argp->error;
6553 if (!sev_guest(kvm))
6556 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6559 start = kzalloc(sizeof(*start), GFP_KERNEL_ACCOUNT);
6564 if (params.dh_uaddr) {
6565 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6566 if (IS_ERR(dh_blob)) {
6567 ret = PTR_ERR(dh_blob);
6571 start->dh_cert_address = __sme_set(__pa(dh_blob));
6572 start->dh_cert_len = params.dh_len;
6575 session_blob = NULL;
6576 if (params.session_uaddr) {
6577 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6578 if (IS_ERR(session_blob)) {
6579 ret = PTR_ERR(session_blob);
6583 start->session_address = __sme_set(__pa(session_blob));
6584 start->session_len = params.session_len;
6587 start->handle = params.handle;
6588 start->policy = params.policy;
6590 /* create memory encryption context */
6591 ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6593 goto e_free_session;
6595 /* Bind ASID to this guest */
6596 ret = sev_bind_asid(kvm, start->handle, error);
6598 goto e_free_session;
6600 /* return handle to userspace */
6601 params.handle = start->handle;
6602 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) {
6603 sev_unbind_asid(kvm, start->handle);
6605 goto e_free_session;
6608 sev->handle = start->handle;
6609 sev->fd = argp->sev_fd;
6612 kfree(session_blob);
6620 static unsigned long get_num_contig_pages(unsigned long idx,
6621 struct page **inpages, unsigned long npages)
6623 unsigned long paddr, next_paddr;
6624 unsigned long i = idx + 1, pages = 1;
6626 /* find the number of contiguous pages starting from idx */
6627 paddr = __sme_page_pa(inpages[idx]);
6628 while (i < npages) {
6629 next_paddr = __sme_page_pa(inpages[i++]);
6630 if ((paddr + PAGE_SIZE) == next_paddr) {
6641 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6643 unsigned long vaddr, vaddr_end, next_vaddr, npages, pages, size, i;
6644 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6645 struct kvm_sev_launch_update_data params;
6646 struct sev_data_launch_update_data *data;
6647 struct page **inpages;
6650 if (!sev_guest(kvm))
6653 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6656 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6660 vaddr = params.uaddr;
6662 vaddr_end = vaddr + size;
6664 /* Lock the user memory. */
6665 inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6672 * The LAUNCH_UPDATE command will perform in-place encryption of the
6673 * memory content (i.e it will write the same memory region with C=1).
6674 * It's possible that the cache may contain the data with C=0, i.e.,
6675 * unencrypted so invalidate it first.
6677 sev_clflush_pages(inpages, npages);
6679 for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6683 * If the user buffer is not page-aligned, calculate the offset
6686 offset = vaddr & (PAGE_SIZE - 1);
6688 /* Calculate the number of pages that can be encrypted in one go. */
6689 pages = get_num_contig_pages(i, inpages, npages);
6691 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6693 data->handle = sev->handle;
6695 data->address = __sme_page_pa(inpages[i]) + offset;
6696 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6701 next_vaddr = vaddr + len;
6705 /* content of memory is updated, mark pages dirty */
6706 for (i = 0; i < npages; i++) {
6707 set_page_dirty_lock(inpages[i]);
6708 mark_page_accessed(inpages[i]);
6710 /* unlock the user pages */
6711 sev_unpin_memory(kvm, inpages, npages);
6717 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6719 void __user *measure = (void __user *)(uintptr_t)argp->data;
6720 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6721 struct sev_data_launch_measure *data;
6722 struct kvm_sev_launch_measure params;
6723 void __user *p = NULL;
6727 if (!sev_guest(kvm))
6730 if (copy_from_user(¶ms, measure, sizeof(params)))
6733 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6737 /* User wants to query the blob length */
6741 p = (void __user *)(uintptr_t)params.uaddr;
6743 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6749 blob = kmalloc(params.len, GFP_KERNEL);
6753 data->address = __psp_pa(blob);
6754 data->len = params.len;
6758 data->handle = sev->handle;
6759 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6762 * If we query the session length, FW responded with expected data.
6771 if (copy_to_user(p, blob, params.len))
6776 params.len = data->len;
6777 if (copy_to_user(measure, ¶ms, sizeof(params)))
6786 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6788 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6789 struct sev_data_launch_finish *data;
6792 if (!sev_guest(kvm))
6795 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6799 data->handle = sev->handle;
6800 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6806 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6808 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6809 struct kvm_sev_guest_status params;
6810 struct sev_data_guest_status *data;
6813 if (!sev_guest(kvm))
6816 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6820 data->handle = sev->handle;
6821 ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6825 params.policy = data->policy;
6826 params.state = data->state;
6827 params.handle = data->handle;
6829 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params)))
6836 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6837 unsigned long dst, int size,
6838 int *error, bool enc)
6840 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6841 struct sev_data_dbg *data;
6844 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6848 data->handle = sev->handle;
6849 data->dst_addr = dst;
6850 data->src_addr = src;
6853 ret = sev_issue_cmd(kvm,
6854 enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6860 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6861 unsigned long dst_paddr, int sz, int *err)
6866 * Its safe to read more than we are asked, caller should ensure that
6867 * destination has enough space.
6869 src_paddr = round_down(src_paddr, 16);
6870 offset = src_paddr & 15;
6871 sz = round_up(sz + offset, 16);
6873 return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6876 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6877 unsigned long __user dst_uaddr,
6878 unsigned long dst_paddr,
6881 struct page *tpage = NULL;
6884 /* if inputs are not 16-byte then use intermediate buffer */
6885 if (!IS_ALIGNED(dst_paddr, 16) ||
6886 !IS_ALIGNED(paddr, 16) ||
6887 !IS_ALIGNED(size, 16)) {
6888 tpage = (void *)alloc_page(GFP_KERNEL);
6892 dst_paddr = __sme_page_pa(tpage);
6895 ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6900 offset = paddr & 15;
6901 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6902 page_address(tpage) + offset, size))
6913 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6914 unsigned long __user vaddr,
6915 unsigned long dst_paddr,
6916 unsigned long __user dst_vaddr,
6917 int size, int *error)
6919 struct page *src_tpage = NULL;
6920 struct page *dst_tpage = NULL;
6921 int ret, len = size;
6923 /* If source buffer is not aligned then use an intermediate buffer */
6924 if (!IS_ALIGNED(vaddr, 16)) {
6925 src_tpage = alloc_page(GFP_KERNEL);
6929 if (copy_from_user(page_address(src_tpage),
6930 (void __user *)(uintptr_t)vaddr, size)) {
6931 __free_page(src_tpage);
6935 paddr = __sme_page_pa(src_tpage);
6939 * If destination buffer or length is not aligned then do read-modify-write:
6940 * - decrypt destination in an intermediate buffer
6941 * - copy the source buffer in an intermediate buffer
6942 * - use the intermediate buffer as source buffer
6944 if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6947 dst_tpage = alloc_page(GFP_KERNEL);
6953 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6954 __sme_page_pa(dst_tpage), size, error);
6959 * If source is kernel buffer then use memcpy() otherwise
6962 dst_offset = dst_paddr & 15;
6965 memcpy(page_address(dst_tpage) + dst_offset,
6966 page_address(src_tpage), size);
6968 if (copy_from_user(page_address(dst_tpage) + dst_offset,
6969 (void __user *)(uintptr_t)vaddr, size)) {
6975 paddr = __sme_page_pa(dst_tpage);
6976 dst_paddr = round_down(dst_paddr, 16);
6977 len = round_up(size, 16);
6980 ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6984 __free_page(src_tpage);
6986 __free_page(dst_tpage);
6990 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6992 unsigned long vaddr, vaddr_end, next_vaddr;
6993 unsigned long dst_vaddr;
6994 struct page **src_p, **dst_p;
6995 struct kvm_sev_dbg debug;
7000 if (!sev_guest(kvm))
7003 if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
7006 if (!debug.len || debug.src_uaddr + debug.len < debug.src_uaddr)
7008 if (!debug.dst_uaddr)
7011 vaddr = debug.src_uaddr;
7013 vaddr_end = vaddr + size;
7014 dst_vaddr = debug.dst_uaddr;
7016 for (; vaddr < vaddr_end; vaddr = next_vaddr) {
7017 int len, s_off, d_off;
7019 /* lock userspace source and destination page */
7020 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
7024 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
7026 sev_unpin_memory(kvm, src_p, n);
7031 * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
7032 * memory content (i.e it will write the same memory region with C=1).
7033 * It's possible that the cache may contain the data with C=0, i.e.,
7034 * unencrypted so invalidate it first.
7036 sev_clflush_pages(src_p, 1);
7037 sev_clflush_pages(dst_p, 1);
7040 * Since user buffer may not be page aligned, calculate the
7041 * offset within the page.
7043 s_off = vaddr & ~PAGE_MASK;
7044 d_off = dst_vaddr & ~PAGE_MASK;
7045 len = min_t(size_t, (PAGE_SIZE - s_off), size);
7048 ret = __sev_dbg_decrypt_user(kvm,
7049 __sme_page_pa(src_p[0]) + s_off,
7051 __sme_page_pa(dst_p[0]) + d_off,
7054 ret = __sev_dbg_encrypt_user(kvm,
7055 __sme_page_pa(src_p[0]) + s_off,
7057 __sme_page_pa(dst_p[0]) + d_off,
7061 sev_unpin_memory(kvm, src_p, n);
7062 sev_unpin_memory(kvm, dst_p, n);
7067 next_vaddr = vaddr + len;
7068 dst_vaddr = dst_vaddr + len;
7075 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
7077 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7078 struct sev_data_launch_secret *data;
7079 struct kvm_sev_launch_secret params;
7080 struct page **pages;
7085 if (!sev_guest(kvm))
7088 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
7091 pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
7096 * The secret must be copied into contiguous memory region, lets verify
7097 * that userspace memory pages are contiguous before we issue command.
7099 if (get_num_contig_pages(0, pages, n) != n) {
7101 goto e_unpin_memory;
7105 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
7107 goto e_unpin_memory;
7109 offset = params.guest_uaddr & (PAGE_SIZE - 1);
7110 data->guest_address = __sme_page_pa(pages[0]) + offset;
7111 data->guest_len = params.guest_len;
7113 blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
7115 ret = PTR_ERR(blob);
7119 data->trans_address = __psp_pa(blob);
7120 data->trans_len = params.trans_len;
7122 hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
7127 data->hdr_address = __psp_pa(hdr);
7128 data->hdr_len = params.hdr_len;
7130 data->handle = sev->handle;
7131 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
7140 sev_unpin_memory(kvm, pages, n);
7144 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
7146 struct kvm_sev_cmd sev_cmd;
7149 if (!svm_sev_enabled())
7152 if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
7155 mutex_lock(&kvm->lock);
7157 switch (sev_cmd.id) {
7159 r = sev_guest_init(kvm, &sev_cmd);
7161 case KVM_SEV_LAUNCH_START:
7162 r = sev_launch_start(kvm, &sev_cmd);
7164 case KVM_SEV_LAUNCH_UPDATE_DATA:
7165 r = sev_launch_update_data(kvm, &sev_cmd);
7167 case KVM_SEV_LAUNCH_MEASURE:
7168 r = sev_launch_measure(kvm, &sev_cmd);
7170 case KVM_SEV_LAUNCH_FINISH:
7171 r = sev_launch_finish(kvm, &sev_cmd);
7173 case KVM_SEV_GUEST_STATUS:
7174 r = sev_guest_status(kvm, &sev_cmd);
7176 case KVM_SEV_DBG_DECRYPT:
7177 r = sev_dbg_crypt(kvm, &sev_cmd, true);
7179 case KVM_SEV_DBG_ENCRYPT:
7180 r = sev_dbg_crypt(kvm, &sev_cmd, false);
7182 case KVM_SEV_LAUNCH_SECRET:
7183 r = sev_launch_secret(kvm, &sev_cmd);
7190 if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
7194 mutex_unlock(&kvm->lock);
7198 static int svm_register_enc_region(struct kvm *kvm,
7199 struct kvm_enc_region *range)
7201 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7202 struct enc_region *region;
7205 if (!sev_guest(kvm))
7208 if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
7211 region = kzalloc(sizeof(*region), GFP_KERNEL_ACCOUNT);
7215 region->pages = sev_pin_memory(kvm, range->addr, range->size, ®ion->npages, 1);
7216 if (!region->pages) {
7222 * The guest may change the memory encryption attribute from C=0 -> C=1
7223 * or vice versa for this memory range. Lets make sure caches are
7224 * flushed to ensure that guest data gets written into memory with
7227 sev_clflush_pages(region->pages, region->npages);
7229 region->uaddr = range->addr;
7230 region->size = range->size;
7232 mutex_lock(&kvm->lock);
7233 list_add_tail(®ion->list, &sev->regions_list);
7234 mutex_unlock(&kvm->lock);
7243 static struct enc_region *
7244 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7246 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7247 struct list_head *head = &sev->regions_list;
7248 struct enc_region *i;
7250 list_for_each_entry(i, head, list) {
7251 if (i->uaddr == range->addr &&
7252 i->size == range->size)
7260 static int svm_unregister_enc_region(struct kvm *kvm,
7261 struct kvm_enc_region *range)
7263 struct enc_region *region;
7266 mutex_lock(&kvm->lock);
7268 if (!sev_guest(kvm)) {
7273 region = find_enc_region(kvm, range);
7279 __unregister_enc_region_locked(kvm, region);
7281 mutex_unlock(&kvm->lock);
7285 mutex_unlock(&kvm->lock);
7289 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7291 unsigned long cr4 = kvm_read_cr4(vcpu);
7292 bool smep = cr4 & X86_CR4_SMEP;
7293 bool smap = cr4 & X86_CR4_SMAP;
7294 bool is_user = svm_get_cpl(vcpu) == 3;
7297 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
7300 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
7301 * possible that CPU microcode implementing DecodeAssist will fail
7302 * to read bytes of instruction which caused #NPF. In this case,
7303 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
7304 * return 0 instead of the correct guest instruction bytes.
7306 * This happens because CPU microcode reading instruction bytes
7307 * uses a special opcode which attempts to read data using CPL=0
7308 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
7309 * fault, it gives up and returns no instruction bytes.
7312 * We reach here in case CPU supports DecodeAssist, raised #NPF and
7313 * returned 0 in GuestIntrBytes field of the VMCB.
7314 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
7315 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
7316 * in case vCPU CPL==3 (Because otherwise guest would have triggered
7317 * a SMEP fault instead of #NPF).
7318 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
7319 * As most guests enable SMAP if they have also enabled SMEP, use above
7320 * logic in order to attempt minimize false-positive of detecting errata
7321 * while still preserving all cases semantic correctness.
7324 * To determine what instruction the guest was executing, the hypervisor
7325 * will have to decode the instruction at the instruction pointer.
7327 * In non SEV guest, hypervisor will be able to read the guest
7328 * memory to decode the instruction pointer when insn_len is zero
7329 * so we return true to indicate that decoding is possible.
7331 * But in the SEV guest, the guest memory is encrypted with the
7332 * guest specific key and hypervisor will not be able to decode the
7333 * instruction pointer so we will not able to workaround it. Lets
7334 * print the error and request to kill the guest.
7336 if (smap && (!smep || is_user)) {
7337 if (!sev_guest(vcpu->kvm))
7340 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
7341 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7347 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7349 struct vcpu_svm *svm = to_svm(vcpu);
7352 * TODO: Last condition latch INIT signals on vCPU when
7353 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
7354 * To properly emulate the INIT intercept, SVM should implement
7355 * kvm_x86_ops->check_nested_events() and call nested_svm_vmexit()
7356 * there if an INIT signal is pending.
7358 return !gif_set(svm) ||
7359 (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT));
7362 static bool svm_check_apicv_inhibit_reasons(ulong bit)
7364 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7365 BIT(APICV_INHIBIT_REASON_HYPERV) |
7366 BIT(APICV_INHIBIT_REASON_NESTED) |
7367 BIT(APICV_INHIBIT_REASON_IRQWIN) |
7368 BIT(APICV_INHIBIT_REASON_PIT_REINJ);
7370 return supported & BIT(bit);
7373 static void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate)
7375 avic_update_access_page(kvm, activate);
7378 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7379 .cpu_has_kvm_support = has_svm,
7380 .disabled_by_bios = is_disabled,
7381 .hardware_setup = svm_hardware_setup,
7382 .hardware_unsetup = svm_hardware_unsetup,
7383 .check_processor_compatibility = svm_check_processor_compat,
7384 .hardware_enable = svm_hardware_enable,
7385 .hardware_disable = svm_hardware_disable,
7386 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7387 .has_emulated_msr = svm_has_emulated_msr,
7389 .vcpu_create = svm_create_vcpu,
7390 .vcpu_free = svm_free_vcpu,
7391 .vcpu_reset = svm_vcpu_reset,
7393 .vm_alloc = svm_vm_alloc,
7394 .vm_free = svm_vm_free,
7395 .vm_init = svm_vm_init,
7396 .vm_destroy = svm_vm_destroy,
7398 .prepare_guest_switch = svm_prepare_guest_switch,
7399 .vcpu_load = svm_vcpu_load,
7400 .vcpu_put = svm_vcpu_put,
7401 .vcpu_blocking = svm_vcpu_blocking,
7402 .vcpu_unblocking = svm_vcpu_unblocking,
7404 .update_bp_intercept = update_bp_intercept,
7405 .get_msr_feature = svm_get_msr_feature,
7406 .get_msr = svm_get_msr,
7407 .set_msr = svm_set_msr,
7408 .get_segment_base = svm_get_segment_base,
7409 .get_segment = svm_get_segment,
7410 .set_segment = svm_set_segment,
7411 .get_cpl = svm_get_cpl,
7412 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7413 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7414 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7415 .set_cr0 = svm_set_cr0,
7416 .set_cr3 = svm_set_cr3,
7417 .set_cr4 = svm_set_cr4,
7418 .set_efer = svm_set_efer,
7419 .get_idt = svm_get_idt,
7420 .set_idt = svm_set_idt,
7421 .get_gdt = svm_get_gdt,
7422 .set_gdt = svm_set_gdt,
7423 .get_dr6 = svm_get_dr6,
7424 .set_dr6 = svm_set_dr6,
7425 .set_dr7 = svm_set_dr7,
7426 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7427 .cache_reg = svm_cache_reg,
7428 .get_rflags = svm_get_rflags,
7429 .set_rflags = svm_set_rflags,
7431 .tlb_flush = svm_flush_tlb,
7432 .tlb_flush_gva = svm_flush_tlb_gva,
7434 .run = svm_vcpu_run,
7435 .handle_exit = handle_exit,
7436 .skip_emulated_instruction = skip_emulated_instruction,
7437 .set_interrupt_shadow = svm_set_interrupt_shadow,
7438 .get_interrupt_shadow = svm_get_interrupt_shadow,
7439 .patch_hypercall = svm_patch_hypercall,
7440 .set_irq = svm_set_irq,
7441 .set_nmi = svm_inject_nmi,
7442 .queue_exception = svm_queue_exception,
7443 .cancel_injection = svm_cancel_injection,
7444 .interrupt_allowed = svm_interrupt_allowed,
7445 .nmi_allowed = svm_nmi_allowed,
7446 .get_nmi_mask = svm_get_nmi_mask,
7447 .set_nmi_mask = svm_set_nmi_mask,
7448 .enable_nmi_window = enable_nmi_window,
7449 .enable_irq_window = enable_irq_window,
7450 .update_cr8_intercept = update_cr8_intercept,
7451 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7452 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7453 .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
7454 .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
7455 .load_eoi_exitmap = svm_load_eoi_exitmap,
7456 .hwapic_irr_update = svm_hwapic_irr_update,
7457 .hwapic_isr_update = svm_hwapic_isr_update,
7458 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7459 .apicv_post_state_restore = avic_post_state_restore,
7461 .set_tss_addr = svm_set_tss_addr,
7462 .set_identity_map_addr = svm_set_identity_map_addr,
7463 .get_tdp_level = get_npt_level,
7464 .get_mt_mask = svm_get_mt_mask,
7466 .get_exit_info = svm_get_exit_info,
7468 .get_lpage_level = svm_get_lpage_level,
7470 .cpuid_update = svm_cpuid_update,
7472 .rdtscp_supported = svm_rdtscp_supported,
7473 .invpcid_supported = svm_invpcid_supported,
7474 .mpx_supported = svm_mpx_supported,
7475 .xsaves_supported = svm_xsaves_supported,
7476 .umip_emulated = svm_umip_emulated,
7477 .pt_supported = svm_pt_supported,
7478 .pku_supported = svm_pku_supported,
7480 .set_supported_cpuid = svm_set_supported_cpuid,
7482 .has_wbinvd_exit = svm_has_wbinvd_exit,
7484 .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7485 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7487 .set_tdp_cr3 = set_tdp_cr3,
7489 .check_intercept = svm_check_intercept,
7490 .handle_exit_irqoff = svm_handle_exit_irqoff,
7492 .request_immediate_exit = __kvm_request_immediate_exit,
7494 .sched_in = svm_sched_in,
7496 .pmu_ops = &amd_pmu_ops,
7497 .deliver_posted_interrupt = svm_deliver_avic_intr,
7498 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
7499 .update_pi_irte = svm_update_pi_irte,
7500 .setup_mce = svm_setup_mce,
7502 .smi_allowed = svm_smi_allowed,
7503 .pre_enter_smm = svm_pre_enter_smm,
7504 .pre_leave_smm = svm_pre_leave_smm,
7505 .enable_smi_window = enable_smi_window,
7507 .mem_enc_op = svm_mem_enc_op,
7508 .mem_enc_reg_region = svm_register_enc_region,
7509 .mem_enc_unreg_region = svm_unregister_enc_region,
7511 .nested_enable_evmcs = NULL,
7512 .nested_get_evmcs_version = NULL,
7514 .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
7516 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
7519 static int __init svm_init(void)
7521 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7522 __alignof__(struct vcpu_svm), THIS_MODULE);
7525 static void __exit svm_exit(void)
7530 module_init(svm_init)
7531 module_exit(svm_exit)