arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39
  40 #include <asm/apic.h>
  41 #include <asm/perf_event.h>
  42 #include <asm/tlbflush.h>
  43 #include <asm/desc.h>
  44 #include <asm/debugreg.h>
  45 #include <asm/kvm_para.h>
  46 #include <asm/irq_remapping.h>
  47
  48 #include <asm/virtext.h>
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id svm_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  61
  62 #define IOPM_ALLOC_ORDER 2
  63 #define MSRPM_ALLOC_ORDER 1
  64
  65 #define SEG_TYPE_LDT 2
  66 #define SEG_TYPE_BUSY_TSS16 3
  67
  68 #define SVM_FEATURE_NPT            (1 <<  0)
  69 #define SVM_FEATURE_LBRV           (1 <<  1)
  70 #define SVM_FEATURE_SVML           (1 <<  2)
  71 #define SVM_FEATURE_NRIP           (1 <<  3)
  72 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  73 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  74 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  75 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  76 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  77
  78 #define SVM_AVIC_DOORBELL       0xc001011b
  79
  80 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  81 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  82 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  83
  84 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  85
  86 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  87 #define TSC_RATIO_MIN           0x0000000000000001ULL
  88 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  89
  90 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  91
  92 /*
  93  * 0xff is broadcast, so the max index allowed for physical APIC ID
  94  * table is 0xfe.  APIC IDs above 0xff are reserved.
  95  */
  96 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
  97
  98 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
  99 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 100 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 101
 102 /* AVIC GATAG is encoded using VM and VCPU IDs */
 103 #define AVIC_VCPU_ID_BITS               8
 104 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 105
 106 #define AVIC_VM_ID_BITS                 24
 107 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 108 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 109
 110 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 111                                                 (y & AVIC_VCPU_ID_MASK))
 112 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 113 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 114
 115 static bool erratum_383_found __read_mostly;
 116
 117 static const u32 host_save_user_msrs[] = {
 118 #ifdef CONFIG_X86_64
 119         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 120         MSR_FS_BASE,
 121 #endif
 122         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 123         MSR_TSC_AUX,
 124 };
 125
 126 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 127
 128 struct kvm_vcpu;
 129
 130 struct nested_state {
 131         struct vmcb *hsave;
 132         u64 hsave_msr;
 133         u64 vm_cr_msr;
 134         u64 vmcb;
 135
 136         /* These are the merged vectors */
 137         u32 *msrpm;
 138
 139         /* gpa pointers to the real vectors */
 140         u64 vmcb_msrpm;
 141         u64 vmcb_iopm;
 142
 143         /* A VMEXIT is required but not yet emulated */
 144         bool exit_required;
 145
 146         /* cache for intercepts of the guest */
 147         u32 intercept_cr;
 148         u32 intercept_dr;
 149         u32 intercept_exceptions;
 150         u64 intercept;
 151
 152         /* Nested Paging related state */
 153         u64 nested_cr3;
 154 };
 155
 156 #define MSRPM_OFFSETS   16
 157 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 158
 159 /*
 160  * Set osvw_len to higher value when updated Revision Guides
 161  * are published and we know what the new status bits are
 162  */
 163 static uint64_t osvw_len = 4, osvw_status;
 164
 165 struct vcpu_svm {
 166         struct kvm_vcpu vcpu;
 167         struct vmcb *vmcb;
 168         unsigned long vmcb_pa;
 169         struct svm_cpu_data *svm_data;
 170         uint64_t asid_generation;
 171         uint64_t sysenter_esp;
 172         uint64_t sysenter_eip;
 173         uint64_t tsc_aux;
 174
 175         u64 next_rip;
 176
 177         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 178         struct {
 179                 u16 fs;
 180                 u16 gs;
 181                 u16 ldt;
 182                 u64 gs_base;
 183         } host;
 184
 185         u32 *msrpm;
 186
 187         ulong nmi_iret_rip;
 188
 189         struct nested_state nested;
 190
 191         bool nmi_singlestep;
 192
 193         unsigned int3_injected;
 194         unsigned long int3_rip;
 195         u32 apf_reason;
 196
 197         /* cached guest cpuid flags for faster access */
 198         bool nrips_enabled      : 1;
 199
 200         u32 ldr_reg;
 201         struct page *avic_backing_page;
 202         u64 *avic_physical_id_cache;
 203         bool avic_is_running;
 204
 205         /*
 206          * Per-vcpu list of struct amd_svm_iommu_ir:
 207          * This is used mainly to store interrupt remapping information used
 208          * when update the vcpu affinity. This avoids the need to scan for
 209          * IRTE and try to match ga_tag in the IOMMU driver.
 210          */
 211         struct list_head ir_list;
 212         spinlock_t ir_list_lock;
 213 };
 214
 215 /*
 216  * This is a wrapper of struct amd_iommu_ir_data.
 217  */
 218 struct amd_svm_iommu_ir {
 219         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 220         void *data;             /* Storing pointer to struct amd_ir_data */
 221 };
 222
 223 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 224 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 225
 226 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 227 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 228 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 229 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 230
 231 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 232 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 233
 234 #define MSR_INVALID                     0xffffffffU
 235
 236 static const struct svm_direct_access_msrs {
 237         u32 index;   /* Index of the MSR */
 238         bool always; /* True if intercept is always on */
 239 } direct_access_msrs[] = {
 240         { .index = MSR_STAR,                            .always = true  },
 241         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 242 #ifdef CONFIG_X86_64
 243         { .index = MSR_GS_BASE,                         .always = true  },
 244         { .index = MSR_FS_BASE,                         .always = true  },
 245         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 246         { .index = MSR_LSTAR,                           .always = true  },
 247         { .index = MSR_CSTAR,                           .always = true  },
 248         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 249 #endif
 250         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 251         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 252         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 253         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 254         { .index = MSR_INVALID,                         .always = false },
 255 };
 256
 257 /* enable NPT for AMD64 and X86 with PAE */
 258 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 259 static bool npt_enabled = true;
 260 #else
 261 static bool npt_enabled;
 262 #endif
 263
 264 /* allow nested paging (virtualized MMU) for all guests */
 265 static int npt = true;
 266 module_param(npt, int, S_IRUGO);
 267
 268 /* allow nested virtualization in KVM/SVM */
 269 static int nested = true;
 270 module_param(nested, int, S_IRUGO);
 271
 272 /* enable / disable AVIC */
 273 static int avic;
 274 #ifdef CONFIG_X86_LOCAL_APIC
 275 module_param(avic, int, S_IRUGO);
 276 #endif
 277
 278 /* AVIC VM ID bit masks and lock */
 279 static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
 280 static DEFINE_SPINLOCK(avic_vm_id_lock);
 281
 282 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 283 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 284 static void svm_complete_interrupts(struct vcpu_svm *svm);
 285
 286 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 287 static int nested_svm_intercept(struct vcpu_svm *svm);
 288 static int nested_svm_vmexit(struct vcpu_svm *svm);
 289 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 290                                       bool has_error_code, u32 error_code);
 291
 292 enum {
 293         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 294                             pause filter count */
 295         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 296         VMCB_ASID,       /* ASID */
 297         VMCB_INTR,       /* int_ctl, int_vector */
 298         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 299         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 300         VMCB_DR,         /* DR6, DR7 */
 301         VMCB_DT,         /* GDT, IDT */
 302         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 303         VMCB_CR2,        /* CR2 only */
 304         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 305         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 306                           * AVIC PHYSICAL_TABLE pointer,
 307                           * AVIC LOGICAL_TABLE pointer
 308                           */
 309         VMCB_DIRTY_MAX,
 310 };
 311
 312 /* TPR and CR2 are always written before VMRUN */
 313 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 314
 315 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 316
 317 static inline void mark_all_dirty(struct vmcb *vmcb)
 318 {
 319         vmcb->control.clean = 0;
 320 }
 321
 322 static inline void mark_all_clean(struct vmcb *vmcb)
 323 {
 324         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 325                                & ~VMCB_ALWAYS_DIRTY_MASK;
 326 }
 327
 328 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 329 {
 330         vmcb->control.clean &= ~(1 << bit);
 331 }
 332
 333 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 334 {
 335         return container_of(vcpu, struct vcpu_svm, vcpu);
 336 }
 337
 338 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 339 {
 340         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 341         mark_dirty(svm->vmcb, VMCB_AVIC);
 342 }
 343
 344 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 345 {
 346         struct vcpu_svm *svm = to_svm(vcpu);
 347         u64 *entry = svm->avic_physical_id_cache;
 348
 349         if (!entry)
 350                 return false;
 351
 352         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 353 }
 354
 355 static void recalc_intercepts(struct vcpu_svm *svm)
 356 {
 357         struct vmcb_control_area *c, *h;
 358         struct nested_state *g;
 359
 360         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 361
 362         if (!is_guest_mode(&svm->vcpu))
 363                 return;
 364
 365         c = &svm->vmcb->control;
 366         h = &svm->nested.hsave->control;
 367         g = &svm->nested;
 368
 369         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 370         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 371         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 372         c->intercept = h->intercept | g->intercept;
 373 }
 374
 375 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 376 {
 377         if (is_guest_mode(&svm->vcpu))
 378                 return svm->nested.hsave;
 379         else
 380                 return svm->vmcb;
 381 }
 382
 383 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 384 {
 385         struct vmcb *vmcb = get_host_vmcb(svm);
 386
 387         vmcb->control.intercept_cr |= (1U << bit);
 388
 389         recalc_intercepts(svm);
 390 }
 391
 392 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 393 {
 394         struct vmcb *vmcb = get_host_vmcb(svm);
 395
 396         vmcb->control.intercept_cr &= ~(1U << bit);
 397
 398         recalc_intercepts(svm);
 399 }
 400
 401 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 402 {
 403         struct vmcb *vmcb = get_host_vmcb(svm);
 404
 405         return vmcb->control.intercept_cr & (1U << bit);
 406 }
 407
 408 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 409 {
 410         struct vmcb *vmcb = get_host_vmcb(svm);
 411
 412         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 413                 | (1 << INTERCEPT_DR1_READ)
 414                 | (1 << INTERCEPT_DR2_READ)
 415                 | (1 << INTERCEPT_DR3_READ)
 416                 | (1 << INTERCEPT_DR4_READ)
 417                 | (1 << INTERCEPT_DR5_READ)
 418                 | (1 << INTERCEPT_DR6_READ)
 419                 | (1 << INTERCEPT_DR7_READ)
 420                 | (1 << INTERCEPT_DR0_WRITE)
 421                 | (1 << INTERCEPT_DR1_WRITE)
 422                 | (1 << INTERCEPT_DR2_WRITE)
 423                 | (1 << INTERCEPT_DR3_WRITE)
 424                 | (1 << INTERCEPT_DR4_WRITE)
 425                 | (1 << INTERCEPT_DR5_WRITE)
 426                 | (1 << INTERCEPT_DR6_WRITE)
 427                 | (1 << INTERCEPT_DR7_WRITE);
 428
 429         recalc_intercepts(svm);
 430 }
 431
 432 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 433 {
 434         struct vmcb *vmcb = get_host_vmcb(svm);
 435
 436         vmcb->control.intercept_dr = 0;
 437
 438         recalc_intercepts(svm);
 439 }
 440
 441 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 442 {
 443         struct vmcb *vmcb = get_host_vmcb(svm);
 444
 445         vmcb->control.intercept_exceptions |= (1U << bit);
 446
 447         recalc_intercepts(svm);
 448 }
 449
 450 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 451 {
 452         struct vmcb *vmcb = get_host_vmcb(svm);
 453
 454         vmcb->control.intercept_exceptions &= ~(1U << bit);
 455
 456         recalc_intercepts(svm);
 457 }
 458
 459 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 460 {
 461         struct vmcb *vmcb = get_host_vmcb(svm);
 462
 463         vmcb->control.intercept |= (1ULL << bit);
 464
 465         recalc_intercepts(svm);
 466 }
 467
 468 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 469 {
 470         struct vmcb *vmcb = get_host_vmcb(svm);
 471
 472         vmcb->control.intercept &= ~(1ULL << bit);
 473
 474         recalc_intercepts(svm);
 475 }
 476
 477 static inline void enable_gif(struct vcpu_svm *svm)
 478 {
 479         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 480 }
 481
 482 static inline void disable_gif(struct vcpu_svm *svm)
 483 {
 484         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 485 }
 486
 487 static inline bool gif_set(struct vcpu_svm *svm)
 488 {
 489         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 490 }
 491
 492 static unsigned long iopm_base;
 493
 494 struct kvm_ldttss_desc {
 495         u16 limit0;
 496         u16 base0;
 497         unsigned base1:8, type:5, dpl:2, p:1;
 498         unsigned limit1:4, zero0:3, g:1, base2:8;
 499         u32 base3;
 500         u32 zero1;
 501 } __attribute__((packed));
 502
 503 struct svm_cpu_data {
 504         int cpu;
 505
 506         u64 asid_generation;
 507         u32 max_asid;
 508         u32 next_asid;
 509         struct kvm_ldttss_desc *tss_desc;
 510
 511         struct page *save_area;
 512 };
 513
 514 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 515
 516 struct svm_init_data {
 517         int cpu;
 518         int r;
 519 };
 520
 521 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 522
 523 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 524 #define MSRS_RANGE_SIZE 2048
 525 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 526
 527 static u32 svm_msrpm_offset(u32 msr)
 528 {
 529         u32 offset;
 530         int i;
 531
 532         for (i = 0; i < NUM_MSR_MAPS; i++) {
 533                 if (msr < msrpm_ranges[i] ||
 534                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 535                         continue;
 536
 537                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 538                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 539
 540                 /* Now we have the u8 offset - but need the u32 offset */
 541                 return offset / 4;
 542         }
 543
 544         /* MSR not in any range */
 545         return MSR_INVALID;
 546 }
 547
 548 #define MAX_INST_SIZE 15
 549
 550 static inline void clgi(void)
 551 {
 552         asm volatile (__ex(SVM_CLGI));
 553 }
 554
 555 static inline void stgi(void)
 556 {
 557         asm volatile (__ex(SVM_STGI));
 558 }
 559
 560 static inline void invlpga(unsigned long addr, u32 asid)
 561 {
 562         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 563 }
 564
 565 static int get_npt_level(void)
 566 {
 567 #ifdef CONFIG_X86_64
 568         return PT64_ROOT_LEVEL;
 569 #else
 570         return PT32E_ROOT_LEVEL;
 571 #endif
 572 }
 573
 574 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 575 {
 576         vcpu->arch.efer = efer;
 577         if (!npt_enabled && !(efer & EFER_LMA))
 578                 efer &= ~EFER_LME;
 579
 580         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 581         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 582 }
 583
 584 static int is_external_interrupt(u32 info)
 585 {
 586         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 587         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 588 }
 589
 590 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 591 {
 592         struct vcpu_svm *svm = to_svm(vcpu);
 593         u32 ret = 0;
 594
 595         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 596                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 597         return ret;
 598 }
 599
 600 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 601 {
 602         struct vcpu_svm *svm = to_svm(vcpu);
 603
 604         if (mask == 0)
 605                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 606         else
 607                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 608
 609 }
 610
 611 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 612 {
 613         struct vcpu_svm *svm = to_svm(vcpu);
 614
 615         if (svm->vmcb->control.next_rip != 0) {
 616                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 617                 svm->next_rip = svm->vmcb->control.next_rip;
 618         }
 619
 620         if (!svm->next_rip) {
 621                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 622                                 EMULATE_DONE)
 623                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 624                 return;
 625         }
 626         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 627                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 628                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 629
 630         kvm_rip_write(vcpu, svm->next_rip);
 631         svm_set_interrupt_shadow(vcpu, 0);
 632 }
 633
 634 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 635                                 bool has_error_code, u32 error_code,
 636                                 bool reinject)
 637 {
 638         struct vcpu_svm *svm = to_svm(vcpu);
 639
 640         /*
 641          * If we are within a nested VM we'd better #VMEXIT and let the guest
 642          * handle the exception
 643          */
 644         if (!reinject &&
 645             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 646                 return;
 647
 648         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 649                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 650
 651                 /*
 652                  * For guest debugging where we have to reinject #BP if some
 653                  * INT3 is guest-owned:
 654                  * Emulate nRIP by moving RIP forward. Will fail if injection
 655                  * raises a fault that is not intercepted. Still better than
 656                  * failing in all cases.
 657                  */
 658                 skip_emulated_instruction(&svm->vcpu);
 659                 rip = kvm_rip_read(&svm->vcpu);
 660                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 661                 svm->int3_injected = rip - old_rip;
 662         }
 663
 664         svm->vmcb->control.event_inj = nr
 665                 | SVM_EVTINJ_VALID
 666                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 667                 | SVM_EVTINJ_TYPE_EXEPT;
 668         svm->vmcb->control.event_inj_err = error_code;
 669 }
 670
 671 static void svm_init_erratum_383(void)
 672 {
 673         u32 low, high;
 674         int err;
 675         u64 val;
 676
 677         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 678                 return;
 679
 680         /* Use _safe variants to not break nested virtualization */
 681         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 682         if (err)
 683                 return;
 684
 685         val |= (1ULL << 47);
 686
 687         low  = lower_32_bits(val);
 688         high = upper_32_bits(val);
 689
 690         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 691
 692         erratum_383_found = true;
 693 }
 694
 695 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 696 {
 697         /*
 698          * Guests should see errata 400 and 415 as fixed (assuming that
 699          * HLT and IO instructions are intercepted).
 700          */
 701         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 702         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 703
 704         /*
 705          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 706          * all osvw.status bits inside that length, including bit 0 (which is
 707          * reserved for erratum 298), are valid. However, if host processor's
 708          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 709          * be conservative here and therefore we tell the guest that erratum 298
 710          * is present (because we really don't know).
 711          */
 712         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 713                 vcpu->arch.osvw.status |= 1;
 714 }
 715
 716 static int has_svm(void)
 717 {
 718         const char *msg;
 719
 720         if (!cpu_has_svm(&msg)) {
 721                 printk(KERN_INFO "has_svm: %s\n", msg);
 722                 return 0;
 723         }
 724
 725         return 1;
 726 }
 727
 728 static void svm_hardware_disable(void)
 729 {
 730         /* Make sure we clean up behind us */
 731         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 732                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 733
 734         cpu_svm_disable();
 735
 736         amd_pmu_disable_virt();
 737 }
 738
 739 static int svm_hardware_enable(void)
 740 {
 741
 742         struct svm_cpu_data *sd;
 743         uint64_t efer;
 744         struct desc_struct *gdt;
 745         int me = raw_smp_processor_id();
 746
 747         rdmsrl(MSR_EFER, efer);
 748         if (efer & EFER_SVME)
 749                 return -EBUSY;
 750
 751         if (!has_svm()) {
 752                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 753                 return -EINVAL;
 754         }
 755         sd = per_cpu(svm_data, me);
 756         if (!sd) {
 757                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 758                 return -EINVAL;
 759         }
 760
 761         sd->asid_generation = 1;
 762         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 763         sd->next_asid = sd->max_asid + 1;
 764
 765         gdt = get_current_gdt_rw();
 766         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 767
 768         wrmsrl(MSR_EFER, efer | EFER_SVME);
 769
 770         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 771
 772         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 773                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 774                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 775         }
 776
 777
 778         /*
 779          * Get OSVW bits.
 780          *
 781          * Note that it is possible to have a system with mixed processor
 782          * revisions and therefore different OSVW bits. If bits are not the same
 783          * on different processors then choose the worst case (i.e. if erratum
 784          * is present on one processor and not on another then assume that the
 785          * erratum is present everywhere).
 786          */
 787         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 788                 uint64_t len, status = 0;
 789                 int err;
 790
 791                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 792                 if (!err)
 793                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 794                                                       &err);
 795
 796                 if (err)
 797                         osvw_status = osvw_len = 0;
 798                 else {
 799                         if (len < osvw_len)
 800                                 osvw_len = len;
 801                         osvw_status |= status;
 802                         osvw_status &= (1ULL << osvw_len) - 1;
 803                 }
 804         } else
 805                 osvw_status = osvw_len = 0;
 806
 807         svm_init_erratum_383();
 808
 809         amd_pmu_enable_virt();
 810
 811         return 0;
 812 }
 813
 814 static void svm_cpu_uninit(int cpu)
 815 {
 816         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 817
 818         if (!sd)
 819                 return;
 820
 821         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 822         __free_page(sd->save_area);
 823         kfree(sd);
 824 }
 825
 826 static int svm_cpu_init(int cpu)
 827 {
 828         struct svm_cpu_data *sd;
 829         int r;
 830
 831         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 832         if (!sd)
 833                 return -ENOMEM;
 834         sd->cpu = cpu;
 835         sd->save_area = alloc_page(GFP_KERNEL);
 836         r = -ENOMEM;
 837         if (!sd->save_area)
 838                 goto err_1;
 839
 840         per_cpu(svm_data, cpu) = sd;
 841
 842         return 0;
 843
 844 err_1:
 845         kfree(sd);
 846         return r;
 847
 848 }
 849
 850 static bool valid_msr_intercept(u32 index)
 851 {
 852         int i;
 853
 854         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 855                 if (direct_access_msrs[i].index == index)
 856                         return true;
 857
 858         return false;
 859 }
 860
 861 static void set_msr_interception(u32 *msrpm, unsigned msr,
 862                                  int read, int write)
 863 {
 864         u8 bit_read, bit_write;
 865         unsigned long tmp;
 866         u32 offset;
 867
 868         /*
 869          * If this warning triggers extend the direct_access_msrs list at the
 870          * beginning of the file
 871          */
 872         WARN_ON(!valid_msr_intercept(msr));
 873
 874         offset    = svm_msrpm_offset(msr);
 875         bit_read  = 2 * (msr & 0x0f);
 876         bit_write = 2 * (msr & 0x0f) + 1;
 877         tmp       = msrpm[offset];
 878
 879         BUG_ON(offset == MSR_INVALID);
 880
 881         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 882         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 883
 884         msrpm[offset] = tmp;
 885 }
 886
 887 static void svm_vcpu_init_msrpm(u32 *msrpm)
 888 {
 889         int i;
 890
 891         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 892
 893         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 894                 if (!direct_access_msrs[i].always)
 895                         continue;
 896
 897                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 898         }
 899 }
 900
 901 static void add_msr_offset(u32 offset)
 902 {
 903         int i;
 904
 905         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 906
 907                 /* Offset already in list? */
 908                 if (msrpm_offsets[i] == offset)
 909                         return;
 910
 911                 /* Slot used by another offset? */
 912                 if (msrpm_offsets[i] != MSR_INVALID)
 913                         continue;
 914
 915                 /* Add offset to list */
 916                 msrpm_offsets[i] = offset;
 917
 918                 return;
 919         }
 920
 921         /*
 922          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 923          * increase MSRPM_OFFSETS in this case.
 924          */
 925         BUG();
 926 }
 927
 928 static void init_msrpm_offsets(void)
 929 {
 930         int i;
 931
 932         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 933
 934         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 935                 u32 offset;
 936
 937                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 938                 BUG_ON(offset == MSR_INVALID);
 939
 940                 add_msr_offset(offset);
 941         }
 942 }
 943
 944 static void svm_enable_lbrv(struct vcpu_svm *svm)
 945 {
 946         u32 *msrpm = svm->msrpm;
 947
 948         svm->vmcb->control.lbr_ctl = 1;
 949         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 950         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 951         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 952         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 953 }
 954
 955 static void svm_disable_lbrv(struct vcpu_svm *svm)
 956 {
 957         u32 *msrpm = svm->msrpm;
 958
 959         svm->vmcb->control.lbr_ctl = 0;
 960         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 961         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 962         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 963         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 964 }
 965
 966 /* Note:
 967  * This hash table is used to map VM_ID to a struct kvm_arch,
 968  * when handling AMD IOMMU GALOG notification to schedule in
 969  * a particular vCPU.
 970  */
 971 #define SVM_VM_DATA_HASH_BITS   8
 972 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
 973 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
 974
 975 /* Note:
 976  * This function is called from IOMMU driver to notify
 977  * SVM to schedule in a particular vCPU of a particular VM.
 978  */
 979 static int avic_ga_log_notifier(u32 ga_tag)
 980 {
 981         unsigned long flags;
 982         struct kvm_arch *ka = NULL;
 983         struct kvm_vcpu *vcpu = NULL;
 984         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
 985         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
 986
 987         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
 988
 989         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
 990         hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
 991                 struct kvm *kvm = container_of(ka, struct kvm, arch);
 992                 struct kvm_arch *vm_data = &kvm->arch;
 993
 994                 if (vm_data->avic_vm_id != vm_id)
 995                         continue;
 996                 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
 997                 break;
 998         }
 999         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1000
1001         if (!vcpu)
1002                 return 0;
1003
1004         /* Note:
1005          * At this point, the IOMMU should have already set the pending
1006          * bit in the vAPIC backing page. So, we just need to schedule
1007          * in the vcpu.
1008          */
1009         if (vcpu->mode == OUTSIDE_GUEST_MODE)
1010                 kvm_vcpu_wake_up(vcpu);
1011
1012         return 0;
1013 }
1014
1015 static __init int svm_hardware_setup(void)
1016 {
1017         int cpu;
1018         struct page *iopm_pages;
1019         void *iopm_va;
1020         int r;
1021
1022         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1023
1024         if (!iopm_pages)
1025                 return -ENOMEM;
1026
1027         iopm_va = page_address(iopm_pages);
1028         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1029         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1030
1031         init_msrpm_offsets();
1032
1033         if (boot_cpu_has(X86_FEATURE_NX))
1034                 kvm_enable_efer_bits(EFER_NX);
1035
1036         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1037                 kvm_enable_efer_bits(EFER_FFXSR);
1038
1039         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1040                 kvm_has_tsc_control = true;
1041                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1042                 kvm_tsc_scaling_ratio_frac_bits = 32;
1043         }
1044
1045         if (nested) {
1046                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1047                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1048         }
1049
1050         for_each_possible_cpu(cpu) {
1051                 r = svm_cpu_init(cpu);
1052                 if (r)
1053                         goto err;
1054         }
1055
1056         if (!boot_cpu_has(X86_FEATURE_NPT))
1057                 npt_enabled = false;
1058
1059         if (npt_enabled && !npt) {
1060                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1061                 npt_enabled = false;
1062         }
1063
1064         if (npt_enabled) {
1065                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1066                 kvm_enable_tdp();
1067         } else
1068                 kvm_disable_tdp();
1069
1070         if (avic) {
1071                 if (!npt_enabled ||
1072                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1073                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1074                         avic = false;
1075                 } else {
1076                         pr_info("AVIC enabled\n");
1077
1078                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1079                 }
1080         }
1081
1082         return 0;
1083
1084 err:
1085         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1086         iopm_base = 0;
1087         return r;
1088 }
1089
1090 static __exit void svm_hardware_unsetup(void)
1091 {
1092         int cpu;
1093
1094         for_each_possible_cpu(cpu)
1095                 svm_cpu_uninit(cpu);
1096
1097         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1098         iopm_base = 0;
1099 }
1100
1101 static void init_seg(struct vmcb_seg *seg)
1102 {
1103         seg->selector = 0;
1104         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1105                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1106         seg->limit = 0xffff;
1107         seg->base = 0;
1108 }
1109
1110 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1111 {
1112         seg->selector = 0;
1113         seg->attrib = SVM_SELECTOR_P_MASK | type;
1114         seg->limit = 0xffff;
1115         seg->base = 0;
1116 }
1117
1118 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1119 {
1120         struct vcpu_svm *svm = to_svm(vcpu);
1121         u64 g_tsc_offset = 0;
1122
1123         if (is_guest_mode(vcpu)) {
1124                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1125                                svm->nested.hsave->control.tsc_offset;
1126                 svm->nested.hsave->control.tsc_offset = offset;
1127         } else
1128                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1129                                            svm->vmcb->control.tsc_offset,
1130                                            offset);
1131
1132         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1133
1134         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1135 }
1136
1137 static void avic_init_vmcb(struct vcpu_svm *svm)
1138 {
1139         struct vmcb *vmcb = svm->vmcb;
1140         struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1141         phys_addr_t bpa = page_to_phys(svm->avic_backing_page);
1142         phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page);
1143         phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page);
1144
1145         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1146         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1147         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1148         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1149         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1150         svm->vcpu.arch.apicv_active = true;
1151 }
1152
1153 static void init_vmcb(struct vcpu_svm *svm)
1154 {
1155         struct vmcb_control_area *control = &svm->vmcb->control;
1156         struct vmcb_save_area *save = &svm->vmcb->save;
1157
1158         svm->vcpu.arch.hflags = 0;
1159
1160         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1161         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1162         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1163         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1164         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1165         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1166         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1167                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1168
1169         set_dr_intercepts(svm);
1170
1171         set_exception_intercept(svm, PF_VECTOR);
1172         set_exception_intercept(svm, UD_VECTOR);
1173         set_exception_intercept(svm, MC_VECTOR);
1174         set_exception_intercept(svm, AC_VECTOR);
1175         set_exception_intercept(svm, DB_VECTOR);
1176
1177         set_intercept(svm, INTERCEPT_INTR);
1178         set_intercept(svm, INTERCEPT_NMI);
1179         set_intercept(svm, INTERCEPT_SMI);
1180         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1181         set_intercept(svm, INTERCEPT_RDPMC);
1182         set_intercept(svm, INTERCEPT_CPUID);
1183         set_intercept(svm, INTERCEPT_INVD);
1184         set_intercept(svm, INTERCEPT_HLT);
1185         set_intercept(svm, INTERCEPT_INVLPG);
1186         set_intercept(svm, INTERCEPT_INVLPGA);
1187         set_intercept(svm, INTERCEPT_IOIO_PROT);
1188         set_intercept(svm, INTERCEPT_MSR_PROT);
1189         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1190         set_intercept(svm, INTERCEPT_SHUTDOWN);
1191         set_intercept(svm, INTERCEPT_VMRUN);
1192         set_intercept(svm, INTERCEPT_VMMCALL);
1193         set_intercept(svm, INTERCEPT_VMLOAD);
1194         set_intercept(svm, INTERCEPT_VMSAVE);
1195         set_intercept(svm, INTERCEPT_STGI);
1196         set_intercept(svm, INTERCEPT_CLGI);
1197         set_intercept(svm, INTERCEPT_SKINIT);
1198         set_intercept(svm, INTERCEPT_WBINVD);
1199         set_intercept(svm, INTERCEPT_MONITOR);
1200         set_intercept(svm, INTERCEPT_MWAIT);
1201         set_intercept(svm, INTERCEPT_XSETBV);
1202
1203         control->iopm_base_pa = iopm_base;
1204         control->msrpm_base_pa = __pa(svm->msrpm);
1205         control->int_ctl = V_INTR_MASKING_MASK;
1206
1207         init_seg(&save->es);
1208         init_seg(&save->ss);
1209         init_seg(&save->ds);
1210         init_seg(&save->fs);
1211         init_seg(&save->gs);
1212
1213         save->cs.selector = 0xf000;
1214         save->cs.base = 0xffff0000;
1215         /* Executable/Readable Code Segment */
1216         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1217                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1218         save->cs.limit = 0xffff;
1219
1220         save->gdtr.limit = 0xffff;
1221         save->idtr.limit = 0xffff;
1222
1223         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1224         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1225
1226         svm_set_efer(&svm->vcpu, 0);
1227         save->dr6 = 0xffff0ff0;
1228         kvm_set_rflags(&svm->vcpu, 2);
1229         save->rip = 0x0000fff0;
1230         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1231
1232         /*
1233          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1234          * It also updates the guest-visible cr0 value.
1235          */
1236         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1237         kvm_mmu_reset_context(&svm->vcpu);
1238
1239         save->cr4 = X86_CR4_PAE;
1240         /* rdx = ?? */
1241
1242         if (npt_enabled) {
1243                 /* Setup VMCB for Nested Paging */
1244                 control->nested_ctl = 1;
1245                 clr_intercept(svm, INTERCEPT_INVLPG);
1246                 clr_exception_intercept(svm, PF_VECTOR);
1247                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1248                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1249                 save->g_pat = svm->vcpu.arch.pat;
1250                 save->cr3 = 0;
1251                 save->cr4 = 0;
1252         }
1253         svm->asid_generation = 0;
1254
1255         svm->nested.vmcb = 0;
1256         svm->vcpu.arch.hflags = 0;
1257
1258         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1259                 control->pause_filter_count = 3000;
1260                 set_intercept(svm, INTERCEPT_PAUSE);
1261         }
1262
1263         if (avic)
1264                 avic_init_vmcb(svm);
1265
1266         mark_all_dirty(svm->vmcb);
1267
1268         enable_gif(svm);
1269
1270 }
1271
1272 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, int index)
1273 {
1274         u64 *avic_physical_id_table;
1275         struct kvm_arch *vm_data = &vcpu->kvm->arch;
1276
1277         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1278                 return NULL;
1279
1280         avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1281
1282         return &avic_physical_id_table[index];
1283 }
1284
1285 /**
1286  * Note:
1287  * AVIC hardware walks the nested page table to check permissions,
1288  * but does not use the SPA address specified in the leaf page
1289  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1290  * field of the VMCB. Therefore, we set up the
1291  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1292  */
1293 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1294 {
1295         struct kvm *kvm = vcpu->kvm;
1296         int ret;
1297
1298         if (kvm->arch.apic_access_page_done)
1299                 return 0;
1300
1301         ret = x86_set_memory_region(kvm,
1302                                     APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1303                                     APIC_DEFAULT_PHYS_BASE,
1304                                     PAGE_SIZE);
1305         if (ret)
1306                 return ret;
1307
1308         kvm->arch.apic_access_page_done = true;
1309         return 0;
1310 }
1311
1312 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1313 {
1314         int ret;
1315         u64 *entry, new_entry;
1316         int id = vcpu->vcpu_id;
1317         struct vcpu_svm *svm = to_svm(vcpu);
1318
1319         ret = avic_init_access_page(vcpu);
1320         if (ret)
1321                 return ret;
1322
1323         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1324                 return -EINVAL;
1325
1326         if (!svm->vcpu.arch.apic->regs)
1327                 return -EINVAL;
1328
1329         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1330
1331         /* Setting AVIC backing page address in the phy APIC ID table */
1332         entry = avic_get_physical_id_entry(vcpu, id);
1333         if (!entry)
1334                 return -EINVAL;
1335
1336         new_entry = READ_ONCE(*entry);
1337         new_entry = (page_to_phys(svm->avic_backing_page) &
1338                      AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1339                      AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
1340         WRITE_ONCE(*entry, new_entry);
1341
1342         svm->avic_physical_id_cache = entry;
1343
1344         return 0;
1345 }
1346
1347 static inline int avic_get_next_vm_id(void)
1348 {
1349         int id;
1350
1351         spin_lock(&avic_vm_id_lock);
1352
1353         /* AVIC VM ID is one-based. */
1354         id = find_next_zero_bit(avic_vm_id_bitmap, AVIC_VM_ID_NR, 1);
1355         if (id <= AVIC_VM_ID_MASK)
1356                 __set_bit(id, avic_vm_id_bitmap);
1357         else
1358                 id = -EAGAIN;
1359
1360         spin_unlock(&avic_vm_id_lock);
1361         return id;
1362 }
1363
1364 static inline int avic_free_vm_id(int id)
1365 {
1366         if (id <= 0 || id > AVIC_VM_ID_MASK)
1367                 return -EINVAL;
1368
1369         spin_lock(&avic_vm_id_lock);
1370         __clear_bit(id, avic_vm_id_bitmap);
1371         spin_unlock(&avic_vm_id_lock);
1372         return 0;
1373 }
1374
1375 static void avic_vm_destroy(struct kvm *kvm)
1376 {
1377         unsigned long flags;
1378         struct kvm_arch *vm_data = &kvm->arch;
1379
1380         if (!avic)
1381                 return;
1382
1383         avic_free_vm_id(vm_data->avic_vm_id);
1384
1385         if (vm_data->avic_logical_id_table_page)
1386                 __free_page(vm_data->avic_logical_id_table_page);
1387         if (vm_data->avic_physical_id_table_page)
1388                 __free_page(vm_data->avic_physical_id_table_page);
1389
1390         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1391         hash_del(&vm_data->hnode);
1392         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1393 }
1394
1395 static int avic_vm_init(struct kvm *kvm)
1396 {
1397         unsigned long flags;
1398         int vm_id, err = -ENOMEM;
1399         struct kvm_arch *vm_data = &kvm->arch;
1400         struct page *p_page;
1401         struct page *l_page;
1402
1403         if (!avic)
1404                 return 0;
1405
1406         vm_id = avic_get_next_vm_id();
1407         if (vm_id < 0)
1408                 return vm_id;
1409         vm_data->avic_vm_id = (u32)vm_id;
1410
1411         /* Allocating physical APIC ID table (4KB) */
1412         p_page = alloc_page(GFP_KERNEL);
1413         if (!p_page)
1414                 goto free_avic;
1415
1416         vm_data->avic_physical_id_table_page = p_page;
1417         clear_page(page_address(p_page));
1418
1419         /* Allocating logical APIC ID table (4KB) */
1420         l_page = alloc_page(GFP_KERNEL);
1421         if (!l_page)
1422                 goto free_avic;
1423
1424         vm_data->avic_logical_id_table_page = l_page;
1425         clear_page(page_address(l_page));
1426
1427         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1428         hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1429         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1430
1431         return 0;
1432
1433 free_avic:
1434         avic_vm_destroy(kvm);
1435         return err;
1436 }
1437
1438 static inline int
1439 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1440 {
1441         int ret = 0;
1442         unsigned long flags;
1443         struct amd_svm_iommu_ir *ir;
1444         struct vcpu_svm *svm = to_svm(vcpu);
1445
1446         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1447                 return 0;
1448
1449         /*
1450          * Here, we go through the per-vcpu ir_list to update all existing
1451          * interrupt remapping table entry targeting this vcpu.
1452          */
1453         spin_lock_irqsave(&svm->ir_list_lock, flags);
1454
1455         if (list_empty(&svm->ir_list))
1456                 goto out;
1457
1458         list_for_each_entry(ir, &svm->ir_list, node) {
1459                 ret = amd_iommu_update_ga(cpu, r, ir->data);
1460                 if (ret)
1461                         break;
1462         }
1463 out:
1464         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1465         return ret;
1466 }
1467
1468 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1469 {
1470         u64 entry;
1471         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1472         int h_physical_id = kvm_cpu_get_apicid(cpu);
1473         struct vcpu_svm *svm = to_svm(vcpu);
1474
1475         if (!kvm_vcpu_apicv_active(vcpu))
1476                 return;
1477
1478         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1479                 return;
1480
1481         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1482         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1483
1484         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1485         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1486
1487         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1488         if (svm->avic_is_running)
1489                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1490
1491         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1492         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1493                                         svm->avic_is_running);
1494 }
1495
1496 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1497 {
1498         u64 entry;
1499         struct vcpu_svm *svm = to_svm(vcpu);
1500
1501         if (!kvm_vcpu_apicv_active(vcpu))
1502                 return;
1503
1504         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1505         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1506                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1507
1508         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1509         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1510 }
1511
1512 /**
1513  * This function is called during VCPU halt/unhalt.
1514  */
1515 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1516 {
1517         struct vcpu_svm *svm = to_svm(vcpu);
1518
1519         svm->avic_is_running = is_run;
1520         if (is_run)
1521                 avic_vcpu_load(vcpu, vcpu->cpu);
1522         else
1523                 avic_vcpu_put(vcpu);
1524 }
1525
1526 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1527 {
1528         struct vcpu_svm *svm = to_svm(vcpu);
1529         u32 dummy;
1530         u32 eax = 1;
1531
1532         if (!init_event) {
1533                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1534                                            MSR_IA32_APICBASE_ENABLE;
1535                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1536                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1537         }
1538         init_vmcb(svm);
1539
1540         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1541         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1542
1543         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1544                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1545 }
1546
1547 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1548 {
1549         struct vcpu_svm *svm;
1550         struct page *page;
1551         struct page *msrpm_pages;
1552         struct page *hsave_page;
1553         struct page *nested_msrpm_pages;
1554         int err;
1555
1556         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1557         if (!svm) {
1558                 err = -ENOMEM;
1559                 goto out;
1560         }
1561
1562         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1563         if (err)
1564                 goto free_svm;
1565
1566         err = -ENOMEM;
1567         page = alloc_page(GFP_KERNEL);
1568         if (!page)
1569                 goto uninit;
1570
1571         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1572         if (!msrpm_pages)
1573                 goto free_page1;
1574
1575         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1576         if (!nested_msrpm_pages)
1577                 goto free_page2;
1578
1579         hsave_page = alloc_page(GFP_KERNEL);
1580         if (!hsave_page)
1581                 goto free_page3;
1582
1583         if (avic) {
1584                 err = avic_init_backing_page(&svm->vcpu);
1585                 if (err)
1586                         goto free_page4;
1587
1588                 INIT_LIST_HEAD(&svm->ir_list);
1589                 spin_lock_init(&svm->ir_list_lock);
1590         }
1591
1592         /* We initialize this flag to true to make sure that the is_running
1593          * bit would be set the first time the vcpu is loaded.
1594          */
1595         svm->avic_is_running = true;
1596
1597         svm->nested.hsave = page_address(hsave_page);
1598
1599         svm->msrpm = page_address(msrpm_pages);
1600         svm_vcpu_init_msrpm(svm->msrpm);
1601
1602         svm->nested.msrpm = page_address(nested_msrpm_pages);
1603         svm_vcpu_init_msrpm(svm->nested.msrpm);
1604
1605         svm->vmcb = page_address(page);
1606         clear_page(svm->vmcb);
1607         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1608         svm->asid_generation = 0;
1609         init_vmcb(svm);
1610
1611         svm_init_osvw(&svm->vcpu);
1612
1613         return &svm->vcpu;
1614
1615 free_page4:
1616         __free_page(hsave_page);
1617 free_page3:
1618         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1619 free_page2:
1620         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1621 free_page1:
1622         __free_page(page);
1623 uninit:
1624         kvm_vcpu_uninit(&svm->vcpu);
1625 free_svm:
1626         kmem_cache_free(kvm_vcpu_cache, svm);
1627 out:
1628         return ERR_PTR(err);
1629 }
1630
1631 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1632 {
1633         struct vcpu_svm *svm = to_svm(vcpu);
1634
1635         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1636         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1637         __free_page(virt_to_page(svm->nested.hsave));
1638         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1639         kvm_vcpu_uninit(vcpu);
1640         kmem_cache_free(kvm_vcpu_cache, svm);
1641 }
1642
1643 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1644 {
1645         struct vcpu_svm *svm = to_svm(vcpu);
1646         int i;
1647
1648         if (unlikely(cpu != vcpu->cpu)) {
1649                 svm->asid_generation = 0;
1650                 mark_all_dirty(svm->vmcb);
1651         }
1652
1653 #ifdef CONFIG_X86_64
1654         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1655 #endif
1656         savesegment(fs, svm->host.fs);
1657         savesegment(gs, svm->host.gs);
1658         svm->host.ldt = kvm_read_ldt();
1659
1660         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1661                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1662
1663         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1664                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1665                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1666                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1667                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1668                 }
1669         }
1670         /* This assumes that the kernel never uses MSR_TSC_AUX */
1671         if (static_cpu_has(X86_FEATURE_RDTSCP))
1672                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1673
1674         avic_vcpu_load(vcpu, cpu);
1675 }
1676
1677 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1678 {
1679         struct vcpu_svm *svm = to_svm(vcpu);
1680         int i;
1681
1682         avic_vcpu_put(vcpu);
1683
1684         ++vcpu->stat.host_state_reload;
1685         kvm_load_ldt(svm->host.ldt);
1686 #ifdef CONFIG_X86_64
1687         loadsegment(fs, svm->host.fs);
1688         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1689         load_gs_index(svm->host.gs);
1690 #else
1691 #ifdef CONFIG_X86_32_LAZY_GS
1692         loadsegment(gs, svm->host.gs);
1693 #endif
1694 #endif
1695         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1696                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1697 }
1698
1699 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1700 {
1701         avic_set_running(vcpu, false);
1702 }
1703
1704 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1705 {
1706         avic_set_running(vcpu, true);
1707 }
1708
1709 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1710 {
1711         return to_svm(vcpu)->vmcb->save.rflags;
1712 }
1713
1714 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1715 {
1716        /*
1717         * Any change of EFLAGS.VM is accompanied by a reload of SS
1718         * (caused by either a task switch or an inter-privilege IRET),
1719         * so we do not need to update the CPL here.
1720         */
1721         to_svm(vcpu)->vmcb->save.rflags = rflags;
1722 }
1723
1724 static u32 svm_get_pkru(struct kvm_vcpu *vcpu)
1725 {
1726         return 0;
1727 }
1728
1729 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1730 {
1731         switch (reg) {
1732         case VCPU_EXREG_PDPTR:
1733                 BUG_ON(!npt_enabled);
1734                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1735                 break;
1736         default:
1737                 BUG();
1738         }
1739 }
1740
1741 static void svm_set_vintr(struct vcpu_svm *svm)
1742 {
1743         set_intercept(svm, INTERCEPT_VINTR);
1744 }
1745
1746 static void svm_clear_vintr(struct vcpu_svm *svm)
1747 {
1748         clr_intercept(svm, INTERCEPT_VINTR);
1749 }
1750
1751 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1752 {
1753         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1754
1755         switch (seg) {
1756         case VCPU_SREG_CS: return &save->cs;
1757         case VCPU_SREG_DS: return &save->ds;
1758         case VCPU_SREG_ES: return &save->es;
1759         case VCPU_SREG_FS: return &save->fs;
1760         case VCPU_SREG_GS: return &save->gs;
1761         case VCPU_SREG_SS: return &save->ss;
1762         case VCPU_SREG_TR: return &save->tr;
1763         case VCPU_SREG_LDTR: return &save->ldtr;
1764         }
1765         BUG();
1766         return NULL;
1767 }
1768
1769 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1770 {
1771         struct vmcb_seg *s = svm_seg(vcpu, seg);
1772
1773         return s->base;
1774 }
1775
1776 static void svm_get_segment(struct kvm_vcpu *vcpu,
1777                             struct kvm_segment *var, int seg)
1778 {
1779         struct vmcb_seg *s = svm_seg(vcpu, seg);
1780
1781         var->base = s->base;
1782         var->limit = s->limit;
1783         var->selector = s->selector;
1784         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1785         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1786         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1787         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1788         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1789         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1790         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1791
1792         /*
1793          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1794          * However, the SVM spec states that the G bit is not observed by the
1795          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1796          * So let's synthesize a legal G bit for all segments, this helps
1797          * running KVM nested. It also helps cross-vendor migration, because
1798          * Intel's vmentry has a check on the 'G' bit.
1799          */
1800         var->g = s->limit > 0xfffff;
1801
1802         /*
1803          * AMD's VMCB does not have an explicit unusable field, so emulate it
1804          * for cross vendor migration purposes by "not present"
1805          */
1806         var->unusable = !var->present || (var->type == 0);
1807
1808         switch (seg) {
1809         case VCPU_SREG_TR:
1810                 /*
1811                  * Work around a bug where the busy flag in the tr selector
1812                  * isn't exposed
1813                  */
1814                 var->type |= 0x2;
1815                 break;
1816         case VCPU_SREG_DS:
1817         case VCPU_SREG_ES:
1818         case VCPU_SREG_FS:
1819         case VCPU_SREG_GS:
1820                 /*
1821                  * The accessed bit must always be set in the segment
1822                  * descriptor cache, although it can be cleared in the
1823                  * descriptor, the cached bit always remains at 1. Since
1824                  * Intel has a check on this, set it here to support
1825                  * cross-vendor migration.
1826                  */
1827                 if (!var->unusable)
1828                         var->type |= 0x1;
1829                 break;
1830         case VCPU_SREG_SS:
1831                 /*
1832                  * On AMD CPUs sometimes the DB bit in the segment
1833                  * descriptor is left as 1, although the whole segment has
1834                  * been made unusable. Clear it here to pass an Intel VMX
1835                  * entry check when cross vendor migrating.
1836                  */
1837                 if (var->unusable)
1838                         var->db = 0;
1839                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1840                 break;
1841         }
1842 }
1843
1844 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1845 {
1846         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1847
1848         return save->cpl;
1849 }
1850
1851 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1852 {
1853         struct vcpu_svm *svm = to_svm(vcpu);
1854
1855         dt->size = svm->vmcb->save.idtr.limit;
1856         dt->address = svm->vmcb->save.idtr.base;
1857 }
1858
1859 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1860 {
1861         struct vcpu_svm *svm = to_svm(vcpu);
1862
1863         svm->vmcb->save.idtr.limit = dt->size;
1864         svm->vmcb->save.idtr.base = dt->address ;
1865         mark_dirty(svm->vmcb, VMCB_DT);
1866 }
1867
1868 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1869 {
1870         struct vcpu_svm *svm = to_svm(vcpu);
1871
1872         dt->size = svm->vmcb->save.gdtr.limit;
1873         dt->address = svm->vmcb->save.gdtr.base;
1874 }
1875
1876 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1877 {
1878         struct vcpu_svm *svm = to_svm(vcpu);
1879
1880         svm->vmcb->save.gdtr.limit = dt->size;
1881         svm->vmcb->save.gdtr.base = dt->address ;
1882         mark_dirty(svm->vmcb, VMCB_DT);
1883 }
1884
1885 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1886 {
1887 }
1888
1889 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1890 {
1891 }
1892
1893 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1894 {
1895 }
1896
1897 static void update_cr0_intercept(struct vcpu_svm *svm)
1898 {
1899         ulong gcr0 = svm->vcpu.arch.cr0;
1900         u64 *hcr0 = &svm->vmcb->save.cr0;
1901
1902         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1903                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1904
1905         mark_dirty(svm->vmcb, VMCB_CR);
1906
1907         if (gcr0 == *hcr0) {
1908                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1909                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1910         } else {
1911                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1912                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1913         }
1914 }
1915
1916 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1917 {
1918         struct vcpu_svm *svm = to_svm(vcpu);
1919
1920 #ifdef CONFIG_X86_64
1921         if (vcpu->arch.efer & EFER_LME) {
1922                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1923                         vcpu->arch.efer |= EFER_LMA;
1924                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1925                 }
1926
1927                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1928                         vcpu->arch.efer &= ~EFER_LMA;
1929                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1930                 }
1931         }
1932 #endif
1933         vcpu->arch.cr0 = cr0;
1934
1935         if (!npt_enabled)
1936                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1937
1938         /*
1939          * re-enable caching here because the QEMU bios
1940          * does not do it - this results in some delay at
1941          * reboot
1942          */
1943         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1944                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1945         svm->vmcb->save.cr0 = cr0;
1946         mark_dirty(svm->vmcb, VMCB_CR);
1947         update_cr0_intercept(svm);
1948 }
1949
1950 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1951 {
1952         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1953         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1954
1955         if (cr4 & X86_CR4_VMXE)
1956                 return 1;
1957
1958         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1959                 svm_flush_tlb(vcpu);
1960
1961         vcpu->arch.cr4 = cr4;
1962         if (!npt_enabled)
1963                 cr4 |= X86_CR4_PAE;
1964         cr4 |= host_cr4_mce;
1965         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1966         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1967         return 0;
1968 }
1969
1970 static void svm_set_segment(struct kvm_vcpu *vcpu,
1971                             struct kvm_segment *var, int seg)
1972 {
1973         struct vcpu_svm *svm = to_svm(vcpu);
1974         struct vmcb_seg *s = svm_seg(vcpu, seg);
1975
1976         s->base = var->base;
1977         s->limit = var->limit;
1978         s->selector = var->selector;
1979         if (var->unusable)
1980                 s->attrib = 0;
1981         else {
1982                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1983                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1984                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1985                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1986                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1987                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1988                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1989                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1990         }
1991
1992         /*
1993          * This is always accurate, except if SYSRET returned to a segment
1994          * with SS.DPL != 3.  Intel does not have this quirk, and always
1995          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1996          * would entail passing the CPL to userspace and back.
1997          */
1998         if (seg == VCPU_SREG_SS)
1999                 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2000
2001         mark_dirty(svm->vmcb, VMCB_SEG);
2002 }
2003
2004 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2005 {
2006         struct vcpu_svm *svm = to_svm(vcpu);
2007
2008         clr_exception_intercept(svm, BP_VECTOR);
2009
2010         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2011                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2012                         set_exception_intercept(svm, BP_VECTOR);
2013         } else
2014                 vcpu->guest_debug = 0;
2015 }
2016
2017 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2018 {
2019         if (sd->next_asid > sd->max_asid) {
2020                 ++sd->asid_generation;
2021                 sd->next_asid = 1;
2022                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2023         }
2024
2025         svm->asid_generation = sd->asid_generation;
2026         svm->vmcb->control.asid = sd->next_asid++;
2027
2028         mark_dirty(svm->vmcb, VMCB_ASID);
2029 }
2030
2031 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2032 {
2033         return to_svm(vcpu)->vmcb->save.dr6;
2034 }
2035
2036 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2037 {
2038         struct vcpu_svm *svm = to_svm(vcpu);
2039
2040         svm->vmcb->save.dr6 = value;
2041         mark_dirty(svm->vmcb, VMCB_DR);
2042 }
2043
2044 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2045 {
2046         struct vcpu_svm *svm = to_svm(vcpu);
2047
2048         get_debugreg(vcpu->arch.db[0], 0);
2049         get_debugreg(vcpu->arch.db[1], 1);
2050         get_debugreg(vcpu->arch.db[2], 2);
2051         get_debugreg(vcpu->arch.db[3], 3);
2052         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2053         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2054
2055         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2056         set_dr_intercepts(svm);
2057 }
2058
2059 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2060 {
2061         struct vcpu_svm *svm = to_svm(vcpu);
2062
2063         svm->vmcb->save.dr7 = value;
2064         mark_dirty(svm->vmcb, VMCB_DR);
2065 }
2066
2067 static int pf_interception(struct vcpu_svm *svm)
2068 {
2069         u64 fault_address = svm->vmcb->control.exit_info_2;
2070         u64 error_code;
2071         int r = 1;
2072
2073         switch (svm->apf_reason) {
2074         default:
2075                 error_code = svm->vmcb->control.exit_info_1;
2076
2077                 trace_kvm_page_fault(fault_address, error_code);
2078                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
2079                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
2080                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2081                         svm->vmcb->control.insn_bytes,
2082                         svm->vmcb->control.insn_len);
2083                 break;
2084         case KVM_PV_REASON_PAGE_NOT_PRESENT:
2085                 svm->apf_reason = 0;
2086                 local_irq_disable();
2087                 kvm_async_pf_task_wait(fault_address);
2088                 local_irq_enable();
2089                 break;
2090         case KVM_PV_REASON_PAGE_READY:
2091                 svm->apf_reason = 0;
2092                 local_irq_disable();
2093                 kvm_async_pf_task_wake(fault_address);
2094                 local_irq_enable();
2095                 break;
2096         }
2097         return r;
2098 }
2099
2100 static int db_interception(struct vcpu_svm *svm)
2101 {
2102         struct kvm_run *kvm_run = svm->vcpu.run;
2103
2104         if (!(svm->vcpu.guest_debug &
2105               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2106                 !svm->nmi_singlestep) {
2107                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2108                 return 1;
2109         }
2110
2111         if (svm->nmi_singlestep) {
2112                 svm->nmi_singlestep = false;
2113                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
2114                         svm->vmcb->save.rflags &=
2115                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
2116         }
2117
2118         if (svm->vcpu.guest_debug &
2119             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2120                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2121                 kvm_run->debug.arch.pc =
2122                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2123                 kvm_run->debug.arch.exception = DB_VECTOR;
2124                 return 0;
2125         }
2126
2127         return 1;
2128 }
2129
2130 static int bp_interception(struct vcpu_svm *svm)
2131 {
2132         struct kvm_run *kvm_run = svm->vcpu.run;
2133
2134         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2135         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2136         kvm_run->debug.arch.exception = BP_VECTOR;
2137         return 0;
2138 }
2139
2140 static int ud_interception(struct vcpu_svm *svm)
2141 {
2142         int er;
2143
2144         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2145         if (er != EMULATE_DONE)
2146                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2147         return 1;
2148 }
2149
2150 static int ac_interception(struct vcpu_svm *svm)
2151 {
2152         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2153         return 1;
2154 }
2155
2156 static bool is_erratum_383(void)
2157 {
2158         int err, i;
2159         u64 value;
2160
2161         if (!erratum_383_found)
2162                 return false;
2163
2164         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2165         if (err)
2166                 return false;
2167
2168         /* Bit 62 may or may not be set for this mce */
2169         value &= ~(1ULL << 62);
2170
2171         if (value != 0xb600000000010015ULL)
2172                 return false;
2173
2174         /* Clear MCi_STATUS registers */
2175         for (i = 0; i < 6; ++i)
2176                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2177
2178         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2179         if (!err) {
2180                 u32 low, high;
2181
2182                 value &= ~(1ULL << 2);
2183                 low    = lower_32_bits(value);
2184                 high   = upper_32_bits(value);
2185
2186                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2187         }
2188
2189         /* Flush tlb to evict multi-match entries */
2190         __flush_tlb_all();
2191
2192         return true;
2193 }
2194
2195 static void svm_handle_mce(struct vcpu_svm *svm)
2196 {
2197         if (is_erratum_383()) {
2198                 /*
2199                  * Erratum 383 triggered. Guest state is corrupt so kill the
2200                  * guest.
2201                  */
2202                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2203
2204                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2205
2206                 return;
2207         }
2208
2209         /*
2210          * On an #MC intercept the MCE handler is not called automatically in
2211          * the host. So do it by hand here.
2212          */
2213         asm volatile (
2214                 "int $0x12\n");
2215         /* not sure if we ever come back to this point */
2216
2217         return;
2218 }
2219
2220 static int mc_interception(struct vcpu_svm *svm)
2221 {
2222         return 1;
2223 }
2224
2225 static int shutdown_interception(struct vcpu_svm *svm)
2226 {
2227         struct kvm_run *kvm_run = svm->vcpu.run;
2228
2229         /*
2230          * VMCB is undefined after a SHUTDOWN intercept
2231          * so reinitialize it.
2232          */
2233         clear_page(svm->vmcb);
2234         init_vmcb(svm);
2235
2236         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2237         return 0;
2238 }
2239
2240 static int io_interception(struct vcpu_svm *svm)
2241 {
2242         struct kvm_vcpu *vcpu = &svm->vcpu;
2243         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2244         int size, in, string;
2245         unsigned port;
2246
2247         ++svm->vcpu.stat.io_exits;
2248         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2249         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2250         if (string)
2251                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2252
2253         port = io_info >> 16;
2254         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2255         svm->next_rip = svm->vmcb->control.exit_info_2;
2256         skip_emulated_instruction(&svm->vcpu);
2257
2258         return in ? kvm_fast_pio_in(vcpu, size, port)
2259                   : kvm_fast_pio_out(vcpu, size, port);
2260 }
2261
2262 static int nmi_interception(struct vcpu_svm *svm)
2263 {
2264         return 1;
2265 }
2266
2267 static int intr_interception(struct vcpu_svm *svm)
2268 {
2269         ++svm->vcpu.stat.irq_exits;
2270         return 1;
2271 }
2272
2273 static int nop_on_interception(struct vcpu_svm *svm)
2274 {
2275         return 1;
2276 }
2277
2278 static int halt_interception(struct vcpu_svm *svm)
2279 {
2280         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2281         return kvm_emulate_halt(&svm->vcpu);
2282 }
2283
2284 static int vmmcall_interception(struct vcpu_svm *svm)
2285 {
2286         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2287         return kvm_emulate_hypercall(&svm->vcpu);
2288 }
2289
2290 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2291 {
2292         struct vcpu_svm *svm = to_svm(vcpu);
2293
2294         return svm->nested.nested_cr3;
2295 }
2296
2297 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2298 {
2299         struct vcpu_svm *svm = to_svm(vcpu);
2300         u64 cr3 = svm->nested.nested_cr3;
2301         u64 pdpte;
2302         int ret;
2303
2304         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2305                                        offset_in_page(cr3) + index * 8, 8);
2306         if (ret)
2307                 return 0;
2308         return pdpte;
2309 }
2310
2311 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2312                                    unsigned long root)
2313 {
2314         struct vcpu_svm *svm = to_svm(vcpu);
2315
2316         svm->vmcb->control.nested_cr3 = root;
2317         mark_dirty(svm->vmcb, VMCB_NPT);
2318         svm_flush_tlb(vcpu);
2319 }
2320
2321 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2322                                        struct x86_exception *fault)
2323 {
2324         struct vcpu_svm *svm = to_svm(vcpu);
2325
2326         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2327                 /*
2328                  * TODO: track the cause of the nested page fault, and
2329                  * correctly fill in the high bits of exit_info_1.
2330                  */
2331                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2332                 svm->vmcb->control.exit_code_hi = 0;
2333                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2334                 svm->vmcb->control.exit_info_2 = fault->address;
2335         }
2336
2337         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2338         svm->vmcb->control.exit_info_1 |= fault->error_code;
2339
2340         /*
2341          * The present bit is always zero for page structure faults on real
2342          * hardware.
2343          */
2344         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2345                 svm->vmcb->control.exit_info_1 &= ~1;
2346
2347         nested_svm_vmexit(svm);
2348 }
2349
2350 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2351 {
2352         WARN_ON(mmu_is_nested(vcpu));
2353         kvm_init_shadow_mmu(vcpu);
2354         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
2355         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
2356         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
2357         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2358         vcpu->arch.mmu.shadow_root_level = get_npt_level();
2359         reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2360         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2361 }
2362
2363 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2364 {
2365         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2366 }
2367
2368 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2369 {
2370         if (!(svm->vcpu.arch.efer & EFER_SVME)
2371             || !is_paging(&svm->vcpu)) {
2372                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2373                 return 1;
2374         }
2375
2376         if (svm->vmcb->save.cpl) {
2377                 kvm_inject_gp(&svm->vcpu, 0);
2378                 return 1;
2379         }
2380
2381        return 0;
2382 }
2383
2384 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2385                                       bool has_error_code, u32 error_code)
2386 {
2387         int vmexit;
2388
2389         if (!is_guest_mode(&svm->vcpu))
2390                 return 0;
2391
2392         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2393         svm->vmcb->control.exit_code_hi = 0;
2394         svm->vmcb->control.exit_info_1 = error_code;
2395         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2396
2397         vmexit = nested_svm_intercept(svm);
2398         if (vmexit == NESTED_EXIT_DONE)
2399                 svm->nested.exit_required = true;
2400
2401         return vmexit;
2402 }
2403
2404 /* This function returns true if it is save to enable the irq window */
2405 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2406 {
2407         if (!is_guest_mode(&svm->vcpu))
2408                 return true;
2409
2410         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2411                 return true;
2412
2413         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2414                 return false;
2415
2416         /*
2417          * if vmexit was already requested (by intercepted exception
2418          * for instance) do not overwrite it with "external interrupt"
2419          * vmexit.
2420          */
2421         if (svm->nested.exit_required)
2422                 return false;
2423
2424         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2425         svm->vmcb->control.exit_info_1 = 0;
2426         svm->vmcb->control.exit_info_2 = 0;
2427
2428         if (svm->nested.intercept & 1ULL) {
2429                 /*
2430                  * The #vmexit can't be emulated here directly because this
2431                  * code path runs with irqs and preemption disabled. A
2432                  * #vmexit emulation might sleep. Only signal request for
2433                  * the #vmexit here.
2434                  */
2435                 svm->nested.exit_required = true;
2436                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2437                 return false;
2438         }
2439
2440         return true;
2441 }
2442
2443 /* This function returns true if it is save to enable the nmi window */
2444 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2445 {
2446         if (!is_guest_mode(&svm->vcpu))
2447                 return true;
2448
2449         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2450                 return true;
2451
2452         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2453         svm->nested.exit_required = true;
2454
2455         return false;
2456 }
2457
2458 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2459 {
2460         struct page *page;
2461
2462         might_sleep();
2463
2464         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2465         if (is_error_page(page))
2466                 goto error;
2467
2468         *_page = page;
2469
2470         return kmap(page);
2471
2472 error:
2473         kvm_inject_gp(&svm->vcpu, 0);
2474
2475         return NULL;
2476 }
2477
2478 static void nested_svm_unmap(struct page *page)
2479 {
2480         kunmap(page);
2481         kvm_release_page_dirty(page);
2482 }
2483
2484 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2485 {
2486         unsigned port, size, iopm_len;
2487         u16 val, mask;
2488         u8 start_bit;
2489         u64 gpa;
2490
2491         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2492                 return NESTED_EXIT_HOST;
2493
2494         port = svm->vmcb->control.exit_info_1 >> 16;
2495         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2496                 SVM_IOIO_SIZE_SHIFT;
2497         gpa  = svm->nested.vmcb_iopm + (port / 8);
2498         start_bit = port % 8;
2499         iopm_len = (start_bit + size > 8) ? 2 : 1;
2500         mask = (0xf >> (4 - size)) << start_bit;
2501         val = 0;
2502
2503         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2504                 return NESTED_EXIT_DONE;
2505
2506         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2507 }
2508
2509 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2510 {
2511         u32 offset, msr, value;
2512         int write, mask;
2513
2514         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2515                 return NESTED_EXIT_HOST;
2516
2517         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2518         offset = svm_msrpm_offset(msr);
2519         write  = svm->vmcb->control.exit_info_1 & 1;
2520         mask   = 1 << ((2 * (msr & 0xf)) + write);
2521
2522         if (offset == MSR_INVALID)
2523                 return NESTED_EXIT_DONE;
2524
2525         /* Offset is in 32 bit units but need in 8 bit units */
2526         offset *= 4;
2527
2528         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2529                 return NESTED_EXIT_DONE;
2530
2531         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2532 }
2533
2534 static int nested_svm_exit_special(struct vcpu_svm *svm)
2535 {
2536         u32 exit_code = svm->vmcb->control.exit_code;
2537
2538         switch (exit_code) {
2539         case SVM_EXIT_INTR:
2540         case SVM_EXIT_NMI:
2541         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2542                 return NESTED_EXIT_HOST;
2543         case SVM_EXIT_NPF:
2544                 /* For now we are always handling NPFs when using them */
2545                 if (npt_enabled)
2546                         return NESTED_EXIT_HOST;
2547                 break;
2548         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2549                 /* When we're shadowing, trap PFs, but not async PF */
2550                 if (!npt_enabled && svm->apf_reason == 0)
2551                         return NESTED_EXIT_HOST;
2552                 break;
2553         default:
2554                 break;
2555         }
2556
2557         return NESTED_EXIT_CONTINUE;
2558 }
2559
2560 /*
2561  * If this function returns true, this #vmexit was already handled
2562  */
2563 static int nested_svm_intercept(struct vcpu_svm *svm)
2564 {
2565         u32 exit_code = svm->vmcb->control.exit_code;
2566         int vmexit = NESTED_EXIT_HOST;
2567
2568         switch (exit_code) {
2569         case SVM_EXIT_MSR:
2570                 vmexit = nested_svm_exit_handled_msr(svm);
2571                 break;
2572         case SVM_EXIT_IOIO:
2573                 vmexit = nested_svm_intercept_ioio(svm);
2574                 break;
2575         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2576                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2577                 if (svm->nested.intercept_cr & bit)
2578                         vmexit = NESTED_EXIT_DONE;
2579                 break;
2580         }
2581         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2582                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2583                 if (svm->nested.intercept_dr & bit)
2584                         vmexit = NESTED_EXIT_DONE;
2585                 break;
2586         }
2587         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2588                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2589                 if (svm->nested.intercept_exceptions & excp_bits)
2590                         vmexit = NESTED_EXIT_DONE;
2591                 /* async page fault always cause vmexit */
2592                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2593                          svm->apf_reason != 0)
2594                         vmexit = NESTED_EXIT_DONE;
2595                 break;
2596         }
2597         case SVM_EXIT_ERR: {
2598                 vmexit = NESTED_EXIT_DONE;
2599                 break;
2600         }
2601         default: {
2602                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2603                 if (svm->nested.intercept & exit_bits)
2604                         vmexit = NESTED_EXIT_DONE;
2605         }
2606         }
2607
2608         return vmexit;
2609 }
2610
2611 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2612 {
2613         int vmexit;
2614
2615         vmexit = nested_svm_intercept(svm);
2616
2617         if (vmexit == NESTED_EXIT_DONE)
2618                 nested_svm_vmexit(svm);
2619
2620         return vmexit;
2621 }
2622
2623 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2624 {
2625         struct vmcb_control_area *dst  = &dst_vmcb->control;
2626         struct vmcb_control_area *from = &from_vmcb->control;
2627
2628         dst->intercept_cr         = from->intercept_cr;
2629         dst->intercept_dr         = from->intercept_dr;
2630         dst->intercept_exceptions = from->intercept_exceptions;
2631         dst->intercept            = from->intercept;
2632         dst->iopm_base_pa         = from->iopm_base_pa;
2633         dst->msrpm_base_pa        = from->msrpm_base_pa;
2634         dst->tsc_offset           = from->tsc_offset;
2635         dst->asid                 = from->asid;
2636         dst->tlb_ctl              = from->tlb_ctl;
2637         dst->int_ctl              = from->int_ctl;
2638         dst->int_vector           = from->int_vector;
2639         dst->int_state            = from->int_state;
2640         dst->exit_code            = from->exit_code;
2641         dst->exit_code_hi         = from->exit_code_hi;
2642         dst->exit_info_1          = from->exit_info_1;
2643         dst->exit_info_2          = from->exit_info_2;
2644         dst->exit_int_info        = from->exit_int_info;
2645         dst->exit_int_info_err    = from->exit_int_info_err;
2646         dst->nested_ctl           = from->nested_ctl;
2647         dst->event_inj            = from->event_inj;
2648         dst->event_inj_err        = from->event_inj_err;
2649         dst->nested_cr3           = from->nested_cr3;
2650         dst->lbr_ctl              = from->lbr_ctl;
2651 }
2652
2653 static int nested_svm_vmexit(struct vcpu_svm *svm)
2654 {
2655         struct vmcb *nested_vmcb;
2656         struct vmcb *hsave = svm->nested.hsave;
2657         struct vmcb *vmcb = svm->vmcb;
2658         struct page *page;
2659
2660         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2661                                        vmcb->control.exit_info_1,
2662                                        vmcb->control.exit_info_2,
2663                                        vmcb->control.exit_int_info,
2664                                        vmcb->control.exit_int_info_err,
2665                                        KVM_ISA_SVM);
2666
2667         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2668         if (!nested_vmcb)
2669                 return 1;
2670
2671         /* Exit Guest-Mode */
2672         leave_guest_mode(&svm->vcpu);
2673         svm->nested.vmcb = 0;
2674
2675         /* Give the current vmcb to the guest */
2676         disable_gif(svm);
2677
2678         nested_vmcb->save.es     = vmcb->save.es;
2679         nested_vmcb->save.cs     = vmcb->save.cs;
2680         nested_vmcb->save.ss     = vmcb->save.ss;
2681         nested_vmcb->save.ds     = vmcb->save.ds;
2682         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2683         nested_vmcb->save.idtr   = vmcb->save.idtr;
2684         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2685         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2686         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2687         nested_vmcb->save.cr2    = vmcb->save.cr2;
2688         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2689         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2690         nested_vmcb->save.rip    = vmcb->save.rip;
2691         nested_vmcb->save.rsp    = vmcb->save.rsp;
2692         nested_vmcb->save.rax    = vmcb->save.rax;
2693         nested_vmcb->save.dr7    = vmcb->save.dr7;
2694         nested_vmcb->save.dr6    = vmcb->save.dr6;
2695         nested_vmcb->save.cpl    = vmcb->save.cpl;
2696
2697         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2698         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2699         nested_vmcb->control.int_state         = vmcb->control.int_state;
2700         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2701         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2702         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2703         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2704         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2705         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2706
2707         if (svm->nrips_enabled)
2708                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
2709
2710         /*
2711          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2712          * to make sure that we do not lose injected events. So check event_inj
2713          * here and copy it to exit_int_info if it is valid.
2714          * Exit_int_info and event_inj can't be both valid because the case
2715          * below only happens on a VMRUN instruction intercept which has
2716          * no valid exit_int_info set.
2717          */
2718         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2719                 struct vmcb_control_area *nc = &nested_vmcb->control;
2720
2721                 nc->exit_int_info     = vmcb->control.event_inj;
2722                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2723         }
2724
2725         nested_vmcb->control.tlb_ctl           = 0;
2726         nested_vmcb->control.event_inj         = 0;
2727         nested_vmcb->control.event_inj_err     = 0;
2728
2729         /* We always set V_INTR_MASKING and remember the old value in hflags */
2730         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2731                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2732
2733         /* Restore the original control entries */
2734         copy_vmcb_control_area(vmcb, hsave);
2735
2736         kvm_clear_exception_queue(&svm->vcpu);
2737         kvm_clear_interrupt_queue(&svm->vcpu);
2738
2739         svm->nested.nested_cr3 = 0;
2740
2741         /* Restore selected save entries */
2742         svm->vmcb->save.es = hsave->save.es;
2743         svm->vmcb->save.cs = hsave->save.cs;
2744         svm->vmcb->save.ss = hsave->save.ss;
2745         svm->vmcb->save.ds = hsave->save.ds;
2746         svm->vmcb->save.gdtr = hsave->save.gdtr;
2747         svm->vmcb->save.idtr = hsave->save.idtr;
2748         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2749         svm_set_efer(&svm->vcpu, hsave->save.efer);
2750         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2751         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2752         if (npt_enabled) {
2753                 svm->vmcb->save.cr3 = hsave->save.cr3;
2754                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2755         } else {
2756                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2757         }
2758         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2759         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2760         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2761         svm->vmcb->save.dr7 = 0;
2762         svm->vmcb->save.cpl = 0;
2763         svm->vmcb->control.exit_int_info = 0;
2764
2765         mark_all_dirty(svm->vmcb);
2766
2767         nested_svm_unmap(page);
2768
2769         nested_svm_uninit_mmu_context(&svm->vcpu);
2770         kvm_mmu_reset_context(&svm->vcpu);
2771         kvm_mmu_load(&svm->vcpu);
2772
2773         return 0;
2774 }
2775
2776 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2777 {
2778         /*
2779          * This function merges the msr permission bitmaps of kvm and the
2780          * nested vmcb. It is optimized in that it only merges the parts where
2781          * the kvm msr permission bitmap may contain zero bits
2782          */
2783         int i;
2784
2785         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2786                 return true;
2787
2788         for (i = 0; i < MSRPM_OFFSETS; i++) {
2789                 u32 value, p;
2790                 u64 offset;
2791
2792                 if (msrpm_offsets[i] == 0xffffffff)
2793                         break;
2794
2795                 p      = msrpm_offsets[i];
2796                 offset = svm->nested.vmcb_msrpm + (p * 4);
2797
2798                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2799                         return false;
2800
2801                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2802         }
2803
2804         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2805
2806         return true;
2807 }
2808
2809 static bool nested_vmcb_checks(struct vmcb *vmcb)
2810 {
2811         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2812                 return false;
2813
2814         if (vmcb->control.asid == 0)
2815                 return false;
2816
2817         if (vmcb->control.nested_ctl && !npt_enabled)
2818                 return false;
2819
2820         return true;
2821 }
2822
2823 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2824 {
2825         struct vmcb *nested_vmcb;
2826         struct vmcb *hsave = svm->nested.hsave;
2827         struct vmcb *vmcb = svm->vmcb;
2828         struct page *page;
2829         u64 vmcb_gpa;
2830
2831         vmcb_gpa = svm->vmcb->save.rax;
2832
2833         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2834         if (!nested_vmcb)
2835                 return false;
2836
2837         if (!nested_vmcb_checks(nested_vmcb)) {
2838                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2839                 nested_vmcb->control.exit_code_hi = 0;
2840                 nested_vmcb->control.exit_info_1  = 0;
2841                 nested_vmcb->control.exit_info_2  = 0;
2842
2843                 nested_svm_unmap(page);
2844
2845                 return false;
2846         }
2847
2848         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2849                                nested_vmcb->save.rip,
2850                                nested_vmcb->control.int_ctl,
2851                                nested_vmcb->control.event_inj,
2852                                nested_vmcb->control.nested_ctl);
2853
2854         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2855                                     nested_vmcb->control.intercept_cr >> 16,
2856                                     nested_vmcb->control.intercept_exceptions,
2857                                     nested_vmcb->control.intercept);
2858
2859         /* Clear internal status */
2860         kvm_clear_exception_queue(&svm->vcpu);
2861         kvm_clear_interrupt_queue(&svm->vcpu);
2862
2863         /*
2864          * Save the old vmcb, so we don't need to pick what we save, but can
2865          * restore everything when a VMEXIT occurs
2866          */
2867         hsave->save.es     = vmcb->save.es;
2868         hsave->save.cs     = vmcb->save.cs;
2869         hsave->save.ss     = vmcb->save.ss;
2870         hsave->save.ds     = vmcb->save.ds;
2871         hsave->save.gdtr   = vmcb->save.gdtr;
2872         hsave->save.idtr   = vmcb->save.idtr;
2873         hsave->save.efer   = svm->vcpu.arch.efer;
2874         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2875         hsave->save.cr4    = svm->vcpu.arch.cr4;
2876         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2877         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2878         hsave->save.rsp    = vmcb->save.rsp;
2879         hsave->save.rax    = vmcb->save.rax;
2880         if (npt_enabled)
2881                 hsave->save.cr3    = vmcb->save.cr3;
2882         else
2883                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2884
2885         copy_vmcb_control_area(hsave, vmcb);
2886
2887         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2888                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2889         else
2890                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2891
2892         if (nested_vmcb->control.nested_ctl) {
2893                 kvm_mmu_unload(&svm->vcpu);
2894                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2895                 nested_svm_init_mmu_context(&svm->vcpu);
2896         }
2897
2898         /* Load the nested guest state */
2899         svm->vmcb->save.es = nested_vmcb->save.es;
2900         svm->vmcb->save.cs = nested_vmcb->save.cs;
2901         svm->vmcb->save.ss = nested_vmcb->save.ss;
2902         svm->vmcb->save.ds = nested_vmcb->save.ds;
2903         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2904         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2905         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2906         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2907         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2908         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2909         if (npt_enabled) {
2910                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2911                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2912         } else
2913                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2914
2915         /* Guest paging mode is active - reset mmu */
2916         kvm_mmu_reset_context(&svm->vcpu);
2917
2918         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2919         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2920         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2921         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2922
2923         /* In case we don't even reach vcpu_run, the fields are not updated */
2924         svm->vmcb->save.rax = nested_vmcb->save.rax;
2925         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2926         svm->vmcb->save.rip = nested_vmcb->save.rip;
2927         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2928         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2929         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2930
2931         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2932         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2933
2934         /* cache intercepts */
2935         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2936         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2937         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2938         svm->nested.intercept            = nested_vmcb->control.intercept;
2939
2940         svm_flush_tlb(&svm->vcpu);
2941         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2942         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2943                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2944         else
2945                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2946
2947         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2948                 /* We only want the cr8 intercept bits of the guest */
2949                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2950                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2951         }
2952
2953         /* We don't want to see VMMCALLs from a nested guest */
2954         clr_intercept(svm, INTERCEPT_VMMCALL);
2955
2956         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2957         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2958         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2959         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2960         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2961         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2962
2963         nested_svm_unmap(page);
2964
2965         /* Enter Guest-Mode */
2966         enter_guest_mode(&svm->vcpu);
2967
2968         /*
2969          * Merge guest and host intercepts - must be called  with vcpu in
2970          * guest-mode to take affect here
2971          */
2972         recalc_intercepts(svm);
2973
2974         svm->nested.vmcb = vmcb_gpa;
2975
2976         enable_gif(svm);
2977
2978         mark_all_dirty(svm->vmcb);
2979
2980         return true;
2981 }
2982
2983 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2984 {
2985         to_vmcb->save.fs = from_vmcb->save.fs;
2986         to_vmcb->save.gs = from_vmcb->save.gs;
2987         to_vmcb->save.tr = from_vmcb->save.tr;
2988         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2989         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2990         to_vmcb->save.star = from_vmcb->save.star;
2991         to_vmcb->save.lstar = from_vmcb->save.lstar;
2992         to_vmcb->save.cstar = from_vmcb->save.cstar;
2993         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2994         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2995         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2996         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2997 }
2998
2999 static int vmload_interception(struct vcpu_svm *svm)
3000 {
3001         struct vmcb *nested_vmcb;
3002         struct page *page;
3003
3004         if (nested_svm_check_permissions(svm))
3005                 return 1;
3006
3007         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3008         if (!nested_vmcb)
3009                 return 1;
3010
3011         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3012         skip_emulated_instruction(&svm->vcpu);
3013
3014         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3015         nested_svm_unmap(page);
3016
3017         return 1;
3018 }
3019
3020 static int vmsave_interception(struct vcpu_svm *svm)
3021 {
3022         struct vmcb *nested_vmcb;
3023         struct page *page;
3024
3025         if (nested_svm_check_permissions(svm))
3026                 return 1;
3027
3028         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3029         if (!nested_vmcb)
3030                 return 1;
3031
3032         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3033         skip_emulated_instruction(&svm->vcpu);
3034
3035         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3036         nested_svm_unmap(page);
3037
3038         return 1;
3039 }
3040
3041 static int vmrun_interception(struct vcpu_svm *svm)
3042 {
3043         if (nested_svm_check_permissions(svm))
3044                 return 1;
3045
3046         /* Save rip after vmrun instruction */
3047         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3048
3049         if (!nested_svm_vmrun(svm))
3050                 return 1;
3051
3052         if (!nested_svm_vmrun_msrpm(svm))
3053                 goto failed;
3054
3055         return 1;
3056
3057 failed:
3058
3059         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3060         svm->vmcb->control.exit_code_hi = 0;
3061         svm->vmcb->control.exit_info_1  = 0;
3062         svm->vmcb->control.exit_info_2  = 0;
3063
3064         nested_svm_vmexit(svm);
3065
3066         return 1;
3067 }
3068
3069 static int stgi_interception(struct vcpu_svm *svm)
3070 {
3071         if (nested_svm_check_permissions(svm))
3072                 return 1;
3073
3074         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3075         skip_emulated_instruction(&svm->vcpu);
3076         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3077
3078         enable_gif(svm);
3079
3080         return 1;
3081 }
3082
3083 static int clgi_interception(struct vcpu_svm *svm)
3084 {
3085         if (nested_svm_check_permissions(svm))
3086                 return 1;
3087
3088         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3089         skip_emulated_instruction(&svm->vcpu);
3090
3091         disable_gif(svm);
3092
3093         /* After a CLGI no interrupts should come */
3094         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3095                 svm_clear_vintr(svm);
3096                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3097                 mark_dirty(svm->vmcb, VMCB_INTR);
3098         }
3099
3100         return 1;
3101 }
3102
3103 static int invlpga_interception(struct vcpu_svm *svm)
3104 {
3105         struct kvm_vcpu *vcpu = &svm->vcpu;
3106
3107         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3108                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3109
3110         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3111         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3112
3113         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3114         skip_emulated_instruction(&svm->vcpu);
3115         return 1;
3116 }
3117
3118 static int skinit_interception(struct vcpu_svm *svm)
3119 {
3120         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3121
3122         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3123         return 1;
3124 }
3125
3126 static int wbinvd_interception(struct vcpu_svm *svm)
3127 {
3128         return kvm_emulate_wbinvd(&svm->vcpu);
3129 }
3130
3131 static int xsetbv_interception(struct vcpu_svm *svm)
3132 {
3133         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3134         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3135
3136         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3137                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3138                 skip_emulated_instruction(&svm->vcpu);
3139         }
3140
3141         return 1;
3142 }
3143
3144 static int task_switch_interception(struct vcpu_svm *svm)
3145 {
3146         u16 tss_selector;
3147         int reason;
3148         int int_type = svm->vmcb->control.exit_int_info &
3149                 SVM_EXITINTINFO_TYPE_MASK;
3150         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3151         uint32_t type =
3152                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3153         uint32_t idt_v =
3154                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3155         bool has_error_code = false;
3156         u32 error_code = 0;
3157
3158         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3159
3160         if (svm->vmcb->control.exit_info_2 &
3161             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3162                 reason = TASK_SWITCH_IRET;
3163         else if (svm->vmcb->control.exit_info_2 &
3164                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3165                 reason = TASK_SWITCH_JMP;
3166         else if (idt_v)
3167                 reason = TASK_SWITCH_GATE;
3168         else
3169                 reason = TASK_SWITCH_CALL;
3170
3171         if (reason == TASK_SWITCH_GATE) {
3172                 switch (type) {
3173                 case SVM_EXITINTINFO_TYPE_NMI:
3174                         svm->vcpu.arch.nmi_injected = false;
3175                         break;
3176                 case SVM_EXITINTINFO_TYPE_EXEPT:
3177                         if (svm->vmcb->control.exit_info_2 &
3178                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3179                                 has_error_code = true;
3180                                 error_code =
3181                                         (u32)svm->vmcb->control.exit_info_2;
3182                         }
3183                         kvm_clear_exception_queue(&svm->vcpu);
3184                         break;
3185                 case SVM_EXITINTINFO_TYPE_INTR:
3186                         kvm_clear_interrupt_queue(&svm->vcpu);
3187                         break;
3188                 default:
3189                         break;
3190                 }
3191         }
3192
3193         if (reason != TASK_SWITCH_GATE ||
3194             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3195             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3196              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3197                 skip_emulated_instruction(&svm->vcpu);
3198
3199         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3200                 int_vec = -1;
3201
3202         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3203                                 has_error_code, error_code) == EMULATE_FAIL) {
3204                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3205                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3206                 svm->vcpu.run->internal.ndata = 0;
3207                 return 0;
3208         }
3209         return 1;
3210 }
3211
3212 static int cpuid_interception(struct vcpu_svm *svm)
3213 {
3214         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3215         return kvm_emulate_cpuid(&svm->vcpu);
3216 }
3217
3218 static int iret_interception(struct vcpu_svm *svm)
3219 {
3220         ++svm->vcpu.stat.nmi_window_exits;
3221         clr_intercept(svm, INTERCEPT_IRET);
3222         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3223         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3224         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3225         return 1;
3226 }
3227
3228 static int invlpg_interception(struct vcpu_svm *svm)
3229 {
3230         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3231                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3232
3233         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3234         skip_emulated_instruction(&svm->vcpu);
3235         return 1;
3236 }
3237
3238 static int emulate_on_interception(struct vcpu_svm *svm)
3239 {
3240         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3241 }
3242
3243 static int rdpmc_interception(struct vcpu_svm *svm)
3244 {
3245         int err;
3246
3247         if (!static_cpu_has(X86_FEATURE_NRIPS))
3248                 return emulate_on_interception(svm);
3249
3250         err = kvm_rdpmc(&svm->vcpu);
3251         return kvm_complete_insn_gp(&svm->vcpu, err);
3252 }
3253
3254 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3255                                             unsigned long val)
3256 {
3257         unsigned long cr0 = svm->vcpu.arch.cr0;
3258         bool ret = false;
3259         u64 intercept;
3260
3261         intercept = svm->nested.intercept;
3262
3263         if (!is_guest_mode(&svm->vcpu) ||
3264             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3265                 return false;
3266
3267         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3268         val &= ~SVM_CR0_SELECTIVE_MASK;
3269
3270         if (cr0 ^ val) {
3271                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3272                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3273         }
3274
3275         return ret;
3276 }
3277
3278 #define CR_VALID (1ULL << 63)
3279
3280 static int cr_interception(struct vcpu_svm *svm)
3281 {
3282         int reg, cr;
3283         unsigned long val;
3284         int err;
3285
3286         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3287                 return emulate_on_interception(svm);
3288
3289         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3290                 return emulate_on_interception(svm);
3291
3292         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3293         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3294                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3295         else
3296                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3297
3298         err = 0;
3299         if (cr >= 16) { /* mov to cr */
3300                 cr -= 16;
3301                 val = kvm_register_read(&svm->vcpu, reg);
3302                 switch (cr) {
3303                 case 0:
3304                         if (!check_selective_cr0_intercepted(svm, val))
3305                                 err = kvm_set_cr0(&svm->vcpu, val);
3306                         else
3307                                 return 1;
3308
3309                         break;
3310                 case 3:
3311                         err = kvm_set_cr3(&svm->vcpu, val);
3312                         break;
3313                 case 4:
3314                         err = kvm_set_cr4(&svm->vcpu, val);
3315                         break;
3316                 case 8:
3317                         err = kvm_set_cr8(&svm->vcpu, val);
3318                         break;
3319                 default:
3320                         WARN(1, "unhandled write to CR%d", cr);
3321                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3322                         return 1;
3323                 }
3324         } else { /* mov from cr */
3325                 switch (cr) {
3326                 case 0:
3327                         val = kvm_read_cr0(&svm->vcpu);
3328                         break;
3329                 case 2:
3330                         val = svm->vcpu.arch.cr2;
3331                         break;
3332                 case 3:
3333                         val = kvm_read_cr3(&svm->vcpu);
3334                         break;
3335                 case 4:
3336                         val = kvm_read_cr4(&svm->vcpu);
3337                         break;
3338                 case 8:
3339                         val = kvm_get_cr8(&svm->vcpu);
3340                         break;
3341                 default:
3342                         WARN(1, "unhandled read from CR%d", cr);
3343                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3344                         return 1;
3345                 }
3346                 kvm_register_write(&svm->vcpu, reg, val);
3347         }
3348         return kvm_complete_insn_gp(&svm->vcpu, err);
3349 }
3350
3351 static int dr_interception(struct vcpu_svm *svm)
3352 {
3353         int reg, dr;
3354         unsigned long val;
3355
3356         if (svm->vcpu.guest_debug == 0) {
3357                 /*
3358                  * No more DR vmexits; force a reload of the debug registers
3359                  * and reenter on this instruction.  The next vmexit will
3360                  * retrieve the full state of the debug registers.
3361                  */
3362                 clr_dr_intercepts(svm);
3363                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3364                 return 1;
3365         }
3366
3367         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3368                 return emulate_on_interception(svm);
3369
3370         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3371         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3372
3373         if (dr >= 16) { /* mov to DRn */
3374                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3375                         return 1;
3376                 val = kvm_register_read(&svm->vcpu, reg);
3377                 kvm_set_dr(&svm->vcpu, dr - 16, val);
3378         } else {
3379                 if (!kvm_require_dr(&svm->vcpu, dr))
3380                         return 1;
3381                 kvm_get_dr(&svm->vcpu, dr, &val);
3382                 kvm_register_write(&svm->vcpu, reg, val);
3383         }
3384
3385         skip_emulated_instruction(&svm->vcpu);
3386
3387         return 1;
3388 }
3389
3390 static int cr8_write_interception(struct vcpu_svm *svm)
3391 {
3392         struct kvm_run *kvm_run = svm->vcpu.run;
3393         int r;
3394
3395         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3396         /* instruction emulation calls kvm_set_cr8() */
3397         r = cr_interception(svm);
3398         if (lapic_in_kernel(&svm->vcpu))
3399                 return r;
3400         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3401                 return r;
3402         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3403         return 0;
3404 }
3405
3406 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3407 {
3408         struct vcpu_svm *svm = to_svm(vcpu);
3409
3410         switch (msr_info->index) {
3411         case MSR_IA32_TSC: {
3412                 msr_info->data = svm->vmcb->control.tsc_offset +
3413                         kvm_scale_tsc(vcpu, rdtsc());
3414
3415                 break;
3416         }
3417         case MSR_STAR:
3418                 msr_info->data = svm->vmcb->save.star;
3419                 break;
3420 #ifdef CONFIG_X86_64
3421         case MSR_LSTAR:
3422                 msr_info->data = svm->vmcb->save.lstar;
3423                 break;
3424         case MSR_CSTAR:
3425                 msr_info->data = svm->vmcb->save.cstar;
3426                 break;
3427         case MSR_KERNEL_GS_BASE:
3428                 msr_info->data = svm->vmcb->save.kernel_gs_base;
3429                 break;
3430         case MSR_SYSCALL_MASK:
3431                 msr_info->data = svm->vmcb->save.sfmask;
3432                 break;
3433 #endif
3434         case MSR_IA32_SYSENTER_CS:
3435                 msr_info->data = svm->vmcb->save.sysenter_cs;
3436                 break;
3437         case MSR_IA32_SYSENTER_EIP:
3438                 msr_info->data = svm->sysenter_eip;
3439                 break;
3440         case MSR_IA32_SYSENTER_ESP:
3441                 msr_info->data = svm->sysenter_esp;
3442                 break;
3443         case MSR_TSC_AUX:
3444                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3445                         return 1;
3446                 msr_info->data = svm->tsc_aux;
3447                 break;
3448         /*
3449          * Nobody will change the following 5 values in the VMCB so we can
3450          * safely return them on rdmsr. They will always be 0 until LBRV is
3451          * implemented.
3452          */
3453         case MSR_IA32_DEBUGCTLMSR:
3454                 msr_info->data = svm->vmcb->save.dbgctl;
3455                 break;
3456         case MSR_IA32_LASTBRANCHFROMIP:
3457                 msr_info->data = svm->vmcb->save.br_from;
3458                 break;
3459         case MSR_IA32_LASTBRANCHTOIP:
3460                 msr_info->data = svm->vmcb->save.br_to;
3461                 break;
3462         case MSR_IA32_LASTINTFROMIP:
3463                 msr_info->data = svm->vmcb->save.last_excp_from;
3464                 break;
3465         case MSR_IA32_LASTINTTOIP:
3466                 msr_info->data = svm->vmcb->save.last_excp_to;
3467                 break;
3468         case MSR_VM_HSAVE_PA:
3469                 msr_info->data = svm->nested.hsave_msr;
3470                 break;
3471         case MSR_VM_CR:
3472                 msr_info->data = svm->nested.vm_cr_msr;
3473                 break;
3474         case MSR_IA32_UCODE_REV:
3475                 msr_info->data = 0x01000065;
3476                 break;
3477         case MSR_F15H_IC_CFG: {
3478
3479                 int family, model;
3480
3481                 family = guest_cpuid_family(vcpu);
3482                 model  = guest_cpuid_model(vcpu);
3483
3484                 if (family < 0 || model < 0)
3485                         return kvm_get_msr_common(vcpu, msr_info);
3486
3487                 msr_info->data = 0;
3488
3489                 if (family == 0x15 &&
3490                     (model >= 0x2 && model < 0x20))
3491                         msr_info->data = 0x1E;
3492                 }
3493                 break;
3494         default:
3495                 return kvm_get_msr_common(vcpu, msr_info);
3496         }
3497         return 0;
3498 }
3499
3500 static int rdmsr_interception(struct vcpu_svm *svm)
3501 {
3502         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3503         struct msr_data msr_info;
3504
3505         msr_info.index = ecx;
3506         msr_info.host_initiated = false;
3507         if (svm_get_msr(&svm->vcpu, &msr_info)) {
3508                 trace_kvm_msr_read_ex(ecx);
3509                 kvm_inject_gp(&svm->vcpu, 0);
3510         } else {
3511                 trace_kvm_msr_read(ecx, msr_info.data);
3512
3513                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3514                                    msr_info.data & 0xffffffff);
3515                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3516                                    msr_info.data >> 32);
3517                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3518                 skip_emulated_instruction(&svm->vcpu);
3519         }
3520         return 1;
3521 }
3522
3523 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3524 {
3525         struct vcpu_svm *svm = to_svm(vcpu);
3526         int svm_dis, chg_mask;
3527
3528         if (data & ~SVM_VM_CR_VALID_MASK)
3529                 return 1;
3530
3531         chg_mask = SVM_VM_CR_VALID_MASK;
3532
3533         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3534                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3535
3536         svm->nested.vm_cr_msr &= ~chg_mask;
3537         svm->nested.vm_cr_msr |= (data & chg_mask);
3538
3539         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3540
3541         /* check for svm_disable while efer.svme is set */
3542         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3543                 return 1;
3544
3545         return 0;
3546 }
3547
3548 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3549 {
3550         struct vcpu_svm *svm = to_svm(vcpu);
3551
3552         u32 ecx = msr->index;
3553         u64 data = msr->data;
3554         switch (ecx) {
3555         case MSR_IA32_TSC:
3556                 kvm_write_tsc(vcpu, msr);
3557                 break;
3558         case MSR_STAR:
3559                 svm->vmcb->save.star = data;
3560                 break;
3561 #ifdef CONFIG_X86_64
3562         case MSR_LSTAR:
3563                 svm->vmcb->save.lstar = data;
3564                 break;
3565         case MSR_CSTAR:
3566                 svm->vmcb->save.cstar = data;
3567                 break;
3568         case MSR_KERNEL_GS_BASE:
3569                 svm->vmcb->save.kernel_gs_base = data;
3570                 break;
3571         case MSR_SYSCALL_MASK:
3572                 svm->vmcb->save.sfmask = data;
3573                 break;
3574 #endif
3575         case MSR_IA32_SYSENTER_CS:
3576                 svm->vmcb->save.sysenter_cs = data;
3577                 break;
3578         case MSR_IA32_SYSENTER_EIP:
3579                 svm->sysenter_eip = data;
3580                 svm->vmcb->save.sysenter_eip = data;
3581                 break;
3582         case MSR_IA32_SYSENTER_ESP:
3583                 svm->sysenter_esp = data;
3584                 svm->vmcb->save.sysenter_esp = data;
3585                 break;
3586         case MSR_TSC_AUX:
3587                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3588                         return 1;
3589
3590                 /*
3591                  * This is rare, so we update the MSR here instead of using
3592                  * direct_access_msrs.  Doing that would require a rdmsr in
3593                  * svm_vcpu_put.
3594                  */
3595                 svm->tsc_aux = data;
3596                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3597                 break;
3598         case MSR_IA32_DEBUGCTLMSR:
3599                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3600                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3601                                     __func__, data);
3602                         break;
3603                 }
3604                 if (data & DEBUGCTL_RESERVED_BITS)
3605                         return 1;
3606
3607                 svm->vmcb->save.dbgctl = data;
3608                 mark_dirty(svm->vmcb, VMCB_LBR);
3609                 if (data & (1ULL<<0))
3610                         svm_enable_lbrv(svm);
3611                 else
3612                         svm_disable_lbrv(svm);
3613                 break;
3614         case MSR_VM_HSAVE_PA:
3615                 svm->nested.hsave_msr = data;
3616                 break;
3617         case MSR_VM_CR:
3618                 return svm_set_vm_cr(vcpu, data);
3619         case MSR_VM_IGNNE:
3620                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3621                 break;
3622         case MSR_IA32_APICBASE:
3623                 if (kvm_vcpu_apicv_active(vcpu))
3624                         avic_update_vapic_bar(to_svm(vcpu), data);
3625                 /* Follow through */
3626         default:
3627                 return kvm_set_msr_common(vcpu, msr);
3628         }
3629         return 0;
3630 }
3631
3632 static int wrmsr_interception(struct vcpu_svm *svm)
3633 {
3634         struct msr_data msr;
3635         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3636         u64 data = kvm_read_edx_eax(&svm->vcpu);
3637
3638         msr.data = data;
3639         msr.index = ecx;
3640         msr.host_initiated = false;
3641
3642         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3643         if (kvm_set_msr(&svm->vcpu, &msr)) {
3644                 trace_kvm_msr_write_ex(ecx, data);
3645                 kvm_inject_gp(&svm->vcpu, 0);
3646         } else {
3647                 trace_kvm_msr_write(ecx, data);
3648                 skip_emulated_instruction(&svm->vcpu);
3649         }
3650         return 1;
3651 }
3652
3653 static int msr_interception(struct vcpu_svm *svm)
3654 {
3655         if (svm->vmcb->control.exit_info_1)
3656                 return wrmsr_interception(svm);
3657         else
3658                 return rdmsr_interception(svm);
3659 }
3660
3661 static int interrupt_window_interception(struct vcpu_svm *svm)
3662 {
3663         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3664         svm_clear_vintr(svm);
3665         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3666         mark_dirty(svm->vmcb, VMCB_INTR);
3667         ++svm->vcpu.stat.irq_window_exits;
3668         return 1;
3669 }
3670
3671 static int pause_interception(struct vcpu_svm *svm)
3672 {
3673         kvm_vcpu_on_spin(&(svm->vcpu));
3674         return 1;
3675 }
3676
3677 static int nop_interception(struct vcpu_svm *svm)
3678 {
3679         skip_emulated_instruction(&(svm->vcpu));
3680         return 1;
3681 }
3682
3683 static int monitor_interception(struct vcpu_svm *svm)
3684 {
3685         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3686         return nop_interception(svm);
3687 }
3688
3689 static int mwait_interception(struct vcpu_svm *svm)
3690 {
3691         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3692         return nop_interception(svm);
3693 }
3694
3695 enum avic_ipi_failure_cause {
3696         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3697         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3698         AVIC_IPI_FAILURE_INVALID_TARGET,
3699         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3700 };
3701
3702 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3703 {
3704         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3705         u32 icrl = svm->vmcb->control.exit_info_1;
3706         u32 id = svm->vmcb->control.exit_info_2 >> 32;
3707         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3708         struct kvm_lapic *apic = svm->vcpu.arch.apic;
3709
3710         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3711
3712         switch (id) {
3713         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3714                 /*
3715                  * AVIC hardware handles the generation of
3716                  * IPIs when the specified Message Type is Fixed
3717                  * (also known as fixed delivery mode) and
3718                  * the Trigger Mode is edge-triggered. The hardware
3719                  * also supports self and broadcast delivery modes
3720                  * specified via the Destination Shorthand(DSH)
3721                  * field of the ICRL. Logical and physical APIC ID
3722                  * formats are supported. All other IPI types cause
3723                  * a #VMEXIT, which needs to emulated.
3724                  */
3725                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3726                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3727                 break;
3728         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3729                 int i;
3730                 struct kvm_vcpu *vcpu;
3731                 struct kvm *kvm = svm->vcpu.kvm;
3732                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3733
3734                 /*
3735                  * At this point, we expect that the AVIC HW has already
3736                  * set the appropriate IRR bits on the valid target
3737                  * vcpus. So, we just need to kick the appropriate vcpu.
3738                  */
3739                 kvm_for_each_vcpu(i, vcpu, kvm) {
3740                         bool m = kvm_apic_match_dest(vcpu, apic,
3741                                                      icrl & KVM_APIC_SHORT_MASK,
3742                                                      GET_APIC_DEST_FIELD(icrh),
3743                                                      icrl & KVM_APIC_DEST_MASK);
3744
3745                         if (m && !avic_vcpu_is_running(vcpu))
3746                                 kvm_vcpu_wake_up(vcpu);
3747                 }
3748                 break;
3749         }
3750         case AVIC_IPI_FAILURE_INVALID_TARGET:
3751                 break;
3752         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3753                 WARN_ONCE(1, "Invalid backing page\n");
3754                 break;
3755         default:
3756                 pr_err("Unknown IPI interception\n");
3757         }
3758
3759         return 1;
3760 }
3761
3762 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3763 {
3764         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3765         int index;
3766         u32 *logical_apic_id_table;
3767         int dlid = GET_APIC_LOGICAL_ID(ldr);
3768
3769         if (!dlid)
3770                 return NULL;
3771
3772         if (flat) { /* flat */
3773                 index = ffs(dlid) - 1;
3774                 if (index > 7)
3775                         return NULL;
3776         } else { /* cluster */
3777                 int cluster = (dlid & 0xf0) >> 4;
3778                 int apic = ffs(dlid & 0x0f) - 1;
3779
3780                 if ((apic < 0) || (apic > 7) ||
3781                     (cluster >= 0xf))
3782                         return NULL;
3783                 index = (cluster << 2) + apic;
3784         }
3785
3786         logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3787
3788         return &logical_apic_id_table[index];
3789 }
3790
3791 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3792                           bool valid)
3793 {
3794         bool flat;
3795         u32 *entry, new_entry;
3796
3797         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3798         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3799         if (!entry)
3800                 return -EINVAL;
3801
3802         new_entry = READ_ONCE(*entry);
3803         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3804         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3805         if (valid)
3806                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3807         else
3808                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3809         WRITE_ONCE(*entry, new_entry);
3810
3811         return 0;
3812 }
3813
3814 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3815 {
3816         int ret;
3817         struct vcpu_svm *svm = to_svm(vcpu);
3818         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3819
3820         if (!ldr)
3821                 return 1;
3822
3823         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3824         if (ret && svm->ldr_reg) {
3825                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3826                 svm->ldr_reg = 0;
3827         } else {
3828                 svm->ldr_reg = ldr;
3829         }
3830         return ret;
3831 }
3832
3833 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3834 {
3835         u64 *old, *new;
3836         struct vcpu_svm *svm = to_svm(vcpu);
3837         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3838         u32 id = (apic_id_reg >> 24) & 0xff;
3839
3840         if (vcpu->vcpu_id == id)
3841                 return 0;
3842
3843         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3844         new = avic_get_physical_id_entry(vcpu, id);
3845         if (!new || !old)
3846                 return 1;
3847
3848         /* We need to move physical_id_entry to new offset */
3849         *new = *old;
3850         *old = 0ULL;
3851         to_svm(vcpu)->avic_physical_id_cache = new;
3852
3853         /*
3854          * Also update the guest physical APIC ID in the logical
3855          * APIC ID table entry if already setup the LDR.
3856          */
3857         if (svm->ldr_reg)
3858                 avic_handle_ldr_update(vcpu);
3859
3860         return 0;
3861 }
3862
3863 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3864 {
3865         struct vcpu_svm *svm = to_svm(vcpu);
3866         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3867         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3868         u32 mod = (dfr >> 28) & 0xf;
3869
3870         /*
3871          * We assume that all local APICs are using the same type.
3872          * If this changes, we need to flush the AVIC logical
3873          * APID id table.
3874          */
3875         if (vm_data->ldr_mode == mod)
3876                 return 0;
3877
3878         clear_page(page_address(vm_data->avic_logical_id_table_page));
3879         vm_data->ldr_mode = mod;
3880
3881         if (svm->ldr_reg)
3882                 avic_handle_ldr_update(vcpu);
3883         return 0;
3884 }
3885
3886 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3887 {
3888         struct kvm_lapic *apic = svm->vcpu.arch.apic;
3889         u32 offset = svm->vmcb->control.exit_info_1 &
3890                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3891
3892         switch (offset) {
3893         case APIC_ID:
3894                 if (avic_handle_apic_id_update(&svm->vcpu))
3895                         return 0;
3896                 break;
3897         case APIC_LDR:
3898                 if (avic_handle_ldr_update(&svm->vcpu))
3899                         return 0;
3900                 break;
3901         case APIC_DFR:
3902                 avic_handle_dfr_update(&svm->vcpu);
3903                 break;
3904         default:
3905                 break;
3906         }
3907
3908         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
3909
3910         return 1;
3911 }
3912
3913 static bool is_avic_unaccelerated_access_trap(u32 offset)
3914 {
3915         bool ret = false;
3916
3917         switch (offset) {
3918         case APIC_ID:
3919         case APIC_EOI:
3920         case APIC_RRR:
3921         case APIC_LDR:
3922         case APIC_DFR:
3923         case APIC_SPIV:
3924         case APIC_ESR:
3925         case APIC_ICR:
3926         case APIC_LVTT:
3927         case APIC_LVTTHMR:
3928         case APIC_LVTPC:
3929         case APIC_LVT0:
3930         case APIC_LVT1:
3931         case APIC_LVTERR:
3932         case APIC_TMICT:
3933         case APIC_TDCR:
3934                 ret = true;
3935                 break;
3936         default:
3937                 break;
3938         }
3939         return ret;
3940 }
3941
3942 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
3943 {
3944         int ret = 0;
3945         u32 offset = svm->vmcb->control.exit_info_1 &
3946                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3947         u32 vector = svm->vmcb->control.exit_info_2 &
3948                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
3949         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
3950                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
3951         bool trap = is_avic_unaccelerated_access_trap(offset);
3952
3953         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
3954                                             trap, write, vector);
3955         if (trap) {
3956                 /* Handling Trap */
3957                 WARN_ONCE(!write, "svm: Handling trap read.\n");
3958                 ret = avic_unaccel_trap_write(svm);
3959         } else {
3960                 /* Handling Fault */
3961                 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
3962         }
3963
3964         return ret;
3965 }
3966
3967 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3968         [SVM_EXIT_READ_CR0]                     = cr_interception,
3969         [SVM_EXIT_READ_CR3]                     = cr_interception,
3970         [SVM_EXIT_READ_CR4]                     = cr_interception,
3971         [SVM_EXIT_READ_CR8]                     = cr_interception,
3972         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
3973         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3974         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3975         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3976         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3977         [SVM_EXIT_READ_DR0]                     = dr_interception,
3978         [SVM_EXIT_READ_DR1]                     = dr_interception,
3979         [SVM_EXIT_READ_DR2]                     = dr_interception,
3980         [SVM_EXIT_READ_DR3]                     = dr_interception,
3981         [SVM_EXIT_READ_DR4]                     = dr_interception,
3982         [SVM_EXIT_READ_DR5]                     = dr_interception,
3983         [SVM_EXIT_READ_DR6]                     = dr_interception,
3984         [SVM_EXIT_READ_DR7]                     = dr_interception,
3985         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3986         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3987         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3988         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3989         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3990         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3991         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3992         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3993         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3994         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3995         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3996         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3997         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3998         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
3999         [SVM_EXIT_INTR]                         = intr_interception,
4000         [SVM_EXIT_NMI]                          = nmi_interception,
4001         [SVM_EXIT_SMI]                          = nop_on_interception,
4002         [SVM_EXIT_INIT]                         = nop_on_interception,
4003         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4004         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4005         [SVM_EXIT_CPUID]                        = cpuid_interception,
4006         [SVM_EXIT_IRET]                         = iret_interception,
4007         [SVM_EXIT_INVD]                         = emulate_on_interception,
4008         [SVM_EXIT_PAUSE]                        = pause_interception,
4009         [SVM_EXIT_HLT]                          = halt_interception,
4010         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4011         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4012         [SVM_EXIT_IOIO]                         = io_interception,
4013         [SVM_EXIT_MSR]                          = msr_interception,
4014         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4015         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4016         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4017         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4018         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4019         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4020         [SVM_EXIT_STGI]                         = stgi_interception,
4021         [SVM_EXIT_CLGI]                         = clgi_interception,
4022         [SVM_EXIT_SKINIT]                       = skinit_interception,
4023         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4024         [SVM_EXIT_MONITOR]                      = monitor_interception,
4025         [SVM_EXIT_MWAIT]                        = mwait_interception,
4026         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4027         [SVM_EXIT_NPF]                          = pf_interception,
4028         [SVM_EXIT_RSM]                          = emulate_on_interception,
4029         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4030         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4031 };
4032
4033 static void dump_vmcb(struct kvm_vcpu *vcpu)
4034 {
4035         struct vcpu_svm *svm = to_svm(vcpu);
4036         struct vmcb_control_area *control = &svm->vmcb->control;
4037         struct vmcb_save_area *save = &svm->vmcb->save;
4038
4039         pr_err("VMCB Control Area:\n");
4040         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4041         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4042         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4043         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4044         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4045         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4046         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4047         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4048         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4049         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4050         pr_err("%-20s%d\n", "asid:", control->asid);
4051         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4052         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4053         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4054         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4055         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4056         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4057         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4058         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4059         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4060         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4061         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4062         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4063         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4064         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4065         pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
4066         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4067         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4068         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4069         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4070         pr_err("VMCB State Save Area:\n");
4071         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4072                "es:",
4073                save->es.selector, save->es.attrib,
4074                save->es.limit, save->es.base);
4075         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4076                "cs:",
4077                save->cs.selector, save->cs.attrib,
4078                save->cs.limit, save->cs.base);
4079         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4080                "ss:",
4081                save->ss.selector, save->ss.attrib,
4082                save->ss.limit, save->ss.base);
4083         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4084                "ds:",
4085                save->ds.selector, save->ds.attrib,
4086                save->ds.limit, save->ds.base);
4087         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4088                "fs:",
4089                save->fs.selector, save->fs.attrib,
4090                save->fs.limit, save->fs.base);
4091         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4092                "gs:",
4093                save->gs.selector, save->gs.attrib,
4094                save->gs.limit, save->gs.base);
4095         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4096                "gdtr:",
4097                save->gdtr.selector, save->gdtr.attrib,
4098                save->gdtr.limit, save->gdtr.base);
4099         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4100                "ldtr:",
4101                save->ldtr.selector, save->ldtr.attrib,
4102                save->ldtr.limit, save->ldtr.base);
4103         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4104                "idtr:",
4105                save->idtr.selector, save->idtr.attrib,
4106                save->idtr.limit, save->idtr.base);
4107         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4108                "tr:",
4109                save->tr.selector, save->tr.attrib,
4110                save->tr.limit, save->tr.base);
4111         pr_err("cpl:            %d                efer:         %016llx\n",
4112                 save->cpl, save->efer);
4113         pr_err("%-15s %016llx %-13s %016llx\n",
4114                "cr0:", save->cr0, "cr2:", save->cr2);
4115         pr_err("%-15s %016llx %-13s %016llx\n",
4116                "cr3:", save->cr3, "cr4:", save->cr4);
4117         pr_err("%-15s %016llx %-13s %016llx\n",
4118                "dr6:", save->dr6, "dr7:", save->dr7);
4119         pr_err("%-15s %016llx %-13s %016llx\n",
4120                "rip:", save->rip, "rflags:", save->rflags);
4121         pr_err("%-15s %016llx %-13s %016llx\n",
4122                "rsp:", save->rsp, "rax:", save->rax);
4123         pr_err("%-15s %016llx %-13s %016llx\n",
4124                "star:", save->star, "lstar:", save->lstar);
4125         pr_err("%-15s %016llx %-13s %016llx\n",
4126                "cstar:", save->cstar, "sfmask:", save->sfmask);
4127         pr_err("%-15s %016llx %-13s %016llx\n",
4128                "kernel_gs_base:", save->kernel_gs_base,
4129                "sysenter_cs:", save->sysenter_cs);
4130         pr_err("%-15s %016llx %-13s %016llx\n",
4131                "sysenter_esp:", save->sysenter_esp,
4132                "sysenter_eip:", save->sysenter_eip);
4133         pr_err("%-15s %016llx %-13s %016llx\n",
4134                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4135         pr_err("%-15s %016llx %-13s %016llx\n",
4136                "br_from:", save->br_from, "br_to:", save->br_to);
4137         pr_err("%-15s %016llx %-13s %016llx\n",
4138                "excp_from:", save->last_excp_from,
4139                "excp_to:", save->last_excp_to);
4140 }
4141
4142 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4143 {
4144         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4145
4146         *info1 = control->exit_info_1;
4147         *info2 = control->exit_info_2;
4148 }
4149
4150 static int handle_exit(struct kvm_vcpu *vcpu)
4151 {
4152         struct vcpu_svm *svm = to_svm(vcpu);
4153         struct kvm_run *kvm_run = vcpu->run;
4154         u32 exit_code = svm->vmcb->control.exit_code;
4155
4156         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4157
4158         vcpu->arch.gpa_available = (exit_code == SVM_EXIT_NPF);
4159
4160         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4161                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4162         if (npt_enabled)
4163                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4164
4165         if (unlikely(svm->nested.exit_required)) {
4166                 nested_svm_vmexit(svm);
4167                 svm->nested.exit_required = false;
4168
4169                 return 1;
4170         }
4171
4172         if (is_guest_mode(vcpu)) {
4173                 int vmexit;
4174
4175                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4176                                         svm->vmcb->control.exit_info_1,
4177                                         svm->vmcb->control.exit_info_2,
4178                                         svm->vmcb->control.exit_int_info,
4179                                         svm->vmcb->control.exit_int_info_err,
4180                                         KVM_ISA_SVM);
4181
4182                 vmexit = nested_svm_exit_special(svm);
4183
4184                 if (vmexit == NESTED_EXIT_CONTINUE)
4185                         vmexit = nested_svm_exit_handled(svm);
4186
4187                 if (vmexit == NESTED_EXIT_DONE)
4188                         return 1;
4189         }
4190
4191         svm_complete_interrupts(svm);
4192
4193         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4194                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4195                 kvm_run->fail_entry.hardware_entry_failure_reason
4196                         = svm->vmcb->control.exit_code;
4197                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4198                 dump_vmcb(vcpu);
4199                 return 0;
4200         }
4201
4202         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4203             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4204             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4205             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4206                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4207                        "exit_code 0x%x\n",
4208                        __func__, svm->vmcb->control.exit_int_info,
4209                        exit_code);
4210
4211         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4212             || !svm_exit_handlers[exit_code]) {
4213                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4214                 kvm_queue_exception(vcpu, UD_VECTOR);
4215                 return 1;
4216         }
4217
4218         return svm_exit_handlers[exit_code](svm);
4219 }
4220
4221 static void reload_tss(struct kvm_vcpu *vcpu)
4222 {
4223         int cpu = raw_smp_processor_id();
4224
4225         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4226         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4227         load_TR_desc();
4228 }
4229
4230 static void pre_svm_run(struct vcpu_svm *svm)
4231 {
4232         int cpu = raw_smp_processor_id();
4233
4234         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4235
4236         /* FIXME: handle wraparound of asid_generation */
4237         if (svm->asid_generation != sd->asid_generation)
4238                 new_asid(svm, sd);
4239 }
4240
4241 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4242 {
4243         struct vcpu_svm *svm = to_svm(vcpu);
4244
4245         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4246         vcpu->arch.hflags |= HF_NMI_MASK;
4247         set_intercept(svm, INTERCEPT_IRET);
4248         ++vcpu->stat.nmi_injections;
4249 }
4250
4251 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4252 {
4253         struct vmcb_control_area *control;
4254
4255         /* The following fields are ignored when AVIC is enabled */
4256         control = &svm->vmcb->control;
4257         control->int_vector = irq;
4258         control->int_ctl &= ~V_INTR_PRIO_MASK;
4259         control->int_ctl |= V_IRQ_MASK |
4260                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4261         mark_dirty(svm->vmcb, VMCB_INTR);
4262 }
4263
4264 static void svm_set_irq(struct kvm_vcpu *vcpu)
4265 {
4266         struct vcpu_svm *svm = to_svm(vcpu);
4267
4268         BUG_ON(!(gif_set(svm)));
4269
4270         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4271         ++vcpu->stat.irq_injections;
4272
4273         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4274                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4275 }
4276
4277 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4278 {
4279         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4280 }
4281
4282 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4283 {
4284         struct vcpu_svm *svm = to_svm(vcpu);
4285
4286         if (svm_nested_virtualize_tpr(vcpu) ||
4287             kvm_vcpu_apicv_active(vcpu))
4288                 return;
4289
4290         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4291
4292         if (irr == -1)
4293                 return;
4294
4295         if (tpr >= irr)
4296                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4297 }
4298
4299 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4300 {
4301         return;
4302 }
4303
4304 static bool svm_get_enable_apicv(void)
4305 {
4306         return avic;
4307 }
4308
4309 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4310 {
4311 }
4312
4313 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4314 {
4315 }
4316
4317 /* Note: Currently only used by Hyper-V. */
4318 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4319 {
4320         struct vcpu_svm *svm = to_svm(vcpu);
4321         struct vmcb *vmcb = svm->vmcb;
4322
4323         if (!avic)
4324                 return;
4325
4326         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4327         mark_dirty(vmcb, VMCB_INTR);
4328 }
4329
4330 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4331 {
4332         return;
4333 }
4334
4335 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4336 {
4337         kvm_lapic_set_irr(vec, vcpu->arch.apic);
4338         smp_mb__after_atomic();
4339
4340         if (avic_vcpu_is_running(vcpu))
4341                 wrmsrl(SVM_AVIC_DOORBELL,
4342                        kvm_cpu_get_apicid(vcpu->cpu));
4343         else
4344                 kvm_vcpu_wake_up(vcpu);
4345 }
4346
4347 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4348 {
4349         unsigned long flags;
4350         struct amd_svm_iommu_ir *cur;
4351
4352         spin_lock_irqsave(&svm->ir_list_lock, flags);
4353         list_for_each_entry(cur, &svm->ir_list, node) {
4354                 if (cur->data != pi->ir_data)
4355                         continue;
4356                 list_del(&cur->node);
4357                 kfree(cur);
4358                 break;
4359         }
4360         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4361 }
4362
4363 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4364 {
4365         int ret = 0;
4366         unsigned long flags;
4367         struct amd_svm_iommu_ir *ir;
4368
4369         /**
4370          * In some cases, the existing irte is updaed and re-set,
4371          * so we need to check here if it's already been * added
4372          * to the ir_list.
4373          */
4374         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4375                 struct kvm *kvm = svm->vcpu.kvm;
4376                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4377                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4378                 struct vcpu_svm *prev_svm;
4379
4380                 if (!prev_vcpu) {
4381                         ret = -EINVAL;
4382                         goto out;
4383                 }
4384
4385                 prev_svm = to_svm(prev_vcpu);
4386                 svm_ir_list_del(prev_svm, pi);
4387         }
4388
4389         /**
4390          * Allocating new amd_iommu_pi_data, which will get
4391          * add to the per-vcpu ir_list.
4392          */
4393         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4394         if (!ir) {
4395                 ret = -ENOMEM;
4396                 goto out;
4397         }
4398         ir->data = pi->ir_data;
4399
4400         spin_lock_irqsave(&svm->ir_list_lock, flags);
4401         list_add(&ir->node, &svm->ir_list);
4402         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4403 out:
4404         return ret;
4405 }
4406
4407 /**
4408  * Note:
4409  * The HW cannot support posting multicast/broadcast
4410  * interrupts to a vCPU. So, we still use legacy interrupt
4411  * remapping for these kind of interrupts.
4412  *
4413  * For lowest-priority interrupts, we only support
4414  * those with single CPU as the destination, e.g. user
4415  * configures the interrupts via /proc/irq or uses
4416  * irqbalance to make the interrupts single-CPU.
4417  */
4418 static int
4419 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4420                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4421 {
4422         struct kvm_lapic_irq irq;
4423         struct kvm_vcpu *vcpu = NULL;
4424
4425         kvm_set_msi_irq(kvm, e, &irq);
4426
4427         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4428                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4429                          __func__, irq.vector);
4430                 return -1;
4431         }
4432
4433         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4434                  irq.vector);
4435         *svm = to_svm(vcpu);
4436         vcpu_info->pi_desc_addr = page_to_phys((*svm)->avic_backing_page);
4437         vcpu_info->vector = irq.vector;
4438
4439         return 0;
4440 }
4441
4442 /*
4443  * svm_update_pi_irte - set IRTE for Posted-Interrupts
4444  *
4445  * @kvm: kvm
4446  * @host_irq: host irq of the interrupt
4447  * @guest_irq: gsi of the interrupt
4448  * @set: set or unset PI
4449  * returns 0 on success, < 0 on failure
4450  */
4451 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4452                               uint32_t guest_irq, bool set)
4453 {
4454         struct kvm_kernel_irq_routing_entry *e;
4455         struct kvm_irq_routing_table *irq_rt;
4456         int idx, ret = -EINVAL;
4457
4458         if (!kvm_arch_has_assigned_device(kvm) ||
4459             !irq_remapping_cap(IRQ_POSTING_CAP))
4460                 return 0;
4461
4462         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4463                  __func__, host_irq, guest_irq, set);
4464
4465         idx = srcu_read_lock(&kvm->irq_srcu);
4466         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4467         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4468
4469         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4470                 struct vcpu_data vcpu_info;
4471                 struct vcpu_svm *svm = NULL;
4472
4473                 if (e->type != KVM_IRQ_ROUTING_MSI)
4474                         continue;
4475
4476                 /**
4477                  * Here, we setup with legacy mode in the following cases:
4478                  * 1. When cannot target interrupt to a specific vcpu.
4479                  * 2. Unsetting posted interrupt.
4480                  * 3. APIC virtialization is disabled for the vcpu.
4481                  */
4482                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4483                     kvm_vcpu_apicv_active(&svm->vcpu)) {
4484                         struct amd_iommu_pi_data pi;
4485
4486                         /* Try to enable guest_mode in IRTE */
4487                         pi.base = page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK;
4488                         pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4489                                                      svm->vcpu.vcpu_id);
4490                         pi.is_guest_mode = true;
4491                         pi.vcpu_data = &vcpu_info;
4492                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4493
4494                         /**
4495                          * Here, we successfully setting up vcpu affinity in
4496                          * IOMMU guest mode. Now, we need to store the posted
4497                          * interrupt information in a per-vcpu ir_list so that
4498                          * we can reference to them directly when we update vcpu
4499                          * scheduling information in IOMMU irte.
4500                          */
4501                         if (!ret && pi.is_guest_mode)
4502                                 svm_ir_list_add(svm, &pi);
4503                 } else {
4504                         /* Use legacy mode in IRTE */
4505                         struct amd_iommu_pi_data pi;
4506
4507                         /**
4508                          * Here, pi is used to:
4509                          * - Tell IOMMU to use legacy mode for this interrupt.
4510                          * - Retrieve ga_tag of prior interrupt remapping data.
4511                          */
4512                         pi.is_guest_mode = false;
4513                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4514
4515                         /**
4516                          * Check if the posted interrupt was previously
4517                          * setup with the guest_mode by checking if the ga_tag
4518                          * was cached. If so, we need to clean up the per-vcpu
4519                          * ir_list.
4520                          */
4521                         if (!ret && pi.prev_ga_tag) {
4522                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4523                                 struct kvm_vcpu *vcpu;
4524
4525                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
4526                                 if (vcpu)
4527                                         svm_ir_list_del(to_svm(vcpu), &pi);
4528                         }
4529                 }
4530
4531                 if (!ret && svm) {
4532                         trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4533                                                  host_irq, e->gsi,
4534                                                  vcpu_info.vector,
4535                                                  vcpu_info.pi_desc_addr, set);
4536                 }
4537
4538                 if (ret < 0) {
4539                         pr_err("%s: failed to update PI IRTE\n", __func__);
4540                         goto out;
4541                 }
4542         }
4543
4544         ret = 0;
4545 out:
4546         srcu_read_unlock(&kvm->irq_srcu, idx);
4547         return ret;
4548 }
4549
4550 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4551 {
4552         struct vcpu_svm *svm = to_svm(vcpu);
4553         struct vmcb *vmcb = svm->vmcb;
4554         int ret;
4555         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4556               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4557         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4558
4559         return ret;
4560 }
4561
4562 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4563 {
4564         struct vcpu_svm *svm = to_svm(vcpu);
4565
4566         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4567 }
4568
4569 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4570 {
4571         struct vcpu_svm *svm = to_svm(vcpu);
4572
4573         if (masked) {
4574                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4575                 set_intercept(svm, INTERCEPT_IRET);
4576         } else {
4577                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4578                 clr_intercept(svm, INTERCEPT_IRET);
4579         }
4580 }
4581
4582 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4583 {
4584         struct vcpu_svm *svm = to_svm(vcpu);
4585         struct vmcb *vmcb = svm->vmcb;
4586         int ret;
4587
4588         if (!gif_set(svm) ||
4589              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4590                 return 0;
4591
4592         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4593
4594         if (is_guest_mode(vcpu))
4595                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4596
4597         return ret;
4598 }
4599
4600 static void enable_irq_window(struct kvm_vcpu *vcpu)
4601 {
4602         struct vcpu_svm *svm = to_svm(vcpu);
4603
4604         if (kvm_vcpu_apicv_active(vcpu))
4605                 return;
4606
4607         /*
4608          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4609          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
4610          * get that intercept, this function will be called again though and
4611          * we'll get the vintr intercept.
4612          */
4613         if (gif_set(svm) && nested_svm_intr(svm)) {
4614                 svm_set_vintr(svm);
4615                 svm_inject_irq(svm, 0x0);
4616         }
4617 }
4618
4619 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4620 {
4621         struct vcpu_svm *svm = to_svm(vcpu);
4622
4623         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4624             == HF_NMI_MASK)
4625                 return; /* IRET will cause a vm exit */
4626
4627         /*
4628          * Something prevents NMI from been injected. Single step over possible
4629          * problem (IRET or exception injection or interrupt shadow)
4630          */
4631         svm->nmi_singlestep = true;
4632         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4633 }
4634
4635 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4636 {
4637         return 0;
4638 }
4639
4640 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4641 {
4642         struct vcpu_svm *svm = to_svm(vcpu);
4643
4644         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4645                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4646         else
4647                 svm->asid_generation--;
4648 }
4649
4650 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4651 {
4652 }
4653
4654 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4655 {
4656         struct vcpu_svm *svm = to_svm(vcpu);
4657
4658         if (svm_nested_virtualize_tpr(vcpu))
4659                 return;
4660
4661         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4662                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4663                 kvm_set_cr8(vcpu, cr8);
4664         }
4665 }
4666
4667 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4668 {
4669         struct vcpu_svm *svm = to_svm(vcpu);
4670         u64 cr8;
4671
4672         if (svm_nested_virtualize_tpr(vcpu) ||
4673             kvm_vcpu_apicv_active(vcpu))
4674                 return;
4675
4676         cr8 = kvm_get_cr8(vcpu);
4677         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4678         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4679 }
4680
4681 static void svm_complete_interrupts(struct vcpu_svm *svm)
4682 {
4683         u8 vector;
4684         int type;
4685         u32 exitintinfo = svm->vmcb->control.exit_int_info;
4686         unsigned int3_injected = svm->int3_injected;
4687
4688         svm->int3_injected = 0;
4689
4690         /*
4691          * If we've made progress since setting HF_IRET_MASK, we've
4692          * executed an IRET and can allow NMI injection.
4693          */
4694         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4695             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4696                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4697                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4698         }
4699
4700         svm->vcpu.arch.nmi_injected = false;
4701         kvm_clear_exception_queue(&svm->vcpu);
4702         kvm_clear_interrupt_queue(&svm->vcpu);
4703
4704         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4705                 return;
4706
4707         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4708
4709         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4710         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4711
4712         switch (type) {
4713         case SVM_EXITINTINFO_TYPE_NMI:
4714                 svm->vcpu.arch.nmi_injected = true;
4715                 break;
4716         case SVM_EXITINTINFO_TYPE_EXEPT:
4717                 /*
4718                  * In case of software exceptions, do not reinject the vector,
4719                  * but re-execute the instruction instead. Rewind RIP first
4720                  * if we emulated INT3 before.
4721                  */
4722                 if (kvm_exception_is_soft(vector)) {
4723                         if (vector == BP_VECTOR && int3_injected &&
4724                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4725                                 kvm_rip_write(&svm->vcpu,
4726                                               kvm_rip_read(&svm->vcpu) -
4727                                               int3_injected);
4728                         break;
4729                 }
4730                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4731                         u32 err = svm->vmcb->control.exit_int_info_err;
4732                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
4733
4734                 } else
4735                         kvm_requeue_exception(&svm->vcpu, vector);
4736                 break;
4737         case SVM_EXITINTINFO_TYPE_INTR:
4738                 kvm_queue_interrupt(&svm->vcpu, vector, false);
4739                 break;
4740         default:
4741                 break;
4742         }
4743 }
4744
4745 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4746 {
4747         struct vcpu_svm *svm = to_svm(vcpu);
4748         struct vmcb_control_area *control = &svm->vmcb->control;
4749
4750         control->exit_int_info = control->event_inj;
4751         control->exit_int_info_err = control->event_inj_err;
4752         control->event_inj = 0;
4753         svm_complete_interrupts(svm);
4754 }
4755
4756 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4757 {
4758         struct vcpu_svm *svm = to_svm(vcpu);
4759
4760         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4761         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4762         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4763
4764         /*
4765          * A vmexit emulation is required before the vcpu can be executed
4766          * again.
4767          */
4768         if (unlikely(svm->nested.exit_required))
4769                 return;
4770
4771         pre_svm_run(svm);
4772
4773         sync_lapic_to_cr8(vcpu);
4774
4775         svm->vmcb->save.cr2 = vcpu->arch.cr2;
4776
4777         clgi();
4778
4779         local_irq_enable();
4780
4781         asm volatile (
4782                 "push %%" _ASM_BP "; \n\t"
4783                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4784                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4785                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4786                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4787                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4788                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4789 #ifdef CONFIG_X86_64
4790                 "mov %c[r8](%[svm]),  %%r8  \n\t"
4791                 "mov %c[r9](%[svm]),  %%r9  \n\t"
4792                 "mov %c[r10](%[svm]), %%r10 \n\t"
4793                 "mov %c[r11](%[svm]), %%r11 \n\t"
4794                 "mov %c[r12](%[svm]), %%r12 \n\t"
4795                 "mov %c[r13](%[svm]), %%r13 \n\t"
4796                 "mov %c[r14](%[svm]), %%r14 \n\t"
4797                 "mov %c[r15](%[svm]), %%r15 \n\t"
4798 #endif
4799
4800                 /* Enter guest mode */
4801                 "push %%" _ASM_AX " \n\t"
4802                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4803                 __ex(SVM_VMLOAD) "\n\t"
4804                 __ex(SVM_VMRUN) "\n\t"
4805                 __ex(SVM_VMSAVE) "\n\t"
4806                 "pop %%" _ASM_AX " \n\t"
4807
4808                 /* Save guest registers, load host registers */
4809                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4810                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4811                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4812                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4813                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4814                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4815 #ifdef CONFIG_X86_64
4816                 "mov %%r8,  %c[r8](%[svm]) \n\t"
4817                 "mov %%r9,  %c[r9](%[svm]) \n\t"
4818                 "mov %%r10, %c[r10](%[svm]) \n\t"
4819                 "mov %%r11, %c[r11](%[svm]) \n\t"
4820                 "mov %%r12, %c[r12](%[svm]) \n\t"
4821                 "mov %%r13, %c[r13](%[svm]) \n\t"
4822                 "mov %%r14, %c[r14](%[svm]) \n\t"
4823                 "mov %%r15, %c[r15](%[svm]) \n\t"
4824 #endif
4825                 "pop %%" _ASM_BP
4826                 :
4827                 : [svm]"a"(svm),
4828                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4829                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4830                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4831                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4832                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4833                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4834                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4835 #ifdef CONFIG_X86_64
4836                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4837                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4838                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4839                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4840                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4841                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4842                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4843                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4844 #endif
4845                 : "cc", "memory"
4846 #ifdef CONFIG_X86_64
4847                 , "rbx", "rcx", "rdx", "rsi", "rdi"
4848                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4849 #else
4850                 , "ebx", "ecx", "edx", "esi", "edi"
4851 #endif
4852                 );
4853
4854 #ifdef CONFIG_X86_64
4855         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4856 #else
4857         loadsegment(fs, svm->host.fs);
4858 #ifndef CONFIG_X86_32_LAZY_GS
4859         loadsegment(gs, svm->host.gs);
4860 #endif
4861 #endif
4862
4863         reload_tss(vcpu);
4864
4865         local_irq_disable();
4866
4867         vcpu->arch.cr2 = svm->vmcb->save.cr2;
4868         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4869         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4870         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4871
4872         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4873                 kvm_before_handle_nmi(&svm->vcpu);
4874
4875         stgi();
4876
4877         /* Any pending NMI will happen here */
4878
4879         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4880                 kvm_after_handle_nmi(&svm->vcpu);
4881
4882         sync_cr8_to_lapic(vcpu);
4883
4884         svm->next_rip = 0;
4885
4886         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4887
4888         /* if exit due to PF check for async PF */
4889         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4890                 svm->apf_reason = kvm_read_and_reset_pf_reason();
4891
4892         if (npt_enabled) {
4893                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4894                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4895         }
4896
4897         /*
4898          * We need to handle MC intercepts here before the vcpu has a chance to
4899          * change the physical cpu
4900          */
4901         if (unlikely(svm->vmcb->control.exit_code ==
4902                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
4903                 svm_handle_mce(svm);
4904
4905         mark_all_clean(svm->vmcb);
4906 }
4907
4908 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4909 {
4910         struct vcpu_svm *svm = to_svm(vcpu);
4911
4912         svm->vmcb->save.cr3 = root;
4913         mark_dirty(svm->vmcb, VMCB_CR);
4914         svm_flush_tlb(vcpu);
4915 }
4916
4917 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4918 {
4919         struct vcpu_svm *svm = to_svm(vcpu);
4920
4921         svm->vmcb->control.nested_cr3 = root;
4922         mark_dirty(svm->vmcb, VMCB_NPT);
4923
4924         /* Also sync guest cr3 here in case we live migrate */
4925         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4926         mark_dirty(svm->vmcb, VMCB_CR);
4927
4928         svm_flush_tlb(vcpu);
4929 }
4930
4931 static int is_disabled(void)
4932 {
4933         u64 vm_cr;
4934
4935         rdmsrl(MSR_VM_CR, vm_cr);
4936         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4937                 return 1;
4938
4939         return 0;
4940 }
4941
4942 static void
4943 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4944 {
4945         /*
4946          * Patch in the VMMCALL instruction:
4947          */
4948         hypercall[0] = 0x0f;
4949         hypercall[1] = 0x01;
4950         hypercall[2] = 0xd9;
4951 }
4952
4953 static void svm_check_processor_compat(void *rtn)
4954 {
4955         *(int *)rtn = 0;
4956 }
4957
4958 static bool svm_cpu_has_accelerated_tpr(void)
4959 {
4960         return false;
4961 }
4962
4963 static bool svm_has_high_real_mode_segbase(void)
4964 {
4965         return true;
4966 }
4967
4968 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4969 {
4970         return 0;
4971 }
4972
4973 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4974 {
4975         struct vcpu_svm *svm = to_svm(vcpu);
4976         struct kvm_cpuid_entry2 *entry;
4977
4978         /* Update nrips enabled cache */
4979         svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
4980
4981         if (!kvm_vcpu_apicv_active(vcpu))
4982                 return;
4983
4984         entry = kvm_find_cpuid_entry(vcpu, 1, 0);
4985         if (entry)
4986                 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
4987 }
4988
4989 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4990 {
4991         switch (func) {
4992         case 0x1:
4993                 if (avic)
4994                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
4995                 break;
4996         case 0x80000001:
4997                 if (nested)
4998                         entry->ecx |= (1 << 2); /* Set SVM bit */
4999                 break;
5000         case 0x8000000A:
5001                 entry->eax = 1; /* SVM revision 1 */
5002                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5003                                    ASID emulation to nested SVM */
5004                 entry->ecx = 0; /* Reserved */
5005                 entry->edx = 0; /* Per default do not support any
5006                                    additional features */
5007
5008                 /* Support next_rip if host supports it */
5009                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5010                         entry->edx |= SVM_FEATURE_NRIP;
5011
5012                 /* Support NPT for the guest if enabled */
5013                 if (npt_enabled)
5014                         entry->edx |= SVM_FEATURE_NPT;
5015
5016                 break;
5017         }
5018 }
5019
5020 static int svm_get_lpage_level(void)
5021 {
5022         return PT_PDPE_LEVEL;
5023 }
5024
5025 static bool svm_rdtscp_supported(void)
5026 {
5027         return boot_cpu_has(X86_FEATURE_RDTSCP);
5028 }
5029
5030 static bool svm_invpcid_supported(void)
5031 {
5032         return false;
5033 }
5034
5035 static bool svm_mpx_supported(void)
5036 {
5037         return false;
5038 }
5039
5040 static bool svm_xsaves_supported(void)
5041 {
5042         return false;
5043 }
5044
5045 static bool svm_has_wbinvd_exit(void)
5046 {
5047         return true;
5048 }
5049
5050 #define PRE_EX(exit)  { .exit_code = (exit), \
5051                         .stage = X86_ICPT_PRE_EXCEPT, }
5052 #define POST_EX(exit) { .exit_code = (exit), \
5053                         .stage = X86_ICPT_POST_EXCEPT, }
5054 #define POST_MEM(exit) { .exit_code = (exit), \
5055                         .stage = X86_ICPT_POST_MEMACCESS, }
5056
5057 static const struct __x86_intercept {
5058         u32 exit_code;
5059         enum x86_intercept_stage stage;
5060 } x86_intercept_map[] = {
5061         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5062         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5063         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5064         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5065         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5066         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5067         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5068         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5069         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5070         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5071         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5072         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5073         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5074         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5075         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5076         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5077         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5078         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5079         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5080         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5081         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5082         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5083         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5084         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5085         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5086         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5087         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
5088         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
5089         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
5090         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
5091         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
5092         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
5093         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
5094         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
5095         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
5096         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
5097         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
5098         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
5099         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
5100         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
5101         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
5102         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
5103         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
5104         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
5105         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
5106         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
5107 };
5108
5109 #undef PRE_EX
5110 #undef POST_EX
5111 #undef POST_MEM
5112
5113 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5114                                struct x86_instruction_info *info,
5115                                enum x86_intercept_stage stage)
5116 {
5117         struct vcpu_svm *svm = to_svm(vcpu);
5118         int vmexit, ret = X86EMUL_CONTINUE;
5119         struct __x86_intercept icpt_info;
5120         struct vmcb *vmcb = svm->vmcb;
5121
5122         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5123                 goto out;
5124
5125         icpt_info = x86_intercept_map[info->intercept];
5126
5127         if (stage != icpt_info.stage)
5128                 goto out;
5129
5130         switch (icpt_info.exit_code) {
5131         case SVM_EXIT_READ_CR0:
5132                 if (info->intercept == x86_intercept_cr_read)
5133                         icpt_info.exit_code += info->modrm_reg;
5134                 break;
5135         case SVM_EXIT_WRITE_CR0: {
5136                 unsigned long cr0, val;
5137                 u64 intercept;
5138
5139                 if (info->intercept == x86_intercept_cr_write)
5140                         icpt_info.exit_code += info->modrm_reg;
5141
5142                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5143                     info->intercept == x86_intercept_clts)
5144                         break;
5145
5146                 intercept = svm->nested.intercept;
5147
5148                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5149                         break;
5150
5151                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5152                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
5153
5154                 if (info->intercept == x86_intercept_lmsw) {
5155                         cr0 &= 0xfUL;
5156                         val &= 0xfUL;
5157                         /* lmsw can't clear PE - catch this here */
5158                         if (cr0 & X86_CR0_PE)
5159                                 val |= X86_CR0_PE;
5160                 }
5161
5162                 if (cr0 ^ val)
5163                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5164
5165                 break;
5166         }
5167         case SVM_EXIT_READ_DR0:
5168         case SVM_EXIT_WRITE_DR0:
5169                 icpt_info.exit_code += info->modrm_reg;
5170                 break;
5171         case SVM_EXIT_MSR:
5172                 if (info->intercept == x86_intercept_wrmsr)
5173                         vmcb->control.exit_info_1 = 1;
5174                 else
5175                         vmcb->control.exit_info_1 = 0;
5176                 break;
5177         case SVM_EXIT_PAUSE:
5178                 /*
5179                  * We get this for NOP only, but pause
5180                  * is rep not, check this here
5181                  */
5182                 if (info->rep_prefix != REPE_PREFIX)
5183                         goto out;
5184         case SVM_EXIT_IOIO: {
5185                 u64 exit_info;
5186                 u32 bytes;
5187
5188                 if (info->intercept == x86_intercept_in ||
5189                     info->intercept == x86_intercept_ins) {
5190                         exit_info = ((info->src_val & 0xffff) << 16) |
5191                                 SVM_IOIO_TYPE_MASK;
5192                         bytes = info->dst_bytes;
5193                 } else {
5194                         exit_info = (info->dst_val & 0xffff) << 16;
5195                         bytes = info->src_bytes;
5196                 }
5197
5198                 if (info->intercept == x86_intercept_outs ||
5199                     info->intercept == x86_intercept_ins)
5200                         exit_info |= SVM_IOIO_STR_MASK;
5201
5202                 if (info->rep_prefix)
5203                         exit_info |= SVM_IOIO_REP_MASK;
5204
5205                 bytes = min(bytes, 4u);
5206
5207                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5208
5209                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5210
5211                 vmcb->control.exit_info_1 = exit_info;
5212                 vmcb->control.exit_info_2 = info->next_rip;
5213
5214                 break;
5215         }
5216         default:
5217                 break;
5218         }
5219
5220         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5221         if (static_cpu_has(X86_FEATURE_NRIPS))
5222                 vmcb->control.next_rip  = info->next_rip;
5223         vmcb->control.exit_code = icpt_info.exit_code;
5224         vmexit = nested_svm_exit_handled(svm);
5225
5226         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5227                                            : X86EMUL_CONTINUE;
5228
5229 out:
5230         return ret;
5231 }
5232
5233 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5234 {
5235         local_irq_enable();
5236         /*
5237          * We must have an instruction with interrupts enabled, so
5238          * the timer interrupt isn't delayed by the interrupt shadow.
5239          */
5240         asm("nop");
5241         local_irq_disable();
5242 }
5243
5244 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5245 {
5246 }
5247
5248 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5249 {
5250         if (avic_handle_apic_id_update(vcpu) != 0)
5251                 return;
5252         if (avic_handle_dfr_update(vcpu) != 0)
5253                 return;
5254         avic_handle_ldr_update(vcpu);
5255 }
5256
5257 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5258         .cpu_has_kvm_support = has_svm,
5259         .disabled_by_bios = is_disabled,
5260         .hardware_setup = svm_hardware_setup,
5261         .hardware_unsetup = svm_hardware_unsetup,
5262         .check_processor_compatibility = svm_check_processor_compat,
5263         .hardware_enable = svm_hardware_enable,
5264         .hardware_disable = svm_hardware_disable,
5265         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5266         .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5267
5268         .vcpu_create = svm_create_vcpu,
5269         .vcpu_free = svm_free_vcpu,
5270         .vcpu_reset = svm_vcpu_reset,
5271
5272         .vm_init = avic_vm_init,
5273         .vm_destroy = avic_vm_destroy,
5274
5275         .prepare_guest_switch = svm_prepare_guest_switch,
5276         .vcpu_load = svm_vcpu_load,
5277         .vcpu_put = svm_vcpu_put,
5278         .vcpu_blocking = svm_vcpu_blocking,
5279         .vcpu_unblocking = svm_vcpu_unblocking,
5280
5281         .update_bp_intercept = update_bp_intercept,
5282         .get_msr = svm_get_msr,
5283         .set_msr = svm_set_msr,
5284         .get_segment_base = svm_get_segment_base,
5285         .get_segment = svm_get_segment,
5286         .set_segment = svm_set_segment,
5287         .get_cpl = svm_get_cpl,
5288         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5289         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5290         .decache_cr3 = svm_decache_cr3,
5291         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5292         .set_cr0 = svm_set_cr0,
5293         .set_cr3 = svm_set_cr3,
5294         .set_cr4 = svm_set_cr4,
5295         .set_efer = svm_set_efer,
5296         .get_idt = svm_get_idt,
5297         .set_idt = svm_set_idt,
5298         .get_gdt = svm_get_gdt,
5299         .set_gdt = svm_set_gdt,
5300         .get_dr6 = svm_get_dr6,
5301         .set_dr6 = svm_set_dr6,
5302         .set_dr7 = svm_set_dr7,
5303         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5304         .cache_reg = svm_cache_reg,
5305         .get_rflags = svm_get_rflags,
5306         .set_rflags = svm_set_rflags,
5307
5308         .get_pkru = svm_get_pkru,
5309
5310         .tlb_flush = svm_flush_tlb,
5311
5312         .run = svm_vcpu_run,
5313         .handle_exit = handle_exit,
5314         .skip_emulated_instruction = skip_emulated_instruction,
5315         .set_interrupt_shadow = svm_set_interrupt_shadow,
5316         .get_interrupt_shadow = svm_get_interrupt_shadow,
5317         .patch_hypercall = svm_patch_hypercall,
5318         .set_irq = svm_set_irq,
5319         .set_nmi = svm_inject_nmi,
5320         .queue_exception = svm_queue_exception,
5321         .cancel_injection = svm_cancel_injection,
5322         .interrupt_allowed = svm_interrupt_allowed,
5323         .nmi_allowed = svm_nmi_allowed,
5324         .get_nmi_mask = svm_get_nmi_mask,
5325         .set_nmi_mask = svm_set_nmi_mask,
5326         .enable_nmi_window = enable_nmi_window,
5327         .enable_irq_window = enable_irq_window,
5328         .update_cr8_intercept = update_cr8_intercept,
5329         .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5330         .get_enable_apicv = svm_get_enable_apicv,
5331         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5332         .load_eoi_exitmap = svm_load_eoi_exitmap,
5333         .hwapic_irr_update = svm_hwapic_irr_update,
5334         .hwapic_isr_update = svm_hwapic_isr_update,
5335         .apicv_post_state_restore = avic_post_state_restore,
5336
5337         .set_tss_addr = svm_set_tss_addr,
5338         .get_tdp_level = get_npt_level,
5339         .get_mt_mask = svm_get_mt_mask,
5340
5341         .get_exit_info = svm_get_exit_info,
5342
5343         .get_lpage_level = svm_get_lpage_level,
5344
5345         .cpuid_update = svm_cpuid_update,
5346
5347         .rdtscp_supported = svm_rdtscp_supported,
5348         .invpcid_supported = svm_invpcid_supported,
5349         .mpx_supported = svm_mpx_supported,
5350         .xsaves_supported = svm_xsaves_supported,
5351
5352         .set_supported_cpuid = svm_set_supported_cpuid,
5353
5354         .has_wbinvd_exit = svm_has_wbinvd_exit,
5355
5356         .write_tsc_offset = svm_write_tsc_offset,
5357
5358         .set_tdp_cr3 = set_tdp_cr3,
5359
5360         .check_intercept = svm_check_intercept,
5361         .handle_external_intr = svm_handle_external_intr,
5362
5363         .sched_in = svm_sched_in,
5364
5365         .pmu_ops = &amd_pmu_ops,
5366         .deliver_posted_interrupt = svm_deliver_avic_intr,
5367         .update_pi_irte = svm_update_pi_irte,
5368 };
5369
5370 static int __init svm_init(void)
5371 {
5372         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5373                         __alignof__(struct vcpu_svm), THIS_MODULE);
5374 }
5375
5376 static void __exit svm_exit(void)
5377 {
5378         kvm_exit();
5379 }
5380
5381 module_init(svm_init)
5382 module_exit(svm_exit)