arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23 #include "cpuid.h"
  24
  25 #include <linux/module.h>
  26 #include <linux/mod_devicetable.h>
  27 #include <linux/kernel.h>
  28 #include <linux/vmalloc.h>
  29 #include <linux/highmem.h>
  30 #include <linux/sched.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33
  34 #include <asm/perf_event.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/desc.h>
  37 #include <asm/debugreg.h>
  38 #include <asm/kvm_para.h>
  39
  40 #include <asm/virtext.h>
  41 #include "trace.h"
  42
  43 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  44
  45 MODULE_AUTHOR("Qumranet");
  46 MODULE_LICENSE("GPL");
  47
  48 static const struct x86_cpu_id svm_cpu_id[] = {
  49         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  50         {}
  51 };
  52 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  53
  54 #define IOPM_ALLOC_ORDER 2
  55 #define MSRPM_ALLOC_ORDER 1
  56
  57 #define SEG_TYPE_LDT 2
  58 #define SEG_TYPE_BUSY_TSS16 3
  59
  60 #define SVM_FEATURE_NPT            (1 <<  0)
  61 #define SVM_FEATURE_LBRV           (1 <<  1)
  62 #define SVM_FEATURE_SVML           (1 <<  2)
  63 #define SVM_FEATURE_NRIP           (1 <<  3)
  64 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  65 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  66 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  67 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  68 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  69
  70 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  71 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  72 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  73
  74 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  75
  76 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  77 #define TSC_RATIO_MIN           0x0000000000000001ULL
  78 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  79
  80 static bool erratum_383_found __read_mostly;
  81
  82 static const u32 host_save_user_msrs[] = {
  83 #ifdef CONFIG_X86_64
  84         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  85         MSR_FS_BASE,
  86 #endif
  87         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  88 };
  89
  90 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  91
  92 struct kvm_vcpu;
  93
  94 struct nested_state {
  95         struct vmcb *hsave;
  96         u64 hsave_msr;
  97         u64 vm_cr_msr;
  98         u64 vmcb;
  99
 100         /* These are the merged vectors */
 101         u32 *msrpm;
 102
 103         /* gpa pointers to the real vectors */
 104         u64 vmcb_msrpm;
 105         u64 vmcb_iopm;
 106
 107         /* A VMEXIT is required but not yet emulated */
 108         bool exit_required;
 109
 110         /* cache for intercepts of the guest */
 111         u32 intercept_cr;
 112         u32 intercept_dr;
 113         u32 intercept_exceptions;
 114         u64 intercept;
 115
 116         /* Nested Paging related state */
 117         u64 nested_cr3;
 118 };
 119
 120 #define MSRPM_OFFSETS   16
 121 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 122
 123 /*
 124  * Set osvw_len to higher value when updated Revision Guides
 125  * are published and we know what the new status bits are
 126  */
 127 static uint64_t osvw_len = 4, osvw_status;
 128
 129 struct vcpu_svm {
 130         struct kvm_vcpu vcpu;
 131         struct vmcb *vmcb;
 132         unsigned long vmcb_pa;
 133         struct svm_cpu_data *svm_data;
 134         uint64_t asid_generation;
 135         uint64_t sysenter_esp;
 136         uint64_t sysenter_eip;
 137
 138         u64 next_rip;
 139
 140         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 141         struct {
 142                 u16 fs;
 143                 u16 gs;
 144                 u16 ldt;
 145                 u64 gs_base;
 146         } host;
 147
 148         u32 *msrpm;
 149
 150         ulong nmi_iret_rip;
 151
 152         struct nested_state nested;
 153
 154         bool nmi_singlestep;
 155
 156         unsigned int3_injected;
 157         unsigned long int3_rip;
 158         u32 apf_reason;
 159
 160         u64  tsc_ratio;
 161 };
 162
 163 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 164 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 165
 166 #define MSR_INVALID                     0xffffffffU
 167
 168 static const struct svm_direct_access_msrs {
 169         u32 index;   /* Index of the MSR */
 170         bool always; /* True if intercept is always on */
 171 } direct_access_msrs[] = {
 172         { .index = MSR_STAR,                            .always = true  },
 173         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 174 #ifdef CONFIG_X86_64
 175         { .index = MSR_GS_BASE,                         .always = true  },
 176         { .index = MSR_FS_BASE,                         .always = true  },
 177         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 178         { .index = MSR_LSTAR,                           .always = true  },
 179         { .index = MSR_CSTAR,                           .always = true  },
 180         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 181 #endif
 182         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 183         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 184         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 185         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 186         { .index = MSR_INVALID,                         .always = false },
 187 };
 188
 189 /* enable NPT for AMD64 and X86 with PAE */
 190 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 191 static bool npt_enabled = true;
 192 #else
 193 static bool npt_enabled;
 194 #endif
 195
 196 /* allow nested paging (virtualized MMU) for all guests */
 197 static int npt = true;
 198 module_param(npt, int, S_IRUGO);
 199
 200 /* allow nested virtualization in KVM/SVM */
 201 static int nested = true;
 202 module_param(nested, int, S_IRUGO);
 203
 204 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 205 static void svm_complete_interrupts(struct vcpu_svm *svm);
 206
 207 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 208 static int nested_svm_intercept(struct vcpu_svm *svm);
 209 static int nested_svm_vmexit(struct vcpu_svm *svm);
 210 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 211                                       bool has_error_code, u32 error_code);
 212 static u64 __scale_tsc(u64 ratio, u64 tsc);
 213
 214 enum {
 215         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 216                             pause filter count */
 217         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 218         VMCB_ASID,       /* ASID */
 219         VMCB_INTR,       /* int_ctl, int_vector */
 220         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 221         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 222         VMCB_DR,         /* DR6, DR7 */
 223         VMCB_DT,         /* GDT, IDT */
 224         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 225         VMCB_CR2,        /* CR2 only */
 226         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 227         VMCB_DIRTY_MAX,
 228 };
 229
 230 /* TPR and CR2 are always written before VMRUN */
 231 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 232
 233 static inline void mark_all_dirty(struct vmcb *vmcb)
 234 {
 235         vmcb->control.clean = 0;
 236 }
 237
 238 static inline void mark_all_clean(struct vmcb *vmcb)
 239 {
 240         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 241                                & ~VMCB_ALWAYS_DIRTY_MASK;
 242 }
 243
 244 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 245 {
 246         vmcb->control.clean &= ~(1 << bit);
 247 }
 248
 249 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 250 {
 251         return container_of(vcpu, struct vcpu_svm, vcpu);
 252 }
 253
 254 static void recalc_intercepts(struct vcpu_svm *svm)
 255 {
 256         struct vmcb_control_area *c, *h;
 257         struct nested_state *g;
 258
 259         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 260
 261         if (!is_guest_mode(&svm->vcpu))
 262                 return;
 263
 264         c = &svm->vmcb->control;
 265         h = &svm->nested.hsave->control;
 266         g = &svm->nested;
 267
 268         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 269         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 270         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 271         c->intercept = h->intercept | g->intercept;
 272 }
 273
 274 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 275 {
 276         if (is_guest_mode(&svm->vcpu))
 277                 return svm->nested.hsave;
 278         else
 279                 return svm->vmcb;
 280 }
 281
 282 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 283 {
 284         struct vmcb *vmcb = get_host_vmcb(svm);
 285
 286         vmcb->control.intercept_cr |= (1U << bit);
 287
 288         recalc_intercepts(svm);
 289 }
 290
 291 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 292 {
 293         struct vmcb *vmcb = get_host_vmcb(svm);
 294
 295         vmcb->control.intercept_cr &= ~(1U << bit);
 296
 297         recalc_intercepts(svm);
 298 }
 299
 300 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 301 {
 302         struct vmcb *vmcb = get_host_vmcb(svm);
 303
 304         return vmcb->control.intercept_cr & (1U << bit);
 305 }
 306
 307 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 308 {
 309         struct vmcb *vmcb = get_host_vmcb(svm);
 310
 311         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 312                 | (1 << INTERCEPT_DR1_READ)
 313                 | (1 << INTERCEPT_DR2_READ)
 314                 | (1 << INTERCEPT_DR3_READ)
 315                 | (1 << INTERCEPT_DR4_READ)
 316                 | (1 << INTERCEPT_DR5_READ)
 317                 | (1 << INTERCEPT_DR6_READ)
 318                 | (1 << INTERCEPT_DR7_READ)
 319                 | (1 << INTERCEPT_DR0_WRITE)
 320                 | (1 << INTERCEPT_DR1_WRITE)
 321                 | (1 << INTERCEPT_DR2_WRITE)
 322                 | (1 << INTERCEPT_DR3_WRITE)
 323                 | (1 << INTERCEPT_DR4_WRITE)
 324                 | (1 << INTERCEPT_DR5_WRITE)
 325                 | (1 << INTERCEPT_DR6_WRITE)
 326                 | (1 << INTERCEPT_DR7_WRITE);
 327
 328         recalc_intercepts(svm);
 329 }
 330
 331 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 332 {
 333         struct vmcb *vmcb = get_host_vmcb(svm);
 334
 335         vmcb->control.intercept_dr = 0;
 336
 337         recalc_intercepts(svm);
 338 }
 339
 340 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 341 {
 342         struct vmcb *vmcb = get_host_vmcb(svm);
 343
 344         vmcb->control.intercept_exceptions |= (1U << bit);
 345
 346         recalc_intercepts(svm);
 347 }
 348
 349 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 350 {
 351         struct vmcb *vmcb = get_host_vmcb(svm);
 352
 353         vmcb->control.intercept_exceptions &= ~(1U << bit);
 354
 355         recalc_intercepts(svm);
 356 }
 357
 358 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 359 {
 360         struct vmcb *vmcb = get_host_vmcb(svm);
 361
 362         vmcb->control.intercept |= (1ULL << bit);
 363
 364         recalc_intercepts(svm);
 365 }
 366
 367 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 368 {
 369         struct vmcb *vmcb = get_host_vmcb(svm);
 370
 371         vmcb->control.intercept &= ~(1ULL << bit);
 372
 373         recalc_intercepts(svm);
 374 }
 375
 376 static inline void enable_gif(struct vcpu_svm *svm)
 377 {
 378         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 379 }
 380
 381 static inline void disable_gif(struct vcpu_svm *svm)
 382 {
 383         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 384 }
 385
 386 static inline bool gif_set(struct vcpu_svm *svm)
 387 {
 388         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 389 }
 390
 391 static unsigned long iopm_base;
 392
 393 struct kvm_ldttss_desc {
 394         u16 limit0;
 395         u16 base0;
 396         unsigned base1:8, type:5, dpl:2, p:1;
 397         unsigned limit1:4, zero0:3, g:1, base2:8;
 398         u32 base3;
 399         u32 zero1;
 400 } __attribute__((packed));
 401
 402 struct svm_cpu_data {
 403         int cpu;
 404
 405         u64 asid_generation;
 406         u32 max_asid;
 407         u32 next_asid;
 408         struct kvm_ldttss_desc *tss_desc;
 409
 410         struct page *save_area;
 411 };
 412
 413 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 414
 415 struct svm_init_data {
 416         int cpu;
 417         int r;
 418 };
 419
 420 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 421
 422 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 423 #define MSRS_RANGE_SIZE 2048
 424 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 425
 426 static u32 svm_msrpm_offset(u32 msr)
 427 {
 428         u32 offset;
 429         int i;
 430
 431         for (i = 0; i < NUM_MSR_MAPS; i++) {
 432                 if (msr < msrpm_ranges[i] ||
 433                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 434                         continue;
 435
 436                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 437                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 438
 439                 /* Now we have the u8 offset - but need the u32 offset */
 440                 return offset / 4;
 441         }
 442
 443         /* MSR not in any range */
 444         return MSR_INVALID;
 445 }
 446
 447 #define MAX_INST_SIZE 15
 448
 449 static inline void clgi(void)
 450 {
 451         asm volatile (__ex(SVM_CLGI));
 452 }
 453
 454 static inline void stgi(void)
 455 {
 456         asm volatile (__ex(SVM_STGI));
 457 }
 458
 459 static inline void invlpga(unsigned long addr, u32 asid)
 460 {
 461         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 462 }
 463
 464 static int get_npt_level(void)
 465 {
 466 #ifdef CONFIG_X86_64
 467         return PT64_ROOT_LEVEL;
 468 #else
 469         return PT32E_ROOT_LEVEL;
 470 #endif
 471 }
 472
 473 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 474 {
 475         vcpu->arch.efer = efer;
 476         if (!npt_enabled && !(efer & EFER_LMA))
 477                 efer &= ~EFER_LME;
 478
 479         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 480         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 481 }
 482
 483 static int is_external_interrupt(u32 info)
 484 {
 485         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 486         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 487 }
 488
 489 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 490 {
 491         struct vcpu_svm *svm = to_svm(vcpu);
 492         u32 ret = 0;
 493
 494         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 495                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 496         return ret;
 497 }
 498
 499 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 500 {
 501         struct vcpu_svm *svm = to_svm(vcpu);
 502
 503         if (mask == 0)
 504                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 505         else
 506                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 507
 508 }
 509
 510 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 511 {
 512         struct vcpu_svm *svm = to_svm(vcpu);
 513
 514         if (svm->vmcb->control.next_rip != 0)
 515                 svm->next_rip = svm->vmcb->control.next_rip;
 516
 517         if (!svm->next_rip) {
 518                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 519                                 EMULATE_DONE)
 520                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 521                 return;
 522         }
 523         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 524                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 525                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 526
 527         kvm_rip_write(vcpu, svm->next_rip);
 528         svm_set_interrupt_shadow(vcpu, 0);
 529 }
 530
 531 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 532                                 bool has_error_code, u32 error_code,
 533                                 bool reinject)
 534 {
 535         struct vcpu_svm *svm = to_svm(vcpu);
 536
 537         /*
 538          * If we are within a nested VM we'd better #VMEXIT and let the guest
 539          * handle the exception
 540          */
 541         if (!reinject &&
 542             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 543                 return;
 544
 545         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 546                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 547
 548                 /*
 549                  * For guest debugging where we have to reinject #BP if some
 550                  * INT3 is guest-owned:
 551                  * Emulate nRIP by moving RIP forward. Will fail if injection
 552                  * raises a fault that is not intercepted. Still better than
 553                  * failing in all cases.
 554                  */
 555                 skip_emulated_instruction(&svm->vcpu);
 556                 rip = kvm_rip_read(&svm->vcpu);
 557                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 558                 svm->int3_injected = rip - old_rip;
 559         }
 560
 561         svm->vmcb->control.event_inj = nr
 562                 | SVM_EVTINJ_VALID
 563                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 564                 | SVM_EVTINJ_TYPE_EXEPT;
 565         svm->vmcb->control.event_inj_err = error_code;
 566 }
 567
 568 static void svm_init_erratum_383(void)
 569 {
 570         u32 low, high;
 571         int err;
 572         u64 val;
 573
 574         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 575                 return;
 576
 577         /* Use _safe variants to not break nested virtualization */
 578         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 579         if (err)
 580                 return;
 581
 582         val |= (1ULL << 47);
 583
 584         low  = lower_32_bits(val);
 585         high = upper_32_bits(val);
 586
 587         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 588
 589         erratum_383_found = true;
 590 }
 591
 592 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 593 {
 594         /*
 595          * Guests should see errata 400 and 415 as fixed (assuming that
 596          * HLT and IO instructions are intercepted).
 597          */
 598         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 599         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 600
 601         /*
 602          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 603          * all osvw.status bits inside that length, including bit 0 (which is
 604          * reserved for erratum 298), are valid. However, if host processor's
 605          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 606          * be conservative here and therefore we tell the guest that erratum 298
 607          * is present (because we really don't know).
 608          */
 609         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 610                 vcpu->arch.osvw.status |= 1;
 611 }
 612
 613 static int has_svm(void)
 614 {
 615         const char *msg;
 616
 617         if (!cpu_has_svm(&msg)) {
 618                 printk(KERN_INFO "has_svm: %s\n", msg);
 619                 return 0;
 620         }
 621
 622         return 1;
 623 }
 624
 625 static void svm_hardware_disable(void)
 626 {
 627         /* Make sure we clean up behind us */
 628         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 629                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 630
 631         cpu_svm_disable();
 632
 633         amd_pmu_disable_virt();
 634 }
 635
 636 static int svm_hardware_enable(void)
 637 {
 638
 639         struct svm_cpu_data *sd;
 640         uint64_t efer;
 641         struct desc_ptr gdt_descr;
 642         struct desc_struct *gdt;
 643         int me = raw_smp_processor_id();
 644
 645         rdmsrl(MSR_EFER, efer);
 646         if (efer & EFER_SVME)
 647                 return -EBUSY;
 648
 649         if (!has_svm()) {
 650                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 651                 return -EINVAL;
 652         }
 653         sd = per_cpu(svm_data, me);
 654         if (!sd) {
 655                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 656                 return -EINVAL;
 657         }
 658
 659         sd->asid_generation = 1;
 660         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 661         sd->next_asid = sd->max_asid + 1;
 662
 663         native_store_gdt(&gdt_descr);
 664         gdt = (struct desc_struct *)gdt_descr.address;
 665         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 666
 667         wrmsrl(MSR_EFER, efer | EFER_SVME);
 668
 669         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 670
 671         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 672                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 673                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 674         }
 675
 676
 677         /*
 678          * Get OSVW bits.
 679          *
 680          * Note that it is possible to have a system with mixed processor
 681          * revisions and therefore different OSVW bits. If bits are not the same
 682          * on different processors then choose the worst case (i.e. if erratum
 683          * is present on one processor and not on another then assume that the
 684          * erratum is present everywhere).
 685          */
 686         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 687                 uint64_t len, status = 0;
 688                 int err;
 689
 690                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 691                 if (!err)
 692                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 693                                                       &err);
 694
 695                 if (err)
 696                         osvw_status = osvw_len = 0;
 697                 else {
 698                         if (len < osvw_len)
 699                                 osvw_len = len;
 700                         osvw_status |= status;
 701                         osvw_status &= (1ULL << osvw_len) - 1;
 702                 }
 703         } else
 704                 osvw_status = osvw_len = 0;
 705
 706         svm_init_erratum_383();
 707
 708         amd_pmu_enable_virt();
 709
 710         return 0;
 711 }
 712
 713 static void svm_cpu_uninit(int cpu)
 714 {
 715         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 716
 717         if (!sd)
 718                 return;
 719
 720         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 721         __free_page(sd->save_area);
 722         kfree(sd);
 723 }
 724
 725 static int svm_cpu_init(int cpu)
 726 {
 727         struct svm_cpu_data *sd;
 728         int r;
 729
 730         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 731         if (!sd)
 732                 return -ENOMEM;
 733         sd->cpu = cpu;
 734         sd->save_area = alloc_page(GFP_KERNEL);
 735         r = -ENOMEM;
 736         if (!sd->save_area)
 737                 goto err_1;
 738
 739         per_cpu(svm_data, cpu) = sd;
 740
 741         return 0;
 742
 743 err_1:
 744         kfree(sd);
 745         return r;
 746
 747 }
 748
 749 static bool valid_msr_intercept(u32 index)
 750 {
 751         int i;
 752
 753         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 754                 if (direct_access_msrs[i].index == index)
 755                         return true;
 756
 757         return false;
 758 }
 759
 760 static void set_msr_interception(u32 *msrpm, unsigned msr,
 761                                  int read, int write)
 762 {
 763         u8 bit_read, bit_write;
 764         unsigned long tmp;
 765         u32 offset;
 766
 767         /*
 768          * If this warning triggers extend the direct_access_msrs list at the
 769          * beginning of the file
 770          */
 771         WARN_ON(!valid_msr_intercept(msr));
 772
 773         offset    = svm_msrpm_offset(msr);
 774         bit_read  = 2 * (msr & 0x0f);
 775         bit_write = 2 * (msr & 0x0f) + 1;
 776         tmp       = msrpm[offset];
 777
 778         BUG_ON(offset == MSR_INVALID);
 779
 780         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 781         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 782
 783         msrpm[offset] = tmp;
 784 }
 785
 786 static void svm_vcpu_init_msrpm(u32 *msrpm)
 787 {
 788         int i;
 789
 790         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 791
 792         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 793                 if (!direct_access_msrs[i].always)
 794                         continue;
 795
 796                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 797         }
 798 }
 799
 800 static void add_msr_offset(u32 offset)
 801 {
 802         int i;
 803
 804         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 805
 806                 /* Offset already in list? */
 807                 if (msrpm_offsets[i] == offset)
 808                         return;
 809
 810                 /* Slot used by another offset? */
 811                 if (msrpm_offsets[i] != MSR_INVALID)
 812                         continue;
 813
 814                 /* Add offset to list */
 815                 msrpm_offsets[i] = offset;
 816
 817                 return;
 818         }
 819
 820         /*
 821          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 822          * increase MSRPM_OFFSETS in this case.
 823          */
 824         BUG();
 825 }
 826
 827 static void init_msrpm_offsets(void)
 828 {
 829         int i;
 830
 831         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 832
 833         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 834                 u32 offset;
 835
 836                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 837                 BUG_ON(offset == MSR_INVALID);
 838
 839                 add_msr_offset(offset);
 840         }
 841 }
 842
 843 static void svm_enable_lbrv(struct vcpu_svm *svm)
 844 {
 845         u32 *msrpm = svm->msrpm;
 846
 847         svm->vmcb->control.lbr_ctl = 1;
 848         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 849         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 850         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 851         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 852 }
 853
 854 static void svm_disable_lbrv(struct vcpu_svm *svm)
 855 {
 856         u32 *msrpm = svm->msrpm;
 857
 858         svm->vmcb->control.lbr_ctl = 0;
 859         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 860         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 861         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 862         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 863 }
 864
 865 static __init int svm_hardware_setup(void)
 866 {
 867         int cpu;
 868         struct page *iopm_pages;
 869         void *iopm_va;
 870         int r;
 871
 872         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 873
 874         if (!iopm_pages)
 875                 return -ENOMEM;
 876
 877         iopm_va = page_address(iopm_pages);
 878         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 879         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 880
 881         init_msrpm_offsets();
 882
 883         if (boot_cpu_has(X86_FEATURE_NX))
 884                 kvm_enable_efer_bits(EFER_NX);
 885
 886         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 887                 kvm_enable_efer_bits(EFER_FFXSR);
 888
 889         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 890                 u64 max;
 891
 892                 kvm_has_tsc_control = true;
 893
 894                 /*
 895                  * Make sure the user can only configure tsc_khz values that
 896                  * fit into a signed integer.
 897                  * A min value is not calculated needed because it will always
 898                  * be 1 on all machines and a value of 0 is used to disable
 899                  * tsc-scaling for the vcpu.
 900                  */
 901                 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
 902
 903                 kvm_max_guest_tsc_khz = max;
 904         }
 905
 906         if (nested) {
 907                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 908                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 909         }
 910
 911         for_each_possible_cpu(cpu) {
 912                 r = svm_cpu_init(cpu);
 913                 if (r)
 914                         goto err;
 915         }
 916
 917         if (!boot_cpu_has(X86_FEATURE_NPT))
 918                 npt_enabled = false;
 919
 920         if (npt_enabled && !npt) {
 921                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 922                 npt_enabled = false;
 923         }
 924
 925         if (npt_enabled) {
 926                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 927                 kvm_enable_tdp();
 928         } else
 929                 kvm_disable_tdp();
 930
 931         return 0;
 932
 933 err:
 934         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 935         iopm_base = 0;
 936         return r;
 937 }
 938
 939 static __exit void svm_hardware_unsetup(void)
 940 {
 941         int cpu;
 942
 943         for_each_possible_cpu(cpu)
 944                 svm_cpu_uninit(cpu);
 945
 946         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 947         iopm_base = 0;
 948 }
 949
 950 static void init_seg(struct vmcb_seg *seg)
 951 {
 952         seg->selector = 0;
 953         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 954                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 955         seg->limit = 0xffff;
 956         seg->base = 0;
 957 }
 958
 959 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 960 {
 961         seg->selector = 0;
 962         seg->attrib = SVM_SELECTOR_P_MASK | type;
 963         seg->limit = 0xffff;
 964         seg->base = 0;
 965 }
 966
 967 static u64 __scale_tsc(u64 ratio, u64 tsc)
 968 {
 969         u64 mult, frac, _tsc;
 970
 971         mult  = ratio >> 32;
 972         frac  = ratio & ((1ULL << 32) - 1);
 973
 974         _tsc  = tsc;
 975         _tsc *= mult;
 976         _tsc += (tsc >> 32) * frac;
 977         _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
 978
 979         return _tsc;
 980 }
 981
 982 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
 983 {
 984         struct vcpu_svm *svm = to_svm(vcpu);
 985         u64 _tsc = tsc;
 986
 987         if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
 988                 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
 989
 990         return _tsc;
 991 }
 992
 993 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
 994 {
 995         struct vcpu_svm *svm = to_svm(vcpu);
 996         u64 ratio;
 997         u64 khz;
 998
 999         /* Guest TSC same frequency as host TSC? */
1000         if (!scale) {
1001                 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1002                 return;
1003         }
1004
1005         /* TSC scaling supported? */
1006         if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1007                 if (user_tsc_khz > tsc_khz) {
1008                         vcpu->arch.tsc_catchup = 1;
1009                         vcpu->arch.tsc_always_catchup = 1;
1010                 } else
1011                         WARN(1, "user requested TSC rate below hardware speed\n");
1012                 return;
1013         }
1014
1015         khz = user_tsc_khz;
1016
1017         /* TSC scaling required  - calculate ratio */
1018         ratio = khz << 32;
1019         do_div(ratio, tsc_khz);
1020
1021         if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1022                 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1023                                 user_tsc_khz);
1024                 return;
1025         }
1026         svm->tsc_ratio             = ratio;
1027 }
1028
1029 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1030 {
1031         struct vcpu_svm *svm = to_svm(vcpu);
1032
1033         return svm->vmcb->control.tsc_offset;
1034 }
1035
1036 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1037 {
1038         struct vcpu_svm *svm = to_svm(vcpu);
1039         u64 g_tsc_offset = 0;
1040
1041         if (is_guest_mode(vcpu)) {
1042                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1043                                svm->nested.hsave->control.tsc_offset;
1044                 svm->nested.hsave->control.tsc_offset = offset;
1045         } else
1046                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1047                                            svm->vmcb->control.tsc_offset,
1048                                            offset);
1049
1050         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1051
1052         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1053 }
1054
1055 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1056 {
1057         struct vcpu_svm *svm = to_svm(vcpu);
1058
1059         if (host) {
1060                 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
1061                         WARN_ON(adjustment < 0);
1062                 adjustment = svm_scale_tsc(vcpu, (u64)adjustment);
1063         }
1064
1065         svm->vmcb->control.tsc_offset += adjustment;
1066         if (is_guest_mode(vcpu))
1067                 svm->nested.hsave->control.tsc_offset += adjustment;
1068         else
1069                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1070                                      svm->vmcb->control.tsc_offset - adjustment,
1071                                      svm->vmcb->control.tsc_offset);
1072
1073         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1074 }
1075
1076 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1077 {
1078         u64 tsc;
1079
1080         tsc = svm_scale_tsc(vcpu, native_read_tsc());
1081
1082         return target_tsc - tsc;
1083 }
1084
1085 static void init_vmcb(struct vcpu_svm *svm)
1086 {
1087         struct vmcb_control_area *control = &svm->vmcb->control;
1088         struct vmcb_save_area *save = &svm->vmcb->save;
1089
1090         svm->vcpu.fpu_active = 1;
1091         svm->vcpu.arch.hflags = 0;
1092
1093         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1094         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1095         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1096         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1097         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1098         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1099         set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1100
1101         set_dr_intercepts(svm);
1102
1103         set_exception_intercept(svm, PF_VECTOR);
1104         set_exception_intercept(svm, UD_VECTOR);
1105         set_exception_intercept(svm, MC_VECTOR);
1106
1107         set_intercept(svm, INTERCEPT_INTR);
1108         set_intercept(svm, INTERCEPT_NMI);
1109         set_intercept(svm, INTERCEPT_SMI);
1110         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1111         set_intercept(svm, INTERCEPT_RDPMC);
1112         set_intercept(svm, INTERCEPT_CPUID);
1113         set_intercept(svm, INTERCEPT_INVD);
1114         set_intercept(svm, INTERCEPT_HLT);
1115         set_intercept(svm, INTERCEPT_INVLPG);
1116         set_intercept(svm, INTERCEPT_INVLPGA);
1117         set_intercept(svm, INTERCEPT_IOIO_PROT);
1118         set_intercept(svm, INTERCEPT_MSR_PROT);
1119         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1120         set_intercept(svm, INTERCEPT_SHUTDOWN);
1121         set_intercept(svm, INTERCEPT_VMRUN);
1122         set_intercept(svm, INTERCEPT_VMMCALL);
1123         set_intercept(svm, INTERCEPT_VMLOAD);
1124         set_intercept(svm, INTERCEPT_VMSAVE);
1125         set_intercept(svm, INTERCEPT_STGI);
1126         set_intercept(svm, INTERCEPT_CLGI);
1127         set_intercept(svm, INTERCEPT_SKINIT);
1128         set_intercept(svm, INTERCEPT_WBINVD);
1129         set_intercept(svm, INTERCEPT_MONITOR);
1130         set_intercept(svm, INTERCEPT_MWAIT);
1131         set_intercept(svm, INTERCEPT_XSETBV);
1132
1133         control->iopm_base_pa = iopm_base;
1134         control->msrpm_base_pa = __pa(svm->msrpm);
1135         control->int_ctl = V_INTR_MASKING_MASK;
1136
1137         init_seg(&save->es);
1138         init_seg(&save->ss);
1139         init_seg(&save->ds);
1140         init_seg(&save->fs);
1141         init_seg(&save->gs);
1142
1143         save->cs.selector = 0xf000;
1144         save->cs.base = 0xffff0000;
1145         /* Executable/Readable Code Segment */
1146         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1147                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1148         save->cs.limit = 0xffff;
1149
1150         save->gdtr.limit = 0xffff;
1151         save->idtr.limit = 0xffff;
1152
1153         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1154         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1155
1156         svm_set_efer(&svm->vcpu, 0);
1157         save->dr6 = 0xffff0ff0;
1158         kvm_set_rflags(&svm->vcpu, 2);
1159         save->rip = 0x0000fff0;
1160         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1161
1162         /*
1163          * This is the guest-visible cr0 value.
1164          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1165          */
1166         svm->vcpu.arch.cr0 = 0;
1167         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1168
1169         save->cr4 = X86_CR4_PAE;
1170         /* rdx = ?? */
1171
1172         if (npt_enabled) {
1173                 /* Setup VMCB for Nested Paging */
1174                 control->nested_ctl = 1;
1175                 clr_intercept(svm, INTERCEPT_INVLPG);
1176                 clr_exception_intercept(svm, PF_VECTOR);
1177                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1178                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1179                 save->g_pat = 0x0007040600070406ULL;
1180                 save->cr3 = 0;
1181                 save->cr4 = 0;
1182         }
1183         svm->asid_generation = 0;
1184
1185         svm->nested.vmcb = 0;
1186         svm->vcpu.arch.hflags = 0;
1187
1188         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1189                 control->pause_filter_count = 3000;
1190                 set_intercept(svm, INTERCEPT_PAUSE);
1191         }
1192
1193         mark_all_dirty(svm->vmcb);
1194
1195         enable_gif(svm);
1196 }
1197
1198 static void svm_vcpu_reset(struct kvm_vcpu *vcpu)
1199 {
1200         struct vcpu_svm *svm = to_svm(vcpu);
1201         u32 dummy;
1202         u32 eax = 1;
1203
1204         init_vmcb(svm);
1205
1206         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1207         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1208 }
1209
1210 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1211 {
1212         struct vcpu_svm *svm;
1213         struct page *page;
1214         struct page *msrpm_pages;
1215         struct page *hsave_page;
1216         struct page *nested_msrpm_pages;
1217         int err;
1218
1219         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1220         if (!svm) {
1221                 err = -ENOMEM;
1222                 goto out;
1223         }
1224
1225         svm->tsc_ratio = TSC_RATIO_DEFAULT;
1226
1227         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1228         if (err)
1229                 goto free_svm;
1230
1231         err = -ENOMEM;
1232         page = alloc_page(GFP_KERNEL);
1233         if (!page)
1234                 goto uninit;
1235
1236         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1237         if (!msrpm_pages)
1238                 goto free_page1;
1239
1240         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1241         if (!nested_msrpm_pages)
1242                 goto free_page2;
1243
1244         hsave_page = alloc_page(GFP_KERNEL);
1245         if (!hsave_page)
1246                 goto free_page3;
1247
1248         svm->nested.hsave = page_address(hsave_page);
1249
1250         svm->msrpm = page_address(msrpm_pages);
1251         svm_vcpu_init_msrpm(svm->msrpm);
1252
1253         svm->nested.msrpm = page_address(nested_msrpm_pages);
1254         svm_vcpu_init_msrpm(svm->nested.msrpm);
1255
1256         svm->vmcb = page_address(page);
1257         clear_page(svm->vmcb);
1258         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1259         svm->asid_generation = 0;
1260         init_vmcb(svm);
1261
1262         svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1263                                    MSR_IA32_APICBASE_ENABLE;
1264         if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1265                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1266
1267         svm_init_osvw(&svm->vcpu);
1268
1269         return &svm->vcpu;
1270
1271 free_page3:
1272         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1273 free_page2:
1274         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1275 free_page1:
1276         __free_page(page);
1277 uninit:
1278         kvm_vcpu_uninit(&svm->vcpu);
1279 free_svm:
1280         kmem_cache_free(kvm_vcpu_cache, svm);
1281 out:
1282         return ERR_PTR(err);
1283 }
1284
1285 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1286 {
1287         struct vcpu_svm *svm = to_svm(vcpu);
1288
1289         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1290         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1291         __free_page(virt_to_page(svm->nested.hsave));
1292         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1293         kvm_vcpu_uninit(vcpu);
1294         kmem_cache_free(kvm_vcpu_cache, svm);
1295 }
1296
1297 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1298 {
1299         struct vcpu_svm *svm = to_svm(vcpu);
1300         int i;
1301
1302         if (unlikely(cpu != vcpu->cpu)) {
1303                 svm->asid_generation = 0;
1304                 mark_all_dirty(svm->vmcb);
1305         }
1306
1307 #ifdef CONFIG_X86_64
1308         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1309 #endif
1310         savesegment(fs, svm->host.fs);
1311         savesegment(gs, svm->host.gs);
1312         svm->host.ldt = kvm_read_ldt();
1313
1314         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1315                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1316
1317         if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1318             svm->tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1319                 __this_cpu_write(current_tsc_ratio, svm->tsc_ratio);
1320                 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1321         }
1322 }
1323
1324 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1325 {
1326         struct vcpu_svm *svm = to_svm(vcpu);
1327         int i;
1328
1329         ++vcpu->stat.host_state_reload;
1330         kvm_load_ldt(svm->host.ldt);
1331 #ifdef CONFIG_X86_64
1332         loadsegment(fs, svm->host.fs);
1333         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1334         load_gs_index(svm->host.gs);
1335 #else
1336 #ifdef CONFIG_X86_32_LAZY_GS
1337         loadsegment(gs, svm->host.gs);
1338 #endif
1339 #endif
1340         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1341                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1342 }
1343
1344 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1345 {
1346         return to_svm(vcpu)->vmcb->save.rflags;
1347 }
1348
1349 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1350 {
1351        /*
1352         * Any change of EFLAGS.VM is accompained by a reload of SS
1353         * (caused by either a task switch or an inter-privilege IRET),
1354         * so we do not need to update the CPL here.
1355         */
1356         to_svm(vcpu)->vmcb->save.rflags = rflags;
1357 }
1358
1359 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1360 {
1361         switch (reg) {
1362         case VCPU_EXREG_PDPTR:
1363                 BUG_ON(!npt_enabled);
1364                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1365                 break;
1366         default:
1367                 BUG();
1368         }
1369 }
1370
1371 static void svm_set_vintr(struct vcpu_svm *svm)
1372 {
1373         set_intercept(svm, INTERCEPT_VINTR);
1374 }
1375
1376 static void svm_clear_vintr(struct vcpu_svm *svm)
1377 {
1378         clr_intercept(svm, INTERCEPT_VINTR);
1379 }
1380
1381 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1382 {
1383         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1384
1385         switch (seg) {
1386         case VCPU_SREG_CS: return &save->cs;
1387         case VCPU_SREG_DS: return &save->ds;
1388         case VCPU_SREG_ES: return &save->es;
1389         case VCPU_SREG_FS: return &save->fs;
1390         case VCPU_SREG_GS: return &save->gs;
1391         case VCPU_SREG_SS: return &save->ss;
1392         case VCPU_SREG_TR: return &save->tr;
1393         case VCPU_SREG_LDTR: return &save->ldtr;
1394         }
1395         BUG();
1396         return NULL;
1397 }
1398
1399 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1400 {
1401         struct vmcb_seg *s = svm_seg(vcpu, seg);
1402
1403         return s->base;
1404 }
1405
1406 static void svm_get_segment(struct kvm_vcpu *vcpu,
1407                             struct kvm_segment *var, int seg)
1408 {
1409         struct vmcb_seg *s = svm_seg(vcpu, seg);
1410
1411         var->base = s->base;
1412         var->limit = s->limit;
1413         var->selector = s->selector;
1414         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1415         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1416         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1417         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1418         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1419         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1420         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1421
1422         /*
1423          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1424          * However, the SVM spec states that the G bit is not observed by the
1425          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1426          * So let's synthesize a legal G bit for all segments, this helps
1427          * running KVM nested. It also helps cross-vendor migration, because
1428          * Intel's vmentry has a check on the 'G' bit.
1429          */
1430         var->g = s->limit > 0xfffff;
1431
1432         /*
1433          * AMD's VMCB does not have an explicit unusable field, so emulate it
1434          * for cross vendor migration purposes by "not present"
1435          */
1436         var->unusable = !var->present || (var->type == 0);
1437
1438         switch (seg) {
1439         case VCPU_SREG_TR:
1440                 /*
1441                  * Work around a bug where the busy flag in the tr selector
1442                  * isn't exposed
1443                  */
1444                 var->type |= 0x2;
1445                 break;
1446         case VCPU_SREG_DS:
1447         case VCPU_SREG_ES:
1448         case VCPU_SREG_FS:
1449         case VCPU_SREG_GS:
1450                 /*
1451                  * The accessed bit must always be set in the segment
1452                  * descriptor cache, although it can be cleared in the
1453                  * descriptor, the cached bit always remains at 1. Since
1454                  * Intel has a check on this, set it here to support
1455                  * cross-vendor migration.
1456                  */
1457                 if (!var->unusable)
1458                         var->type |= 0x1;
1459                 break;
1460         case VCPU_SREG_SS:
1461                 /*
1462                  * On AMD CPUs sometimes the DB bit in the segment
1463                  * descriptor is left as 1, although the whole segment has
1464                  * been made unusable. Clear it here to pass an Intel VMX
1465                  * entry check when cross vendor migrating.
1466                  */
1467                 if (var->unusable)
1468                         var->db = 0;
1469                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1470                 break;
1471         }
1472 }
1473
1474 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1475 {
1476         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1477
1478         return save->cpl;
1479 }
1480
1481 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1482 {
1483         struct vcpu_svm *svm = to_svm(vcpu);
1484
1485         dt->size = svm->vmcb->save.idtr.limit;
1486         dt->address = svm->vmcb->save.idtr.base;
1487 }
1488
1489 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1490 {
1491         struct vcpu_svm *svm = to_svm(vcpu);
1492
1493         svm->vmcb->save.idtr.limit = dt->size;
1494         svm->vmcb->save.idtr.base = dt->address ;
1495         mark_dirty(svm->vmcb, VMCB_DT);
1496 }
1497
1498 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1499 {
1500         struct vcpu_svm *svm = to_svm(vcpu);
1501
1502         dt->size = svm->vmcb->save.gdtr.limit;
1503         dt->address = svm->vmcb->save.gdtr.base;
1504 }
1505
1506 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1507 {
1508         struct vcpu_svm *svm = to_svm(vcpu);
1509
1510         svm->vmcb->save.gdtr.limit = dt->size;
1511         svm->vmcb->save.gdtr.base = dt->address ;
1512         mark_dirty(svm->vmcb, VMCB_DT);
1513 }
1514
1515 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1516 {
1517 }
1518
1519 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1520 {
1521 }
1522
1523 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1524 {
1525 }
1526
1527 static void update_cr0_intercept(struct vcpu_svm *svm)
1528 {
1529         ulong gcr0 = svm->vcpu.arch.cr0;
1530         u64 *hcr0 = &svm->vmcb->save.cr0;
1531
1532         if (!svm->vcpu.fpu_active)
1533                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1534         else
1535                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1536                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1537
1538         mark_dirty(svm->vmcb, VMCB_CR);
1539
1540         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1541                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1542                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1543         } else {
1544                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1545                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1546         }
1547 }
1548
1549 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1550 {
1551         struct vcpu_svm *svm = to_svm(vcpu);
1552
1553 #ifdef CONFIG_X86_64
1554         if (vcpu->arch.efer & EFER_LME) {
1555                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1556                         vcpu->arch.efer |= EFER_LMA;
1557                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1558                 }
1559
1560                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1561                         vcpu->arch.efer &= ~EFER_LMA;
1562                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1563                 }
1564         }
1565 #endif
1566         vcpu->arch.cr0 = cr0;
1567
1568         if (!npt_enabled)
1569                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1570
1571         if (!vcpu->fpu_active)
1572                 cr0 |= X86_CR0_TS;
1573         /*
1574          * re-enable caching here because the QEMU bios
1575          * does not do it - this results in some delay at
1576          * reboot
1577          */
1578         if (!(vcpu->kvm->arch.disabled_quirks & KVM_QUIRK_CD_NW_CLEARED))
1579                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1580         svm->vmcb->save.cr0 = cr0;
1581         mark_dirty(svm->vmcb, VMCB_CR);
1582         update_cr0_intercept(svm);
1583 }
1584
1585 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1586 {
1587         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1588         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1589
1590         if (cr4 & X86_CR4_VMXE)
1591                 return 1;
1592
1593         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1594                 svm_flush_tlb(vcpu);
1595
1596         vcpu->arch.cr4 = cr4;
1597         if (!npt_enabled)
1598                 cr4 |= X86_CR4_PAE;
1599         cr4 |= host_cr4_mce;
1600         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1601         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1602         return 0;
1603 }
1604
1605 static void svm_set_segment(struct kvm_vcpu *vcpu,
1606                             struct kvm_segment *var, int seg)
1607 {
1608         struct vcpu_svm *svm = to_svm(vcpu);
1609         struct vmcb_seg *s = svm_seg(vcpu, seg);
1610
1611         s->base = var->base;
1612         s->limit = var->limit;
1613         s->selector = var->selector;
1614         if (var->unusable)
1615                 s->attrib = 0;
1616         else {
1617                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1618                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1619                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1620                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1621                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1622                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1623                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1624                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1625         }
1626
1627         /*
1628          * This is always accurate, except if SYSRET returned to a segment
1629          * with SS.DPL != 3.  Intel does not have this quirk, and always
1630          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1631          * would entail passing the CPL to userspace and back.
1632          */
1633         if (seg == VCPU_SREG_SS)
1634                 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1635
1636         mark_dirty(svm->vmcb, VMCB_SEG);
1637 }
1638
1639 static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1640 {
1641         struct vcpu_svm *svm = to_svm(vcpu);
1642
1643         clr_exception_intercept(svm, DB_VECTOR);
1644         clr_exception_intercept(svm, BP_VECTOR);
1645
1646         if (svm->nmi_singlestep)
1647                 set_exception_intercept(svm, DB_VECTOR);
1648
1649         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1650                 if (vcpu->guest_debug &
1651                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1652                         set_exception_intercept(svm, DB_VECTOR);
1653                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1654                         set_exception_intercept(svm, BP_VECTOR);
1655         } else
1656                 vcpu->guest_debug = 0;
1657 }
1658
1659 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1660 {
1661         if (sd->next_asid > sd->max_asid) {
1662                 ++sd->asid_generation;
1663                 sd->next_asid = 1;
1664                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1665         }
1666
1667         svm->asid_generation = sd->asid_generation;
1668         svm->vmcb->control.asid = sd->next_asid++;
1669
1670         mark_dirty(svm->vmcb, VMCB_ASID);
1671 }
1672
1673 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1674 {
1675         return to_svm(vcpu)->vmcb->save.dr6;
1676 }
1677
1678 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1679 {
1680         struct vcpu_svm *svm = to_svm(vcpu);
1681
1682         svm->vmcb->save.dr6 = value;
1683         mark_dirty(svm->vmcb, VMCB_DR);
1684 }
1685
1686 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1687 {
1688         struct vcpu_svm *svm = to_svm(vcpu);
1689
1690         get_debugreg(vcpu->arch.db[0], 0);
1691         get_debugreg(vcpu->arch.db[1], 1);
1692         get_debugreg(vcpu->arch.db[2], 2);
1693         get_debugreg(vcpu->arch.db[3], 3);
1694         vcpu->arch.dr6 = svm_get_dr6(vcpu);
1695         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1696
1697         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1698         set_dr_intercepts(svm);
1699 }
1700
1701 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1702 {
1703         struct vcpu_svm *svm = to_svm(vcpu);
1704
1705         svm->vmcb->save.dr7 = value;
1706         mark_dirty(svm->vmcb, VMCB_DR);
1707 }
1708
1709 static int pf_interception(struct vcpu_svm *svm)
1710 {
1711         u64 fault_address = svm->vmcb->control.exit_info_2;
1712         u32 error_code;
1713         int r = 1;
1714
1715         switch (svm->apf_reason) {
1716         default:
1717                 error_code = svm->vmcb->control.exit_info_1;
1718
1719                 trace_kvm_page_fault(fault_address, error_code);
1720                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1721                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1722                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1723                         svm->vmcb->control.insn_bytes,
1724                         svm->vmcb->control.insn_len);
1725                 break;
1726         case KVM_PV_REASON_PAGE_NOT_PRESENT:
1727                 svm->apf_reason = 0;
1728                 local_irq_disable();
1729                 kvm_async_pf_task_wait(fault_address);
1730                 local_irq_enable();
1731                 break;
1732         case KVM_PV_REASON_PAGE_READY:
1733                 svm->apf_reason = 0;
1734                 local_irq_disable();
1735                 kvm_async_pf_task_wake(fault_address);
1736                 local_irq_enable();
1737                 break;
1738         }
1739         return r;
1740 }
1741
1742 static int db_interception(struct vcpu_svm *svm)
1743 {
1744         struct kvm_run *kvm_run = svm->vcpu.run;
1745
1746         if (!(svm->vcpu.guest_debug &
1747               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1748                 !svm->nmi_singlestep) {
1749                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1750                 return 1;
1751         }
1752
1753         if (svm->nmi_singlestep) {
1754                 svm->nmi_singlestep = false;
1755                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1756                         svm->vmcb->save.rflags &=
1757                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1758                 update_db_bp_intercept(&svm->vcpu);
1759         }
1760
1761         if (svm->vcpu.guest_debug &
1762             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1763                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1764                 kvm_run->debug.arch.pc =
1765                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1766                 kvm_run->debug.arch.exception = DB_VECTOR;
1767                 return 0;
1768         }
1769
1770         return 1;
1771 }
1772
1773 static int bp_interception(struct vcpu_svm *svm)
1774 {
1775         struct kvm_run *kvm_run = svm->vcpu.run;
1776
1777         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1778         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1779         kvm_run->debug.arch.exception = BP_VECTOR;
1780         return 0;
1781 }
1782
1783 static int ud_interception(struct vcpu_svm *svm)
1784 {
1785         int er;
1786
1787         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1788         if (er != EMULATE_DONE)
1789                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1790         return 1;
1791 }
1792
1793 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1794 {
1795         struct vcpu_svm *svm = to_svm(vcpu);
1796
1797         clr_exception_intercept(svm, NM_VECTOR);
1798
1799         svm->vcpu.fpu_active = 1;
1800         update_cr0_intercept(svm);
1801 }
1802
1803 static int nm_interception(struct vcpu_svm *svm)
1804 {
1805         svm_fpu_activate(&svm->vcpu);
1806         return 1;
1807 }
1808
1809 static bool is_erratum_383(void)
1810 {
1811         int err, i;
1812         u64 value;
1813
1814         if (!erratum_383_found)
1815                 return false;
1816
1817         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1818         if (err)
1819                 return false;
1820
1821         /* Bit 62 may or may not be set for this mce */
1822         value &= ~(1ULL << 62);
1823
1824         if (value != 0xb600000000010015ULL)
1825                 return false;
1826
1827         /* Clear MCi_STATUS registers */
1828         for (i = 0; i < 6; ++i)
1829                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1830
1831         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1832         if (!err) {
1833                 u32 low, high;
1834
1835                 value &= ~(1ULL << 2);
1836                 low    = lower_32_bits(value);
1837                 high   = upper_32_bits(value);
1838
1839                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1840         }
1841
1842         /* Flush tlb to evict multi-match entries */
1843         __flush_tlb_all();
1844
1845         return true;
1846 }
1847
1848 static void svm_handle_mce(struct vcpu_svm *svm)
1849 {
1850         if (is_erratum_383()) {
1851                 /*
1852                  * Erratum 383 triggered. Guest state is corrupt so kill the
1853                  * guest.
1854                  */
1855                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1856
1857                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1858
1859                 return;
1860         }
1861
1862         /*
1863          * On an #MC intercept the MCE handler is not called automatically in
1864          * the host. So do it by hand here.
1865          */
1866         asm volatile (
1867                 "int $0x12\n");
1868         /* not sure if we ever come back to this point */
1869
1870         return;
1871 }
1872
1873 static int mc_interception(struct vcpu_svm *svm)
1874 {
1875         return 1;
1876 }
1877
1878 static int shutdown_interception(struct vcpu_svm *svm)
1879 {
1880         struct kvm_run *kvm_run = svm->vcpu.run;
1881
1882         /*
1883          * VMCB is undefined after a SHUTDOWN intercept
1884          * so reinitialize it.
1885          */
1886         clear_page(svm->vmcb);
1887         init_vmcb(svm);
1888
1889         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1890         return 0;
1891 }
1892
1893 static int io_interception(struct vcpu_svm *svm)
1894 {
1895         struct kvm_vcpu *vcpu = &svm->vcpu;
1896         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1897         int size, in, string;
1898         unsigned port;
1899
1900         ++svm->vcpu.stat.io_exits;
1901         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1902         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1903         if (string || in)
1904                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1905
1906         port = io_info >> 16;
1907         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1908         svm->next_rip = svm->vmcb->control.exit_info_2;
1909         skip_emulated_instruction(&svm->vcpu);
1910
1911         return kvm_fast_pio_out(vcpu, size, port);
1912 }
1913
1914 static int nmi_interception(struct vcpu_svm *svm)
1915 {
1916         return 1;
1917 }
1918
1919 static int intr_interception(struct vcpu_svm *svm)
1920 {
1921         ++svm->vcpu.stat.irq_exits;
1922         return 1;
1923 }
1924
1925 static int nop_on_interception(struct vcpu_svm *svm)
1926 {
1927         return 1;
1928 }
1929
1930 static int halt_interception(struct vcpu_svm *svm)
1931 {
1932         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1933         return kvm_emulate_halt(&svm->vcpu);
1934 }
1935
1936 static int vmmcall_interception(struct vcpu_svm *svm)
1937 {
1938         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1939         kvm_emulate_hypercall(&svm->vcpu);
1940         return 1;
1941 }
1942
1943 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1944 {
1945         struct vcpu_svm *svm = to_svm(vcpu);
1946
1947         return svm->nested.nested_cr3;
1948 }
1949
1950 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1951 {
1952         struct vcpu_svm *svm = to_svm(vcpu);
1953         u64 cr3 = svm->nested.nested_cr3;
1954         u64 pdpte;
1955         int ret;
1956
1957         ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1958                                   offset_in_page(cr3) + index * 8, 8);
1959         if (ret)
1960                 return 0;
1961         return pdpte;
1962 }
1963
1964 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1965                                    unsigned long root)
1966 {
1967         struct vcpu_svm *svm = to_svm(vcpu);
1968
1969         svm->vmcb->control.nested_cr3 = root;
1970         mark_dirty(svm->vmcb, VMCB_NPT);
1971         svm_flush_tlb(vcpu);
1972 }
1973
1974 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1975                                        struct x86_exception *fault)
1976 {
1977         struct vcpu_svm *svm = to_svm(vcpu);
1978
1979         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
1980                 /*
1981                  * TODO: track the cause of the nested page fault, and
1982                  * correctly fill in the high bits of exit_info_1.
1983                  */
1984                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1985                 svm->vmcb->control.exit_code_hi = 0;
1986                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
1987                 svm->vmcb->control.exit_info_2 = fault->address;
1988         }
1989
1990         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
1991         svm->vmcb->control.exit_info_1 |= fault->error_code;
1992
1993         /*
1994          * The present bit is always zero for page structure faults on real
1995          * hardware.
1996          */
1997         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
1998                 svm->vmcb->control.exit_info_1 &= ~1;
1999
2000         nested_svm_vmexit(svm);
2001 }
2002
2003 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2004 {
2005         WARN_ON(mmu_is_nested(vcpu));
2006         kvm_init_shadow_mmu(vcpu);
2007         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
2008         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
2009         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
2010         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2011         vcpu->arch.mmu.shadow_root_level = get_npt_level();
2012         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2013 }
2014
2015 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2016 {
2017         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2018 }
2019
2020 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2021 {
2022         if (!(svm->vcpu.arch.efer & EFER_SVME)
2023             || !is_paging(&svm->vcpu)) {
2024                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2025                 return 1;
2026         }
2027
2028         if (svm->vmcb->save.cpl) {
2029                 kvm_inject_gp(&svm->vcpu, 0);
2030                 return 1;
2031         }
2032
2033        return 0;
2034 }
2035
2036 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2037                                       bool has_error_code, u32 error_code)
2038 {
2039         int vmexit;
2040
2041         if (!is_guest_mode(&svm->vcpu))
2042                 return 0;
2043
2044         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2045         svm->vmcb->control.exit_code_hi = 0;
2046         svm->vmcb->control.exit_info_1 = error_code;
2047         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2048
2049         vmexit = nested_svm_intercept(svm);
2050         if (vmexit == NESTED_EXIT_DONE)
2051                 svm->nested.exit_required = true;
2052
2053         return vmexit;
2054 }
2055
2056 /* This function returns true if it is save to enable the irq window */
2057 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2058 {
2059         if (!is_guest_mode(&svm->vcpu))
2060                 return true;
2061
2062         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2063                 return true;
2064
2065         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2066                 return false;
2067
2068         /*
2069          * if vmexit was already requested (by intercepted exception
2070          * for instance) do not overwrite it with "external interrupt"
2071          * vmexit.
2072          */
2073         if (svm->nested.exit_required)
2074                 return false;
2075
2076         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2077         svm->vmcb->control.exit_info_1 = 0;
2078         svm->vmcb->control.exit_info_2 = 0;
2079
2080         if (svm->nested.intercept & 1ULL) {
2081                 /*
2082                  * The #vmexit can't be emulated here directly because this
2083                  * code path runs with irqs and preemption disabled. A
2084                  * #vmexit emulation might sleep. Only signal request for
2085                  * the #vmexit here.
2086                  */
2087                 svm->nested.exit_required = true;
2088                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2089                 return false;
2090         }
2091
2092         return true;
2093 }
2094
2095 /* This function returns true if it is save to enable the nmi window */
2096 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2097 {
2098         if (!is_guest_mode(&svm->vcpu))
2099                 return true;
2100
2101         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2102                 return true;
2103
2104         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2105         svm->nested.exit_required = true;
2106
2107         return false;
2108 }
2109
2110 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2111 {
2112         struct page *page;
2113
2114         might_sleep();
2115
2116         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2117         if (is_error_page(page))
2118                 goto error;
2119
2120         *_page = page;
2121
2122         return kmap(page);
2123
2124 error:
2125         kvm_inject_gp(&svm->vcpu, 0);
2126
2127         return NULL;
2128 }
2129
2130 static void nested_svm_unmap(struct page *page)
2131 {
2132         kunmap(page);
2133         kvm_release_page_dirty(page);
2134 }
2135
2136 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2137 {
2138         unsigned port, size, iopm_len;
2139         u16 val, mask;
2140         u8 start_bit;
2141         u64 gpa;
2142
2143         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2144                 return NESTED_EXIT_HOST;
2145
2146         port = svm->vmcb->control.exit_info_1 >> 16;
2147         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2148                 SVM_IOIO_SIZE_SHIFT;
2149         gpa  = svm->nested.vmcb_iopm + (port / 8);
2150         start_bit = port % 8;
2151         iopm_len = (start_bit + size > 8) ? 2 : 1;
2152         mask = (0xf >> (4 - size)) << start_bit;
2153         val = 0;
2154
2155         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, iopm_len))
2156                 return NESTED_EXIT_DONE;
2157
2158         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2159 }
2160
2161 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2162 {
2163         u32 offset, msr, value;
2164         int write, mask;
2165
2166         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2167                 return NESTED_EXIT_HOST;
2168
2169         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2170         offset = svm_msrpm_offset(msr);
2171         write  = svm->vmcb->control.exit_info_1 & 1;
2172         mask   = 1 << ((2 * (msr & 0xf)) + write);
2173
2174         if (offset == MSR_INVALID)
2175                 return NESTED_EXIT_DONE;
2176
2177         /* Offset is in 32 bit units but need in 8 bit units */
2178         offset *= 4;
2179
2180         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2181                 return NESTED_EXIT_DONE;
2182
2183         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2184 }
2185
2186 static int nested_svm_exit_special(struct vcpu_svm *svm)
2187 {
2188         u32 exit_code = svm->vmcb->control.exit_code;
2189
2190         switch (exit_code) {
2191         case SVM_EXIT_INTR:
2192         case SVM_EXIT_NMI:
2193         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2194                 return NESTED_EXIT_HOST;
2195         case SVM_EXIT_NPF:
2196                 /* For now we are always handling NPFs when using them */
2197                 if (npt_enabled)
2198                         return NESTED_EXIT_HOST;
2199                 break;
2200         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2201                 /* When we're shadowing, trap PFs, but not async PF */
2202                 if (!npt_enabled && svm->apf_reason == 0)
2203                         return NESTED_EXIT_HOST;
2204                 break;
2205         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2206                 nm_interception(svm);
2207                 break;
2208         default:
2209                 break;
2210         }
2211
2212         return NESTED_EXIT_CONTINUE;
2213 }
2214
2215 /*
2216  * If this function returns true, this #vmexit was already handled
2217  */
2218 static int nested_svm_intercept(struct vcpu_svm *svm)
2219 {
2220         u32 exit_code = svm->vmcb->control.exit_code;
2221         int vmexit = NESTED_EXIT_HOST;
2222
2223         switch (exit_code) {
2224         case SVM_EXIT_MSR:
2225                 vmexit = nested_svm_exit_handled_msr(svm);
2226                 break;
2227         case SVM_EXIT_IOIO:
2228                 vmexit = nested_svm_intercept_ioio(svm);
2229                 break;
2230         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2231                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2232                 if (svm->nested.intercept_cr & bit)
2233                         vmexit = NESTED_EXIT_DONE;
2234                 break;
2235         }
2236         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2237                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2238                 if (svm->nested.intercept_dr & bit)
2239                         vmexit = NESTED_EXIT_DONE;
2240                 break;
2241         }
2242         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2243                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2244                 if (svm->nested.intercept_exceptions & excp_bits)
2245                         vmexit = NESTED_EXIT_DONE;
2246                 /* async page fault always cause vmexit */
2247                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2248                          svm->apf_reason != 0)
2249                         vmexit = NESTED_EXIT_DONE;
2250                 break;
2251         }
2252         case SVM_EXIT_ERR: {
2253                 vmexit = NESTED_EXIT_DONE;
2254                 break;
2255         }
2256         default: {
2257                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2258                 if (svm->nested.intercept & exit_bits)
2259                         vmexit = NESTED_EXIT_DONE;
2260         }
2261         }
2262
2263         return vmexit;
2264 }
2265
2266 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2267 {
2268         int vmexit;
2269
2270         vmexit = nested_svm_intercept(svm);
2271
2272         if (vmexit == NESTED_EXIT_DONE)
2273                 nested_svm_vmexit(svm);
2274
2275         return vmexit;
2276 }
2277
2278 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2279 {
2280         struct vmcb_control_area *dst  = &dst_vmcb->control;
2281         struct vmcb_control_area *from = &from_vmcb->control;
2282
2283         dst->intercept_cr         = from->intercept_cr;
2284         dst->intercept_dr         = from->intercept_dr;
2285         dst->intercept_exceptions = from->intercept_exceptions;
2286         dst->intercept            = from->intercept;
2287         dst->iopm_base_pa         = from->iopm_base_pa;
2288         dst->msrpm_base_pa        = from->msrpm_base_pa;
2289         dst->tsc_offset           = from->tsc_offset;
2290         dst->asid                 = from->asid;
2291         dst->tlb_ctl              = from->tlb_ctl;
2292         dst->int_ctl              = from->int_ctl;
2293         dst->int_vector           = from->int_vector;
2294         dst->int_state            = from->int_state;
2295         dst->exit_code            = from->exit_code;
2296         dst->exit_code_hi         = from->exit_code_hi;
2297         dst->exit_info_1          = from->exit_info_1;
2298         dst->exit_info_2          = from->exit_info_2;
2299         dst->exit_int_info        = from->exit_int_info;
2300         dst->exit_int_info_err    = from->exit_int_info_err;
2301         dst->nested_ctl           = from->nested_ctl;
2302         dst->event_inj            = from->event_inj;
2303         dst->event_inj_err        = from->event_inj_err;
2304         dst->nested_cr3           = from->nested_cr3;
2305         dst->lbr_ctl              = from->lbr_ctl;
2306 }
2307
2308 static int nested_svm_vmexit(struct vcpu_svm *svm)
2309 {
2310         struct vmcb *nested_vmcb;
2311         struct vmcb *hsave = svm->nested.hsave;
2312         struct vmcb *vmcb = svm->vmcb;
2313         struct page *page;
2314
2315         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2316                                        vmcb->control.exit_info_1,
2317                                        vmcb->control.exit_info_2,
2318                                        vmcb->control.exit_int_info,
2319                                        vmcb->control.exit_int_info_err,
2320                                        KVM_ISA_SVM);
2321
2322         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2323         if (!nested_vmcb)
2324                 return 1;
2325
2326         /* Exit Guest-Mode */
2327         leave_guest_mode(&svm->vcpu);
2328         svm->nested.vmcb = 0;
2329
2330         /* Give the current vmcb to the guest */
2331         disable_gif(svm);
2332
2333         nested_vmcb->save.es     = vmcb->save.es;
2334         nested_vmcb->save.cs     = vmcb->save.cs;
2335         nested_vmcb->save.ss     = vmcb->save.ss;
2336         nested_vmcb->save.ds     = vmcb->save.ds;
2337         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2338         nested_vmcb->save.idtr   = vmcb->save.idtr;
2339         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2340         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2341         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2342         nested_vmcb->save.cr2    = vmcb->save.cr2;
2343         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2344         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2345         nested_vmcb->save.rip    = vmcb->save.rip;
2346         nested_vmcb->save.rsp    = vmcb->save.rsp;
2347         nested_vmcb->save.rax    = vmcb->save.rax;
2348         nested_vmcb->save.dr7    = vmcb->save.dr7;
2349         nested_vmcb->save.dr6    = vmcb->save.dr6;
2350         nested_vmcb->save.cpl    = vmcb->save.cpl;
2351
2352         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2353         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2354         nested_vmcb->control.int_state         = vmcb->control.int_state;
2355         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2356         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2357         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2358         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2359         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2360         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2361         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
2362
2363         /*
2364          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2365          * to make sure that we do not lose injected events. So check event_inj
2366          * here and copy it to exit_int_info if it is valid.
2367          * Exit_int_info and event_inj can't be both valid because the case
2368          * below only happens on a VMRUN instruction intercept which has
2369          * no valid exit_int_info set.
2370          */
2371         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2372                 struct vmcb_control_area *nc = &nested_vmcb->control;
2373
2374                 nc->exit_int_info     = vmcb->control.event_inj;
2375                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2376         }
2377
2378         nested_vmcb->control.tlb_ctl           = 0;
2379         nested_vmcb->control.event_inj         = 0;
2380         nested_vmcb->control.event_inj_err     = 0;
2381
2382         /* We always set V_INTR_MASKING and remember the old value in hflags */
2383         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2384                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2385
2386         /* Restore the original control entries */
2387         copy_vmcb_control_area(vmcb, hsave);
2388
2389         kvm_clear_exception_queue(&svm->vcpu);
2390         kvm_clear_interrupt_queue(&svm->vcpu);
2391
2392         svm->nested.nested_cr3 = 0;
2393
2394         /* Restore selected save entries */
2395         svm->vmcb->save.es = hsave->save.es;
2396         svm->vmcb->save.cs = hsave->save.cs;
2397         svm->vmcb->save.ss = hsave->save.ss;
2398         svm->vmcb->save.ds = hsave->save.ds;
2399         svm->vmcb->save.gdtr = hsave->save.gdtr;
2400         svm->vmcb->save.idtr = hsave->save.idtr;
2401         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2402         svm_set_efer(&svm->vcpu, hsave->save.efer);
2403         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2404         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2405         if (npt_enabled) {
2406                 svm->vmcb->save.cr3 = hsave->save.cr3;
2407                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2408         } else {
2409                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2410         }
2411         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2412         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2413         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2414         svm->vmcb->save.dr7 = 0;
2415         svm->vmcb->save.cpl = 0;
2416         svm->vmcb->control.exit_int_info = 0;
2417
2418         mark_all_dirty(svm->vmcb);
2419
2420         nested_svm_unmap(page);
2421
2422         nested_svm_uninit_mmu_context(&svm->vcpu);
2423         kvm_mmu_reset_context(&svm->vcpu);
2424         kvm_mmu_load(&svm->vcpu);
2425
2426         return 0;
2427 }
2428
2429 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2430 {
2431         /*
2432          * This function merges the msr permission bitmaps of kvm and the
2433          * nested vmcb. It is optimized in that it only merges the parts where
2434          * the kvm msr permission bitmap may contain zero bits
2435          */
2436         int i;
2437
2438         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2439                 return true;
2440
2441         for (i = 0; i < MSRPM_OFFSETS; i++) {
2442                 u32 value, p;
2443                 u64 offset;
2444
2445                 if (msrpm_offsets[i] == 0xffffffff)
2446                         break;
2447
2448                 p      = msrpm_offsets[i];
2449                 offset = svm->nested.vmcb_msrpm + (p * 4);
2450
2451                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2452                         return false;
2453
2454                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2455         }
2456
2457         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2458
2459         return true;
2460 }
2461
2462 static bool nested_vmcb_checks(struct vmcb *vmcb)
2463 {
2464         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2465                 return false;
2466
2467         if (vmcb->control.asid == 0)
2468                 return false;
2469
2470         if (vmcb->control.nested_ctl && !npt_enabled)
2471                 return false;
2472
2473         return true;
2474 }
2475
2476 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2477 {
2478         struct vmcb *nested_vmcb;
2479         struct vmcb *hsave = svm->nested.hsave;
2480         struct vmcb *vmcb = svm->vmcb;
2481         struct page *page;
2482         u64 vmcb_gpa;
2483
2484         vmcb_gpa = svm->vmcb->save.rax;
2485
2486         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2487         if (!nested_vmcb)
2488                 return false;
2489
2490         if (!nested_vmcb_checks(nested_vmcb)) {
2491                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2492                 nested_vmcb->control.exit_code_hi = 0;
2493                 nested_vmcb->control.exit_info_1  = 0;
2494                 nested_vmcb->control.exit_info_2  = 0;
2495
2496                 nested_svm_unmap(page);
2497
2498                 return false;
2499         }
2500
2501         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2502                                nested_vmcb->save.rip,
2503                                nested_vmcb->control.int_ctl,
2504                                nested_vmcb->control.event_inj,
2505                                nested_vmcb->control.nested_ctl);
2506
2507         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2508                                     nested_vmcb->control.intercept_cr >> 16,
2509                                     nested_vmcb->control.intercept_exceptions,
2510                                     nested_vmcb->control.intercept);
2511
2512         /* Clear internal status */
2513         kvm_clear_exception_queue(&svm->vcpu);
2514         kvm_clear_interrupt_queue(&svm->vcpu);
2515
2516         /*
2517          * Save the old vmcb, so we don't need to pick what we save, but can
2518          * restore everything when a VMEXIT occurs
2519          */
2520         hsave->save.es     = vmcb->save.es;
2521         hsave->save.cs     = vmcb->save.cs;
2522         hsave->save.ss     = vmcb->save.ss;
2523         hsave->save.ds     = vmcb->save.ds;
2524         hsave->save.gdtr   = vmcb->save.gdtr;
2525         hsave->save.idtr   = vmcb->save.idtr;
2526         hsave->save.efer   = svm->vcpu.arch.efer;
2527         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2528         hsave->save.cr4    = svm->vcpu.arch.cr4;
2529         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2530         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2531         hsave->save.rsp    = vmcb->save.rsp;
2532         hsave->save.rax    = vmcb->save.rax;
2533         if (npt_enabled)
2534                 hsave->save.cr3    = vmcb->save.cr3;
2535         else
2536                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2537
2538         copy_vmcb_control_area(hsave, vmcb);
2539
2540         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2541                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2542         else
2543                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2544
2545         if (nested_vmcb->control.nested_ctl) {
2546                 kvm_mmu_unload(&svm->vcpu);
2547                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2548                 nested_svm_init_mmu_context(&svm->vcpu);
2549         }
2550
2551         /* Load the nested guest state */
2552         svm->vmcb->save.es = nested_vmcb->save.es;
2553         svm->vmcb->save.cs = nested_vmcb->save.cs;
2554         svm->vmcb->save.ss = nested_vmcb->save.ss;
2555         svm->vmcb->save.ds = nested_vmcb->save.ds;
2556         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2557         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2558         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2559         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2560         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2561         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2562         if (npt_enabled) {
2563                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2564                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2565         } else
2566                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2567
2568         /* Guest paging mode is active - reset mmu */
2569         kvm_mmu_reset_context(&svm->vcpu);
2570
2571         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2572         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2573         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2574         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2575
2576         /* In case we don't even reach vcpu_run, the fields are not updated */
2577         svm->vmcb->save.rax = nested_vmcb->save.rax;
2578         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2579         svm->vmcb->save.rip = nested_vmcb->save.rip;
2580         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2581         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2582         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2583
2584         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2585         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2586
2587         /* cache intercepts */
2588         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2589         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2590         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2591         svm->nested.intercept            = nested_vmcb->control.intercept;
2592
2593         svm_flush_tlb(&svm->vcpu);
2594         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2595         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2596                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2597         else
2598                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2599
2600         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2601                 /* We only want the cr8 intercept bits of the guest */
2602                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2603                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2604         }
2605
2606         /* We don't want to see VMMCALLs from a nested guest */
2607         clr_intercept(svm, INTERCEPT_VMMCALL);
2608
2609         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2610         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2611         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2612         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2613         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2614         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2615
2616         nested_svm_unmap(page);
2617
2618         /* Enter Guest-Mode */
2619         enter_guest_mode(&svm->vcpu);
2620
2621         /*
2622          * Merge guest and host intercepts - must be called  with vcpu in
2623          * guest-mode to take affect here
2624          */
2625         recalc_intercepts(svm);
2626
2627         svm->nested.vmcb = vmcb_gpa;
2628
2629         enable_gif(svm);
2630
2631         mark_all_dirty(svm->vmcb);
2632
2633         return true;
2634 }
2635
2636 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2637 {
2638         to_vmcb->save.fs = from_vmcb->save.fs;
2639         to_vmcb->save.gs = from_vmcb->save.gs;
2640         to_vmcb->save.tr = from_vmcb->save.tr;
2641         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2642         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2643         to_vmcb->save.star = from_vmcb->save.star;
2644         to_vmcb->save.lstar = from_vmcb->save.lstar;
2645         to_vmcb->save.cstar = from_vmcb->save.cstar;
2646         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2647         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2648         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2649         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2650 }
2651
2652 static int vmload_interception(struct vcpu_svm *svm)
2653 {
2654         struct vmcb *nested_vmcb;
2655         struct page *page;
2656
2657         if (nested_svm_check_permissions(svm))
2658                 return 1;
2659
2660         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2661         if (!nested_vmcb)
2662                 return 1;
2663
2664         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2665         skip_emulated_instruction(&svm->vcpu);
2666
2667         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2668         nested_svm_unmap(page);
2669
2670         return 1;
2671 }
2672
2673 static int vmsave_interception(struct vcpu_svm *svm)
2674 {
2675         struct vmcb *nested_vmcb;
2676         struct page *page;
2677
2678         if (nested_svm_check_permissions(svm))
2679                 return 1;
2680
2681         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2682         if (!nested_vmcb)
2683                 return 1;
2684
2685         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2686         skip_emulated_instruction(&svm->vcpu);
2687
2688         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2689         nested_svm_unmap(page);
2690
2691         return 1;
2692 }
2693
2694 static int vmrun_interception(struct vcpu_svm *svm)
2695 {
2696         if (nested_svm_check_permissions(svm))
2697                 return 1;
2698
2699         /* Save rip after vmrun instruction */
2700         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2701
2702         if (!nested_svm_vmrun(svm))
2703                 return 1;
2704
2705         if (!nested_svm_vmrun_msrpm(svm))
2706                 goto failed;
2707
2708         return 1;
2709
2710 failed:
2711
2712         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2713         svm->vmcb->control.exit_code_hi = 0;
2714         svm->vmcb->control.exit_info_1  = 0;
2715         svm->vmcb->control.exit_info_2  = 0;
2716
2717         nested_svm_vmexit(svm);
2718
2719         return 1;
2720 }
2721
2722 static int stgi_interception(struct vcpu_svm *svm)
2723 {
2724         if (nested_svm_check_permissions(svm))
2725                 return 1;
2726
2727         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2728         skip_emulated_instruction(&svm->vcpu);
2729         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2730
2731         enable_gif(svm);
2732
2733         return 1;
2734 }
2735
2736 static int clgi_interception(struct vcpu_svm *svm)
2737 {
2738         if (nested_svm_check_permissions(svm))
2739                 return 1;
2740
2741         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2742         skip_emulated_instruction(&svm->vcpu);
2743
2744         disable_gif(svm);
2745
2746         /* After a CLGI no interrupts should come */
2747         svm_clear_vintr(svm);
2748         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2749
2750         mark_dirty(svm->vmcb, VMCB_INTR);
2751
2752         return 1;
2753 }
2754
2755 static int invlpga_interception(struct vcpu_svm *svm)
2756 {
2757         struct kvm_vcpu *vcpu = &svm->vcpu;
2758
2759         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
2760                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2761
2762         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2763         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2764
2765         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2766         skip_emulated_instruction(&svm->vcpu);
2767         return 1;
2768 }
2769
2770 static int skinit_interception(struct vcpu_svm *svm)
2771 {
2772         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2773
2774         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2775         return 1;
2776 }
2777
2778 static int wbinvd_interception(struct vcpu_svm *svm)
2779 {
2780         kvm_emulate_wbinvd(&svm->vcpu);
2781         return 1;
2782 }
2783
2784 static int xsetbv_interception(struct vcpu_svm *svm)
2785 {
2786         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2787         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2788
2789         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2790                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2791                 skip_emulated_instruction(&svm->vcpu);
2792         }
2793
2794         return 1;
2795 }
2796
2797 static int task_switch_interception(struct vcpu_svm *svm)
2798 {
2799         u16 tss_selector;
2800         int reason;
2801         int int_type = svm->vmcb->control.exit_int_info &
2802                 SVM_EXITINTINFO_TYPE_MASK;
2803         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2804         uint32_t type =
2805                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2806         uint32_t idt_v =
2807                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2808         bool has_error_code = false;
2809         u32 error_code = 0;
2810
2811         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2812
2813         if (svm->vmcb->control.exit_info_2 &
2814             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2815                 reason = TASK_SWITCH_IRET;
2816         else if (svm->vmcb->control.exit_info_2 &
2817                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2818                 reason = TASK_SWITCH_JMP;
2819         else if (idt_v)
2820                 reason = TASK_SWITCH_GATE;
2821         else
2822                 reason = TASK_SWITCH_CALL;
2823
2824         if (reason == TASK_SWITCH_GATE) {
2825                 switch (type) {
2826                 case SVM_EXITINTINFO_TYPE_NMI:
2827                         svm->vcpu.arch.nmi_injected = false;
2828                         break;
2829                 case SVM_EXITINTINFO_TYPE_EXEPT:
2830                         if (svm->vmcb->control.exit_info_2 &
2831                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2832                                 has_error_code = true;
2833                                 error_code =
2834                                         (u32)svm->vmcb->control.exit_info_2;
2835                         }
2836                         kvm_clear_exception_queue(&svm->vcpu);
2837                         break;
2838                 case SVM_EXITINTINFO_TYPE_INTR:
2839                         kvm_clear_interrupt_queue(&svm->vcpu);
2840                         break;
2841                 default:
2842                         break;
2843                 }
2844         }
2845
2846         if (reason != TASK_SWITCH_GATE ||
2847             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2848             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2849              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2850                 skip_emulated_instruction(&svm->vcpu);
2851
2852         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2853                 int_vec = -1;
2854
2855         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2856                                 has_error_code, error_code) == EMULATE_FAIL) {
2857                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2858                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2859                 svm->vcpu.run->internal.ndata = 0;
2860                 return 0;
2861         }
2862         return 1;
2863 }
2864
2865 static int cpuid_interception(struct vcpu_svm *svm)
2866 {
2867         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2868         kvm_emulate_cpuid(&svm->vcpu);
2869         return 1;
2870 }
2871
2872 static int iret_interception(struct vcpu_svm *svm)
2873 {
2874         ++svm->vcpu.stat.nmi_window_exits;
2875         clr_intercept(svm, INTERCEPT_IRET);
2876         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2877         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2878         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2879         return 1;
2880 }
2881
2882 static int invlpg_interception(struct vcpu_svm *svm)
2883 {
2884         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2885                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2886
2887         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2888         skip_emulated_instruction(&svm->vcpu);
2889         return 1;
2890 }
2891
2892 static int emulate_on_interception(struct vcpu_svm *svm)
2893 {
2894         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2895 }
2896
2897 static int rdpmc_interception(struct vcpu_svm *svm)
2898 {
2899         int err;
2900
2901         if (!static_cpu_has(X86_FEATURE_NRIPS))
2902                 return emulate_on_interception(svm);
2903
2904         err = kvm_rdpmc(&svm->vcpu);
2905         kvm_complete_insn_gp(&svm->vcpu, err);
2906
2907         return 1;
2908 }
2909
2910 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2911                                             unsigned long val)
2912 {
2913         unsigned long cr0 = svm->vcpu.arch.cr0;
2914         bool ret = false;
2915         u64 intercept;
2916
2917         intercept = svm->nested.intercept;
2918
2919         if (!is_guest_mode(&svm->vcpu) ||
2920             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2921                 return false;
2922
2923         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2924         val &= ~SVM_CR0_SELECTIVE_MASK;
2925
2926         if (cr0 ^ val) {
2927                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2928                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2929         }
2930
2931         return ret;
2932 }
2933
2934 #define CR_VALID (1ULL << 63)
2935
2936 static int cr_interception(struct vcpu_svm *svm)
2937 {
2938         int reg, cr;
2939         unsigned long val;
2940         int err;
2941
2942         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2943                 return emulate_on_interception(svm);
2944
2945         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2946                 return emulate_on_interception(svm);
2947
2948         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2949         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2950                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2951         else
2952                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2953
2954         err = 0;
2955         if (cr >= 16) { /* mov to cr */
2956                 cr -= 16;
2957                 val = kvm_register_read(&svm->vcpu, reg);
2958                 switch (cr) {
2959                 case 0:
2960                         if (!check_selective_cr0_intercepted(svm, val))
2961                                 err = kvm_set_cr0(&svm->vcpu, val);
2962                         else
2963                                 return 1;
2964
2965                         break;
2966                 case 3:
2967                         err = kvm_set_cr3(&svm->vcpu, val);
2968                         break;
2969                 case 4:
2970                         err = kvm_set_cr4(&svm->vcpu, val);
2971                         break;
2972                 case 8:
2973                         err = kvm_set_cr8(&svm->vcpu, val);
2974                         break;
2975                 default:
2976                         WARN(1, "unhandled write to CR%d", cr);
2977                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2978                         return 1;
2979                 }
2980         } else { /* mov from cr */
2981                 switch (cr) {
2982                 case 0:
2983                         val = kvm_read_cr0(&svm->vcpu);
2984                         break;
2985                 case 2:
2986                         val = svm->vcpu.arch.cr2;
2987                         break;
2988                 case 3:
2989                         val = kvm_read_cr3(&svm->vcpu);
2990                         break;
2991                 case 4:
2992                         val = kvm_read_cr4(&svm->vcpu);
2993                         break;
2994                 case 8:
2995                         val = kvm_get_cr8(&svm->vcpu);
2996                         break;
2997                 default:
2998                         WARN(1, "unhandled read from CR%d", cr);
2999                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3000                         return 1;
3001                 }
3002                 kvm_register_write(&svm->vcpu, reg, val);
3003         }
3004         kvm_complete_insn_gp(&svm->vcpu, err);
3005
3006         return 1;
3007 }
3008
3009 static int dr_interception(struct vcpu_svm *svm)
3010 {
3011         int reg, dr;
3012         unsigned long val;
3013
3014         if (svm->vcpu.guest_debug == 0) {
3015                 /*
3016                  * No more DR vmexits; force a reload of the debug registers
3017                  * and reenter on this instruction.  The next vmexit will
3018                  * retrieve the full state of the debug registers.
3019                  */
3020                 clr_dr_intercepts(svm);
3021                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3022                 return 1;
3023         }
3024
3025         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3026                 return emulate_on_interception(svm);
3027
3028         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3029         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3030
3031         if (dr >= 16) { /* mov to DRn */
3032                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3033                         return 1;
3034                 val = kvm_register_read(&svm->vcpu, reg);
3035                 kvm_set_dr(&svm->vcpu, dr - 16, val);
3036         } else {
3037                 if (!kvm_require_dr(&svm->vcpu, dr))
3038                         return 1;
3039                 kvm_get_dr(&svm->vcpu, dr, &val);
3040                 kvm_register_write(&svm->vcpu, reg, val);
3041         }
3042
3043         skip_emulated_instruction(&svm->vcpu);
3044
3045         return 1;
3046 }
3047
3048 static int cr8_write_interception(struct vcpu_svm *svm)
3049 {
3050         struct kvm_run *kvm_run = svm->vcpu.run;
3051         int r;
3052
3053         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3054         /* instruction emulation calls kvm_set_cr8() */
3055         r = cr_interception(svm);
3056         if (irqchip_in_kernel(svm->vcpu.kvm))
3057                 return r;
3058         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3059                 return r;
3060         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3061         return 0;
3062 }
3063
3064 static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3065 {
3066         struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3067         return vmcb->control.tsc_offset +
3068                 svm_scale_tsc(vcpu, host_tsc);
3069 }
3070
3071 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
3072 {
3073         struct vcpu_svm *svm = to_svm(vcpu);
3074
3075         switch (ecx) {
3076         case MSR_IA32_TSC: {
3077                 *data = svm->vmcb->control.tsc_offset +
3078                         svm_scale_tsc(vcpu, native_read_tsc());
3079
3080                 break;
3081         }
3082         case MSR_STAR:
3083                 *data = svm->vmcb->save.star;
3084                 break;
3085 #ifdef CONFIG_X86_64
3086         case MSR_LSTAR:
3087                 *data = svm->vmcb->save.lstar;
3088                 break;
3089         case MSR_CSTAR:
3090                 *data = svm->vmcb->save.cstar;
3091                 break;
3092         case MSR_KERNEL_GS_BASE:
3093                 *data = svm->vmcb->save.kernel_gs_base;
3094                 break;
3095         case MSR_SYSCALL_MASK:
3096                 *data = svm->vmcb->save.sfmask;
3097                 break;
3098 #endif
3099         case MSR_IA32_SYSENTER_CS:
3100                 *data = svm->vmcb->save.sysenter_cs;
3101                 break;
3102         case MSR_IA32_SYSENTER_EIP:
3103                 *data = svm->sysenter_eip;
3104                 break;
3105         case MSR_IA32_SYSENTER_ESP:
3106                 *data = svm->sysenter_esp;
3107                 break;
3108         /*
3109          * Nobody will change the following 5 values in the VMCB so we can
3110          * safely return them on rdmsr. They will always be 0 until LBRV is
3111          * implemented.
3112          */
3113         case MSR_IA32_DEBUGCTLMSR:
3114                 *data = svm->vmcb->save.dbgctl;
3115                 break;
3116         case MSR_IA32_LASTBRANCHFROMIP:
3117                 *data = svm->vmcb->save.br_from;
3118                 break;
3119         case MSR_IA32_LASTBRANCHTOIP:
3120                 *data = svm->vmcb->save.br_to;
3121                 break;
3122         case MSR_IA32_LASTINTFROMIP:
3123                 *data = svm->vmcb->save.last_excp_from;
3124                 break;
3125         case MSR_IA32_LASTINTTOIP:
3126                 *data = svm->vmcb->save.last_excp_to;
3127                 break;
3128         case MSR_VM_HSAVE_PA:
3129                 *data = svm->nested.hsave_msr;
3130                 break;
3131         case MSR_VM_CR:
3132                 *data = svm->nested.vm_cr_msr;
3133                 break;
3134         case MSR_IA32_UCODE_REV:
3135                 *data = 0x01000065;
3136                 break;
3137         default:
3138                 return kvm_get_msr_common(vcpu, ecx, data);
3139         }
3140         return 0;
3141 }
3142
3143 static int rdmsr_interception(struct vcpu_svm *svm)
3144 {
3145         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3146         u64 data;
3147
3148         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3149                 trace_kvm_msr_read_ex(ecx);
3150                 kvm_inject_gp(&svm->vcpu, 0);
3151         } else {
3152                 trace_kvm_msr_read(ecx, data);
3153
3154                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, data & 0xffffffff);
3155                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX, data >> 32);
3156                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3157                 skip_emulated_instruction(&svm->vcpu);
3158         }
3159         return 1;
3160 }
3161
3162 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3163 {
3164         struct vcpu_svm *svm = to_svm(vcpu);
3165         int svm_dis, chg_mask;
3166
3167         if (data & ~SVM_VM_CR_VALID_MASK)
3168                 return 1;
3169
3170         chg_mask = SVM_VM_CR_VALID_MASK;
3171
3172         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3173                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3174
3175         svm->nested.vm_cr_msr &= ~chg_mask;
3176         svm->nested.vm_cr_msr |= (data & chg_mask);
3177
3178         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3179
3180         /* check for svm_disable while efer.svme is set */
3181         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3182                 return 1;
3183
3184         return 0;
3185 }
3186
3187 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3188 {
3189         struct vcpu_svm *svm = to_svm(vcpu);
3190
3191         u32 ecx = msr->index;
3192         u64 data = msr->data;
3193         switch (ecx) {
3194         case MSR_IA32_TSC:
3195                 kvm_write_tsc(vcpu, msr);
3196                 break;
3197         case MSR_STAR:
3198                 svm->vmcb->save.star = data;
3199                 break;
3200 #ifdef CONFIG_X86_64
3201         case MSR_LSTAR:
3202                 svm->vmcb->save.lstar = data;
3203                 break;
3204         case MSR_CSTAR:
3205                 svm->vmcb->save.cstar = data;
3206                 break;
3207         case MSR_KERNEL_GS_BASE:
3208                 svm->vmcb->save.kernel_gs_base = data;
3209                 break;
3210         case MSR_SYSCALL_MASK:
3211                 svm->vmcb->save.sfmask = data;
3212                 break;
3213 #endif
3214         case MSR_IA32_SYSENTER_CS:
3215                 svm->vmcb->save.sysenter_cs = data;
3216                 break;
3217         case MSR_IA32_SYSENTER_EIP:
3218                 svm->sysenter_eip = data;
3219                 svm->vmcb->save.sysenter_eip = data;
3220                 break;
3221         case MSR_IA32_SYSENTER_ESP:
3222                 svm->sysenter_esp = data;
3223                 svm->vmcb->save.sysenter_esp = data;
3224                 break;
3225         case MSR_IA32_DEBUGCTLMSR:
3226                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3227                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3228                                     __func__, data);
3229                         break;
3230                 }
3231                 if (data & DEBUGCTL_RESERVED_BITS)
3232                         return 1;
3233
3234                 svm->vmcb->save.dbgctl = data;
3235                 mark_dirty(svm->vmcb, VMCB_LBR);
3236                 if (data & (1ULL<<0))
3237                         svm_enable_lbrv(svm);
3238                 else
3239                         svm_disable_lbrv(svm);
3240                 break;
3241         case MSR_VM_HSAVE_PA:
3242                 svm->nested.hsave_msr = data;
3243                 break;
3244         case MSR_VM_CR:
3245                 return svm_set_vm_cr(vcpu, data);
3246         case MSR_VM_IGNNE:
3247                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3248                 break;
3249         default:
3250                 return kvm_set_msr_common(vcpu, msr);
3251         }
3252         return 0;
3253 }
3254
3255 static int wrmsr_interception(struct vcpu_svm *svm)
3256 {
3257         struct msr_data msr;
3258         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3259         u64 data = kvm_read_edx_eax(&svm->vcpu);
3260
3261         msr.data = data;
3262         msr.index = ecx;
3263         msr.host_initiated = false;
3264
3265         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3266         if (kvm_set_msr(&svm->vcpu, &msr)) {
3267                 trace_kvm_msr_write_ex(ecx, data);
3268                 kvm_inject_gp(&svm->vcpu, 0);
3269         } else {
3270                 trace_kvm_msr_write(ecx, data);
3271                 skip_emulated_instruction(&svm->vcpu);
3272         }
3273         return 1;
3274 }
3275
3276 static int msr_interception(struct vcpu_svm *svm)
3277 {
3278         if (svm->vmcb->control.exit_info_1)
3279                 return wrmsr_interception(svm);
3280         else
3281                 return rdmsr_interception(svm);
3282 }
3283
3284 static int interrupt_window_interception(struct vcpu_svm *svm)
3285 {
3286         struct kvm_run *kvm_run = svm->vcpu.run;
3287
3288         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3289         svm_clear_vintr(svm);
3290         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3291         mark_dirty(svm->vmcb, VMCB_INTR);
3292         ++svm->vcpu.stat.irq_window_exits;
3293         /*
3294          * If the user space waits to inject interrupts, exit as soon as
3295          * possible
3296          */
3297         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3298             kvm_run->request_interrupt_window &&
3299             !kvm_cpu_has_interrupt(&svm->vcpu)) {
3300                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3301                 return 0;
3302         }
3303
3304         return 1;
3305 }
3306
3307 static int pause_interception(struct vcpu_svm *svm)
3308 {
3309         kvm_vcpu_on_spin(&(svm->vcpu));
3310         return 1;
3311 }
3312
3313 static int nop_interception(struct vcpu_svm *svm)
3314 {
3315         skip_emulated_instruction(&(svm->vcpu));
3316         return 1;
3317 }
3318
3319 static int monitor_interception(struct vcpu_svm *svm)
3320 {
3321         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3322         return nop_interception(svm);
3323 }
3324
3325 static int mwait_interception(struct vcpu_svm *svm)
3326 {
3327         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3328         return nop_interception(svm);
3329 }
3330
3331 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3332         [SVM_EXIT_READ_CR0]                     = cr_interception,
3333         [SVM_EXIT_READ_CR3]                     = cr_interception,
3334         [SVM_EXIT_READ_CR4]                     = cr_interception,
3335         [SVM_EXIT_READ_CR8]                     = cr_interception,
3336         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
3337         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3338         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3339         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3340         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3341         [SVM_EXIT_READ_DR0]                     = dr_interception,
3342         [SVM_EXIT_READ_DR1]                     = dr_interception,
3343         [SVM_EXIT_READ_DR2]                     = dr_interception,
3344         [SVM_EXIT_READ_DR3]                     = dr_interception,
3345         [SVM_EXIT_READ_DR4]                     = dr_interception,
3346         [SVM_EXIT_READ_DR5]                     = dr_interception,
3347         [SVM_EXIT_READ_DR6]                     = dr_interception,
3348         [SVM_EXIT_READ_DR7]                     = dr_interception,
3349         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3350         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3351         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3352         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3353         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3354         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3355         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3356         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3357         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3358         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3359         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3360         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3361         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
3362         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3363         [SVM_EXIT_INTR]                         = intr_interception,
3364         [SVM_EXIT_NMI]                          = nmi_interception,
3365         [SVM_EXIT_SMI]                          = nop_on_interception,
3366         [SVM_EXIT_INIT]                         = nop_on_interception,
3367         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3368         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
3369         [SVM_EXIT_CPUID]                        = cpuid_interception,
3370         [SVM_EXIT_IRET]                         = iret_interception,
3371         [SVM_EXIT_INVD]                         = emulate_on_interception,
3372         [SVM_EXIT_PAUSE]                        = pause_interception,
3373         [SVM_EXIT_HLT]                          = halt_interception,
3374         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3375         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3376         [SVM_EXIT_IOIO]                         = io_interception,
3377         [SVM_EXIT_MSR]                          = msr_interception,
3378         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3379         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3380         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3381         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3382         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3383         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3384         [SVM_EXIT_STGI]                         = stgi_interception,
3385         [SVM_EXIT_CLGI]                         = clgi_interception,
3386         [SVM_EXIT_SKINIT]                       = skinit_interception,
3387         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
3388         [SVM_EXIT_MONITOR]                      = monitor_interception,
3389         [SVM_EXIT_MWAIT]                        = mwait_interception,
3390         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3391         [SVM_EXIT_NPF]                          = pf_interception,
3392 };
3393
3394 static void dump_vmcb(struct kvm_vcpu *vcpu)
3395 {
3396         struct vcpu_svm *svm = to_svm(vcpu);
3397         struct vmcb_control_area *control = &svm->vmcb->control;
3398         struct vmcb_save_area *save = &svm->vmcb->save;
3399
3400         pr_err("VMCB Control Area:\n");
3401         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3402         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3403         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3404         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3405         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3406         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3407         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3408         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3409         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3410         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3411         pr_err("%-20s%d\n", "asid:", control->asid);
3412         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3413         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3414         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3415         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3416         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3417         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3418         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3419         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3420         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3421         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3422         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3423         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3424         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3425         pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3426         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3427         pr_err("VMCB State Save Area:\n");
3428         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3429                "es:",
3430                save->es.selector, save->es.attrib,
3431                save->es.limit, save->es.base);
3432         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3433                "cs:",
3434                save->cs.selector, save->cs.attrib,
3435                save->cs.limit, save->cs.base);
3436         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3437                "ss:",
3438                save->ss.selector, save->ss.attrib,
3439                save->ss.limit, save->ss.base);
3440         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3441                "ds:",
3442                save->ds.selector, save->ds.attrib,
3443                save->ds.limit, save->ds.base);
3444         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3445                "fs:",
3446                save->fs.selector, save->fs.attrib,
3447                save->fs.limit, save->fs.base);
3448         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3449                "gs:",
3450                save->gs.selector, save->gs.attrib,
3451                save->gs.limit, save->gs.base);
3452         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3453                "gdtr:",
3454                save->gdtr.selector, save->gdtr.attrib,
3455                save->gdtr.limit, save->gdtr.base);
3456         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3457                "ldtr:",
3458                save->ldtr.selector, save->ldtr.attrib,
3459                save->ldtr.limit, save->ldtr.base);
3460         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3461                "idtr:",
3462                save->idtr.selector, save->idtr.attrib,
3463                save->idtr.limit, save->idtr.base);
3464         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3465                "tr:",
3466                save->tr.selector, save->tr.attrib,
3467                save->tr.limit, save->tr.base);
3468         pr_err("cpl:            %d                efer:         %016llx\n",
3469                 save->cpl, save->efer);
3470         pr_err("%-15s %016llx %-13s %016llx\n",
3471                "cr0:", save->cr0, "cr2:", save->cr2);
3472         pr_err("%-15s %016llx %-13s %016llx\n",
3473                "cr3:", save->cr3, "cr4:", save->cr4);
3474         pr_err("%-15s %016llx %-13s %016llx\n",
3475                "dr6:", save->dr6, "dr7:", save->dr7);
3476         pr_err("%-15s %016llx %-13s %016llx\n",
3477                "rip:", save->rip, "rflags:", save->rflags);
3478         pr_err("%-15s %016llx %-13s %016llx\n",
3479                "rsp:", save->rsp, "rax:", save->rax);
3480         pr_err("%-15s %016llx %-13s %016llx\n",
3481                "star:", save->star, "lstar:", save->lstar);
3482         pr_err("%-15s %016llx %-13s %016llx\n",
3483                "cstar:", save->cstar, "sfmask:", save->sfmask);
3484         pr_err("%-15s %016llx %-13s %016llx\n",
3485                "kernel_gs_base:", save->kernel_gs_base,
3486                "sysenter_cs:", save->sysenter_cs);
3487         pr_err("%-15s %016llx %-13s %016llx\n",
3488                "sysenter_esp:", save->sysenter_esp,
3489                "sysenter_eip:", save->sysenter_eip);
3490         pr_err("%-15s %016llx %-13s %016llx\n",
3491                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3492         pr_err("%-15s %016llx %-13s %016llx\n",
3493                "br_from:", save->br_from, "br_to:", save->br_to);
3494         pr_err("%-15s %016llx %-13s %016llx\n",
3495                "excp_from:", save->last_excp_from,
3496                "excp_to:", save->last_excp_to);
3497 }
3498
3499 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3500 {
3501         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3502
3503         *info1 = control->exit_info_1;
3504         *info2 = control->exit_info_2;
3505 }
3506
3507 static int handle_exit(struct kvm_vcpu *vcpu)
3508 {
3509         struct vcpu_svm *svm = to_svm(vcpu);
3510         struct kvm_run *kvm_run = vcpu->run;
3511         u32 exit_code = svm->vmcb->control.exit_code;
3512
3513         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3514                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3515         if (npt_enabled)
3516                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3517
3518         if (unlikely(svm->nested.exit_required)) {
3519                 nested_svm_vmexit(svm);
3520                 svm->nested.exit_required = false;
3521
3522                 return 1;
3523         }
3524
3525         if (is_guest_mode(vcpu)) {
3526                 int vmexit;
3527
3528                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3529                                         svm->vmcb->control.exit_info_1,
3530                                         svm->vmcb->control.exit_info_2,
3531                                         svm->vmcb->control.exit_int_info,
3532                                         svm->vmcb->control.exit_int_info_err,
3533                                         KVM_ISA_SVM);
3534
3535                 vmexit = nested_svm_exit_special(svm);
3536
3537                 if (vmexit == NESTED_EXIT_CONTINUE)
3538                         vmexit = nested_svm_exit_handled(svm);
3539
3540                 if (vmexit == NESTED_EXIT_DONE)
3541                         return 1;
3542         }
3543
3544         svm_complete_interrupts(svm);
3545
3546         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3547                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3548                 kvm_run->fail_entry.hardware_entry_failure_reason
3549                         = svm->vmcb->control.exit_code;
3550                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3551                 dump_vmcb(vcpu);
3552                 return 0;
3553         }
3554
3555         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3556             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3557             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3558             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3559                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3560                        "exit_code 0x%x\n",
3561                        __func__, svm->vmcb->control.exit_int_info,
3562                        exit_code);
3563
3564         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3565             || !svm_exit_handlers[exit_code]) {
3566                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
3567                 kvm_queue_exception(vcpu, UD_VECTOR);
3568                 return 1;
3569         }
3570
3571         return svm_exit_handlers[exit_code](svm);
3572 }
3573
3574 static void reload_tss(struct kvm_vcpu *vcpu)
3575 {
3576         int cpu = raw_smp_processor_id();
3577
3578         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3579         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3580         load_TR_desc();
3581 }
3582
3583 static void pre_svm_run(struct vcpu_svm *svm)
3584 {
3585         int cpu = raw_smp_processor_id();
3586
3587         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3588
3589         /* FIXME: handle wraparound of asid_generation */
3590         if (svm->asid_generation != sd->asid_generation)
3591                 new_asid(svm, sd);
3592 }
3593
3594 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3595 {
3596         struct vcpu_svm *svm = to_svm(vcpu);
3597
3598         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3599         vcpu->arch.hflags |= HF_NMI_MASK;
3600         set_intercept(svm, INTERCEPT_IRET);
3601         ++vcpu->stat.nmi_injections;
3602 }
3603
3604 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3605 {
3606         struct vmcb_control_area *control;
3607
3608         control = &svm->vmcb->control;
3609         control->int_vector = irq;
3610         control->int_ctl &= ~V_INTR_PRIO_MASK;
3611         control->int_ctl |= V_IRQ_MASK |
3612                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3613         mark_dirty(svm->vmcb, VMCB_INTR);
3614 }
3615
3616 static void svm_set_irq(struct kvm_vcpu *vcpu)
3617 {
3618         struct vcpu_svm *svm = to_svm(vcpu);
3619
3620         BUG_ON(!(gif_set(svm)));
3621
3622         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3623         ++vcpu->stat.irq_injections;
3624
3625         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3626                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3627 }
3628
3629 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3630 {
3631         struct vcpu_svm *svm = to_svm(vcpu);
3632
3633         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3634                 return;
3635
3636         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3637
3638         if (irr == -1)
3639                 return;
3640
3641         if (tpr >= irr)
3642                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3643 }
3644
3645 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3646 {
3647         return;
3648 }
3649
3650 static int svm_vm_has_apicv(struct kvm *kvm)
3651 {
3652         return 0;
3653 }
3654
3655 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3656 {
3657         return;
3658 }
3659
3660 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3661 {
3662         return;
3663 }
3664
3665 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3666 {
3667         struct vcpu_svm *svm = to_svm(vcpu);
3668         struct vmcb *vmcb = svm->vmcb;
3669         int ret;
3670         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3671               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3672         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3673
3674         return ret;
3675 }
3676
3677 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3678 {
3679         struct vcpu_svm *svm = to_svm(vcpu);
3680
3681         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3682 }
3683
3684 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3685 {
3686         struct vcpu_svm *svm = to_svm(vcpu);
3687
3688         if (masked) {
3689                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3690                 set_intercept(svm, INTERCEPT_IRET);
3691         } else {
3692                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3693                 clr_intercept(svm, INTERCEPT_IRET);
3694         }
3695 }
3696
3697 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3698 {
3699         struct vcpu_svm *svm = to_svm(vcpu);
3700         struct vmcb *vmcb = svm->vmcb;
3701         int ret;
3702
3703         if (!gif_set(svm) ||
3704              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3705                 return 0;
3706
3707         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3708
3709         if (is_guest_mode(vcpu))
3710                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3711
3712         return ret;
3713 }
3714
3715 static void enable_irq_window(struct kvm_vcpu *vcpu)
3716 {
3717         struct vcpu_svm *svm = to_svm(vcpu);
3718
3719         /*
3720          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3721          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3722          * get that intercept, this function will be called again though and
3723          * we'll get the vintr intercept.
3724          */
3725         if (gif_set(svm) && nested_svm_intr(svm)) {
3726                 svm_set_vintr(svm);
3727                 svm_inject_irq(svm, 0x0);
3728         }
3729 }
3730
3731 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3732 {
3733         struct vcpu_svm *svm = to_svm(vcpu);
3734
3735         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3736             == HF_NMI_MASK)
3737                 return; /* IRET will cause a vm exit */
3738
3739         /*
3740          * Something prevents NMI from been injected. Single step over possible
3741          * problem (IRET or exception injection or interrupt shadow)
3742          */
3743         svm->nmi_singlestep = true;
3744         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3745         update_db_bp_intercept(vcpu);
3746 }
3747
3748 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3749 {
3750         return 0;
3751 }
3752
3753 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3754 {
3755         struct vcpu_svm *svm = to_svm(vcpu);
3756
3757         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3758                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3759         else
3760                 svm->asid_generation--;
3761 }
3762
3763 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3764 {
3765 }
3766
3767 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3768 {
3769         struct vcpu_svm *svm = to_svm(vcpu);
3770
3771         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3772                 return;
3773
3774         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3775                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3776                 kvm_set_cr8(vcpu, cr8);
3777         }
3778 }
3779
3780 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3781 {
3782         struct vcpu_svm *svm = to_svm(vcpu);
3783         u64 cr8;
3784
3785         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3786                 return;
3787
3788         cr8 = kvm_get_cr8(vcpu);
3789         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3790         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3791 }
3792
3793 static void svm_complete_interrupts(struct vcpu_svm *svm)
3794 {
3795         u8 vector;
3796         int type;
3797         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3798         unsigned int3_injected = svm->int3_injected;
3799
3800         svm->int3_injected = 0;
3801
3802         /*
3803          * If we've made progress since setting HF_IRET_MASK, we've
3804          * executed an IRET and can allow NMI injection.
3805          */
3806         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3807             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3808                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3809                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3810         }
3811
3812         svm->vcpu.arch.nmi_injected = false;
3813         kvm_clear_exception_queue(&svm->vcpu);
3814         kvm_clear_interrupt_queue(&svm->vcpu);
3815
3816         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3817                 return;
3818
3819         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3820
3821         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3822         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3823
3824         switch (type) {
3825         case SVM_EXITINTINFO_TYPE_NMI:
3826                 svm->vcpu.arch.nmi_injected = true;
3827                 break;
3828         case SVM_EXITINTINFO_TYPE_EXEPT:
3829                 /*
3830                  * In case of software exceptions, do not reinject the vector,
3831                  * but re-execute the instruction instead. Rewind RIP first
3832                  * if we emulated INT3 before.
3833                  */
3834                 if (kvm_exception_is_soft(vector)) {
3835                         if (vector == BP_VECTOR && int3_injected &&
3836                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3837                                 kvm_rip_write(&svm->vcpu,
3838                                               kvm_rip_read(&svm->vcpu) -
3839                                               int3_injected);
3840                         break;
3841                 }
3842                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3843                         u32 err = svm->vmcb->control.exit_int_info_err;
3844                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3845
3846                 } else
3847                         kvm_requeue_exception(&svm->vcpu, vector);
3848                 break;
3849         case SVM_EXITINTINFO_TYPE_INTR:
3850                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3851                 break;
3852         default:
3853                 break;
3854         }
3855 }
3856
3857 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3858 {
3859         struct vcpu_svm *svm = to_svm(vcpu);
3860         struct vmcb_control_area *control = &svm->vmcb->control;
3861
3862         control->exit_int_info = control->event_inj;
3863         control->exit_int_info_err = control->event_inj_err;
3864         control->event_inj = 0;
3865         svm_complete_interrupts(svm);
3866 }
3867
3868 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3869 {
3870         struct vcpu_svm *svm = to_svm(vcpu);
3871
3872         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3873         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3874         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3875
3876         /*
3877          * A vmexit emulation is required before the vcpu can be executed
3878          * again.
3879          */
3880         if (unlikely(svm->nested.exit_required))
3881                 return;
3882
3883         pre_svm_run(svm);
3884
3885         sync_lapic_to_cr8(vcpu);
3886
3887         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3888
3889         clgi();
3890
3891         local_irq_enable();
3892
3893         asm volatile (
3894                 "push %%" _ASM_BP "; \n\t"
3895                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
3896                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
3897                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
3898                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
3899                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
3900                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
3901 #ifdef CONFIG_X86_64
3902                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3903                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3904                 "mov %c[r10](%[svm]), %%r10 \n\t"
3905                 "mov %c[r11](%[svm]), %%r11 \n\t"
3906                 "mov %c[r12](%[svm]), %%r12 \n\t"
3907                 "mov %c[r13](%[svm]), %%r13 \n\t"
3908                 "mov %c[r14](%[svm]), %%r14 \n\t"
3909                 "mov %c[r15](%[svm]), %%r15 \n\t"
3910 #endif
3911
3912                 /* Enter guest mode */
3913                 "push %%" _ASM_AX " \n\t"
3914                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
3915                 __ex(SVM_VMLOAD) "\n\t"
3916                 __ex(SVM_VMRUN) "\n\t"
3917                 __ex(SVM_VMSAVE) "\n\t"
3918                 "pop %%" _ASM_AX " \n\t"
3919
3920                 /* Save guest registers, load host registers */
3921                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
3922                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
3923                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
3924                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
3925                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
3926                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
3927 #ifdef CONFIG_X86_64
3928                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3929                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3930                 "mov %%r10, %c[r10](%[svm]) \n\t"
3931                 "mov %%r11, %c[r11](%[svm]) \n\t"
3932                 "mov %%r12, %c[r12](%[svm]) \n\t"
3933                 "mov %%r13, %c[r13](%[svm]) \n\t"
3934                 "mov %%r14, %c[r14](%[svm]) \n\t"
3935                 "mov %%r15, %c[r15](%[svm]) \n\t"
3936 #endif
3937                 "pop %%" _ASM_BP
3938                 :
3939                 : [svm]"a"(svm),
3940                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3941                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3942                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3943                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3944                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3945                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3946                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3947 #ifdef CONFIG_X86_64
3948                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3949                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3950                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3951                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3952                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3953                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3954                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3955                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3956 #endif
3957                 : "cc", "memory"
3958 #ifdef CONFIG_X86_64
3959                 , "rbx", "rcx", "rdx", "rsi", "rdi"
3960                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3961 #else
3962                 , "ebx", "ecx", "edx", "esi", "edi"
3963 #endif
3964                 );
3965
3966 #ifdef CONFIG_X86_64
3967         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3968 #else
3969         loadsegment(fs, svm->host.fs);
3970 #ifndef CONFIG_X86_32_LAZY_GS
3971         loadsegment(gs, svm->host.gs);
3972 #endif
3973 #endif
3974
3975         reload_tss(vcpu);
3976
3977         local_irq_disable();
3978
3979         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3980         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3981         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3982         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3983
3984         trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3985
3986         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3987                 kvm_before_handle_nmi(&svm->vcpu);
3988
3989         stgi();
3990
3991         /* Any pending NMI will happen here */
3992
3993         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3994                 kvm_after_handle_nmi(&svm->vcpu);
3995
3996         sync_cr8_to_lapic(vcpu);
3997
3998         svm->next_rip = 0;
3999
4000         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4001
4002         /* if exit due to PF check for async PF */
4003         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4004                 svm->apf_reason = kvm_read_and_reset_pf_reason();
4005
4006         if (npt_enabled) {
4007                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4008                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4009         }
4010
4011         /*
4012          * We need to handle MC intercepts here before the vcpu has a chance to
4013          * change the physical cpu
4014          */
4015         if (unlikely(svm->vmcb->control.exit_code ==
4016                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
4017                 svm_handle_mce(svm);
4018
4019         mark_all_clean(svm->vmcb);
4020 }
4021
4022 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4023 {
4024         struct vcpu_svm *svm = to_svm(vcpu);
4025
4026         svm->vmcb->save.cr3 = root;
4027         mark_dirty(svm->vmcb, VMCB_CR);
4028         svm_flush_tlb(vcpu);
4029 }
4030
4031 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4032 {
4033         struct vcpu_svm *svm = to_svm(vcpu);
4034
4035         svm->vmcb->control.nested_cr3 = root;
4036         mark_dirty(svm->vmcb, VMCB_NPT);
4037
4038         /* Also sync guest cr3 here in case we live migrate */
4039         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4040         mark_dirty(svm->vmcb, VMCB_CR);
4041
4042         svm_flush_tlb(vcpu);
4043 }
4044
4045 static int is_disabled(void)
4046 {
4047         u64 vm_cr;
4048
4049         rdmsrl(MSR_VM_CR, vm_cr);
4050         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4051                 return 1;
4052
4053         return 0;
4054 }
4055
4056 static void
4057 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4058 {
4059         /*
4060          * Patch in the VMMCALL instruction:
4061          */
4062         hypercall[0] = 0x0f;
4063         hypercall[1] = 0x01;
4064         hypercall[2] = 0xd9;
4065 }
4066
4067 static void svm_check_processor_compat(void *rtn)
4068 {
4069         *(int *)rtn = 0;
4070 }
4071
4072 static bool svm_cpu_has_accelerated_tpr(void)
4073 {
4074         return false;
4075 }
4076
4077 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4078 {
4079         return 0;
4080 }
4081
4082 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4083 {
4084 }
4085
4086 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4087 {
4088         switch (func) {
4089         case 0x80000001:
4090                 if (nested)
4091                         entry->ecx |= (1 << 2); /* Set SVM bit */
4092                 break;
4093         case 0x8000000A:
4094                 entry->eax = 1; /* SVM revision 1 */
4095                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4096                                    ASID emulation to nested SVM */
4097                 entry->ecx = 0; /* Reserved */
4098                 entry->edx = 0; /* Per default do not support any
4099                                    additional features */
4100
4101                 /* Support next_rip if host supports it */
4102                 if (boot_cpu_has(X86_FEATURE_NRIPS))
4103                         entry->edx |= SVM_FEATURE_NRIP;
4104
4105                 /* Support NPT for the guest if enabled */
4106                 if (npt_enabled)
4107                         entry->edx |= SVM_FEATURE_NPT;
4108
4109                 break;
4110         }
4111 }
4112
4113 static int svm_get_lpage_level(void)
4114 {
4115         return PT_PDPE_LEVEL;
4116 }
4117
4118 static bool svm_rdtscp_supported(void)
4119 {
4120         return false;
4121 }
4122
4123 static bool svm_invpcid_supported(void)
4124 {
4125         return false;
4126 }
4127
4128 static bool svm_mpx_supported(void)
4129 {
4130         return false;
4131 }
4132
4133 static bool svm_xsaves_supported(void)
4134 {
4135         return false;
4136 }
4137
4138 static bool svm_has_wbinvd_exit(void)
4139 {
4140         return true;
4141 }
4142
4143 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4144 {
4145         struct vcpu_svm *svm = to_svm(vcpu);
4146
4147         set_exception_intercept(svm, NM_VECTOR);
4148         update_cr0_intercept(svm);
4149 }
4150
4151 #define PRE_EX(exit)  { .exit_code = (exit), \
4152                         .stage = X86_ICPT_PRE_EXCEPT, }
4153 #define POST_EX(exit) { .exit_code = (exit), \
4154                         .stage = X86_ICPT_POST_EXCEPT, }
4155 #define POST_MEM(exit) { .exit_code = (exit), \
4156                         .stage = X86_ICPT_POST_MEMACCESS, }
4157
4158 static const struct __x86_intercept {
4159         u32 exit_code;
4160         enum x86_intercept_stage stage;
4161 } x86_intercept_map[] = {
4162         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
4163         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
4164         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
4165         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
4166         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
4167         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
4168         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
4169         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
4170         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
4171         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
4172         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
4173         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
4174         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
4175         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
4176         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
4177         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
4178         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
4179         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4180         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4181         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4182         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4183         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4184         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4185         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4186         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4187         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4188         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4189         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4190         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4191         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4192         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4193         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4194         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4195         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4196         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4197         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4198         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4199         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4200         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4201         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4202         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4203         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4204         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4205         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4206         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4207         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4208 };
4209
4210 #undef PRE_EX
4211 #undef POST_EX
4212 #undef POST_MEM
4213
4214 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4215                                struct x86_instruction_info *info,
4216                                enum x86_intercept_stage stage)
4217 {
4218         struct vcpu_svm *svm = to_svm(vcpu);
4219         int vmexit, ret = X86EMUL_CONTINUE;
4220         struct __x86_intercept icpt_info;
4221         struct vmcb *vmcb = svm->vmcb;
4222
4223         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4224                 goto out;
4225
4226         icpt_info = x86_intercept_map[info->intercept];
4227
4228         if (stage != icpt_info.stage)
4229                 goto out;
4230
4231         switch (icpt_info.exit_code) {
4232         case SVM_EXIT_READ_CR0:
4233                 if (info->intercept == x86_intercept_cr_read)
4234                         icpt_info.exit_code += info->modrm_reg;
4235                 break;
4236         case SVM_EXIT_WRITE_CR0: {
4237                 unsigned long cr0, val;
4238                 u64 intercept;
4239
4240                 if (info->intercept == x86_intercept_cr_write)
4241                         icpt_info.exit_code += info->modrm_reg;
4242
4243                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4244                     info->intercept == x86_intercept_clts)
4245                         break;
4246
4247                 intercept = svm->nested.intercept;
4248
4249                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4250                         break;
4251
4252                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4253                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4254
4255                 if (info->intercept == x86_intercept_lmsw) {
4256                         cr0 &= 0xfUL;
4257                         val &= 0xfUL;
4258                         /* lmsw can't clear PE - catch this here */
4259                         if (cr0 & X86_CR0_PE)
4260                                 val |= X86_CR0_PE;
4261                 }
4262
4263                 if (cr0 ^ val)
4264                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4265
4266                 break;
4267         }
4268         case SVM_EXIT_READ_DR0:
4269         case SVM_EXIT_WRITE_DR0:
4270                 icpt_info.exit_code += info->modrm_reg;
4271                 break;
4272         case SVM_EXIT_MSR:
4273                 if (info->intercept == x86_intercept_wrmsr)
4274                         vmcb->control.exit_info_1 = 1;
4275                 else
4276                         vmcb->control.exit_info_1 = 0;
4277                 break;
4278         case SVM_EXIT_PAUSE:
4279                 /*
4280                  * We get this for NOP only, but pause
4281                  * is rep not, check this here
4282                  */
4283                 if (info->rep_prefix != REPE_PREFIX)
4284                         goto out;
4285         case SVM_EXIT_IOIO: {
4286                 u64 exit_info;
4287                 u32 bytes;
4288
4289                 if (info->intercept == x86_intercept_in ||
4290                     info->intercept == x86_intercept_ins) {
4291                         exit_info = ((info->src_val & 0xffff) << 16) |
4292                                 SVM_IOIO_TYPE_MASK;
4293                         bytes = info->dst_bytes;
4294                 } else {
4295                         exit_info = (info->dst_val & 0xffff) << 16;
4296                         bytes = info->src_bytes;
4297                 }
4298
4299                 if (info->intercept == x86_intercept_outs ||
4300                     info->intercept == x86_intercept_ins)
4301                         exit_info |= SVM_IOIO_STR_MASK;
4302
4303                 if (info->rep_prefix)
4304                         exit_info |= SVM_IOIO_REP_MASK;
4305
4306                 bytes = min(bytes, 4u);
4307
4308                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4309
4310                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4311
4312                 vmcb->control.exit_info_1 = exit_info;
4313                 vmcb->control.exit_info_2 = info->next_rip;
4314
4315                 break;
4316         }
4317         default:
4318                 break;
4319         }
4320
4321         vmcb->control.next_rip  = info->next_rip;
4322         vmcb->control.exit_code = icpt_info.exit_code;
4323         vmexit = nested_svm_exit_handled(svm);
4324
4325         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4326                                            : X86EMUL_CONTINUE;
4327
4328 out:
4329         return ret;
4330 }
4331
4332 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4333 {
4334         local_irq_enable();
4335 }
4336
4337 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4338 {
4339 }
4340
4341 static struct kvm_x86_ops svm_x86_ops = {
4342         .cpu_has_kvm_support = has_svm,
4343         .disabled_by_bios = is_disabled,
4344         .hardware_setup = svm_hardware_setup,
4345         .hardware_unsetup = svm_hardware_unsetup,
4346         .check_processor_compatibility = svm_check_processor_compat,
4347         .hardware_enable = svm_hardware_enable,
4348         .hardware_disable = svm_hardware_disable,
4349         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4350
4351         .vcpu_create = svm_create_vcpu,
4352         .vcpu_free = svm_free_vcpu,
4353         .vcpu_reset = svm_vcpu_reset,
4354
4355         .prepare_guest_switch = svm_prepare_guest_switch,
4356         .vcpu_load = svm_vcpu_load,
4357         .vcpu_put = svm_vcpu_put,
4358
4359         .update_db_bp_intercept = update_db_bp_intercept,
4360         .get_msr = svm_get_msr,
4361         .set_msr = svm_set_msr,
4362         .get_segment_base = svm_get_segment_base,
4363         .get_segment = svm_get_segment,
4364         .set_segment = svm_set_segment,
4365         .get_cpl = svm_get_cpl,
4366         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4367         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4368         .decache_cr3 = svm_decache_cr3,
4369         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4370         .set_cr0 = svm_set_cr0,
4371         .set_cr3 = svm_set_cr3,
4372         .set_cr4 = svm_set_cr4,
4373         .set_efer = svm_set_efer,
4374         .get_idt = svm_get_idt,
4375         .set_idt = svm_set_idt,
4376         .get_gdt = svm_get_gdt,
4377         .set_gdt = svm_set_gdt,
4378         .get_dr6 = svm_get_dr6,
4379         .set_dr6 = svm_set_dr6,
4380         .set_dr7 = svm_set_dr7,
4381         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4382         .cache_reg = svm_cache_reg,
4383         .get_rflags = svm_get_rflags,
4384         .set_rflags = svm_set_rflags,
4385         .fpu_deactivate = svm_fpu_deactivate,
4386
4387         .tlb_flush = svm_flush_tlb,
4388
4389         .run = svm_vcpu_run,
4390         .handle_exit = handle_exit,
4391         .skip_emulated_instruction = skip_emulated_instruction,
4392         .set_interrupt_shadow = svm_set_interrupt_shadow,
4393         .get_interrupt_shadow = svm_get_interrupt_shadow,
4394         .patch_hypercall = svm_patch_hypercall,
4395         .set_irq = svm_set_irq,
4396         .set_nmi = svm_inject_nmi,
4397         .queue_exception = svm_queue_exception,
4398         .cancel_injection = svm_cancel_injection,
4399         .interrupt_allowed = svm_interrupt_allowed,
4400         .nmi_allowed = svm_nmi_allowed,
4401         .get_nmi_mask = svm_get_nmi_mask,
4402         .set_nmi_mask = svm_set_nmi_mask,
4403         .enable_nmi_window = enable_nmi_window,
4404         .enable_irq_window = enable_irq_window,
4405         .update_cr8_intercept = update_cr8_intercept,
4406         .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4407         .vm_has_apicv = svm_vm_has_apicv,
4408         .load_eoi_exitmap = svm_load_eoi_exitmap,
4409         .sync_pir_to_irr = svm_sync_pir_to_irr,
4410
4411         .set_tss_addr = svm_set_tss_addr,
4412         .get_tdp_level = get_npt_level,
4413         .get_mt_mask = svm_get_mt_mask,
4414
4415         .get_exit_info = svm_get_exit_info,
4416
4417         .get_lpage_level = svm_get_lpage_level,
4418
4419         .cpuid_update = svm_cpuid_update,
4420
4421         .rdtscp_supported = svm_rdtscp_supported,
4422         .invpcid_supported = svm_invpcid_supported,
4423         .mpx_supported = svm_mpx_supported,
4424         .xsaves_supported = svm_xsaves_supported,
4425
4426         .set_supported_cpuid = svm_set_supported_cpuid,
4427
4428         .has_wbinvd_exit = svm_has_wbinvd_exit,
4429
4430         .set_tsc_khz = svm_set_tsc_khz,
4431         .read_tsc_offset = svm_read_tsc_offset,
4432         .write_tsc_offset = svm_write_tsc_offset,
4433         .adjust_tsc_offset = svm_adjust_tsc_offset,
4434         .compute_tsc_offset = svm_compute_tsc_offset,
4435         .read_l1_tsc = svm_read_l1_tsc,
4436
4437         .set_tdp_cr3 = set_tdp_cr3,
4438
4439         .check_intercept = svm_check_intercept,
4440         .handle_external_intr = svm_handle_external_intr,
4441
4442         .sched_in = svm_sched_in,
4443 };
4444
4445 static int __init svm_init(void)
4446 {
4447         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4448                         __alignof__(struct vcpu_svm), THIS_MODULE);
4449 }
4450
4451 static void __exit svm_exit(void)
4452 {
4453         kvm_exit();
4454 }
4455
4456 module_init(svm_init)
4457 module_exit(svm_exit)