2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
18 #define pr_fmt(fmt) "SVM: " fmt
20 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
40 #include <linux/psp-sev.h>
41 #include <linux/file.h>
42 #include <linux/pagemap.h>
43 #include <linux/swap.h>
46 #include <asm/perf_event.h>
47 #include <asm/tlbflush.h>
49 #include <asm/debugreg.h>
50 #include <asm/kvm_para.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/spec-ctrl.h>
54 #include <asm/virtext.h>
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id svm_cpu_id[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_SVM),
66 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
68 #define IOPM_ALLOC_ORDER 2
69 #define MSRPM_ALLOC_ORDER 1
71 #define SEG_TYPE_LDT 2
72 #define SEG_TYPE_BUSY_TSS16 3
74 #define SVM_FEATURE_NPT (1 << 0)
75 #define SVM_FEATURE_LBRV (1 << 1)
76 #define SVM_FEATURE_SVML (1 << 2)
77 #define SVM_FEATURE_NRIP (1 << 3)
78 #define SVM_FEATURE_TSC_RATE (1 << 4)
79 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
80 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
81 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
82 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
84 #define SVM_AVIC_DOORBELL 0xc001011b
86 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
87 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
88 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
92 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
93 #define TSC_RATIO_MIN 0x0000000000000001ULL
94 #define TSC_RATIO_MAX 0x000000ffffffffffULL
96 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
99 * 0xff is broadcast, so the max index allowed for physical APIC ID
100 * table is 0xfe. APIC IDs above 0xff are reserved.
102 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
108 /* AVIC GATAG is encoded using VM and VCPU IDs */
109 #define AVIC_VCPU_ID_BITS 8
110 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
112 #define AVIC_VM_ID_BITS 24
113 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
114 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
116 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
117 (y & AVIC_VCPU_ID_MASK))
118 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
119 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
121 static bool erratum_383_found __read_mostly;
123 static const u32 host_save_user_msrs[] = {
125 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
128 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
134 struct kvm_sev_info {
135 bool active; /* SEV enabled guest */
136 unsigned int asid; /* ASID used for this guest */
137 unsigned int handle; /* SEV firmware handle */
138 int fd; /* SEV device fd */
139 unsigned long pages_locked; /* Number of pages locked */
140 struct list_head regions_list; /* List of registered regions */
146 /* Struct members for AVIC */
148 struct page *avic_logical_id_table_page;
149 struct page *avic_physical_id_table_page;
150 struct hlist_node hnode;
152 struct kvm_sev_info sev_info;
157 struct nested_state {
163 /* These are the merged vectors */
166 /* gpa pointers to the real vectors */
170 /* A VMEXIT is required but not yet emulated */
173 /* cache for intercepts of the guest */
176 u32 intercept_exceptions;
179 /* Nested Paging related state */
183 #define MSRPM_OFFSETS 16
184 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
187 * Set osvw_len to higher value when updated Revision Guides
188 * are published and we know what the new status bits are
190 static uint64_t osvw_len = 4, osvw_status;
193 struct kvm_vcpu vcpu;
195 unsigned long vmcb_pa;
196 struct svm_cpu_data *svm_data;
197 uint64_t asid_generation;
198 uint64_t sysenter_esp;
199 uint64_t sysenter_eip;
206 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
216 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
217 * translated into the appropriate L2_CFG bits on the host to
218 * perform speculative control.
226 struct nested_state nested;
229 u64 nmi_singlestep_guest_rflags;
231 unsigned int3_injected;
232 unsigned long int3_rip;
234 /* cached guest cpuid flags for faster access */
235 bool nrips_enabled : 1;
239 struct page *avic_backing_page;
240 u64 *avic_physical_id_cache;
241 bool avic_is_running;
244 * Per-vcpu list of struct amd_svm_iommu_ir:
245 * This is used mainly to store interrupt remapping information used
246 * when update the vcpu affinity. This avoids the need to scan for
247 * IRTE and try to match ga_tag in the IOMMU driver.
249 struct list_head ir_list;
250 spinlock_t ir_list_lock;
252 /* which host CPU was used for running this vcpu */
253 unsigned int last_cpu;
257 * This is a wrapper of struct amd_iommu_ir_data.
259 struct amd_svm_iommu_ir {
260 struct list_head node; /* Used by SVM for per-vcpu ir_list */
261 void *data; /* Storing pointer to struct amd_ir_data */
264 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
265 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
266 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
268 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
269 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
270 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
271 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
273 static DEFINE_PER_CPU(u64, current_tsc_ratio);
274 #define TSC_RATIO_DEFAULT 0x0100000000ULL
276 #define MSR_INVALID 0xffffffffU
278 static const struct svm_direct_access_msrs {
279 u32 index; /* Index of the MSR */
280 bool always; /* True if intercept is always on */
281 } direct_access_msrs[] = {
282 { .index = MSR_STAR, .always = true },
283 { .index = MSR_IA32_SYSENTER_CS, .always = true },
285 { .index = MSR_GS_BASE, .always = true },
286 { .index = MSR_FS_BASE, .always = true },
287 { .index = MSR_KERNEL_GS_BASE, .always = true },
288 { .index = MSR_LSTAR, .always = true },
289 { .index = MSR_CSTAR, .always = true },
290 { .index = MSR_SYSCALL_MASK, .always = true },
292 { .index = MSR_IA32_SPEC_CTRL, .always = false },
293 { .index = MSR_IA32_PRED_CMD, .always = false },
294 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
295 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
296 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
297 { .index = MSR_IA32_LASTINTTOIP, .always = false },
298 { .index = MSR_INVALID, .always = false },
301 /* enable NPT for AMD64 and X86 with PAE */
302 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
303 static bool npt_enabled = true;
305 static bool npt_enabled;
309 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
310 * pause_filter_count: On processors that support Pause filtering(indicated
311 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
312 * count value. On VMRUN this value is loaded into an internal counter.
313 * Each time a pause instruction is executed, this counter is decremented
314 * until it reaches zero at which time a #VMEXIT is generated if pause
315 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
316 * Intercept Filtering for more details.
317 * This also indicate if ple logic enabled.
319 * pause_filter_thresh: In addition, some processor families support advanced
320 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
321 * the amount of time a guest is allowed to execute in a pause loop.
322 * In this mode, a 16-bit pause filter threshold field is added in the
323 * VMCB. The threshold value is a cycle count that is used to reset the
324 * pause counter. As with simple pause filtering, VMRUN loads the pause
325 * count value from VMCB into an internal counter. Then, on each pause
326 * instruction the hardware checks the elapsed number of cycles since
327 * the most recent pause instruction against the pause filter threshold.
328 * If the elapsed cycle count is greater than the pause filter threshold,
329 * then the internal pause count is reloaded from the VMCB and execution
330 * continues. If the elapsed cycle count is less than the pause filter
331 * threshold, then the internal pause count is decremented. If the count
332 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
333 * triggered. If advanced pause filtering is supported and pause filter
334 * threshold field is set to zero, the filter will operate in the simpler,
338 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
339 module_param(pause_filter_thresh, ushort, 0444);
341 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
342 module_param(pause_filter_count, ushort, 0444);
344 /* Default doubles per-vcpu window every exit. */
345 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
346 module_param(pause_filter_count_grow, ushort, 0444);
348 /* Default resets per-vcpu window every exit to pause_filter_count. */
349 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
350 module_param(pause_filter_count_shrink, ushort, 0444);
352 /* Default is to compute the maximum so we can never overflow. */
353 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
354 module_param(pause_filter_count_max, ushort, 0444);
356 /* allow nested paging (virtualized MMU) for all guests */
357 static int npt = true;
358 module_param(npt, int, S_IRUGO);
360 /* allow nested virtualization in KVM/SVM */
361 static int nested = true;
362 module_param(nested, int, S_IRUGO);
364 /* enable / disable AVIC */
366 #ifdef CONFIG_X86_LOCAL_APIC
367 module_param(avic, int, S_IRUGO);
370 /* enable/disable Virtual VMLOAD VMSAVE */
371 static int vls = true;
372 module_param(vls, int, 0444);
374 /* enable/disable Virtual GIF */
375 static int vgif = true;
376 module_param(vgif, int, 0444);
378 /* enable/disable SEV support */
379 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
380 module_param(sev, int, 0444);
382 static bool __read_mostly dump_invalid_vmcb = 0;
383 module_param(dump_invalid_vmcb, bool, 0644);
385 static u8 rsm_ins_bytes[] = "\x0f\xaa";
387 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
388 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
389 static void svm_complete_interrupts(struct vcpu_svm *svm);
391 static int nested_svm_exit_handled(struct vcpu_svm *svm);
392 static int nested_svm_intercept(struct vcpu_svm *svm);
393 static int nested_svm_vmexit(struct vcpu_svm *svm);
394 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
395 bool has_error_code, u32 error_code);
398 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
399 pause filter count */
400 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
401 VMCB_ASID, /* ASID */
402 VMCB_INTR, /* int_ctl, int_vector */
403 VMCB_NPT, /* npt_en, nCR3, gPAT */
404 VMCB_CR, /* CR0, CR3, CR4, EFER */
405 VMCB_DR, /* DR6, DR7 */
406 VMCB_DT, /* GDT, IDT */
407 VMCB_SEG, /* CS, DS, SS, ES, CPL */
408 VMCB_CR2, /* CR2 only */
409 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
410 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
411 * AVIC PHYSICAL_TABLE pointer,
412 * AVIC LOGICAL_TABLE pointer
417 /* TPR and CR2 are always written before VMRUN */
418 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
420 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
422 static unsigned int max_sev_asid;
423 static unsigned int min_sev_asid;
424 static unsigned long *sev_asid_bitmap;
425 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
428 struct list_head list;
429 unsigned long npages;
436 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
438 return container_of(kvm, struct kvm_svm, kvm);
441 static inline bool svm_sev_enabled(void)
443 return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
446 static inline bool sev_guest(struct kvm *kvm)
448 #ifdef CONFIG_KVM_AMD_SEV
449 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
457 static inline int sev_get_asid(struct kvm *kvm)
459 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
464 static inline void mark_all_dirty(struct vmcb *vmcb)
466 vmcb->control.clean = 0;
469 static inline void mark_all_clean(struct vmcb *vmcb)
471 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
472 & ~VMCB_ALWAYS_DIRTY_MASK;
475 static inline void mark_dirty(struct vmcb *vmcb, int bit)
477 vmcb->control.clean &= ~(1 << bit);
480 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
482 return container_of(vcpu, struct vcpu_svm, vcpu);
485 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
487 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
488 mark_dirty(svm->vmcb, VMCB_AVIC);
491 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
493 struct vcpu_svm *svm = to_svm(vcpu);
494 u64 *entry = svm->avic_physical_id_cache;
499 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
502 static void recalc_intercepts(struct vcpu_svm *svm)
504 struct vmcb_control_area *c, *h;
505 struct nested_state *g;
507 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
509 if (!is_guest_mode(&svm->vcpu))
512 c = &svm->vmcb->control;
513 h = &svm->nested.hsave->control;
516 c->intercept_cr = h->intercept_cr | g->intercept_cr;
517 c->intercept_dr = h->intercept_dr | g->intercept_dr;
518 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
519 c->intercept = h->intercept | g->intercept;
522 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
524 if (is_guest_mode(&svm->vcpu))
525 return svm->nested.hsave;
530 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
532 struct vmcb *vmcb = get_host_vmcb(svm);
534 vmcb->control.intercept_cr |= (1U << bit);
536 recalc_intercepts(svm);
539 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
541 struct vmcb *vmcb = get_host_vmcb(svm);
543 vmcb->control.intercept_cr &= ~(1U << bit);
545 recalc_intercepts(svm);
548 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
550 struct vmcb *vmcb = get_host_vmcb(svm);
552 return vmcb->control.intercept_cr & (1U << bit);
555 static inline void set_dr_intercepts(struct vcpu_svm *svm)
557 struct vmcb *vmcb = get_host_vmcb(svm);
559 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
560 | (1 << INTERCEPT_DR1_READ)
561 | (1 << INTERCEPT_DR2_READ)
562 | (1 << INTERCEPT_DR3_READ)
563 | (1 << INTERCEPT_DR4_READ)
564 | (1 << INTERCEPT_DR5_READ)
565 | (1 << INTERCEPT_DR6_READ)
566 | (1 << INTERCEPT_DR7_READ)
567 | (1 << INTERCEPT_DR0_WRITE)
568 | (1 << INTERCEPT_DR1_WRITE)
569 | (1 << INTERCEPT_DR2_WRITE)
570 | (1 << INTERCEPT_DR3_WRITE)
571 | (1 << INTERCEPT_DR4_WRITE)
572 | (1 << INTERCEPT_DR5_WRITE)
573 | (1 << INTERCEPT_DR6_WRITE)
574 | (1 << INTERCEPT_DR7_WRITE);
576 recalc_intercepts(svm);
579 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
581 struct vmcb *vmcb = get_host_vmcb(svm);
583 vmcb->control.intercept_dr = 0;
585 recalc_intercepts(svm);
588 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
590 struct vmcb *vmcb = get_host_vmcb(svm);
592 vmcb->control.intercept_exceptions |= (1U << bit);
594 recalc_intercepts(svm);
597 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
599 struct vmcb *vmcb = get_host_vmcb(svm);
601 vmcb->control.intercept_exceptions &= ~(1U << bit);
603 recalc_intercepts(svm);
606 static inline void set_intercept(struct vcpu_svm *svm, int bit)
608 struct vmcb *vmcb = get_host_vmcb(svm);
610 vmcb->control.intercept |= (1ULL << bit);
612 recalc_intercepts(svm);
615 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
617 struct vmcb *vmcb = get_host_vmcb(svm);
619 vmcb->control.intercept &= ~(1ULL << bit);
621 recalc_intercepts(svm);
624 static inline bool vgif_enabled(struct vcpu_svm *svm)
626 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
629 static inline void enable_gif(struct vcpu_svm *svm)
631 if (vgif_enabled(svm))
632 svm->vmcb->control.int_ctl |= V_GIF_MASK;
634 svm->vcpu.arch.hflags |= HF_GIF_MASK;
637 static inline void disable_gif(struct vcpu_svm *svm)
639 if (vgif_enabled(svm))
640 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
642 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
645 static inline bool gif_set(struct vcpu_svm *svm)
647 if (vgif_enabled(svm))
648 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
650 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
653 static unsigned long iopm_base;
655 struct kvm_ldttss_desc {
658 unsigned base1:8, type:5, dpl:2, p:1;
659 unsigned limit1:4, zero0:3, g:1, base2:8;
662 } __attribute__((packed));
664 struct svm_cpu_data {
671 struct kvm_ldttss_desc *tss_desc;
673 struct page *save_area;
674 struct vmcb *current_vmcb;
676 /* index = sev_asid, value = vmcb pointer */
677 struct vmcb **sev_vmcbs;
680 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
682 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
684 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
685 #define MSRS_RANGE_SIZE 2048
686 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
688 static u32 svm_msrpm_offset(u32 msr)
693 for (i = 0; i < NUM_MSR_MAPS; i++) {
694 if (msr < msrpm_ranges[i] ||
695 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
698 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
699 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
701 /* Now we have the u8 offset - but need the u32 offset */
705 /* MSR not in any range */
709 #define MAX_INST_SIZE 15
711 static inline void clgi(void)
713 asm volatile (__ex("clgi"));
716 static inline void stgi(void)
718 asm volatile (__ex("stgi"));
721 static inline void invlpga(unsigned long addr, u32 asid)
723 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
726 static int get_npt_level(struct kvm_vcpu *vcpu)
729 return PT64_ROOT_4LEVEL;
731 return PT32E_ROOT_LEVEL;
735 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
737 vcpu->arch.efer = efer;
738 if (!npt_enabled && !(efer & EFER_LMA))
741 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
742 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
745 static int is_external_interrupt(u32 info)
747 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
748 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
751 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
753 struct vcpu_svm *svm = to_svm(vcpu);
756 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
757 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
761 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
763 struct vcpu_svm *svm = to_svm(vcpu);
766 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
768 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
772 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
774 struct vcpu_svm *svm = to_svm(vcpu);
776 if (svm->vmcb->control.next_rip != 0) {
777 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
778 svm->next_rip = svm->vmcb->control.next_rip;
781 if (!svm->next_rip) {
782 if (kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) !=
784 printk(KERN_DEBUG "%s: NOP\n", __func__);
787 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
788 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
789 __func__, kvm_rip_read(vcpu), svm->next_rip);
791 kvm_rip_write(vcpu, svm->next_rip);
792 svm_set_interrupt_shadow(vcpu, 0);
795 static void svm_queue_exception(struct kvm_vcpu *vcpu)
797 struct vcpu_svm *svm = to_svm(vcpu);
798 unsigned nr = vcpu->arch.exception.nr;
799 bool has_error_code = vcpu->arch.exception.has_error_code;
800 bool reinject = vcpu->arch.exception.injected;
801 u32 error_code = vcpu->arch.exception.error_code;
804 * If we are within a nested VM we'd better #VMEXIT and let the guest
805 * handle the exception
808 nested_svm_check_exception(svm, nr, has_error_code, error_code))
811 kvm_deliver_exception_payload(&svm->vcpu);
813 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
814 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
817 * For guest debugging where we have to reinject #BP if some
818 * INT3 is guest-owned:
819 * Emulate nRIP by moving RIP forward. Will fail if injection
820 * raises a fault that is not intercepted. Still better than
821 * failing in all cases.
823 skip_emulated_instruction(&svm->vcpu);
824 rip = kvm_rip_read(&svm->vcpu);
825 svm->int3_rip = rip + svm->vmcb->save.cs.base;
826 svm->int3_injected = rip - old_rip;
829 svm->vmcb->control.event_inj = nr
831 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
832 | SVM_EVTINJ_TYPE_EXEPT;
833 svm->vmcb->control.event_inj_err = error_code;
836 static void svm_init_erratum_383(void)
842 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
845 /* Use _safe variants to not break nested virtualization */
846 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
852 low = lower_32_bits(val);
853 high = upper_32_bits(val);
855 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
857 erratum_383_found = true;
860 static void svm_init_osvw(struct kvm_vcpu *vcpu)
863 * Guests should see errata 400 and 415 as fixed (assuming that
864 * HLT and IO instructions are intercepted).
866 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
867 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
870 * By increasing VCPU's osvw.length to 3 we are telling the guest that
871 * all osvw.status bits inside that length, including bit 0 (which is
872 * reserved for erratum 298), are valid. However, if host processor's
873 * osvw_len is 0 then osvw_status[0] carries no information. We need to
874 * be conservative here and therefore we tell the guest that erratum 298
875 * is present (because we really don't know).
877 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
878 vcpu->arch.osvw.status |= 1;
881 static int has_svm(void)
885 if (!cpu_has_svm(&msg)) {
886 printk(KERN_INFO "has_svm: %s\n", msg);
893 static void svm_hardware_disable(void)
895 /* Make sure we clean up behind us */
896 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
897 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
901 amd_pmu_disable_virt();
904 static int svm_hardware_enable(void)
907 struct svm_cpu_data *sd;
909 struct desc_struct *gdt;
910 int me = raw_smp_processor_id();
912 rdmsrl(MSR_EFER, efer);
913 if (efer & EFER_SVME)
917 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
920 sd = per_cpu(svm_data, me);
922 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
926 sd->asid_generation = 1;
927 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
928 sd->next_asid = sd->max_asid + 1;
929 sd->min_asid = max_sev_asid + 1;
931 gdt = get_current_gdt_rw();
932 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
934 wrmsrl(MSR_EFER, efer | EFER_SVME);
936 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
938 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
939 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
940 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
947 * Note that it is possible to have a system with mixed processor
948 * revisions and therefore different OSVW bits. If bits are not the same
949 * on different processors then choose the worst case (i.e. if erratum
950 * is present on one processor and not on another then assume that the
951 * erratum is present everywhere).
953 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
954 uint64_t len, status = 0;
957 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
959 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
963 osvw_status = osvw_len = 0;
967 osvw_status |= status;
968 osvw_status &= (1ULL << osvw_len) - 1;
971 osvw_status = osvw_len = 0;
973 svm_init_erratum_383();
975 amd_pmu_enable_virt();
980 static void svm_cpu_uninit(int cpu)
982 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
987 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
988 kfree(sd->sev_vmcbs);
989 __free_page(sd->save_area);
993 static int svm_cpu_init(int cpu)
995 struct svm_cpu_data *sd;
998 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
1003 sd->save_area = alloc_page(GFP_KERNEL);
1007 if (svm_sev_enabled()) {
1009 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1016 per_cpu(svm_data, cpu) = sd;
1026 static bool valid_msr_intercept(u32 index)
1030 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1031 if (direct_access_msrs[i].index == index)
1037 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1044 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1045 to_svm(vcpu)->msrpm;
1047 offset = svm_msrpm_offset(msr);
1048 bit_write = 2 * (msr & 0x0f) + 1;
1049 tmp = msrpm[offset];
1051 BUG_ON(offset == MSR_INVALID);
1053 return !!test_bit(bit_write, &tmp);
1056 static void set_msr_interception(u32 *msrpm, unsigned msr,
1057 int read, int write)
1059 u8 bit_read, bit_write;
1064 * If this warning triggers extend the direct_access_msrs list at the
1065 * beginning of the file
1067 WARN_ON(!valid_msr_intercept(msr));
1069 offset = svm_msrpm_offset(msr);
1070 bit_read = 2 * (msr & 0x0f);
1071 bit_write = 2 * (msr & 0x0f) + 1;
1072 tmp = msrpm[offset];
1074 BUG_ON(offset == MSR_INVALID);
1076 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
1077 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1079 msrpm[offset] = tmp;
1082 static void svm_vcpu_init_msrpm(u32 *msrpm)
1086 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1088 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1089 if (!direct_access_msrs[i].always)
1092 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1096 static void add_msr_offset(u32 offset)
1100 for (i = 0; i < MSRPM_OFFSETS; ++i) {
1102 /* Offset already in list? */
1103 if (msrpm_offsets[i] == offset)
1106 /* Slot used by another offset? */
1107 if (msrpm_offsets[i] != MSR_INVALID)
1110 /* Add offset to list */
1111 msrpm_offsets[i] = offset;
1117 * If this BUG triggers the msrpm_offsets table has an overflow. Just
1118 * increase MSRPM_OFFSETS in this case.
1123 static void init_msrpm_offsets(void)
1127 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1129 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1132 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1133 BUG_ON(offset == MSR_INVALID);
1135 add_msr_offset(offset);
1139 static void svm_enable_lbrv(struct vcpu_svm *svm)
1141 u32 *msrpm = svm->msrpm;
1143 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1144 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1145 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1146 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1147 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1150 static void svm_disable_lbrv(struct vcpu_svm *svm)
1152 u32 *msrpm = svm->msrpm;
1154 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1155 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1156 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1157 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1158 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1161 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1163 svm->nmi_singlestep = false;
1165 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1166 /* Clear our flags if they were not set by the guest */
1167 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1168 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1169 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1170 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1175 * This hash table is used to map VM_ID to a struct kvm_svm,
1176 * when handling AMD IOMMU GALOG notification to schedule in
1177 * a particular vCPU.
1179 #define SVM_VM_DATA_HASH_BITS 8
1180 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1181 static u32 next_vm_id = 0;
1182 static bool next_vm_id_wrapped = 0;
1183 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1186 * This function is called from IOMMU driver to notify
1187 * SVM to schedule in a particular vCPU of a particular VM.
1189 static int avic_ga_log_notifier(u32 ga_tag)
1191 unsigned long flags;
1192 struct kvm_svm *kvm_svm;
1193 struct kvm_vcpu *vcpu = NULL;
1194 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1195 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1197 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1199 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1200 hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1201 if (kvm_svm->avic_vm_id != vm_id)
1203 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1206 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1209 * At this point, the IOMMU should have already set the pending
1210 * bit in the vAPIC backing page. So, we just need to schedule
1214 kvm_vcpu_wake_up(vcpu);
1219 static __init int sev_hardware_setup(void)
1221 struct sev_user_data_status *status;
1224 /* Maximum number of encrypted guests supported simultaneously */
1225 max_sev_asid = cpuid_ecx(0x8000001F);
1230 /* Minimum ASID value that should be used for SEV guest */
1231 min_sev_asid = cpuid_edx(0x8000001F);
1233 /* Initialize SEV ASID bitmap */
1234 sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1235 if (!sev_asid_bitmap)
1238 status = kmalloc(sizeof(*status), GFP_KERNEL);
1243 * Check SEV platform status.
1245 * PLATFORM_STATUS can be called in any state, if we failed to query
1246 * the PLATFORM status then either PSP firmware does not support SEV
1247 * feature or SEV firmware is dead.
1249 rc = sev_platform_status(status, NULL);
1253 pr_info("SEV supported\n");
1260 static void grow_ple_window(struct kvm_vcpu *vcpu)
1262 struct vcpu_svm *svm = to_svm(vcpu);
1263 struct vmcb_control_area *control = &svm->vmcb->control;
1264 int old = control->pause_filter_count;
1266 control->pause_filter_count = __grow_ple_window(old,
1268 pause_filter_count_grow,
1269 pause_filter_count_max);
1271 if (control->pause_filter_count != old)
1272 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1274 trace_kvm_ple_window_grow(vcpu->vcpu_id,
1275 control->pause_filter_count, old);
1278 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1280 struct vcpu_svm *svm = to_svm(vcpu);
1281 struct vmcb_control_area *control = &svm->vmcb->control;
1282 int old = control->pause_filter_count;
1284 control->pause_filter_count =
1285 __shrink_ple_window(old,
1287 pause_filter_count_shrink,
1288 pause_filter_count);
1289 if (control->pause_filter_count != old)
1290 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1292 trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1293 control->pause_filter_count, old);
1296 static __init int svm_hardware_setup(void)
1299 struct page *iopm_pages;
1303 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1308 iopm_va = page_address(iopm_pages);
1309 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1310 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1312 init_msrpm_offsets();
1314 if (boot_cpu_has(X86_FEATURE_NX))
1315 kvm_enable_efer_bits(EFER_NX);
1317 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1318 kvm_enable_efer_bits(EFER_FFXSR);
1320 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1321 kvm_has_tsc_control = true;
1322 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1323 kvm_tsc_scaling_ratio_frac_bits = 32;
1326 /* Check for pause filtering support */
1327 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1328 pause_filter_count = 0;
1329 pause_filter_thresh = 0;
1330 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1331 pause_filter_thresh = 0;
1335 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1336 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1340 if (boot_cpu_has(X86_FEATURE_SEV) &&
1341 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1342 r = sev_hardware_setup();
1350 for_each_possible_cpu(cpu) {
1351 r = svm_cpu_init(cpu);
1356 if (!boot_cpu_has(X86_FEATURE_NPT))
1357 npt_enabled = false;
1359 if (npt_enabled && !npt) {
1360 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1361 npt_enabled = false;
1365 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1372 !boot_cpu_has(X86_FEATURE_AVIC) ||
1373 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1376 pr_info("AVIC enabled\n");
1378 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1384 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1385 !IS_ENABLED(CONFIG_X86_64)) {
1388 pr_info("Virtual VMLOAD VMSAVE supported\n");
1393 if (!boot_cpu_has(X86_FEATURE_VGIF))
1396 pr_info("Virtual GIF supported\n");
1402 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1407 static __exit void svm_hardware_unsetup(void)
1411 if (svm_sev_enabled())
1412 bitmap_free(sev_asid_bitmap);
1414 for_each_possible_cpu(cpu)
1415 svm_cpu_uninit(cpu);
1417 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1421 static void init_seg(struct vmcb_seg *seg)
1424 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1425 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1426 seg->limit = 0xffff;
1430 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1433 seg->attrib = SVM_SELECTOR_P_MASK | type;
1434 seg->limit = 0xffff;
1438 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1440 struct vcpu_svm *svm = to_svm(vcpu);
1442 if (is_guest_mode(vcpu))
1443 return svm->nested.hsave->control.tsc_offset;
1445 return vcpu->arch.tsc_offset;
1448 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1450 struct vcpu_svm *svm = to_svm(vcpu);
1451 u64 g_tsc_offset = 0;
1453 if (is_guest_mode(vcpu)) {
1454 /* Write L1's TSC offset. */
1455 g_tsc_offset = svm->vmcb->control.tsc_offset -
1456 svm->nested.hsave->control.tsc_offset;
1457 svm->nested.hsave->control.tsc_offset = offset;
1460 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1461 svm->vmcb->control.tsc_offset - g_tsc_offset,
1464 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1466 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1467 return svm->vmcb->control.tsc_offset;
1470 static void avic_init_vmcb(struct vcpu_svm *svm)
1472 struct vmcb *vmcb = svm->vmcb;
1473 struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1474 phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1475 phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1476 phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1478 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1479 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1480 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1481 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1482 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1485 static void init_vmcb(struct vcpu_svm *svm)
1487 struct vmcb_control_area *control = &svm->vmcb->control;
1488 struct vmcb_save_area *save = &svm->vmcb->save;
1490 svm->vcpu.arch.hflags = 0;
1492 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1493 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1494 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1495 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1496 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1497 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1498 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1499 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1501 set_dr_intercepts(svm);
1503 set_exception_intercept(svm, PF_VECTOR);
1504 set_exception_intercept(svm, UD_VECTOR);
1505 set_exception_intercept(svm, MC_VECTOR);
1506 set_exception_intercept(svm, AC_VECTOR);
1507 set_exception_intercept(svm, DB_VECTOR);
1509 * Guest access to VMware backdoor ports could legitimately
1510 * trigger #GP because of TSS I/O permission bitmap.
1511 * We intercept those #GP and allow access to them anyway
1514 if (enable_vmware_backdoor)
1515 set_exception_intercept(svm, GP_VECTOR);
1517 set_intercept(svm, INTERCEPT_INTR);
1518 set_intercept(svm, INTERCEPT_NMI);
1519 set_intercept(svm, INTERCEPT_SMI);
1520 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1521 set_intercept(svm, INTERCEPT_RDPMC);
1522 set_intercept(svm, INTERCEPT_CPUID);
1523 set_intercept(svm, INTERCEPT_INVD);
1524 set_intercept(svm, INTERCEPT_INVLPG);
1525 set_intercept(svm, INTERCEPT_INVLPGA);
1526 set_intercept(svm, INTERCEPT_IOIO_PROT);
1527 set_intercept(svm, INTERCEPT_MSR_PROT);
1528 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1529 set_intercept(svm, INTERCEPT_SHUTDOWN);
1530 set_intercept(svm, INTERCEPT_VMRUN);
1531 set_intercept(svm, INTERCEPT_VMMCALL);
1532 set_intercept(svm, INTERCEPT_VMLOAD);
1533 set_intercept(svm, INTERCEPT_VMSAVE);
1534 set_intercept(svm, INTERCEPT_STGI);
1535 set_intercept(svm, INTERCEPT_CLGI);
1536 set_intercept(svm, INTERCEPT_SKINIT);
1537 set_intercept(svm, INTERCEPT_WBINVD);
1538 set_intercept(svm, INTERCEPT_XSETBV);
1539 set_intercept(svm, INTERCEPT_RSM);
1541 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1542 set_intercept(svm, INTERCEPT_MONITOR);
1543 set_intercept(svm, INTERCEPT_MWAIT);
1546 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1547 set_intercept(svm, INTERCEPT_HLT);
1549 control->iopm_base_pa = __sme_set(iopm_base);
1550 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1551 control->int_ctl = V_INTR_MASKING_MASK;
1553 init_seg(&save->es);
1554 init_seg(&save->ss);
1555 init_seg(&save->ds);
1556 init_seg(&save->fs);
1557 init_seg(&save->gs);
1559 save->cs.selector = 0xf000;
1560 save->cs.base = 0xffff0000;
1561 /* Executable/Readable Code Segment */
1562 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1563 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1564 save->cs.limit = 0xffff;
1566 save->gdtr.limit = 0xffff;
1567 save->idtr.limit = 0xffff;
1569 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1570 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1572 svm_set_efer(&svm->vcpu, 0);
1573 save->dr6 = 0xffff0ff0;
1574 kvm_set_rflags(&svm->vcpu, 2);
1575 save->rip = 0x0000fff0;
1576 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1579 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1580 * It also updates the guest-visible cr0 value.
1582 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1583 kvm_mmu_reset_context(&svm->vcpu);
1585 save->cr4 = X86_CR4_PAE;
1589 /* Setup VMCB for Nested Paging */
1590 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1591 clr_intercept(svm, INTERCEPT_INVLPG);
1592 clr_exception_intercept(svm, PF_VECTOR);
1593 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1594 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1595 save->g_pat = svm->vcpu.arch.pat;
1599 svm->asid_generation = 0;
1601 svm->nested.vmcb = 0;
1602 svm->vcpu.arch.hflags = 0;
1604 if (pause_filter_count) {
1605 control->pause_filter_count = pause_filter_count;
1606 if (pause_filter_thresh)
1607 control->pause_filter_thresh = pause_filter_thresh;
1608 set_intercept(svm, INTERCEPT_PAUSE);
1610 clr_intercept(svm, INTERCEPT_PAUSE);
1613 if (kvm_vcpu_apicv_active(&svm->vcpu))
1614 avic_init_vmcb(svm);
1617 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1618 * in VMCB and clear intercepts to avoid #VMEXIT.
1621 clr_intercept(svm, INTERCEPT_VMLOAD);
1622 clr_intercept(svm, INTERCEPT_VMSAVE);
1623 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1627 clr_intercept(svm, INTERCEPT_STGI);
1628 clr_intercept(svm, INTERCEPT_CLGI);
1629 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1632 if (sev_guest(svm->vcpu.kvm)) {
1633 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1634 clr_exception_intercept(svm, UD_VECTOR);
1637 mark_all_dirty(svm->vmcb);
1643 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1646 u64 *avic_physical_id_table;
1647 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1649 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1652 avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1654 return &avic_physical_id_table[index];
1659 * AVIC hardware walks the nested page table to check permissions,
1660 * but does not use the SPA address specified in the leaf page
1661 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1662 * field of the VMCB. Therefore, we set up the
1663 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1665 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1667 struct kvm *kvm = vcpu->kvm;
1670 mutex_lock(&kvm->slots_lock);
1671 if (kvm->arch.apic_access_page_done)
1674 ret = __x86_set_memory_region(kvm,
1675 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1676 APIC_DEFAULT_PHYS_BASE,
1681 kvm->arch.apic_access_page_done = true;
1683 mutex_unlock(&kvm->slots_lock);
1687 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1690 u64 *entry, new_entry;
1691 int id = vcpu->vcpu_id;
1692 struct vcpu_svm *svm = to_svm(vcpu);
1694 ret = avic_init_access_page(vcpu);
1698 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1701 if (!svm->vcpu.arch.apic->regs)
1704 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1706 /* Setting AVIC backing page address in the phy APIC ID table */
1707 entry = avic_get_physical_id_entry(vcpu, id);
1711 new_entry = READ_ONCE(*entry);
1712 new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1713 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1714 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1715 WRITE_ONCE(*entry, new_entry);
1717 svm->avic_physical_id_cache = entry;
1722 static void __sev_asid_free(int asid)
1724 struct svm_cpu_data *sd;
1728 clear_bit(pos, sev_asid_bitmap);
1730 for_each_possible_cpu(cpu) {
1731 sd = per_cpu(svm_data, cpu);
1732 sd->sev_vmcbs[pos] = NULL;
1736 static void sev_asid_free(struct kvm *kvm)
1738 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1740 __sev_asid_free(sev->asid);
1743 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1745 struct sev_data_decommission *decommission;
1746 struct sev_data_deactivate *data;
1751 data = kzalloc(sizeof(*data), GFP_KERNEL);
1755 /* deactivate handle */
1756 data->handle = handle;
1757 sev_guest_deactivate(data, NULL);
1759 wbinvd_on_all_cpus();
1760 sev_guest_df_flush(NULL);
1763 decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1767 /* decommission handle */
1768 decommission->handle = handle;
1769 sev_guest_decommission(decommission, NULL);
1771 kfree(decommission);
1774 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1775 unsigned long ulen, unsigned long *n,
1778 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1779 unsigned long npages, npinned, size;
1780 unsigned long locked, lock_limit;
1781 struct page **pages;
1782 unsigned long first, last;
1784 if (ulen == 0 || uaddr + ulen < uaddr)
1787 /* Calculate number of pages. */
1788 first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1789 last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1790 npages = (last - first + 1);
1792 locked = sev->pages_locked + npages;
1793 lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1794 if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1795 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1799 /* Avoid using vmalloc for smaller buffers. */
1800 size = npages * sizeof(struct page *);
1801 if (size > PAGE_SIZE)
1802 pages = __vmalloc(size, GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1805 pages = kmalloc(size, GFP_KERNEL_ACCOUNT);
1810 /* Pin the user virtual address. */
1811 npinned = get_user_pages_fast(uaddr, npages, FOLL_WRITE, pages);
1812 if (npinned != npages) {
1813 pr_err("SEV: Failure locking %lu pages.\n", npages);
1818 sev->pages_locked = locked;
1824 release_pages(pages, npinned);
1830 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1831 unsigned long npages)
1833 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1835 release_pages(pages, npages);
1837 sev->pages_locked -= npages;
1840 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1842 uint8_t *page_virtual;
1845 if (npages == 0 || pages == NULL)
1848 for (i = 0; i < npages; i++) {
1849 page_virtual = kmap_atomic(pages[i]);
1850 clflush_cache_range(page_virtual, PAGE_SIZE);
1851 kunmap_atomic(page_virtual);
1855 static void __unregister_enc_region_locked(struct kvm *kvm,
1856 struct enc_region *region)
1859 * The guest may change the memory encryption attribute from C=0 -> C=1
1860 * or vice versa for this memory range. Lets make sure caches are
1861 * flushed to ensure that guest data gets written into memory with
1864 sev_clflush_pages(region->pages, region->npages);
1866 sev_unpin_memory(kvm, region->pages, region->npages);
1867 list_del(®ion->list);
1871 static struct kvm *svm_vm_alloc(void)
1873 struct kvm_svm *kvm_svm = __vmalloc(sizeof(struct kvm_svm),
1874 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1876 return &kvm_svm->kvm;
1879 static void svm_vm_free(struct kvm *kvm)
1881 vfree(to_kvm_svm(kvm));
1884 static void sev_vm_destroy(struct kvm *kvm)
1886 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1887 struct list_head *head = &sev->regions_list;
1888 struct list_head *pos, *q;
1890 if (!sev_guest(kvm))
1893 mutex_lock(&kvm->lock);
1896 * if userspace was terminated before unregistering the memory regions
1897 * then lets unpin all the registered memory.
1899 if (!list_empty(head)) {
1900 list_for_each_safe(pos, q, head) {
1901 __unregister_enc_region_locked(kvm,
1902 list_entry(pos, struct enc_region, list));
1906 mutex_unlock(&kvm->lock);
1908 sev_unbind_asid(kvm, sev->handle);
1912 static void avic_vm_destroy(struct kvm *kvm)
1914 unsigned long flags;
1915 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1920 if (kvm_svm->avic_logical_id_table_page)
1921 __free_page(kvm_svm->avic_logical_id_table_page);
1922 if (kvm_svm->avic_physical_id_table_page)
1923 __free_page(kvm_svm->avic_physical_id_table_page);
1925 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1926 hash_del(&kvm_svm->hnode);
1927 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1930 static void svm_vm_destroy(struct kvm *kvm)
1932 avic_vm_destroy(kvm);
1933 sev_vm_destroy(kvm);
1936 static int avic_vm_init(struct kvm *kvm)
1938 unsigned long flags;
1940 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1942 struct page *p_page;
1943 struct page *l_page;
1949 /* Allocating physical APIC ID table (4KB) */
1950 p_page = alloc_page(GFP_KERNEL_ACCOUNT);
1954 kvm_svm->avic_physical_id_table_page = p_page;
1955 clear_page(page_address(p_page));
1957 /* Allocating logical APIC ID table (4KB) */
1958 l_page = alloc_page(GFP_KERNEL_ACCOUNT);
1962 kvm_svm->avic_logical_id_table_page = l_page;
1963 clear_page(page_address(l_page));
1965 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1967 vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1968 if (vm_id == 0) { /* id is 1-based, zero is not okay */
1969 next_vm_id_wrapped = 1;
1972 /* Is it still in use? Only possible if wrapped at least once */
1973 if (next_vm_id_wrapped) {
1974 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1975 if (k2->avic_vm_id == vm_id)
1979 kvm_svm->avic_vm_id = vm_id;
1980 hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1981 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1986 avic_vm_destroy(kvm);
1991 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1994 unsigned long flags;
1995 struct amd_svm_iommu_ir *ir;
1996 struct vcpu_svm *svm = to_svm(vcpu);
1998 if (!kvm_arch_has_assigned_device(vcpu->kvm))
2002 * Here, we go through the per-vcpu ir_list to update all existing
2003 * interrupt remapping table entry targeting this vcpu.
2005 spin_lock_irqsave(&svm->ir_list_lock, flags);
2007 if (list_empty(&svm->ir_list))
2010 list_for_each_entry(ir, &svm->ir_list, node) {
2011 ret = amd_iommu_update_ga(cpu, r, ir->data);
2016 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2020 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2023 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2024 int h_physical_id = kvm_cpu_get_apicid(cpu);
2025 struct vcpu_svm *svm = to_svm(vcpu);
2027 if (!kvm_vcpu_apicv_active(vcpu))
2031 * Since the host physical APIC id is 8 bits,
2032 * we can support host APIC ID upto 255.
2034 if (WARN_ON(h_physical_id > AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK))
2037 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2038 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2040 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2041 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2043 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2044 if (svm->avic_is_running)
2045 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2047 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2048 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2049 svm->avic_is_running);
2052 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2055 struct vcpu_svm *svm = to_svm(vcpu);
2057 if (!kvm_vcpu_apicv_active(vcpu))
2060 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2061 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2062 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2064 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2065 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2069 * This function is called during VCPU halt/unhalt.
2071 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2073 struct vcpu_svm *svm = to_svm(vcpu);
2075 svm->avic_is_running = is_run;
2077 avic_vcpu_load(vcpu, vcpu->cpu);
2079 avic_vcpu_put(vcpu);
2082 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2084 struct vcpu_svm *svm = to_svm(vcpu);
2088 vcpu->arch.microcode_version = 0x01000065;
2090 svm->virt_spec_ctrl = 0;
2093 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2094 MSR_IA32_APICBASE_ENABLE;
2095 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2096 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2100 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2101 kvm_rdx_write(vcpu, eax);
2103 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2104 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2107 static int avic_init_vcpu(struct vcpu_svm *svm)
2111 if (!kvm_vcpu_apicv_active(&svm->vcpu))
2114 ret = avic_init_backing_page(&svm->vcpu);
2118 INIT_LIST_HEAD(&svm->ir_list);
2119 spin_lock_init(&svm->ir_list_lock);
2120 svm->dfr_reg = APIC_DFR_FLAT;
2125 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2127 struct vcpu_svm *svm;
2129 struct page *msrpm_pages;
2130 struct page *hsave_page;
2131 struct page *nested_msrpm_pages;
2134 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
2140 svm->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
2141 GFP_KERNEL_ACCOUNT);
2142 if (!svm->vcpu.arch.guest_fpu) {
2143 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
2145 goto free_partial_svm;
2148 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2153 page = alloc_page(GFP_KERNEL_ACCOUNT);
2157 msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2161 nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2162 if (!nested_msrpm_pages)
2165 hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
2169 err = avic_init_vcpu(svm);
2173 /* We initialize this flag to true to make sure that the is_running
2174 * bit would be set the first time the vcpu is loaded.
2176 svm->avic_is_running = true;
2178 svm->nested.hsave = page_address(hsave_page);
2180 svm->msrpm = page_address(msrpm_pages);
2181 svm_vcpu_init_msrpm(svm->msrpm);
2183 svm->nested.msrpm = page_address(nested_msrpm_pages);
2184 svm_vcpu_init_msrpm(svm->nested.msrpm);
2186 svm->vmcb = page_address(page);
2187 clear_page(svm->vmcb);
2188 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2189 svm->asid_generation = 0;
2192 svm_init_osvw(&svm->vcpu);
2197 __free_page(hsave_page);
2199 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2201 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2205 kvm_vcpu_uninit(&svm->vcpu);
2207 kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2209 kmem_cache_free(kvm_vcpu_cache, svm);
2211 return ERR_PTR(err);
2214 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2218 for_each_online_cpu(i)
2219 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2222 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2224 struct vcpu_svm *svm = to_svm(vcpu);
2227 * The vmcb page can be recycled, causing a false negative in
2228 * svm_vcpu_load(). So, ensure that no logical CPU has this
2229 * vmcb page recorded as its current vmcb.
2231 svm_clear_current_vmcb(svm->vmcb);
2233 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2234 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2235 __free_page(virt_to_page(svm->nested.hsave));
2236 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2237 kvm_vcpu_uninit(vcpu);
2238 kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2239 kmem_cache_free(kvm_vcpu_cache, svm);
2242 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2244 struct vcpu_svm *svm = to_svm(vcpu);
2245 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2248 if (unlikely(cpu != vcpu->cpu)) {
2249 svm->asid_generation = 0;
2250 mark_all_dirty(svm->vmcb);
2253 #ifdef CONFIG_X86_64
2254 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2256 savesegment(fs, svm->host.fs);
2257 savesegment(gs, svm->host.gs);
2258 svm->host.ldt = kvm_read_ldt();
2260 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2261 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2263 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2264 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2265 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2266 __this_cpu_write(current_tsc_ratio, tsc_ratio);
2267 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2270 /* This assumes that the kernel never uses MSR_TSC_AUX */
2271 if (static_cpu_has(X86_FEATURE_RDTSCP))
2272 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2274 if (sd->current_vmcb != svm->vmcb) {
2275 sd->current_vmcb = svm->vmcb;
2276 indirect_branch_prediction_barrier();
2278 avic_vcpu_load(vcpu, cpu);
2281 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2283 struct vcpu_svm *svm = to_svm(vcpu);
2286 avic_vcpu_put(vcpu);
2288 ++vcpu->stat.host_state_reload;
2289 kvm_load_ldt(svm->host.ldt);
2290 #ifdef CONFIG_X86_64
2291 loadsegment(fs, svm->host.fs);
2292 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2293 load_gs_index(svm->host.gs);
2295 #ifdef CONFIG_X86_32_LAZY_GS
2296 loadsegment(gs, svm->host.gs);
2299 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2300 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2303 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2305 avic_set_running(vcpu, false);
2308 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2310 avic_set_running(vcpu, true);
2313 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2315 struct vcpu_svm *svm = to_svm(vcpu);
2316 unsigned long rflags = svm->vmcb->save.rflags;
2318 if (svm->nmi_singlestep) {
2319 /* Hide our flags if they were not set by the guest */
2320 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2321 rflags &= ~X86_EFLAGS_TF;
2322 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2323 rflags &= ~X86_EFLAGS_RF;
2328 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2330 if (to_svm(vcpu)->nmi_singlestep)
2331 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2334 * Any change of EFLAGS.VM is accompanied by a reload of SS
2335 * (caused by either a task switch or an inter-privilege IRET),
2336 * so we do not need to update the CPL here.
2338 to_svm(vcpu)->vmcb->save.rflags = rflags;
2341 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2344 case VCPU_EXREG_PDPTR:
2345 BUG_ON(!npt_enabled);
2346 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2353 static void svm_set_vintr(struct vcpu_svm *svm)
2355 set_intercept(svm, INTERCEPT_VINTR);
2358 static void svm_clear_vintr(struct vcpu_svm *svm)
2360 clr_intercept(svm, INTERCEPT_VINTR);
2363 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2365 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2368 case VCPU_SREG_CS: return &save->cs;
2369 case VCPU_SREG_DS: return &save->ds;
2370 case VCPU_SREG_ES: return &save->es;
2371 case VCPU_SREG_FS: return &save->fs;
2372 case VCPU_SREG_GS: return &save->gs;
2373 case VCPU_SREG_SS: return &save->ss;
2374 case VCPU_SREG_TR: return &save->tr;
2375 case VCPU_SREG_LDTR: return &save->ldtr;
2381 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2383 struct vmcb_seg *s = svm_seg(vcpu, seg);
2388 static void svm_get_segment(struct kvm_vcpu *vcpu,
2389 struct kvm_segment *var, int seg)
2391 struct vmcb_seg *s = svm_seg(vcpu, seg);
2393 var->base = s->base;
2394 var->limit = s->limit;
2395 var->selector = s->selector;
2396 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2397 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2398 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2399 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2400 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2401 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2402 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2405 * AMD CPUs circa 2014 track the G bit for all segments except CS.
2406 * However, the SVM spec states that the G bit is not observed by the
2407 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2408 * So let's synthesize a legal G bit for all segments, this helps
2409 * running KVM nested. It also helps cross-vendor migration, because
2410 * Intel's vmentry has a check on the 'G' bit.
2412 var->g = s->limit > 0xfffff;
2415 * AMD's VMCB does not have an explicit unusable field, so emulate it
2416 * for cross vendor migration purposes by "not present"
2418 var->unusable = !var->present;
2423 * Work around a bug where the busy flag in the tr selector
2433 * The accessed bit must always be set in the segment
2434 * descriptor cache, although it can be cleared in the
2435 * descriptor, the cached bit always remains at 1. Since
2436 * Intel has a check on this, set it here to support
2437 * cross-vendor migration.
2444 * On AMD CPUs sometimes the DB bit in the segment
2445 * descriptor is left as 1, although the whole segment has
2446 * been made unusable. Clear it here to pass an Intel VMX
2447 * entry check when cross vendor migrating.
2451 /* This is symmetric with svm_set_segment() */
2452 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2457 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2459 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2464 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2466 struct vcpu_svm *svm = to_svm(vcpu);
2468 dt->size = svm->vmcb->save.idtr.limit;
2469 dt->address = svm->vmcb->save.idtr.base;
2472 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2474 struct vcpu_svm *svm = to_svm(vcpu);
2476 svm->vmcb->save.idtr.limit = dt->size;
2477 svm->vmcb->save.idtr.base = dt->address ;
2478 mark_dirty(svm->vmcb, VMCB_DT);
2481 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2483 struct vcpu_svm *svm = to_svm(vcpu);
2485 dt->size = svm->vmcb->save.gdtr.limit;
2486 dt->address = svm->vmcb->save.gdtr.base;
2489 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2491 struct vcpu_svm *svm = to_svm(vcpu);
2493 svm->vmcb->save.gdtr.limit = dt->size;
2494 svm->vmcb->save.gdtr.base = dt->address ;
2495 mark_dirty(svm->vmcb, VMCB_DT);
2498 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2502 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2506 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2510 static void update_cr0_intercept(struct vcpu_svm *svm)
2512 ulong gcr0 = svm->vcpu.arch.cr0;
2513 u64 *hcr0 = &svm->vmcb->save.cr0;
2515 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2516 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2518 mark_dirty(svm->vmcb, VMCB_CR);
2520 if (gcr0 == *hcr0) {
2521 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2522 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2524 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2525 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2529 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2531 struct vcpu_svm *svm = to_svm(vcpu);
2533 #ifdef CONFIG_X86_64
2534 if (vcpu->arch.efer & EFER_LME) {
2535 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2536 vcpu->arch.efer |= EFER_LMA;
2537 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2540 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2541 vcpu->arch.efer &= ~EFER_LMA;
2542 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2546 vcpu->arch.cr0 = cr0;
2549 cr0 |= X86_CR0_PG | X86_CR0_WP;
2552 * re-enable caching here because the QEMU bios
2553 * does not do it - this results in some delay at
2556 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2557 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2558 svm->vmcb->save.cr0 = cr0;
2559 mark_dirty(svm->vmcb, VMCB_CR);
2560 update_cr0_intercept(svm);
2563 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2565 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2566 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2568 if (cr4 & X86_CR4_VMXE)
2571 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2572 svm_flush_tlb(vcpu, true);
2574 vcpu->arch.cr4 = cr4;
2577 cr4 |= host_cr4_mce;
2578 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2579 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2583 static void svm_set_segment(struct kvm_vcpu *vcpu,
2584 struct kvm_segment *var, int seg)
2586 struct vcpu_svm *svm = to_svm(vcpu);
2587 struct vmcb_seg *s = svm_seg(vcpu, seg);
2589 s->base = var->base;
2590 s->limit = var->limit;
2591 s->selector = var->selector;
2592 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2593 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2594 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2595 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2596 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2597 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2598 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2599 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2602 * This is always accurate, except if SYSRET returned to a segment
2603 * with SS.DPL != 3. Intel does not have this quirk, and always
2604 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2605 * would entail passing the CPL to userspace and back.
2607 if (seg == VCPU_SREG_SS)
2608 /* This is symmetric with svm_get_segment() */
2609 svm->vmcb->save.cpl = (var->dpl & 3);
2611 mark_dirty(svm->vmcb, VMCB_SEG);
2614 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2616 struct vcpu_svm *svm = to_svm(vcpu);
2618 clr_exception_intercept(svm, BP_VECTOR);
2620 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2621 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2622 set_exception_intercept(svm, BP_VECTOR);
2624 vcpu->guest_debug = 0;
2627 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2629 if (sd->next_asid > sd->max_asid) {
2630 ++sd->asid_generation;
2631 sd->next_asid = sd->min_asid;
2632 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2635 svm->asid_generation = sd->asid_generation;
2636 svm->vmcb->control.asid = sd->next_asid++;
2638 mark_dirty(svm->vmcb, VMCB_ASID);
2641 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2643 return to_svm(vcpu)->vmcb->save.dr6;
2646 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2648 struct vcpu_svm *svm = to_svm(vcpu);
2650 svm->vmcb->save.dr6 = value;
2651 mark_dirty(svm->vmcb, VMCB_DR);
2654 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2656 struct vcpu_svm *svm = to_svm(vcpu);
2658 get_debugreg(vcpu->arch.db[0], 0);
2659 get_debugreg(vcpu->arch.db[1], 1);
2660 get_debugreg(vcpu->arch.db[2], 2);
2661 get_debugreg(vcpu->arch.db[3], 3);
2662 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2663 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2665 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2666 set_dr_intercepts(svm);
2669 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2671 struct vcpu_svm *svm = to_svm(vcpu);
2673 svm->vmcb->save.dr7 = value;
2674 mark_dirty(svm->vmcb, VMCB_DR);
2677 static int pf_interception(struct vcpu_svm *svm)
2679 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2680 u64 error_code = svm->vmcb->control.exit_info_1;
2682 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2683 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2684 svm->vmcb->control.insn_bytes : NULL,
2685 svm->vmcb->control.insn_len);
2688 static int npf_interception(struct vcpu_svm *svm)
2690 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2691 u64 error_code = svm->vmcb->control.exit_info_1;
2693 trace_kvm_page_fault(fault_address, error_code);
2694 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2695 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2696 svm->vmcb->control.insn_bytes : NULL,
2697 svm->vmcb->control.insn_len);
2700 static int db_interception(struct vcpu_svm *svm)
2702 struct kvm_run *kvm_run = svm->vcpu.run;
2703 struct kvm_vcpu *vcpu = &svm->vcpu;
2705 if (!(svm->vcpu.guest_debug &
2706 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2707 !svm->nmi_singlestep) {
2708 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2712 if (svm->nmi_singlestep) {
2713 disable_nmi_singlestep(svm);
2714 /* Make sure we check for pending NMIs upon entry */
2715 kvm_make_request(KVM_REQ_EVENT, vcpu);
2718 if (svm->vcpu.guest_debug &
2719 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2720 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2721 kvm_run->debug.arch.pc =
2722 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2723 kvm_run->debug.arch.exception = DB_VECTOR;
2730 static int bp_interception(struct vcpu_svm *svm)
2732 struct kvm_run *kvm_run = svm->vcpu.run;
2734 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2735 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2736 kvm_run->debug.arch.exception = BP_VECTOR;
2740 static int ud_interception(struct vcpu_svm *svm)
2742 return handle_ud(&svm->vcpu);
2745 static int ac_interception(struct vcpu_svm *svm)
2747 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2751 static int gp_interception(struct vcpu_svm *svm)
2753 struct kvm_vcpu *vcpu = &svm->vcpu;
2754 u32 error_code = svm->vmcb->control.exit_info_1;
2757 WARN_ON_ONCE(!enable_vmware_backdoor);
2759 er = kvm_emulate_instruction(vcpu,
2760 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2761 if (er == EMULATE_USER_EXIT)
2763 else if (er != EMULATE_DONE)
2764 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2768 static bool is_erratum_383(void)
2773 if (!erratum_383_found)
2776 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2780 /* Bit 62 may or may not be set for this mce */
2781 value &= ~(1ULL << 62);
2783 if (value != 0xb600000000010015ULL)
2786 /* Clear MCi_STATUS registers */
2787 for (i = 0; i < 6; ++i)
2788 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2790 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2794 value &= ~(1ULL << 2);
2795 low = lower_32_bits(value);
2796 high = upper_32_bits(value);
2798 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2801 /* Flush tlb to evict multi-match entries */
2807 static void svm_handle_mce(struct vcpu_svm *svm)
2809 if (is_erratum_383()) {
2811 * Erratum 383 triggered. Guest state is corrupt so kill the
2814 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2816 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2822 * On an #MC intercept the MCE handler is not called automatically in
2823 * the host. So do it by hand here.
2827 /* not sure if we ever come back to this point */
2832 static int mc_interception(struct vcpu_svm *svm)
2837 static int shutdown_interception(struct vcpu_svm *svm)
2839 struct kvm_run *kvm_run = svm->vcpu.run;
2842 * VMCB is undefined after a SHUTDOWN intercept
2843 * so reinitialize it.
2845 clear_page(svm->vmcb);
2848 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2852 static int io_interception(struct vcpu_svm *svm)
2854 struct kvm_vcpu *vcpu = &svm->vcpu;
2855 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2856 int size, in, string;
2859 ++svm->vcpu.stat.io_exits;
2860 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2861 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2863 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
2865 port = io_info >> 16;
2866 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2867 svm->next_rip = svm->vmcb->control.exit_info_2;
2869 return kvm_fast_pio(&svm->vcpu, size, port, in);
2872 static int nmi_interception(struct vcpu_svm *svm)
2877 static int intr_interception(struct vcpu_svm *svm)
2879 ++svm->vcpu.stat.irq_exits;
2883 static int nop_on_interception(struct vcpu_svm *svm)
2888 static int halt_interception(struct vcpu_svm *svm)
2890 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2891 return kvm_emulate_halt(&svm->vcpu);
2894 static int vmmcall_interception(struct vcpu_svm *svm)
2896 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2897 return kvm_emulate_hypercall(&svm->vcpu);
2900 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2902 struct vcpu_svm *svm = to_svm(vcpu);
2904 return svm->nested.nested_cr3;
2907 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2909 struct vcpu_svm *svm = to_svm(vcpu);
2910 u64 cr3 = svm->nested.nested_cr3;
2914 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2915 offset_in_page(cr3) + index * 8, 8);
2921 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2924 struct vcpu_svm *svm = to_svm(vcpu);
2926 svm->vmcb->control.nested_cr3 = __sme_set(root);
2927 mark_dirty(svm->vmcb, VMCB_NPT);
2930 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2931 struct x86_exception *fault)
2933 struct vcpu_svm *svm = to_svm(vcpu);
2935 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2937 * TODO: track the cause of the nested page fault, and
2938 * correctly fill in the high bits of exit_info_1.
2940 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2941 svm->vmcb->control.exit_code_hi = 0;
2942 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2943 svm->vmcb->control.exit_info_2 = fault->address;
2946 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2947 svm->vmcb->control.exit_info_1 |= fault->error_code;
2950 * The present bit is always zero for page structure faults on real
2953 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2954 svm->vmcb->control.exit_info_1 &= ~1;
2956 nested_svm_vmexit(svm);
2959 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2961 WARN_ON(mmu_is_nested(vcpu));
2963 vcpu->arch.mmu = &vcpu->arch.guest_mmu;
2964 kvm_init_shadow_mmu(vcpu);
2965 vcpu->arch.mmu->set_cr3 = nested_svm_set_tdp_cr3;
2966 vcpu->arch.mmu->get_cr3 = nested_svm_get_tdp_cr3;
2967 vcpu->arch.mmu->get_pdptr = nested_svm_get_tdp_pdptr;
2968 vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
2969 vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu);
2970 reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
2971 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2974 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2976 vcpu->arch.mmu = &vcpu->arch.root_mmu;
2977 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
2980 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2982 if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2983 !is_paging(&svm->vcpu)) {
2984 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2988 if (svm->vmcb->save.cpl) {
2989 kvm_inject_gp(&svm->vcpu, 0);
2996 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2997 bool has_error_code, u32 error_code)
3001 if (!is_guest_mode(&svm->vcpu))
3004 vmexit = nested_svm_intercept(svm);
3005 if (vmexit != NESTED_EXIT_DONE)
3008 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
3009 svm->vmcb->control.exit_code_hi = 0;
3010 svm->vmcb->control.exit_info_1 = error_code;
3013 * EXITINFO2 is undefined for all exception intercepts other
3016 if (svm->vcpu.arch.exception.nested_apf)
3017 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
3018 else if (svm->vcpu.arch.exception.has_payload)
3019 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
3021 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
3023 svm->nested.exit_required = true;
3027 /* This function returns true if it is save to enable the irq window */
3028 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3030 if (!is_guest_mode(&svm->vcpu))
3033 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3036 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3040 * if vmexit was already requested (by intercepted exception
3041 * for instance) do not overwrite it with "external interrupt"
3044 if (svm->nested.exit_required)
3047 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
3048 svm->vmcb->control.exit_info_1 = 0;
3049 svm->vmcb->control.exit_info_2 = 0;
3051 if (svm->nested.intercept & 1ULL) {
3053 * The #vmexit can't be emulated here directly because this
3054 * code path runs with irqs and preemption disabled. A
3055 * #vmexit emulation might sleep. Only signal request for
3058 svm->nested.exit_required = true;
3059 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3066 /* This function returns true if it is save to enable the nmi window */
3067 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3069 if (!is_guest_mode(&svm->vcpu))
3072 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3075 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3076 svm->nested.exit_required = true;
3081 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3083 unsigned port, size, iopm_len;
3088 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3089 return NESTED_EXIT_HOST;
3091 port = svm->vmcb->control.exit_info_1 >> 16;
3092 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3093 SVM_IOIO_SIZE_SHIFT;
3094 gpa = svm->nested.vmcb_iopm + (port / 8);
3095 start_bit = port % 8;
3096 iopm_len = (start_bit + size > 8) ? 2 : 1;
3097 mask = (0xf >> (4 - size)) << start_bit;
3100 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3101 return NESTED_EXIT_DONE;
3103 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3106 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3108 u32 offset, msr, value;
3111 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3112 return NESTED_EXIT_HOST;
3114 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3115 offset = svm_msrpm_offset(msr);
3116 write = svm->vmcb->control.exit_info_1 & 1;
3117 mask = 1 << ((2 * (msr & 0xf)) + write);
3119 if (offset == MSR_INVALID)
3120 return NESTED_EXIT_DONE;
3122 /* Offset is in 32 bit units but need in 8 bit units */
3125 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3126 return NESTED_EXIT_DONE;
3128 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3131 /* DB exceptions for our internal use must not cause vmexit */
3132 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3136 /* if we're not singlestepping, it's not ours */
3137 if (!svm->nmi_singlestep)
3138 return NESTED_EXIT_DONE;
3140 /* if it's not a singlestep exception, it's not ours */
3141 if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3142 return NESTED_EXIT_DONE;
3143 if (!(dr6 & DR6_BS))
3144 return NESTED_EXIT_DONE;
3146 /* if the guest is singlestepping, it should get the vmexit */
3147 if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3148 disable_nmi_singlestep(svm);
3149 return NESTED_EXIT_DONE;
3152 /* it's ours, the nested hypervisor must not see this one */
3153 return NESTED_EXIT_HOST;
3156 static int nested_svm_exit_special(struct vcpu_svm *svm)
3158 u32 exit_code = svm->vmcb->control.exit_code;
3160 switch (exit_code) {
3163 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3164 return NESTED_EXIT_HOST;
3166 /* For now we are always handling NPFs when using them */
3168 return NESTED_EXIT_HOST;
3170 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3171 /* When we're shadowing, trap PFs, but not async PF */
3172 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3173 return NESTED_EXIT_HOST;
3179 return NESTED_EXIT_CONTINUE;
3183 * If this function returns true, this #vmexit was already handled
3185 static int nested_svm_intercept(struct vcpu_svm *svm)
3187 u32 exit_code = svm->vmcb->control.exit_code;
3188 int vmexit = NESTED_EXIT_HOST;
3190 switch (exit_code) {
3192 vmexit = nested_svm_exit_handled_msr(svm);
3195 vmexit = nested_svm_intercept_ioio(svm);
3197 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3198 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3199 if (svm->nested.intercept_cr & bit)
3200 vmexit = NESTED_EXIT_DONE;
3203 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3204 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3205 if (svm->nested.intercept_dr & bit)
3206 vmexit = NESTED_EXIT_DONE;
3209 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3210 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3211 if (svm->nested.intercept_exceptions & excp_bits) {
3212 if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3213 vmexit = nested_svm_intercept_db(svm);
3215 vmexit = NESTED_EXIT_DONE;
3217 /* async page fault always cause vmexit */
3218 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3219 svm->vcpu.arch.exception.nested_apf != 0)
3220 vmexit = NESTED_EXIT_DONE;
3223 case SVM_EXIT_ERR: {
3224 vmexit = NESTED_EXIT_DONE;
3228 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3229 if (svm->nested.intercept & exit_bits)
3230 vmexit = NESTED_EXIT_DONE;
3237 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3241 vmexit = nested_svm_intercept(svm);
3243 if (vmexit == NESTED_EXIT_DONE)
3244 nested_svm_vmexit(svm);
3249 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3251 struct vmcb_control_area *dst = &dst_vmcb->control;
3252 struct vmcb_control_area *from = &from_vmcb->control;
3254 dst->intercept_cr = from->intercept_cr;
3255 dst->intercept_dr = from->intercept_dr;
3256 dst->intercept_exceptions = from->intercept_exceptions;
3257 dst->intercept = from->intercept;
3258 dst->iopm_base_pa = from->iopm_base_pa;
3259 dst->msrpm_base_pa = from->msrpm_base_pa;
3260 dst->tsc_offset = from->tsc_offset;
3261 dst->asid = from->asid;
3262 dst->tlb_ctl = from->tlb_ctl;
3263 dst->int_ctl = from->int_ctl;
3264 dst->int_vector = from->int_vector;
3265 dst->int_state = from->int_state;
3266 dst->exit_code = from->exit_code;
3267 dst->exit_code_hi = from->exit_code_hi;
3268 dst->exit_info_1 = from->exit_info_1;
3269 dst->exit_info_2 = from->exit_info_2;
3270 dst->exit_int_info = from->exit_int_info;
3271 dst->exit_int_info_err = from->exit_int_info_err;
3272 dst->nested_ctl = from->nested_ctl;
3273 dst->event_inj = from->event_inj;
3274 dst->event_inj_err = from->event_inj_err;
3275 dst->nested_cr3 = from->nested_cr3;
3276 dst->virt_ext = from->virt_ext;
3277 dst->pause_filter_count = from->pause_filter_count;
3278 dst->pause_filter_thresh = from->pause_filter_thresh;
3281 static int nested_svm_vmexit(struct vcpu_svm *svm)
3284 struct vmcb *nested_vmcb;
3285 struct vmcb *hsave = svm->nested.hsave;
3286 struct vmcb *vmcb = svm->vmcb;
3287 struct kvm_host_map map;
3289 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3290 vmcb->control.exit_info_1,
3291 vmcb->control.exit_info_2,
3292 vmcb->control.exit_int_info,
3293 vmcb->control.exit_int_info_err,
3296 rc = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->nested.vmcb), &map);
3299 kvm_inject_gp(&svm->vcpu, 0);
3303 nested_vmcb = map.hva;
3305 /* Exit Guest-Mode */
3306 leave_guest_mode(&svm->vcpu);
3307 svm->nested.vmcb = 0;
3309 /* Give the current vmcb to the guest */
3312 nested_vmcb->save.es = vmcb->save.es;
3313 nested_vmcb->save.cs = vmcb->save.cs;
3314 nested_vmcb->save.ss = vmcb->save.ss;
3315 nested_vmcb->save.ds = vmcb->save.ds;
3316 nested_vmcb->save.gdtr = vmcb->save.gdtr;
3317 nested_vmcb->save.idtr = vmcb->save.idtr;
3318 nested_vmcb->save.efer = svm->vcpu.arch.efer;
3319 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
3320 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
3321 nested_vmcb->save.cr2 = vmcb->save.cr2;
3322 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
3323 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3324 nested_vmcb->save.rip = vmcb->save.rip;
3325 nested_vmcb->save.rsp = vmcb->save.rsp;
3326 nested_vmcb->save.rax = vmcb->save.rax;
3327 nested_vmcb->save.dr7 = vmcb->save.dr7;
3328 nested_vmcb->save.dr6 = vmcb->save.dr6;
3329 nested_vmcb->save.cpl = vmcb->save.cpl;
3331 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
3332 nested_vmcb->control.int_vector = vmcb->control.int_vector;
3333 nested_vmcb->control.int_state = vmcb->control.int_state;
3334 nested_vmcb->control.exit_code = vmcb->control.exit_code;
3335 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
3336 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
3337 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
3338 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
3339 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3341 if (svm->nrips_enabled)
3342 nested_vmcb->control.next_rip = vmcb->control.next_rip;
3345 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3346 * to make sure that we do not lose injected events. So check event_inj
3347 * here and copy it to exit_int_info if it is valid.
3348 * Exit_int_info and event_inj can't be both valid because the case
3349 * below only happens on a VMRUN instruction intercept which has
3350 * no valid exit_int_info set.
3352 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3353 struct vmcb_control_area *nc = &nested_vmcb->control;
3355 nc->exit_int_info = vmcb->control.event_inj;
3356 nc->exit_int_info_err = vmcb->control.event_inj_err;
3359 nested_vmcb->control.tlb_ctl = 0;
3360 nested_vmcb->control.event_inj = 0;
3361 nested_vmcb->control.event_inj_err = 0;
3363 nested_vmcb->control.pause_filter_count =
3364 svm->vmcb->control.pause_filter_count;
3365 nested_vmcb->control.pause_filter_thresh =
3366 svm->vmcb->control.pause_filter_thresh;
3368 /* We always set V_INTR_MASKING and remember the old value in hflags */
3369 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3370 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3372 /* Restore the original control entries */
3373 copy_vmcb_control_area(vmcb, hsave);
3375 svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3376 kvm_clear_exception_queue(&svm->vcpu);
3377 kvm_clear_interrupt_queue(&svm->vcpu);
3379 svm->nested.nested_cr3 = 0;
3381 /* Restore selected save entries */
3382 svm->vmcb->save.es = hsave->save.es;
3383 svm->vmcb->save.cs = hsave->save.cs;
3384 svm->vmcb->save.ss = hsave->save.ss;
3385 svm->vmcb->save.ds = hsave->save.ds;
3386 svm->vmcb->save.gdtr = hsave->save.gdtr;
3387 svm->vmcb->save.idtr = hsave->save.idtr;
3388 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3389 svm_set_efer(&svm->vcpu, hsave->save.efer);
3390 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3391 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3393 svm->vmcb->save.cr3 = hsave->save.cr3;
3394 svm->vcpu.arch.cr3 = hsave->save.cr3;
3396 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3398 kvm_rax_write(&svm->vcpu, hsave->save.rax);
3399 kvm_rsp_write(&svm->vcpu, hsave->save.rsp);
3400 kvm_rip_write(&svm->vcpu, hsave->save.rip);
3401 svm->vmcb->save.dr7 = 0;
3402 svm->vmcb->save.cpl = 0;
3403 svm->vmcb->control.exit_int_info = 0;
3405 mark_all_dirty(svm->vmcb);
3407 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3409 nested_svm_uninit_mmu_context(&svm->vcpu);
3410 kvm_mmu_reset_context(&svm->vcpu);
3411 kvm_mmu_load(&svm->vcpu);
3414 * Drop what we picked up for L2 via svm_complete_interrupts() so it
3415 * doesn't end up in L1.
3417 svm->vcpu.arch.nmi_injected = false;
3418 kvm_clear_exception_queue(&svm->vcpu);
3419 kvm_clear_interrupt_queue(&svm->vcpu);
3424 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3427 * This function merges the msr permission bitmaps of kvm and the
3428 * nested vmcb. It is optimized in that it only merges the parts where
3429 * the kvm msr permission bitmap may contain zero bits
3433 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3436 for (i = 0; i < MSRPM_OFFSETS; i++) {
3440 if (msrpm_offsets[i] == 0xffffffff)
3443 p = msrpm_offsets[i];
3444 offset = svm->nested.vmcb_msrpm + (p * 4);
3446 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3449 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3452 svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3457 static bool nested_vmcb_checks(struct vmcb *vmcb)
3459 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3462 if (vmcb->control.asid == 0)
3465 if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3472 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3473 struct vmcb *nested_vmcb, struct kvm_host_map *map)
3475 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3476 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3478 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3480 if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3481 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3482 nested_svm_init_mmu_context(&svm->vcpu);
3485 /* Load the nested guest state */
3486 svm->vmcb->save.es = nested_vmcb->save.es;
3487 svm->vmcb->save.cs = nested_vmcb->save.cs;
3488 svm->vmcb->save.ss = nested_vmcb->save.ss;
3489 svm->vmcb->save.ds = nested_vmcb->save.ds;
3490 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3491 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3492 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3493 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3494 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3495 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3497 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3498 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3500 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3502 /* Guest paging mode is active - reset mmu */
3503 kvm_mmu_reset_context(&svm->vcpu);
3505 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3506 kvm_rax_write(&svm->vcpu, nested_vmcb->save.rax);
3507 kvm_rsp_write(&svm->vcpu, nested_vmcb->save.rsp);
3508 kvm_rip_write(&svm->vcpu, nested_vmcb->save.rip);
3510 /* In case we don't even reach vcpu_run, the fields are not updated */
3511 svm->vmcb->save.rax = nested_vmcb->save.rax;
3512 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3513 svm->vmcb->save.rip = nested_vmcb->save.rip;
3514 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3515 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3516 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3518 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3519 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3521 /* cache intercepts */
3522 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3523 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3524 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3525 svm->nested.intercept = nested_vmcb->control.intercept;
3527 svm_flush_tlb(&svm->vcpu, true);
3528 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3529 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3530 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3532 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3534 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3535 /* We only want the cr8 intercept bits of the guest */
3536 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3537 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3540 /* We don't want to see VMMCALLs from a nested guest */
3541 clr_intercept(svm, INTERCEPT_VMMCALL);
3543 svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3544 svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3546 svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3547 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3548 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3549 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3550 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3552 svm->vmcb->control.pause_filter_count =
3553 nested_vmcb->control.pause_filter_count;
3554 svm->vmcb->control.pause_filter_thresh =
3555 nested_vmcb->control.pause_filter_thresh;
3557 kvm_vcpu_unmap(&svm->vcpu, map, true);
3559 /* Enter Guest-Mode */
3560 enter_guest_mode(&svm->vcpu);
3563 * Merge guest and host intercepts - must be called with vcpu in
3564 * guest-mode to take affect here
3566 recalc_intercepts(svm);
3568 svm->nested.vmcb = vmcb_gpa;
3572 mark_all_dirty(svm->vmcb);
3575 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3578 struct vmcb *nested_vmcb;
3579 struct vmcb *hsave = svm->nested.hsave;
3580 struct vmcb *vmcb = svm->vmcb;
3581 struct kvm_host_map map;
3584 vmcb_gpa = svm->vmcb->save.rax;
3586 rc = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb_gpa), &map);
3589 kvm_inject_gp(&svm->vcpu, 0);
3593 nested_vmcb = map.hva;
3595 if (!nested_vmcb_checks(nested_vmcb)) {
3596 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
3597 nested_vmcb->control.exit_code_hi = 0;
3598 nested_vmcb->control.exit_info_1 = 0;
3599 nested_vmcb->control.exit_info_2 = 0;
3601 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3606 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3607 nested_vmcb->save.rip,
3608 nested_vmcb->control.int_ctl,
3609 nested_vmcb->control.event_inj,
3610 nested_vmcb->control.nested_ctl);
3612 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3613 nested_vmcb->control.intercept_cr >> 16,
3614 nested_vmcb->control.intercept_exceptions,
3615 nested_vmcb->control.intercept);
3617 /* Clear internal status */
3618 kvm_clear_exception_queue(&svm->vcpu);
3619 kvm_clear_interrupt_queue(&svm->vcpu);
3622 * Save the old vmcb, so we don't need to pick what we save, but can
3623 * restore everything when a VMEXIT occurs
3625 hsave->save.es = vmcb->save.es;
3626 hsave->save.cs = vmcb->save.cs;
3627 hsave->save.ss = vmcb->save.ss;
3628 hsave->save.ds = vmcb->save.ds;
3629 hsave->save.gdtr = vmcb->save.gdtr;
3630 hsave->save.idtr = vmcb->save.idtr;
3631 hsave->save.efer = svm->vcpu.arch.efer;
3632 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
3633 hsave->save.cr4 = svm->vcpu.arch.cr4;
3634 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3635 hsave->save.rip = kvm_rip_read(&svm->vcpu);
3636 hsave->save.rsp = vmcb->save.rsp;
3637 hsave->save.rax = vmcb->save.rax;
3639 hsave->save.cr3 = vmcb->save.cr3;
3641 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
3643 copy_vmcb_control_area(hsave, vmcb);
3645 enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, &map);
3650 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3652 to_vmcb->save.fs = from_vmcb->save.fs;
3653 to_vmcb->save.gs = from_vmcb->save.gs;
3654 to_vmcb->save.tr = from_vmcb->save.tr;
3655 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3656 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3657 to_vmcb->save.star = from_vmcb->save.star;
3658 to_vmcb->save.lstar = from_vmcb->save.lstar;
3659 to_vmcb->save.cstar = from_vmcb->save.cstar;
3660 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3661 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3662 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3663 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3666 static int vmload_interception(struct vcpu_svm *svm)
3668 struct vmcb *nested_vmcb;
3669 struct kvm_host_map map;
3672 if (nested_svm_check_permissions(svm))
3675 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3678 kvm_inject_gp(&svm->vcpu, 0);
3682 nested_vmcb = map.hva;
3684 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3685 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3687 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3688 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3693 static int vmsave_interception(struct vcpu_svm *svm)
3695 struct vmcb *nested_vmcb;
3696 struct kvm_host_map map;
3699 if (nested_svm_check_permissions(svm))
3702 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3705 kvm_inject_gp(&svm->vcpu, 0);
3709 nested_vmcb = map.hva;
3711 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3712 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3714 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3715 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3720 static int vmrun_interception(struct vcpu_svm *svm)
3722 if (nested_svm_check_permissions(svm))
3725 /* Save rip after vmrun instruction */
3726 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3728 if (!nested_svm_vmrun(svm))
3731 if (!nested_svm_vmrun_msrpm(svm))
3738 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3739 svm->vmcb->control.exit_code_hi = 0;
3740 svm->vmcb->control.exit_info_1 = 0;
3741 svm->vmcb->control.exit_info_2 = 0;
3743 nested_svm_vmexit(svm);
3748 static int stgi_interception(struct vcpu_svm *svm)
3752 if (nested_svm_check_permissions(svm))
3756 * If VGIF is enabled, the STGI intercept is only added to
3757 * detect the opening of the SMI/NMI window; remove it now.
3759 if (vgif_enabled(svm))
3760 clr_intercept(svm, INTERCEPT_STGI);
3762 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3763 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3764 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3771 static int clgi_interception(struct vcpu_svm *svm)
3775 if (nested_svm_check_permissions(svm))
3778 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3779 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3783 /* After a CLGI no interrupts should come */
3784 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3785 svm_clear_vintr(svm);
3786 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3787 mark_dirty(svm->vmcb, VMCB_INTR);
3793 static int invlpga_interception(struct vcpu_svm *svm)
3795 struct kvm_vcpu *vcpu = &svm->vcpu;
3797 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
3798 kvm_rax_read(&svm->vcpu));
3800 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3801 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
3803 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3804 return kvm_skip_emulated_instruction(&svm->vcpu);
3807 static int skinit_interception(struct vcpu_svm *svm)
3809 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
3811 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3815 static int wbinvd_interception(struct vcpu_svm *svm)
3817 return kvm_emulate_wbinvd(&svm->vcpu);
3820 static int xsetbv_interception(struct vcpu_svm *svm)
3822 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3823 u32 index = kvm_rcx_read(&svm->vcpu);
3825 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3826 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3827 return kvm_skip_emulated_instruction(&svm->vcpu);
3833 static int task_switch_interception(struct vcpu_svm *svm)
3837 int int_type = svm->vmcb->control.exit_int_info &
3838 SVM_EXITINTINFO_TYPE_MASK;
3839 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3841 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3843 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3844 bool has_error_code = false;
3847 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3849 if (svm->vmcb->control.exit_info_2 &
3850 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3851 reason = TASK_SWITCH_IRET;
3852 else if (svm->vmcb->control.exit_info_2 &
3853 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3854 reason = TASK_SWITCH_JMP;
3856 reason = TASK_SWITCH_GATE;
3858 reason = TASK_SWITCH_CALL;
3860 if (reason == TASK_SWITCH_GATE) {
3862 case SVM_EXITINTINFO_TYPE_NMI:
3863 svm->vcpu.arch.nmi_injected = false;
3865 case SVM_EXITINTINFO_TYPE_EXEPT:
3866 if (svm->vmcb->control.exit_info_2 &
3867 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3868 has_error_code = true;
3870 (u32)svm->vmcb->control.exit_info_2;
3872 kvm_clear_exception_queue(&svm->vcpu);
3874 case SVM_EXITINTINFO_TYPE_INTR:
3875 kvm_clear_interrupt_queue(&svm->vcpu);
3882 if (reason != TASK_SWITCH_GATE ||
3883 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3884 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3885 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3886 skip_emulated_instruction(&svm->vcpu);
3888 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3891 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3892 has_error_code, error_code) == EMULATE_FAIL) {
3893 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3894 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3895 svm->vcpu.run->internal.ndata = 0;
3901 static int cpuid_interception(struct vcpu_svm *svm)
3903 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3904 return kvm_emulate_cpuid(&svm->vcpu);
3907 static int iret_interception(struct vcpu_svm *svm)
3909 ++svm->vcpu.stat.nmi_window_exits;
3910 clr_intercept(svm, INTERCEPT_IRET);
3911 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3912 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3913 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3917 static int invlpg_interception(struct vcpu_svm *svm)
3919 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3920 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3922 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3923 return kvm_skip_emulated_instruction(&svm->vcpu);
3926 static int emulate_on_interception(struct vcpu_svm *svm)
3928 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3931 static int rsm_interception(struct vcpu_svm *svm)
3933 return kvm_emulate_instruction_from_buffer(&svm->vcpu,
3934 rsm_ins_bytes, 2) == EMULATE_DONE;
3937 static int rdpmc_interception(struct vcpu_svm *svm)
3941 if (!static_cpu_has(X86_FEATURE_NRIPS))
3942 return emulate_on_interception(svm);
3944 err = kvm_rdpmc(&svm->vcpu);
3945 return kvm_complete_insn_gp(&svm->vcpu, err);
3948 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3951 unsigned long cr0 = svm->vcpu.arch.cr0;
3955 intercept = svm->nested.intercept;
3957 if (!is_guest_mode(&svm->vcpu) ||
3958 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3961 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3962 val &= ~SVM_CR0_SELECTIVE_MASK;
3965 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3966 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3972 #define CR_VALID (1ULL << 63)
3974 static int cr_interception(struct vcpu_svm *svm)
3980 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3981 return emulate_on_interception(svm);
3983 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3984 return emulate_on_interception(svm);
3986 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3987 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3988 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3990 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3993 if (cr >= 16) { /* mov to cr */
3995 val = kvm_register_read(&svm->vcpu, reg);
3998 if (!check_selective_cr0_intercepted(svm, val))
3999 err = kvm_set_cr0(&svm->vcpu, val);
4005 err = kvm_set_cr3(&svm->vcpu, val);
4008 err = kvm_set_cr4(&svm->vcpu, val);
4011 err = kvm_set_cr8(&svm->vcpu, val);
4014 WARN(1, "unhandled write to CR%d", cr);
4015 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4018 } else { /* mov from cr */
4021 val = kvm_read_cr0(&svm->vcpu);
4024 val = svm->vcpu.arch.cr2;
4027 val = kvm_read_cr3(&svm->vcpu);
4030 val = kvm_read_cr4(&svm->vcpu);
4033 val = kvm_get_cr8(&svm->vcpu);
4036 WARN(1, "unhandled read from CR%d", cr);
4037 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4040 kvm_register_write(&svm->vcpu, reg, val);
4042 return kvm_complete_insn_gp(&svm->vcpu, err);
4045 static int dr_interception(struct vcpu_svm *svm)
4050 if (svm->vcpu.guest_debug == 0) {
4052 * No more DR vmexits; force a reload of the debug registers
4053 * and reenter on this instruction. The next vmexit will
4054 * retrieve the full state of the debug registers.
4056 clr_dr_intercepts(svm);
4057 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4061 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4062 return emulate_on_interception(svm);
4064 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4065 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4067 if (dr >= 16) { /* mov to DRn */
4068 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4070 val = kvm_register_read(&svm->vcpu, reg);
4071 kvm_set_dr(&svm->vcpu, dr - 16, val);
4073 if (!kvm_require_dr(&svm->vcpu, dr))
4075 kvm_get_dr(&svm->vcpu, dr, &val);
4076 kvm_register_write(&svm->vcpu, reg, val);
4079 return kvm_skip_emulated_instruction(&svm->vcpu);
4082 static int cr8_write_interception(struct vcpu_svm *svm)
4084 struct kvm_run *kvm_run = svm->vcpu.run;
4087 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4088 /* instruction emulation calls kvm_set_cr8() */
4089 r = cr_interception(svm);
4090 if (lapic_in_kernel(&svm->vcpu))
4092 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4094 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4098 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4102 switch (msr->index) {
4103 case MSR_F10H_DECFG:
4104 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4105 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4114 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4116 struct vcpu_svm *svm = to_svm(vcpu);
4118 switch (msr_info->index) {
4120 msr_info->data = svm->vmcb->save.star;
4122 #ifdef CONFIG_X86_64
4124 msr_info->data = svm->vmcb->save.lstar;
4127 msr_info->data = svm->vmcb->save.cstar;
4129 case MSR_KERNEL_GS_BASE:
4130 msr_info->data = svm->vmcb->save.kernel_gs_base;
4132 case MSR_SYSCALL_MASK:
4133 msr_info->data = svm->vmcb->save.sfmask;
4136 case MSR_IA32_SYSENTER_CS:
4137 msr_info->data = svm->vmcb->save.sysenter_cs;
4139 case MSR_IA32_SYSENTER_EIP:
4140 msr_info->data = svm->sysenter_eip;
4142 case MSR_IA32_SYSENTER_ESP:
4143 msr_info->data = svm->sysenter_esp;
4146 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4148 msr_info->data = svm->tsc_aux;
4151 * Nobody will change the following 5 values in the VMCB so we can
4152 * safely return them on rdmsr. They will always be 0 until LBRV is
4155 case MSR_IA32_DEBUGCTLMSR:
4156 msr_info->data = svm->vmcb->save.dbgctl;
4158 case MSR_IA32_LASTBRANCHFROMIP:
4159 msr_info->data = svm->vmcb->save.br_from;
4161 case MSR_IA32_LASTBRANCHTOIP:
4162 msr_info->data = svm->vmcb->save.br_to;
4164 case MSR_IA32_LASTINTFROMIP:
4165 msr_info->data = svm->vmcb->save.last_excp_from;
4167 case MSR_IA32_LASTINTTOIP:
4168 msr_info->data = svm->vmcb->save.last_excp_to;
4170 case MSR_VM_HSAVE_PA:
4171 msr_info->data = svm->nested.hsave_msr;
4174 msr_info->data = svm->nested.vm_cr_msr;
4176 case MSR_IA32_SPEC_CTRL:
4177 if (!msr_info->host_initiated &&
4178 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4179 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4182 msr_info->data = svm->spec_ctrl;
4184 case MSR_AMD64_VIRT_SPEC_CTRL:
4185 if (!msr_info->host_initiated &&
4186 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4189 msr_info->data = svm->virt_spec_ctrl;
4191 case MSR_F15H_IC_CFG: {
4195 family = guest_cpuid_family(vcpu);
4196 model = guest_cpuid_model(vcpu);
4198 if (family < 0 || model < 0)
4199 return kvm_get_msr_common(vcpu, msr_info);
4203 if (family == 0x15 &&
4204 (model >= 0x2 && model < 0x20))
4205 msr_info->data = 0x1E;
4208 case MSR_F10H_DECFG:
4209 msr_info->data = svm->msr_decfg;
4212 return kvm_get_msr_common(vcpu, msr_info);
4217 static int rdmsr_interception(struct vcpu_svm *svm)
4219 u32 ecx = kvm_rcx_read(&svm->vcpu);
4220 struct msr_data msr_info;
4222 msr_info.index = ecx;
4223 msr_info.host_initiated = false;
4224 if (svm_get_msr(&svm->vcpu, &msr_info)) {
4225 trace_kvm_msr_read_ex(ecx);
4226 kvm_inject_gp(&svm->vcpu, 0);
4229 trace_kvm_msr_read(ecx, msr_info.data);
4231 kvm_rax_write(&svm->vcpu, msr_info.data & 0xffffffff);
4232 kvm_rdx_write(&svm->vcpu, msr_info.data >> 32);
4233 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4234 return kvm_skip_emulated_instruction(&svm->vcpu);
4238 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4240 struct vcpu_svm *svm = to_svm(vcpu);
4241 int svm_dis, chg_mask;
4243 if (data & ~SVM_VM_CR_VALID_MASK)
4246 chg_mask = SVM_VM_CR_VALID_MASK;
4248 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4249 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4251 svm->nested.vm_cr_msr &= ~chg_mask;
4252 svm->nested.vm_cr_msr |= (data & chg_mask);
4254 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4256 /* check for svm_disable while efer.svme is set */
4257 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4263 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4265 struct vcpu_svm *svm = to_svm(vcpu);
4267 u32 ecx = msr->index;
4268 u64 data = msr->data;
4270 case MSR_IA32_CR_PAT:
4271 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4273 vcpu->arch.pat = data;
4274 svm->vmcb->save.g_pat = data;
4275 mark_dirty(svm->vmcb, VMCB_NPT);
4277 case MSR_IA32_SPEC_CTRL:
4278 if (!msr->host_initiated &&
4279 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4280 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4283 /* The STIBP bit doesn't fault even if it's not advertised */
4284 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4287 svm->spec_ctrl = data;
4294 * When it's written (to non-zero) for the first time, pass
4298 * The handling of the MSR bitmap for L2 guests is done in
4299 * nested_svm_vmrun_msrpm.
4300 * We update the L1 MSR bit as well since it will end up
4301 * touching the MSR anyway now.
4303 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4305 case MSR_IA32_PRED_CMD:
4306 if (!msr->host_initiated &&
4307 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4310 if (data & ~PRED_CMD_IBPB)
4316 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4317 if (is_guest_mode(vcpu))
4319 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4321 case MSR_AMD64_VIRT_SPEC_CTRL:
4322 if (!msr->host_initiated &&
4323 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4326 if (data & ~SPEC_CTRL_SSBD)
4329 svm->virt_spec_ctrl = data;
4332 svm->vmcb->save.star = data;
4334 #ifdef CONFIG_X86_64
4336 svm->vmcb->save.lstar = data;
4339 svm->vmcb->save.cstar = data;
4341 case MSR_KERNEL_GS_BASE:
4342 svm->vmcb->save.kernel_gs_base = data;
4344 case MSR_SYSCALL_MASK:
4345 svm->vmcb->save.sfmask = data;
4348 case MSR_IA32_SYSENTER_CS:
4349 svm->vmcb->save.sysenter_cs = data;
4351 case MSR_IA32_SYSENTER_EIP:
4352 svm->sysenter_eip = data;
4353 svm->vmcb->save.sysenter_eip = data;
4355 case MSR_IA32_SYSENTER_ESP:
4356 svm->sysenter_esp = data;
4357 svm->vmcb->save.sysenter_esp = data;
4360 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4364 * This is rare, so we update the MSR here instead of using
4365 * direct_access_msrs. Doing that would require a rdmsr in
4368 svm->tsc_aux = data;
4369 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4371 case MSR_IA32_DEBUGCTLMSR:
4372 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4373 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4377 if (data & DEBUGCTL_RESERVED_BITS)
4380 svm->vmcb->save.dbgctl = data;
4381 mark_dirty(svm->vmcb, VMCB_LBR);
4382 if (data & (1ULL<<0))
4383 svm_enable_lbrv(svm);
4385 svm_disable_lbrv(svm);
4387 case MSR_VM_HSAVE_PA:
4388 svm->nested.hsave_msr = data;
4391 return svm_set_vm_cr(vcpu, data);
4393 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4395 case MSR_F10H_DECFG: {
4396 struct kvm_msr_entry msr_entry;
4398 msr_entry.index = msr->index;
4399 if (svm_get_msr_feature(&msr_entry))
4402 /* Check the supported bits */
4403 if (data & ~msr_entry.data)
4406 /* Don't allow the guest to change a bit, #GP */
4407 if (!msr->host_initiated && (data ^ msr_entry.data))
4410 svm->msr_decfg = data;
4413 case MSR_IA32_APICBASE:
4414 if (kvm_vcpu_apicv_active(vcpu))
4415 avic_update_vapic_bar(to_svm(vcpu), data);
4418 return kvm_set_msr_common(vcpu, msr);
4423 static int wrmsr_interception(struct vcpu_svm *svm)
4425 struct msr_data msr;
4426 u32 ecx = kvm_rcx_read(&svm->vcpu);
4427 u64 data = kvm_read_edx_eax(&svm->vcpu);
4431 msr.host_initiated = false;
4433 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4434 if (kvm_set_msr(&svm->vcpu, &msr)) {
4435 trace_kvm_msr_write_ex(ecx, data);
4436 kvm_inject_gp(&svm->vcpu, 0);
4439 trace_kvm_msr_write(ecx, data);
4440 return kvm_skip_emulated_instruction(&svm->vcpu);
4444 static int msr_interception(struct vcpu_svm *svm)
4446 if (svm->vmcb->control.exit_info_1)
4447 return wrmsr_interception(svm);
4449 return rdmsr_interception(svm);
4452 static int interrupt_window_interception(struct vcpu_svm *svm)
4454 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4455 svm_clear_vintr(svm);
4456 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4457 mark_dirty(svm->vmcb, VMCB_INTR);
4458 ++svm->vcpu.stat.irq_window_exits;
4462 static int pause_interception(struct vcpu_svm *svm)
4464 struct kvm_vcpu *vcpu = &svm->vcpu;
4465 bool in_kernel = (svm_get_cpl(vcpu) == 0);
4467 if (pause_filter_thresh)
4468 grow_ple_window(vcpu);
4470 kvm_vcpu_on_spin(vcpu, in_kernel);
4474 static int nop_interception(struct vcpu_svm *svm)
4476 return kvm_skip_emulated_instruction(&(svm->vcpu));
4479 static int monitor_interception(struct vcpu_svm *svm)
4481 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4482 return nop_interception(svm);
4485 static int mwait_interception(struct vcpu_svm *svm)
4487 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4488 return nop_interception(svm);
4491 enum avic_ipi_failure_cause {
4492 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4493 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4494 AVIC_IPI_FAILURE_INVALID_TARGET,
4495 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4498 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4500 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4501 u32 icrl = svm->vmcb->control.exit_info_1;
4502 u32 id = svm->vmcb->control.exit_info_2 >> 32;
4503 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4504 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4506 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4509 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4511 * AVIC hardware handles the generation of
4512 * IPIs when the specified Message Type is Fixed
4513 * (also known as fixed delivery mode) and
4514 * the Trigger Mode is edge-triggered. The hardware
4515 * also supports self and broadcast delivery modes
4516 * specified via the Destination Shorthand(DSH)
4517 * field of the ICRL. Logical and physical APIC ID
4518 * formats are supported. All other IPI types cause
4519 * a #VMEXIT, which needs to emulated.
4521 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4522 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4524 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4526 struct kvm_vcpu *vcpu;
4527 struct kvm *kvm = svm->vcpu.kvm;
4528 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4531 * At this point, we expect that the AVIC HW has already
4532 * set the appropriate IRR bits on the valid target
4533 * vcpus. So, we just need to kick the appropriate vcpu.
4535 kvm_for_each_vcpu(i, vcpu, kvm) {
4536 bool m = kvm_apic_match_dest(vcpu, apic,
4537 icrl & KVM_APIC_SHORT_MASK,
4538 GET_APIC_DEST_FIELD(icrh),
4539 icrl & KVM_APIC_DEST_MASK);
4541 if (m && !avic_vcpu_is_running(vcpu))
4542 kvm_vcpu_wake_up(vcpu);
4546 case AVIC_IPI_FAILURE_INVALID_TARGET:
4547 WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n",
4548 index, svm->vcpu.vcpu_id, icrh, icrl);
4550 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4551 WARN_ONCE(1, "Invalid backing page\n");
4554 pr_err("Unknown IPI interception\n");
4560 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4562 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4564 u32 *logical_apic_id_table;
4565 int dlid = GET_APIC_LOGICAL_ID(ldr);
4570 if (flat) { /* flat */
4571 index = ffs(dlid) - 1;
4574 } else { /* cluster */
4575 int cluster = (dlid & 0xf0) >> 4;
4576 int apic = ffs(dlid & 0x0f) - 1;
4578 if ((apic < 0) || (apic > 7) ||
4581 index = (cluster << 2) + apic;
4584 logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4586 return &logical_apic_id_table[index];
4589 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr)
4592 u32 *entry, new_entry;
4594 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4595 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4599 new_entry = READ_ONCE(*entry);
4600 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4601 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4602 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4603 WRITE_ONCE(*entry, new_entry);
4608 static void avic_invalidate_logical_id_entry(struct kvm_vcpu *vcpu)
4610 struct vcpu_svm *svm = to_svm(vcpu);
4611 bool flat = svm->dfr_reg == APIC_DFR_FLAT;
4612 u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat);
4615 clear_bit(AVIC_LOGICAL_ID_ENTRY_VALID_BIT, (unsigned long *)entry);
4618 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4621 struct vcpu_svm *svm = to_svm(vcpu);
4622 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4624 if (ldr == svm->ldr_reg)
4627 avic_invalidate_logical_id_entry(vcpu);
4630 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr);
4638 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4641 struct vcpu_svm *svm = to_svm(vcpu);
4642 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4643 u32 id = (apic_id_reg >> 24) & 0xff;
4645 if (vcpu->vcpu_id == id)
4648 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4649 new = avic_get_physical_id_entry(vcpu, id);
4653 /* We need to move physical_id_entry to new offset */
4656 to_svm(vcpu)->avic_physical_id_cache = new;
4659 * Also update the guest physical APIC ID in the logical
4660 * APIC ID table entry if already setup the LDR.
4663 avic_handle_ldr_update(vcpu);
4668 static void avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4670 struct vcpu_svm *svm = to_svm(vcpu);
4671 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4673 if (svm->dfr_reg == dfr)
4676 avic_invalidate_logical_id_entry(vcpu);
4680 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4682 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4683 u32 offset = svm->vmcb->control.exit_info_1 &
4684 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4688 if (avic_handle_apic_id_update(&svm->vcpu))
4692 if (avic_handle_ldr_update(&svm->vcpu))
4696 avic_handle_dfr_update(&svm->vcpu);
4702 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4707 static bool is_avic_unaccelerated_access_trap(u32 offset)
4736 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4739 u32 offset = svm->vmcb->control.exit_info_1 &
4740 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4741 u32 vector = svm->vmcb->control.exit_info_2 &
4742 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4743 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4744 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4745 bool trap = is_avic_unaccelerated_access_trap(offset);
4747 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4748 trap, write, vector);
4751 WARN_ONCE(!write, "svm: Handling trap read.\n");
4752 ret = avic_unaccel_trap_write(svm);
4754 /* Handling Fault */
4755 ret = (kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4761 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4762 [SVM_EXIT_READ_CR0] = cr_interception,
4763 [SVM_EXIT_READ_CR3] = cr_interception,
4764 [SVM_EXIT_READ_CR4] = cr_interception,
4765 [SVM_EXIT_READ_CR8] = cr_interception,
4766 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4767 [SVM_EXIT_WRITE_CR0] = cr_interception,
4768 [SVM_EXIT_WRITE_CR3] = cr_interception,
4769 [SVM_EXIT_WRITE_CR4] = cr_interception,
4770 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4771 [SVM_EXIT_READ_DR0] = dr_interception,
4772 [SVM_EXIT_READ_DR1] = dr_interception,
4773 [SVM_EXIT_READ_DR2] = dr_interception,
4774 [SVM_EXIT_READ_DR3] = dr_interception,
4775 [SVM_EXIT_READ_DR4] = dr_interception,
4776 [SVM_EXIT_READ_DR5] = dr_interception,
4777 [SVM_EXIT_READ_DR6] = dr_interception,
4778 [SVM_EXIT_READ_DR7] = dr_interception,
4779 [SVM_EXIT_WRITE_DR0] = dr_interception,
4780 [SVM_EXIT_WRITE_DR1] = dr_interception,
4781 [SVM_EXIT_WRITE_DR2] = dr_interception,
4782 [SVM_EXIT_WRITE_DR3] = dr_interception,
4783 [SVM_EXIT_WRITE_DR4] = dr_interception,
4784 [SVM_EXIT_WRITE_DR5] = dr_interception,
4785 [SVM_EXIT_WRITE_DR6] = dr_interception,
4786 [SVM_EXIT_WRITE_DR7] = dr_interception,
4787 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4788 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4789 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4790 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4791 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4792 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4793 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
4794 [SVM_EXIT_INTR] = intr_interception,
4795 [SVM_EXIT_NMI] = nmi_interception,
4796 [SVM_EXIT_SMI] = nop_on_interception,
4797 [SVM_EXIT_INIT] = nop_on_interception,
4798 [SVM_EXIT_VINTR] = interrupt_window_interception,
4799 [SVM_EXIT_RDPMC] = rdpmc_interception,
4800 [SVM_EXIT_CPUID] = cpuid_interception,
4801 [SVM_EXIT_IRET] = iret_interception,
4802 [SVM_EXIT_INVD] = emulate_on_interception,
4803 [SVM_EXIT_PAUSE] = pause_interception,
4804 [SVM_EXIT_HLT] = halt_interception,
4805 [SVM_EXIT_INVLPG] = invlpg_interception,
4806 [SVM_EXIT_INVLPGA] = invlpga_interception,
4807 [SVM_EXIT_IOIO] = io_interception,
4808 [SVM_EXIT_MSR] = msr_interception,
4809 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4810 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4811 [SVM_EXIT_VMRUN] = vmrun_interception,
4812 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4813 [SVM_EXIT_VMLOAD] = vmload_interception,
4814 [SVM_EXIT_VMSAVE] = vmsave_interception,
4815 [SVM_EXIT_STGI] = stgi_interception,
4816 [SVM_EXIT_CLGI] = clgi_interception,
4817 [SVM_EXIT_SKINIT] = skinit_interception,
4818 [SVM_EXIT_WBINVD] = wbinvd_interception,
4819 [SVM_EXIT_MONITOR] = monitor_interception,
4820 [SVM_EXIT_MWAIT] = mwait_interception,
4821 [SVM_EXIT_XSETBV] = xsetbv_interception,
4822 [SVM_EXIT_NPF] = npf_interception,
4823 [SVM_EXIT_RSM] = rsm_interception,
4824 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4825 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4828 static void dump_vmcb(struct kvm_vcpu *vcpu)
4830 struct vcpu_svm *svm = to_svm(vcpu);
4831 struct vmcb_control_area *control = &svm->vmcb->control;
4832 struct vmcb_save_area *save = &svm->vmcb->save;
4834 if (!dump_invalid_vmcb) {
4835 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
4839 pr_err("VMCB Control Area:\n");
4840 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4841 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4842 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4843 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4844 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4845 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4846 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4847 pr_err("%-20s%d\n", "pause filter threshold:",
4848 control->pause_filter_thresh);
4849 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4850 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4851 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4852 pr_err("%-20s%d\n", "asid:", control->asid);
4853 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4854 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4855 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4856 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4857 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4858 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4859 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4860 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4861 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4862 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4863 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4864 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4865 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4866 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4867 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4868 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4869 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4870 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4871 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4872 pr_err("VMCB State Save Area:\n");
4873 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4875 save->es.selector, save->es.attrib,
4876 save->es.limit, save->es.base);
4877 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4879 save->cs.selector, save->cs.attrib,
4880 save->cs.limit, save->cs.base);
4881 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4883 save->ss.selector, save->ss.attrib,
4884 save->ss.limit, save->ss.base);
4885 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4887 save->ds.selector, save->ds.attrib,
4888 save->ds.limit, save->ds.base);
4889 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4891 save->fs.selector, save->fs.attrib,
4892 save->fs.limit, save->fs.base);
4893 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4895 save->gs.selector, save->gs.attrib,
4896 save->gs.limit, save->gs.base);
4897 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4899 save->gdtr.selector, save->gdtr.attrib,
4900 save->gdtr.limit, save->gdtr.base);
4901 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4903 save->ldtr.selector, save->ldtr.attrib,
4904 save->ldtr.limit, save->ldtr.base);
4905 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4907 save->idtr.selector, save->idtr.attrib,
4908 save->idtr.limit, save->idtr.base);
4909 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4911 save->tr.selector, save->tr.attrib,
4912 save->tr.limit, save->tr.base);
4913 pr_err("cpl: %d efer: %016llx\n",
4914 save->cpl, save->efer);
4915 pr_err("%-15s %016llx %-13s %016llx\n",
4916 "cr0:", save->cr0, "cr2:", save->cr2);
4917 pr_err("%-15s %016llx %-13s %016llx\n",
4918 "cr3:", save->cr3, "cr4:", save->cr4);
4919 pr_err("%-15s %016llx %-13s %016llx\n",
4920 "dr6:", save->dr6, "dr7:", save->dr7);
4921 pr_err("%-15s %016llx %-13s %016llx\n",
4922 "rip:", save->rip, "rflags:", save->rflags);
4923 pr_err("%-15s %016llx %-13s %016llx\n",
4924 "rsp:", save->rsp, "rax:", save->rax);
4925 pr_err("%-15s %016llx %-13s %016llx\n",
4926 "star:", save->star, "lstar:", save->lstar);
4927 pr_err("%-15s %016llx %-13s %016llx\n",
4928 "cstar:", save->cstar, "sfmask:", save->sfmask);
4929 pr_err("%-15s %016llx %-13s %016llx\n",
4930 "kernel_gs_base:", save->kernel_gs_base,
4931 "sysenter_cs:", save->sysenter_cs);
4932 pr_err("%-15s %016llx %-13s %016llx\n",
4933 "sysenter_esp:", save->sysenter_esp,
4934 "sysenter_eip:", save->sysenter_eip);
4935 pr_err("%-15s %016llx %-13s %016llx\n",
4936 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4937 pr_err("%-15s %016llx %-13s %016llx\n",
4938 "br_from:", save->br_from, "br_to:", save->br_to);
4939 pr_err("%-15s %016llx %-13s %016llx\n",
4940 "excp_from:", save->last_excp_from,
4941 "excp_to:", save->last_excp_to);
4944 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4946 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4948 *info1 = control->exit_info_1;
4949 *info2 = control->exit_info_2;
4952 static int handle_exit(struct kvm_vcpu *vcpu)
4954 struct vcpu_svm *svm = to_svm(vcpu);
4955 struct kvm_run *kvm_run = vcpu->run;
4956 u32 exit_code = svm->vmcb->control.exit_code;
4958 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4960 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4961 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4963 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4965 if (unlikely(svm->nested.exit_required)) {
4966 nested_svm_vmexit(svm);
4967 svm->nested.exit_required = false;
4972 if (is_guest_mode(vcpu)) {
4975 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4976 svm->vmcb->control.exit_info_1,
4977 svm->vmcb->control.exit_info_2,
4978 svm->vmcb->control.exit_int_info,
4979 svm->vmcb->control.exit_int_info_err,
4982 vmexit = nested_svm_exit_special(svm);
4984 if (vmexit == NESTED_EXIT_CONTINUE)
4985 vmexit = nested_svm_exit_handled(svm);
4987 if (vmexit == NESTED_EXIT_DONE)
4991 svm_complete_interrupts(svm);
4993 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4994 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4995 kvm_run->fail_entry.hardware_entry_failure_reason
4996 = svm->vmcb->control.exit_code;
5001 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
5002 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
5003 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
5004 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
5005 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
5007 __func__, svm->vmcb->control.exit_int_info,
5010 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
5011 || !svm_exit_handlers[exit_code]) {
5012 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
5013 kvm_queue_exception(vcpu, UD_VECTOR);
5017 return svm_exit_handlers[exit_code](svm);
5020 static void reload_tss(struct kvm_vcpu *vcpu)
5022 int cpu = raw_smp_processor_id();
5024 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5025 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
5029 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
5031 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5032 int asid = sev_get_asid(svm->vcpu.kvm);
5034 /* Assign the asid allocated with this SEV guest */
5035 svm->vmcb->control.asid = asid;
5040 * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5041 * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5043 if (sd->sev_vmcbs[asid] == svm->vmcb &&
5044 svm->last_cpu == cpu)
5047 svm->last_cpu = cpu;
5048 sd->sev_vmcbs[asid] = svm->vmcb;
5049 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5050 mark_dirty(svm->vmcb, VMCB_ASID);
5053 static void pre_svm_run(struct vcpu_svm *svm)
5055 int cpu = raw_smp_processor_id();
5057 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5059 if (sev_guest(svm->vcpu.kvm))
5060 return pre_sev_run(svm, cpu);
5062 /* FIXME: handle wraparound of asid_generation */
5063 if (svm->asid_generation != sd->asid_generation)
5067 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5069 struct vcpu_svm *svm = to_svm(vcpu);
5071 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5072 vcpu->arch.hflags |= HF_NMI_MASK;
5073 set_intercept(svm, INTERCEPT_IRET);
5074 ++vcpu->stat.nmi_injections;
5077 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5079 struct vmcb_control_area *control;
5081 /* The following fields are ignored when AVIC is enabled */
5082 control = &svm->vmcb->control;
5083 control->int_vector = irq;
5084 control->int_ctl &= ~V_INTR_PRIO_MASK;
5085 control->int_ctl |= V_IRQ_MASK |
5086 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5087 mark_dirty(svm->vmcb, VMCB_INTR);
5090 static void svm_set_irq(struct kvm_vcpu *vcpu)
5092 struct vcpu_svm *svm = to_svm(vcpu);
5094 BUG_ON(!(gif_set(svm)));
5096 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5097 ++vcpu->stat.irq_injections;
5099 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5100 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5103 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5105 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5108 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5110 struct vcpu_svm *svm = to_svm(vcpu);
5112 if (svm_nested_virtualize_tpr(vcpu) ||
5113 kvm_vcpu_apicv_active(vcpu))
5116 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5122 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5125 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5130 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5132 return avic && irqchip_split(vcpu->kvm);
5135 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5139 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5143 /* Note: Currently only used by Hyper-V. */
5144 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5146 struct vcpu_svm *svm = to_svm(vcpu);
5147 struct vmcb *vmcb = svm->vmcb;
5149 if (kvm_vcpu_apicv_active(vcpu))
5150 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
5152 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5153 mark_dirty(vmcb, VMCB_AVIC);
5156 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5161 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5163 kvm_lapic_set_irr(vec, vcpu->arch.apic);
5164 smp_mb__after_atomic();
5166 if (avic_vcpu_is_running(vcpu)) {
5167 int cpuid = vcpu->cpu;
5169 if (cpuid != get_cpu())
5170 wrmsrl(SVM_AVIC_DOORBELL, kvm_cpu_get_apicid(cpuid));
5173 kvm_vcpu_wake_up(vcpu);
5176 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5178 unsigned long flags;
5179 struct amd_svm_iommu_ir *cur;
5181 spin_lock_irqsave(&svm->ir_list_lock, flags);
5182 list_for_each_entry(cur, &svm->ir_list, node) {
5183 if (cur->data != pi->ir_data)
5185 list_del(&cur->node);
5189 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5192 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5195 unsigned long flags;
5196 struct amd_svm_iommu_ir *ir;
5199 * In some cases, the existing irte is updaed and re-set,
5200 * so we need to check here if it's already been * added
5203 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5204 struct kvm *kvm = svm->vcpu.kvm;
5205 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5206 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5207 struct vcpu_svm *prev_svm;
5214 prev_svm = to_svm(prev_vcpu);
5215 svm_ir_list_del(prev_svm, pi);
5219 * Allocating new amd_iommu_pi_data, which will get
5220 * add to the per-vcpu ir_list.
5222 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT);
5227 ir->data = pi->ir_data;
5229 spin_lock_irqsave(&svm->ir_list_lock, flags);
5230 list_add(&ir->node, &svm->ir_list);
5231 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5238 * The HW cannot support posting multicast/broadcast
5239 * interrupts to a vCPU. So, we still use legacy interrupt
5240 * remapping for these kind of interrupts.
5242 * For lowest-priority interrupts, we only support
5243 * those with single CPU as the destination, e.g. user
5244 * configures the interrupts via /proc/irq or uses
5245 * irqbalance to make the interrupts single-CPU.
5248 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5249 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5251 struct kvm_lapic_irq irq;
5252 struct kvm_vcpu *vcpu = NULL;
5254 kvm_set_msi_irq(kvm, e, &irq);
5256 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5257 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5258 __func__, irq.vector);
5262 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5264 *svm = to_svm(vcpu);
5265 vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5266 vcpu_info->vector = irq.vector;
5272 * svm_update_pi_irte - set IRTE for Posted-Interrupts
5275 * @host_irq: host irq of the interrupt
5276 * @guest_irq: gsi of the interrupt
5277 * @set: set or unset PI
5278 * returns 0 on success, < 0 on failure
5280 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5281 uint32_t guest_irq, bool set)
5283 struct kvm_kernel_irq_routing_entry *e;
5284 struct kvm_irq_routing_table *irq_rt;
5285 int idx, ret = -EINVAL;
5287 if (!kvm_arch_has_assigned_device(kvm) ||
5288 !irq_remapping_cap(IRQ_POSTING_CAP))
5291 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5292 __func__, host_irq, guest_irq, set);
5294 idx = srcu_read_lock(&kvm->irq_srcu);
5295 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5296 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5298 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5299 struct vcpu_data vcpu_info;
5300 struct vcpu_svm *svm = NULL;
5302 if (e->type != KVM_IRQ_ROUTING_MSI)
5306 * Here, we setup with legacy mode in the following cases:
5307 * 1. When cannot target interrupt to a specific vcpu.
5308 * 2. Unsetting posted interrupt.
5309 * 3. APIC virtialization is disabled for the vcpu.
5311 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5312 kvm_vcpu_apicv_active(&svm->vcpu)) {
5313 struct amd_iommu_pi_data pi;
5315 /* Try to enable guest_mode in IRTE */
5316 pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5318 pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5320 pi.is_guest_mode = true;
5321 pi.vcpu_data = &vcpu_info;
5322 ret = irq_set_vcpu_affinity(host_irq, &pi);
5325 * Here, we successfully setting up vcpu affinity in
5326 * IOMMU guest mode. Now, we need to store the posted
5327 * interrupt information in a per-vcpu ir_list so that
5328 * we can reference to them directly when we update vcpu
5329 * scheduling information in IOMMU irte.
5331 if (!ret && pi.is_guest_mode)
5332 svm_ir_list_add(svm, &pi);
5334 /* Use legacy mode in IRTE */
5335 struct amd_iommu_pi_data pi;
5338 * Here, pi is used to:
5339 * - Tell IOMMU to use legacy mode for this interrupt.
5340 * - Retrieve ga_tag of prior interrupt remapping data.
5342 pi.is_guest_mode = false;
5343 ret = irq_set_vcpu_affinity(host_irq, &pi);
5346 * Check if the posted interrupt was previously
5347 * setup with the guest_mode by checking if the ga_tag
5348 * was cached. If so, we need to clean up the per-vcpu
5351 if (!ret && pi.prev_ga_tag) {
5352 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5353 struct kvm_vcpu *vcpu;
5355 vcpu = kvm_get_vcpu_by_id(kvm, id);
5357 svm_ir_list_del(to_svm(vcpu), &pi);
5362 trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5363 e->gsi, vcpu_info.vector,
5364 vcpu_info.pi_desc_addr, set);
5368 pr_err("%s: failed to update PI IRTE\n", __func__);
5375 srcu_read_unlock(&kvm->irq_srcu, idx);
5379 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5381 struct vcpu_svm *svm = to_svm(vcpu);
5382 struct vmcb *vmcb = svm->vmcb;
5384 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5385 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5386 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5391 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5393 struct vcpu_svm *svm = to_svm(vcpu);
5395 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5398 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5400 struct vcpu_svm *svm = to_svm(vcpu);
5403 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5404 set_intercept(svm, INTERCEPT_IRET);
5406 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5407 clr_intercept(svm, INTERCEPT_IRET);
5411 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5413 struct vcpu_svm *svm = to_svm(vcpu);
5414 struct vmcb *vmcb = svm->vmcb;
5417 if (!gif_set(svm) ||
5418 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5421 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5423 if (is_guest_mode(vcpu))
5424 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5429 static void enable_irq_window(struct kvm_vcpu *vcpu)
5431 struct vcpu_svm *svm = to_svm(vcpu);
5433 if (kvm_vcpu_apicv_active(vcpu))
5437 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5438 * 1, because that's a separate STGI/VMRUN intercept. The next time we
5439 * get that intercept, this function will be called again though and
5440 * we'll get the vintr intercept. However, if the vGIF feature is
5441 * enabled, the STGI interception will not occur. Enable the irq
5442 * window under the assumption that the hardware will set the GIF.
5444 if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5446 svm_inject_irq(svm, 0x0);
5450 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5452 struct vcpu_svm *svm = to_svm(vcpu);
5454 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5456 return; /* IRET will cause a vm exit */
5458 if (!gif_set(svm)) {
5459 if (vgif_enabled(svm))
5460 set_intercept(svm, INTERCEPT_STGI);
5461 return; /* STGI will cause a vm exit */
5464 if (svm->nested.exit_required)
5465 return; /* we're not going to run the guest yet */
5468 * Something prevents NMI from been injected. Single step over possible
5469 * problem (IRET or exception injection or interrupt shadow)
5471 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5472 svm->nmi_singlestep = true;
5473 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5476 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5481 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5486 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5488 struct vcpu_svm *svm = to_svm(vcpu);
5490 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5491 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5493 svm->asid_generation--;
5496 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5498 struct vcpu_svm *svm = to_svm(vcpu);
5500 invlpga(gva, svm->vmcb->control.asid);
5503 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5507 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5509 struct vcpu_svm *svm = to_svm(vcpu);
5511 if (svm_nested_virtualize_tpr(vcpu))
5514 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5515 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5516 kvm_set_cr8(vcpu, cr8);
5520 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5522 struct vcpu_svm *svm = to_svm(vcpu);
5525 if (svm_nested_virtualize_tpr(vcpu) ||
5526 kvm_vcpu_apicv_active(vcpu))
5529 cr8 = kvm_get_cr8(vcpu);
5530 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5531 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5534 static void svm_complete_interrupts(struct vcpu_svm *svm)
5538 u32 exitintinfo = svm->vmcb->control.exit_int_info;
5539 unsigned int3_injected = svm->int3_injected;
5541 svm->int3_injected = 0;
5544 * If we've made progress since setting HF_IRET_MASK, we've
5545 * executed an IRET and can allow NMI injection.
5547 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5548 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5549 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5550 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5553 svm->vcpu.arch.nmi_injected = false;
5554 kvm_clear_exception_queue(&svm->vcpu);
5555 kvm_clear_interrupt_queue(&svm->vcpu);
5557 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5560 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5562 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5563 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5566 case SVM_EXITINTINFO_TYPE_NMI:
5567 svm->vcpu.arch.nmi_injected = true;
5569 case SVM_EXITINTINFO_TYPE_EXEPT:
5571 * In case of software exceptions, do not reinject the vector,
5572 * but re-execute the instruction instead. Rewind RIP first
5573 * if we emulated INT3 before.
5575 if (kvm_exception_is_soft(vector)) {
5576 if (vector == BP_VECTOR && int3_injected &&
5577 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5578 kvm_rip_write(&svm->vcpu,
5579 kvm_rip_read(&svm->vcpu) -
5583 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5584 u32 err = svm->vmcb->control.exit_int_info_err;
5585 kvm_requeue_exception_e(&svm->vcpu, vector, err);
5588 kvm_requeue_exception(&svm->vcpu, vector);
5590 case SVM_EXITINTINFO_TYPE_INTR:
5591 kvm_queue_interrupt(&svm->vcpu, vector, false);
5598 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5600 struct vcpu_svm *svm = to_svm(vcpu);
5601 struct vmcb_control_area *control = &svm->vmcb->control;
5603 control->exit_int_info = control->event_inj;
5604 control->exit_int_info_err = control->event_inj_err;
5605 control->event_inj = 0;
5606 svm_complete_interrupts(svm);
5609 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5611 struct vcpu_svm *svm = to_svm(vcpu);
5613 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5614 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5615 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5618 * A vmexit emulation is required before the vcpu can be executed
5621 if (unlikely(svm->nested.exit_required))
5625 * Disable singlestep if we're injecting an interrupt/exception.
5626 * We don't want our modified rflags to be pushed on the stack where
5627 * we might not be able to easily reset them if we disabled NMI
5630 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5632 * Event injection happens before external interrupts cause a
5633 * vmexit and interrupts are disabled here, so smp_send_reschedule
5634 * is enough to force an immediate vmexit.
5636 disable_nmi_singlestep(svm);
5637 smp_send_reschedule(vcpu->cpu);
5642 sync_lapic_to_cr8(vcpu);
5644 svm->vmcb->save.cr2 = vcpu->arch.cr2;
5647 kvm_load_guest_xcr0(vcpu);
5649 if (lapic_in_kernel(vcpu) &&
5650 vcpu->arch.apic->lapic_timer.timer_advance_ns)
5651 kvm_wait_lapic_expire(vcpu);
5654 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5655 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5656 * is no need to worry about the conditional branch over the wrmsr
5657 * being speculatively taken.
5659 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5664 "push %%" _ASM_BP "; \n\t"
5665 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5666 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5667 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5668 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5669 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5670 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5671 #ifdef CONFIG_X86_64
5672 "mov %c[r8](%[svm]), %%r8 \n\t"
5673 "mov %c[r9](%[svm]), %%r9 \n\t"
5674 "mov %c[r10](%[svm]), %%r10 \n\t"
5675 "mov %c[r11](%[svm]), %%r11 \n\t"
5676 "mov %c[r12](%[svm]), %%r12 \n\t"
5677 "mov %c[r13](%[svm]), %%r13 \n\t"
5678 "mov %c[r14](%[svm]), %%r14 \n\t"
5679 "mov %c[r15](%[svm]), %%r15 \n\t"
5682 /* Enter guest mode */
5683 "push %%" _ASM_AX " \n\t"
5684 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5685 __ex("vmload %%" _ASM_AX) "\n\t"
5686 __ex("vmrun %%" _ASM_AX) "\n\t"
5687 __ex("vmsave %%" _ASM_AX) "\n\t"
5688 "pop %%" _ASM_AX " \n\t"
5690 /* Save guest registers, load host registers */
5691 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5692 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5693 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5694 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5695 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5696 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5697 #ifdef CONFIG_X86_64
5698 "mov %%r8, %c[r8](%[svm]) \n\t"
5699 "mov %%r9, %c[r9](%[svm]) \n\t"
5700 "mov %%r10, %c[r10](%[svm]) \n\t"
5701 "mov %%r11, %c[r11](%[svm]) \n\t"
5702 "mov %%r12, %c[r12](%[svm]) \n\t"
5703 "mov %%r13, %c[r13](%[svm]) \n\t"
5704 "mov %%r14, %c[r14](%[svm]) \n\t"
5705 "mov %%r15, %c[r15](%[svm]) \n\t"
5707 * Clear host registers marked as clobbered to prevent
5710 "xor %%r8d, %%r8d \n\t"
5711 "xor %%r9d, %%r9d \n\t"
5712 "xor %%r10d, %%r10d \n\t"
5713 "xor %%r11d, %%r11d \n\t"
5714 "xor %%r12d, %%r12d \n\t"
5715 "xor %%r13d, %%r13d \n\t"
5716 "xor %%r14d, %%r14d \n\t"
5717 "xor %%r15d, %%r15d \n\t"
5719 "xor %%ebx, %%ebx \n\t"
5720 "xor %%ecx, %%ecx \n\t"
5721 "xor %%edx, %%edx \n\t"
5722 "xor %%esi, %%esi \n\t"
5723 "xor %%edi, %%edi \n\t"
5727 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5728 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5729 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5730 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5731 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5732 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5733 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5734 #ifdef CONFIG_X86_64
5735 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5736 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5737 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5738 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5739 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5740 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5741 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5742 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5745 #ifdef CONFIG_X86_64
5746 , "rbx", "rcx", "rdx", "rsi", "rdi"
5747 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5749 , "ebx", "ecx", "edx", "esi", "edi"
5753 /* Eliminate branch target predictions from guest mode */
5756 #ifdef CONFIG_X86_64
5757 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5759 loadsegment(fs, svm->host.fs);
5760 #ifndef CONFIG_X86_32_LAZY_GS
5761 loadsegment(gs, svm->host.gs);
5766 * We do not use IBRS in the kernel. If this vCPU has used the
5767 * SPEC_CTRL MSR it may have left it on; save the value and
5768 * turn it off. This is much more efficient than blindly adding
5769 * it to the atomic save/restore list. Especially as the former
5770 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5772 * For non-nested case:
5773 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5777 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5780 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5781 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5785 local_irq_disable();
5787 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5789 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5790 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5791 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5792 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5794 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5795 kvm_before_interrupt(&svm->vcpu);
5797 kvm_put_guest_xcr0(vcpu);
5800 /* Any pending NMI will happen here */
5802 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5803 kvm_after_interrupt(&svm->vcpu);
5805 sync_cr8_to_lapic(vcpu);
5809 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5811 /* if exit due to PF check for async PF */
5812 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5813 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5816 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5817 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5821 * We need to handle MC intercepts here before the vcpu has a chance to
5822 * change the physical cpu
5824 if (unlikely(svm->vmcb->control.exit_code ==
5825 SVM_EXIT_EXCP_BASE + MC_VECTOR))
5826 svm_handle_mce(svm);
5828 mark_all_clean(svm->vmcb);
5830 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5832 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5834 struct vcpu_svm *svm = to_svm(vcpu);
5836 svm->vmcb->save.cr3 = __sme_set(root);
5837 mark_dirty(svm->vmcb, VMCB_CR);
5840 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5842 struct vcpu_svm *svm = to_svm(vcpu);
5844 svm->vmcb->control.nested_cr3 = __sme_set(root);
5845 mark_dirty(svm->vmcb, VMCB_NPT);
5847 /* Also sync guest cr3 here in case we live migrate */
5848 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5849 mark_dirty(svm->vmcb, VMCB_CR);
5852 static int is_disabled(void)
5856 rdmsrl(MSR_VM_CR, vm_cr);
5857 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5864 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5867 * Patch in the VMMCALL instruction:
5869 hypercall[0] = 0x0f;
5870 hypercall[1] = 0x01;
5871 hypercall[2] = 0xd9;
5874 static int __init svm_check_processor_compat(void)
5879 static bool svm_cpu_has_accelerated_tpr(void)
5884 static bool svm_has_emulated_msr(int index)
5887 case MSR_IA32_MCG_EXT_CTL:
5896 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5901 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5903 struct vcpu_svm *svm = to_svm(vcpu);
5905 /* Update nrips enabled cache */
5906 svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5908 if (!kvm_vcpu_apicv_active(vcpu))
5911 guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5914 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5919 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5923 entry->ecx |= (1 << 2); /* Set SVM bit */
5926 entry->eax = 1; /* SVM revision 1 */
5927 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5928 ASID emulation to nested SVM */
5929 entry->ecx = 0; /* Reserved */
5930 entry->edx = 0; /* Per default do not support any
5931 additional features */
5933 /* Support next_rip if host supports it */
5934 if (boot_cpu_has(X86_FEATURE_NRIPS))
5935 entry->edx |= SVM_FEATURE_NRIP;
5937 /* Support NPT for the guest if enabled */
5939 entry->edx |= SVM_FEATURE_NPT;
5943 /* Support memory encryption cpuid if host supports it */
5944 if (boot_cpu_has(X86_FEATURE_SEV))
5945 cpuid(0x8000001f, &entry->eax, &entry->ebx,
5946 &entry->ecx, &entry->edx);
5951 static int svm_get_lpage_level(void)
5953 return PT_PDPE_LEVEL;
5956 static bool svm_rdtscp_supported(void)
5958 return boot_cpu_has(X86_FEATURE_RDTSCP);
5961 static bool svm_invpcid_supported(void)
5966 static bool svm_mpx_supported(void)
5971 static bool svm_xsaves_supported(void)
5976 static bool svm_umip_emulated(void)
5981 static bool svm_pt_supported(void)
5986 static bool svm_has_wbinvd_exit(void)
5991 #define PRE_EX(exit) { .exit_code = (exit), \
5992 .stage = X86_ICPT_PRE_EXCEPT, }
5993 #define POST_EX(exit) { .exit_code = (exit), \
5994 .stage = X86_ICPT_POST_EXCEPT, }
5995 #define POST_MEM(exit) { .exit_code = (exit), \
5996 .stage = X86_ICPT_POST_MEMACCESS, }
5998 static const struct __x86_intercept {
6000 enum x86_intercept_stage stage;
6001 } x86_intercept_map[] = {
6002 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
6003 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
6004 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
6005 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
6006 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
6007 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
6008 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
6009 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
6010 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
6011 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
6012 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
6013 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
6014 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
6015 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
6016 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
6017 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
6018 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
6019 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
6020 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
6021 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
6022 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
6023 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
6024 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
6025 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
6026 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
6027 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
6028 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
6029 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
6030 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
6031 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
6032 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
6033 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
6034 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
6035 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
6036 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
6037 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
6038 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
6039 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
6040 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
6041 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
6042 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
6043 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
6044 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
6045 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
6046 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
6047 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
6054 static int svm_check_intercept(struct kvm_vcpu *vcpu,
6055 struct x86_instruction_info *info,
6056 enum x86_intercept_stage stage)
6058 struct vcpu_svm *svm = to_svm(vcpu);
6059 int vmexit, ret = X86EMUL_CONTINUE;
6060 struct __x86_intercept icpt_info;
6061 struct vmcb *vmcb = svm->vmcb;
6063 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6066 icpt_info = x86_intercept_map[info->intercept];
6068 if (stage != icpt_info.stage)
6071 switch (icpt_info.exit_code) {
6072 case SVM_EXIT_READ_CR0:
6073 if (info->intercept == x86_intercept_cr_read)
6074 icpt_info.exit_code += info->modrm_reg;
6076 case SVM_EXIT_WRITE_CR0: {
6077 unsigned long cr0, val;
6080 if (info->intercept == x86_intercept_cr_write)
6081 icpt_info.exit_code += info->modrm_reg;
6083 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6084 info->intercept == x86_intercept_clts)
6087 intercept = svm->nested.intercept;
6089 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6092 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6093 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
6095 if (info->intercept == x86_intercept_lmsw) {
6098 /* lmsw can't clear PE - catch this here */
6099 if (cr0 & X86_CR0_PE)
6104 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6108 case SVM_EXIT_READ_DR0:
6109 case SVM_EXIT_WRITE_DR0:
6110 icpt_info.exit_code += info->modrm_reg;
6113 if (info->intercept == x86_intercept_wrmsr)
6114 vmcb->control.exit_info_1 = 1;
6116 vmcb->control.exit_info_1 = 0;
6118 case SVM_EXIT_PAUSE:
6120 * We get this for NOP only, but pause
6121 * is rep not, check this here
6123 if (info->rep_prefix != REPE_PREFIX)
6126 case SVM_EXIT_IOIO: {
6130 if (info->intercept == x86_intercept_in ||
6131 info->intercept == x86_intercept_ins) {
6132 exit_info = ((info->src_val & 0xffff) << 16) |
6134 bytes = info->dst_bytes;
6136 exit_info = (info->dst_val & 0xffff) << 16;
6137 bytes = info->src_bytes;
6140 if (info->intercept == x86_intercept_outs ||
6141 info->intercept == x86_intercept_ins)
6142 exit_info |= SVM_IOIO_STR_MASK;
6144 if (info->rep_prefix)
6145 exit_info |= SVM_IOIO_REP_MASK;
6147 bytes = min(bytes, 4u);
6149 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6151 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6153 vmcb->control.exit_info_1 = exit_info;
6154 vmcb->control.exit_info_2 = info->next_rip;
6162 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6163 if (static_cpu_has(X86_FEATURE_NRIPS))
6164 vmcb->control.next_rip = info->next_rip;
6165 vmcb->control.exit_code = icpt_info.exit_code;
6166 vmexit = nested_svm_exit_handled(svm);
6168 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6175 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6179 * We must have an instruction with interrupts enabled, so
6180 * the timer interrupt isn't delayed by the interrupt shadow.
6183 local_irq_disable();
6186 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6188 if (pause_filter_thresh)
6189 shrink_ple_window(vcpu);
6192 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6194 if (avic_handle_apic_id_update(vcpu) != 0)
6196 avic_handle_dfr_update(vcpu);
6197 avic_handle_ldr_update(vcpu);
6200 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6202 /* [63:9] are reserved. */
6203 vcpu->arch.mcg_cap &= 0x1ff;
6206 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6208 struct vcpu_svm *svm = to_svm(vcpu);
6210 /* Per APM Vol.2 15.22.2 "Response to SMI" */
6214 if (is_guest_mode(&svm->vcpu) &&
6215 svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6216 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6217 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6218 svm->nested.exit_required = true;
6225 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6227 struct vcpu_svm *svm = to_svm(vcpu);
6230 if (is_guest_mode(vcpu)) {
6231 /* FED8h - SVM Guest */
6232 put_smstate(u64, smstate, 0x7ed8, 1);
6233 /* FEE0h - SVM Guest VMCB Physical Address */
6234 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6236 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6237 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6238 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6240 ret = nested_svm_vmexit(svm);
6247 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
6249 struct vcpu_svm *svm = to_svm(vcpu);
6250 struct vmcb *nested_vmcb;
6251 struct kvm_host_map map;
6255 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
6256 vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
6259 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
6261 nested_vmcb = map.hva;
6262 enter_svm_guest_mode(svm, vmcb, nested_vmcb, &map);
6267 static int enable_smi_window(struct kvm_vcpu *vcpu)
6269 struct vcpu_svm *svm = to_svm(vcpu);
6271 if (!gif_set(svm)) {
6272 if (vgif_enabled(svm))
6273 set_intercept(svm, INTERCEPT_STGI);
6274 /* STGI will cause a vm exit */
6280 static int sev_asid_new(void)
6285 * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6287 pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6288 if (pos >= max_sev_asid)
6291 set_bit(pos, sev_asid_bitmap);
6295 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6297 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6301 if (unlikely(sev->active))
6304 asid = sev_asid_new();
6308 ret = sev_platform_init(&argp->error);
6314 INIT_LIST_HEAD(&sev->regions_list);
6319 __sev_asid_free(asid);
6323 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6325 struct sev_data_activate *data;
6326 int asid = sev_get_asid(kvm);
6329 wbinvd_on_all_cpus();
6331 ret = sev_guest_df_flush(error);
6335 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6339 /* activate ASID on the given handle */
6340 data->handle = handle;
6342 ret = sev_guest_activate(data, error);
6348 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6357 ret = sev_issue_cmd_external_user(f.file, id, data, error);
6363 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6365 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6367 return __sev_issue_cmd(sev->fd, id, data, error);
6370 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6372 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6373 struct sev_data_launch_start *start;
6374 struct kvm_sev_launch_start params;
6375 void *dh_blob, *session_blob;
6376 int *error = &argp->error;
6379 if (!sev_guest(kvm))
6382 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6385 start = kzalloc(sizeof(*start), GFP_KERNEL_ACCOUNT);
6390 if (params.dh_uaddr) {
6391 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6392 if (IS_ERR(dh_blob)) {
6393 ret = PTR_ERR(dh_blob);
6397 start->dh_cert_address = __sme_set(__pa(dh_blob));
6398 start->dh_cert_len = params.dh_len;
6401 session_blob = NULL;
6402 if (params.session_uaddr) {
6403 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6404 if (IS_ERR(session_blob)) {
6405 ret = PTR_ERR(session_blob);
6409 start->session_address = __sme_set(__pa(session_blob));
6410 start->session_len = params.session_len;
6413 start->handle = params.handle;
6414 start->policy = params.policy;
6416 /* create memory encryption context */
6417 ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6419 goto e_free_session;
6421 /* Bind ASID to this guest */
6422 ret = sev_bind_asid(kvm, start->handle, error);
6424 goto e_free_session;
6426 /* return handle to userspace */
6427 params.handle = start->handle;
6428 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) {
6429 sev_unbind_asid(kvm, start->handle);
6431 goto e_free_session;
6434 sev->handle = start->handle;
6435 sev->fd = argp->sev_fd;
6438 kfree(session_blob);
6446 static unsigned long get_num_contig_pages(unsigned long idx,
6447 struct page **inpages, unsigned long npages)
6449 unsigned long paddr, next_paddr;
6450 unsigned long i = idx + 1, pages = 1;
6452 /* find the number of contiguous pages starting from idx */
6453 paddr = __sme_page_pa(inpages[idx]);
6454 while (i < npages) {
6455 next_paddr = __sme_page_pa(inpages[i++]);
6456 if ((paddr + PAGE_SIZE) == next_paddr) {
6467 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6469 unsigned long vaddr, vaddr_end, next_vaddr, npages, pages, size, i;
6470 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6471 struct kvm_sev_launch_update_data params;
6472 struct sev_data_launch_update_data *data;
6473 struct page **inpages;
6476 if (!sev_guest(kvm))
6479 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6482 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6486 vaddr = params.uaddr;
6488 vaddr_end = vaddr + size;
6490 /* Lock the user memory. */
6491 inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6498 * The LAUNCH_UPDATE command will perform in-place encryption of the
6499 * memory content (i.e it will write the same memory region with C=1).
6500 * It's possible that the cache may contain the data with C=0, i.e.,
6501 * unencrypted so invalidate it first.
6503 sev_clflush_pages(inpages, npages);
6505 for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6509 * If the user buffer is not page-aligned, calculate the offset
6512 offset = vaddr & (PAGE_SIZE - 1);
6514 /* Calculate the number of pages that can be encrypted in one go. */
6515 pages = get_num_contig_pages(i, inpages, npages);
6517 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6519 data->handle = sev->handle;
6521 data->address = __sme_page_pa(inpages[i]) + offset;
6522 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6527 next_vaddr = vaddr + len;
6531 /* content of memory is updated, mark pages dirty */
6532 for (i = 0; i < npages; i++) {
6533 set_page_dirty_lock(inpages[i]);
6534 mark_page_accessed(inpages[i]);
6536 /* unlock the user pages */
6537 sev_unpin_memory(kvm, inpages, npages);
6543 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6545 void __user *measure = (void __user *)(uintptr_t)argp->data;
6546 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6547 struct sev_data_launch_measure *data;
6548 struct kvm_sev_launch_measure params;
6549 void __user *p = NULL;
6553 if (!sev_guest(kvm))
6556 if (copy_from_user(¶ms, measure, sizeof(params)))
6559 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6563 /* User wants to query the blob length */
6567 p = (void __user *)(uintptr_t)params.uaddr;
6569 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6575 blob = kmalloc(params.len, GFP_KERNEL);
6579 data->address = __psp_pa(blob);
6580 data->len = params.len;
6584 data->handle = sev->handle;
6585 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6588 * If we query the session length, FW responded with expected data.
6597 if (copy_to_user(p, blob, params.len))
6602 params.len = data->len;
6603 if (copy_to_user(measure, ¶ms, sizeof(params)))
6612 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6614 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6615 struct sev_data_launch_finish *data;
6618 if (!sev_guest(kvm))
6621 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6625 data->handle = sev->handle;
6626 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6632 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6634 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6635 struct kvm_sev_guest_status params;
6636 struct sev_data_guest_status *data;
6639 if (!sev_guest(kvm))
6642 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6646 data->handle = sev->handle;
6647 ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6651 params.policy = data->policy;
6652 params.state = data->state;
6653 params.handle = data->handle;
6655 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params)))
6662 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6663 unsigned long dst, int size,
6664 int *error, bool enc)
6666 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6667 struct sev_data_dbg *data;
6670 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6674 data->handle = sev->handle;
6675 data->dst_addr = dst;
6676 data->src_addr = src;
6679 ret = sev_issue_cmd(kvm,
6680 enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6686 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6687 unsigned long dst_paddr, int sz, int *err)
6692 * Its safe to read more than we are asked, caller should ensure that
6693 * destination has enough space.
6695 src_paddr = round_down(src_paddr, 16);
6696 offset = src_paddr & 15;
6697 sz = round_up(sz + offset, 16);
6699 return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6702 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6703 unsigned long __user dst_uaddr,
6704 unsigned long dst_paddr,
6707 struct page *tpage = NULL;
6710 /* if inputs are not 16-byte then use intermediate buffer */
6711 if (!IS_ALIGNED(dst_paddr, 16) ||
6712 !IS_ALIGNED(paddr, 16) ||
6713 !IS_ALIGNED(size, 16)) {
6714 tpage = (void *)alloc_page(GFP_KERNEL);
6718 dst_paddr = __sme_page_pa(tpage);
6721 ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6726 offset = paddr & 15;
6727 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6728 page_address(tpage) + offset, size))
6739 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6740 unsigned long __user vaddr,
6741 unsigned long dst_paddr,
6742 unsigned long __user dst_vaddr,
6743 int size, int *error)
6745 struct page *src_tpage = NULL;
6746 struct page *dst_tpage = NULL;
6747 int ret, len = size;
6749 /* If source buffer is not aligned then use an intermediate buffer */
6750 if (!IS_ALIGNED(vaddr, 16)) {
6751 src_tpage = alloc_page(GFP_KERNEL);
6755 if (copy_from_user(page_address(src_tpage),
6756 (void __user *)(uintptr_t)vaddr, size)) {
6757 __free_page(src_tpage);
6761 paddr = __sme_page_pa(src_tpage);
6765 * If destination buffer or length is not aligned then do read-modify-write:
6766 * - decrypt destination in an intermediate buffer
6767 * - copy the source buffer in an intermediate buffer
6768 * - use the intermediate buffer as source buffer
6770 if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6773 dst_tpage = alloc_page(GFP_KERNEL);
6779 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6780 __sme_page_pa(dst_tpage), size, error);
6785 * If source is kernel buffer then use memcpy() otherwise
6788 dst_offset = dst_paddr & 15;
6791 memcpy(page_address(dst_tpage) + dst_offset,
6792 page_address(src_tpage), size);
6794 if (copy_from_user(page_address(dst_tpage) + dst_offset,
6795 (void __user *)(uintptr_t)vaddr, size)) {
6801 paddr = __sme_page_pa(dst_tpage);
6802 dst_paddr = round_down(dst_paddr, 16);
6803 len = round_up(size, 16);
6806 ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6810 __free_page(src_tpage);
6812 __free_page(dst_tpage);
6816 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6818 unsigned long vaddr, vaddr_end, next_vaddr;
6819 unsigned long dst_vaddr;
6820 struct page **src_p, **dst_p;
6821 struct kvm_sev_dbg debug;
6826 if (!sev_guest(kvm))
6829 if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6832 if (!debug.len || debug.src_uaddr + debug.len < debug.src_uaddr)
6834 if (!debug.dst_uaddr)
6837 vaddr = debug.src_uaddr;
6839 vaddr_end = vaddr + size;
6840 dst_vaddr = debug.dst_uaddr;
6842 for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6843 int len, s_off, d_off;
6845 /* lock userspace source and destination page */
6846 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6850 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6852 sev_unpin_memory(kvm, src_p, n);
6857 * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6858 * memory content (i.e it will write the same memory region with C=1).
6859 * It's possible that the cache may contain the data with C=0, i.e.,
6860 * unencrypted so invalidate it first.
6862 sev_clflush_pages(src_p, 1);
6863 sev_clflush_pages(dst_p, 1);
6866 * Since user buffer may not be page aligned, calculate the
6867 * offset within the page.
6869 s_off = vaddr & ~PAGE_MASK;
6870 d_off = dst_vaddr & ~PAGE_MASK;
6871 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6874 ret = __sev_dbg_decrypt_user(kvm,
6875 __sme_page_pa(src_p[0]) + s_off,
6877 __sme_page_pa(dst_p[0]) + d_off,
6880 ret = __sev_dbg_encrypt_user(kvm,
6881 __sme_page_pa(src_p[0]) + s_off,
6883 __sme_page_pa(dst_p[0]) + d_off,
6887 sev_unpin_memory(kvm, src_p, n);
6888 sev_unpin_memory(kvm, dst_p, n);
6893 next_vaddr = vaddr + len;
6894 dst_vaddr = dst_vaddr + len;
6901 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6903 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6904 struct sev_data_launch_secret *data;
6905 struct kvm_sev_launch_secret params;
6906 struct page **pages;
6911 if (!sev_guest(kvm))
6914 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6917 pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6922 * The secret must be copied into contiguous memory region, lets verify
6923 * that userspace memory pages are contiguous before we issue command.
6925 if (get_num_contig_pages(0, pages, n) != n) {
6927 goto e_unpin_memory;
6931 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6933 goto e_unpin_memory;
6935 offset = params.guest_uaddr & (PAGE_SIZE - 1);
6936 data->guest_address = __sme_page_pa(pages[0]) + offset;
6937 data->guest_len = params.guest_len;
6939 blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6941 ret = PTR_ERR(blob);
6945 data->trans_address = __psp_pa(blob);
6946 data->trans_len = params.trans_len;
6948 hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6953 data->hdr_address = __psp_pa(hdr);
6954 data->hdr_len = params.hdr_len;
6956 data->handle = sev->handle;
6957 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6966 sev_unpin_memory(kvm, pages, n);
6970 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6972 struct kvm_sev_cmd sev_cmd;
6975 if (!svm_sev_enabled())
6978 if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6981 mutex_lock(&kvm->lock);
6983 switch (sev_cmd.id) {
6985 r = sev_guest_init(kvm, &sev_cmd);
6987 case KVM_SEV_LAUNCH_START:
6988 r = sev_launch_start(kvm, &sev_cmd);
6990 case KVM_SEV_LAUNCH_UPDATE_DATA:
6991 r = sev_launch_update_data(kvm, &sev_cmd);
6993 case KVM_SEV_LAUNCH_MEASURE:
6994 r = sev_launch_measure(kvm, &sev_cmd);
6996 case KVM_SEV_LAUNCH_FINISH:
6997 r = sev_launch_finish(kvm, &sev_cmd);
6999 case KVM_SEV_GUEST_STATUS:
7000 r = sev_guest_status(kvm, &sev_cmd);
7002 case KVM_SEV_DBG_DECRYPT:
7003 r = sev_dbg_crypt(kvm, &sev_cmd, true);
7005 case KVM_SEV_DBG_ENCRYPT:
7006 r = sev_dbg_crypt(kvm, &sev_cmd, false);
7008 case KVM_SEV_LAUNCH_SECRET:
7009 r = sev_launch_secret(kvm, &sev_cmd);
7016 if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
7020 mutex_unlock(&kvm->lock);
7024 static int svm_register_enc_region(struct kvm *kvm,
7025 struct kvm_enc_region *range)
7027 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7028 struct enc_region *region;
7031 if (!sev_guest(kvm))
7034 if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
7037 region = kzalloc(sizeof(*region), GFP_KERNEL_ACCOUNT);
7041 region->pages = sev_pin_memory(kvm, range->addr, range->size, ®ion->npages, 1);
7042 if (!region->pages) {
7048 * The guest may change the memory encryption attribute from C=0 -> C=1
7049 * or vice versa for this memory range. Lets make sure caches are
7050 * flushed to ensure that guest data gets written into memory with
7053 sev_clflush_pages(region->pages, region->npages);
7055 region->uaddr = range->addr;
7056 region->size = range->size;
7058 mutex_lock(&kvm->lock);
7059 list_add_tail(®ion->list, &sev->regions_list);
7060 mutex_unlock(&kvm->lock);
7069 static struct enc_region *
7070 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7072 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7073 struct list_head *head = &sev->regions_list;
7074 struct enc_region *i;
7076 list_for_each_entry(i, head, list) {
7077 if (i->uaddr == range->addr &&
7078 i->size == range->size)
7086 static int svm_unregister_enc_region(struct kvm *kvm,
7087 struct kvm_enc_region *range)
7089 struct enc_region *region;
7092 mutex_lock(&kvm->lock);
7094 if (!sev_guest(kvm)) {
7099 region = find_enc_region(kvm, range);
7105 __unregister_enc_region_locked(kvm, region);
7107 mutex_unlock(&kvm->lock);
7111 mutex_unlock(&kvm->lock);
7115 static uint16_t nested_get_evmcs_version(struct kvm_vcpu *vcpu)
7121 static int nested_enable_evmcs(struct kvm_vcpu *vcpu,
7122 uint16_t *vmcs_version)
7124 /* Intel-only feature */
7128 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7132 is_user = svm_get_cpl(vcpu) == 3;
7133 smap = !kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
7136 * Detect and workaround Errata 1096 Fam_17h_00_0Fh
7138 * In non SEV guest, hypervisor will be able to read the guest
7139 * memory to decode the instruction pointer when insn_len is zero
7140 * so we return true to indicate that decoding is possible.
7142 * But in the SEV guest, the guest memory is encrypted with the
7143 * guest specific key and hypervisor will not be able to decode the
7144 * instruction pointer so we will not able to workaround it. Lets
7145 * print the error and request to kill the guest.
7147 if (is_user && smap) {
7148 if (!sev_guest(vcpu->kvm))
7151 pr_err_ratelimited("KVM: Guest triggered AMD Erratum 1096\n");
7152 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7158 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7159 .cpu_has_kvm_support = has_svm,
7160 .disabled_by_bios = is_disabled,
7161 .hardware_setup = svm_hardware_setup,
7162 .hardware_unsetup = svm_hardware_unsetup,
7163 .check_processor_compatibility = svm_check_processor_compat,
7164 .hardware_enable = svm_hardware_enable,
7165 .hardware_disable = svm_hardware_disable,
7166 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7167 .has_emulated_msr = svm_has_emulated_msr,
7169 .vcpu_create = svm_create_vcpu,
7170 .vcpu_free = svm_free_vcpu,
7171 .vcpu_reset = svm_vcpu_reset,
7173 .vm_alloc = svm_vm_alloc,
7174 .vm_free = svm_vm_free,
7175 .vm_init = avic_vm_init,
7176 .vm_destroy = svm_vm_destroy,
7178 .prepare_guest_switch = svm_prepare_guest_switch,
7179 .vcpu_load = svm_vcpu_load,
7180 .vcpu_put = svm_vcpu_put,
7181 .vcpu_blocking = svm_vcpu_blocking,
7182 .vcpu_unblocking = svm_vcpu_unblocking,
7184 .update_bp_intercept = update_bp_intercept,
7185 .get_msr_feature = svm_get_msr_feature,
7186 .get_msr = svm_get_msr,
7187 .set_msr = svm_set_msr,
7188 .get_segment_base = svm_get_segment_base,
7189 .get_segment = svm_get_segment,
7190 .set_segment = svm_set_segment,
7191 .get_cpl = svm_get_cpl,
7192 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7193 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7194 .decache_cr3 = svm_decache_cr3,
7195 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7196 .set_cr0 = svm_set_cr0,
7197 .set_cr3 = svm_set_cr3,
7198 .set_cr4 = svm_set_cr4,
7199 .set_efer = svm_set_efer,
7200 .get_idt = svm_get_idt,
7201 .set_idt = svm_set_idt,
7202 .get_gdt = svm_get_gdt,
7203 .set_gdt = svm_set_gdt,
7204 .get_dr6 = svm_get_dr6,
7205 .set_dr6 = svm_set_dr6,
7206 .set_dr7 = svm_set_dr7,
7207 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7208 .cache_reg = svm_cache_reg,
7209 .get_rflags = svm_get_rflags,
7210 .set_rflags = svm_set_rflags,
7212 .tlb_flush = svm_flush_tlb,
7213 .tlb_flush_gva = svm_flush_tlb_gva,
7215 .run = svm_vcpu_run,
7216 .handle_exit = handle_exit,
7217 .skip_emulated_instruction = skip_emulated_instruction,
7218 .set_interrupt_shadow = svm_set_interrupt_shadow,
7219 .get_interrupt_shadow = svm_get_interrupt_shadow,
7220 .patch_hypercall = svm_patch_hypercall,
7221 .set_irq = svm_set_irq,
7222 .set_nmi = svm_inject_nmi,
7223 .queue_exception = svm_queue_exception,
7224 .cancel_injection = svm_cancel_injection,
7225 .interrupt_allowed = svm_interrupt_allowed,
7226 .nmi_allowed = svm_nmi_allowed,
7227 .get_nmi_mask = svm_get_nmi_mask,
7228 .set_nmi_mask = svm_set_nmi_mask,
7229 .enable_nmi_window = enable_nmi_window,
7230 .enable_irq_window = enable_irq_window,
7231 .update_cr8_intercept = update_cr8_intercept,
7232 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7233 .get_enable_apicv = svm_get_enable_apicv,
7234 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7235 .load_eoi_exitmap = svm_load_eoi_exitmap,
7236 .hwapic_irr_update = svm_hwapic_irr_update,
7237 .hwapic_isr_update = svm_hwapic_isr_update,
7238 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7239 .apicv_post_state_restore = avic_post_state_restore,
7241 .set_tss_addr = svm_set_tss_addr,
7242 .set_identity_map_addr = svm_set_identity_map_addr,
7243 .get_tdp_level = get_npt_level,
7244 .get_mt_mask = svm_get_mt_mask,
7246 .get_exit_info = svm_get_exit_info,
7248 .get_lpage_level = svm_get_lpage_level,
7250 .cpuid_update = svm_cpuid_update,
7252 .rdtscp_supported = svm_rdtscp_supported,
7253 .invpcid_supported = svm_invpcid_supported,
7254 .mpx_supported = svm_mpx_supported,
7255 .xsaves_supported = svm_xsaves_supported,
7256 .umip_emulated = svm_umip_emulated,
7257 .pt_supported = svm_pt_supported,
7259 .set_supported_cpuid = svm_set_supported_cpuid,
7261 .has_wbinvd_exit = svm_has_wbinvd_exit,
7263 .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7264 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7266 .set_tdp_cr3 = set_tdp_cr3,
7268 .check_intercept = svm_check_intercept,
7269 .handle_external_intr = svm_handle_external_intr,
7271 .request_immediate_exit = __kvm_request_immediate_exit,
7273 .sched_in = svm_sched_in,
7275 .pmu_ops = &amd_pmu_ops,
7276 .deliver_posted_interrupt = svm_deliver_avic_intr,
7277 .update_pi_irte = svm_update_pi_irte,
7278 .setup_mce = svm_setup_mce,
7280 .smi_allowed = svm_smi_allowed,
7281 .pre_enter_smm = svm_pre_enter_smm,
7282 .pre_leave_smm = svm_pre_leave_smm,
7283 .enable_smi_window = enable_smi_window,
7285 .mem_enc_op = svm_mem_enc_op,
7286 .mem_enc_reg_region = svm_register_enc_region,
7287 .mem_enc_unreg_region = svm_unregister_enc_region,
7289 .nested_enable_evmcs = nested_enable_evmcs,
7290 .nested_get_evmcs_version = nested_get_evmcs_version,
7292 .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
7295 static int __init svm_init(void)
7297 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7298 __alignof__(struct vcpu_svm), THIS_MODULE);
7301 static void __exit svm_exit(void)
7306 module_init(svm_init)
7307 module_exit(svm_exit)