1 // SPDX-License-Identifier: GPL-2.0-only
3 * KVM PMU support for AMD
5 * Copyright 2015, Red Hat, Inc. and/or its affiliates.
8 * Wei Huang <wei@redhat.com>
10 * Implementation is based on pmu_intel.c file
12 #include <linux/types.h>
13 #include <linux/kvm_host.h>
14 #include <linux/perf_event.h>
36 /* duplicated from amd_perfmon_event_map, K7 and above should work. */
37 static struct kvm_event_hw_type_mapping amd_event_mapping[] = {
38 [0] = { 0x76, 0x00, PERF_COUNT_HW_CPU_CYCLES },
39 [1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
40 [2] = { 0x7d, 0x07, PERF_COUNT_HW_CACHE_REFERENCES },
41 [3] = { 0x7e, 0x07, PERF_COUNT_HW_CACHE_MISSES },
42 [4] = { 0xc2, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
43 [5] = { 0xc3, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
44 [6] = { 0xd0, 0x00, PERF_COUNT_HW_STALLED_CYCLES_FRONTEND },
45 [7] = { 0xd1, 0x00, PERF_COUNT_HW_STALLED_CYCLES_BACKEND },
48 static unsigned int get_msr_base(struct kvm_pmu *pmu, enum pmu_type type)
50 struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);
52 if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE)) {
53 if (type == PMU_TYPE_COUNTER)
54 return MSR_F15H_PERF_CTR;
56 return MSR_F15H_PERF_CTL;
58 if (type == PMU_TYPE_COUNTER)
59 return MSR_K7_PERFCTR0;
61 return MSR_K7_EVNTSEL0;
65 static enum index msr_to_index(u32 msr)
68 case MSR_F15H_PERF_CTL0:
69 case MSR_F15H_PERF_CTR0:
73 case MSR_F15H_PERF_CTL1:
74 case MSR_F15H_PERF_CTR1:
78 case MSR_F15H_PERF_CTL2:
79 case MSR_F15H_PERF_CTR2:
83 case MSR_F15H_PERF_CTL3:
84 case MSR_F15H_PERF_CTR3:
88 case MSR_F15H_PERF_CTL4:
89 case MSR_F15H_PERF_CTR4:
91 case MSR_F15H_PERF_CTL5:
92 case MSR_F15H_PERF_CTR5:
99 static inline struct kvm_pmc *get_gp_pmc_amd(struct kvm_pmu *pmu, u32 msr,
102 struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);
104 if (!vcpu->kvm->arch.enable_pmu)
108 case MSR_F15H_PERF_CTL0:
109 case MSR_F15H_PERF_CTL1:
110 case MSR_F15H_PERF_CTL2:
111 case MSR_F15H_PERF_CTL3:
112 case MSR_F15H_PERF_CTL4:
113 case MSR_F15H_PERF_CTL5:
114 if (!guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE))
117 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
118 if (type != PMU_TYPE_EVNTSEL)
121 case MSR_F15H_PERF_CTR0:
122 case MSR_F15H_PERF_CTR1:
123 case MSR_F15H_PERF_CTR2:
124 case MSR_F15H_PERF_CTR3:
125 case MSR_F15H_PERF_CTR4:
126 case MSR_F15H_PERF_CTR5:
127 if (!guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE))
130 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
131 if (type != PMU_TYPE_COUNTER)
138 return &pmu->gp_counters[msr_to_index(msr)];
141 static unsigned int amd_pmc_perf_hw_id(struct kvm_pmc *pmc)
143 u8 event_select = pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT;
144 u8 unit_mask = (pmc->eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
147 /* return PERF_COUNT_HW_MAX as AMD doesn't have fixed events */
148 if (WARN_ON(pmc_is_fixed(pmc)))
149 return PERF_COUNT_HW_MAX;
151 for (i = 0; i < ARRAY_SIZE(amd_event_mapping); i++)
152 if (amd_event_mapping[i].eventsel == event_select
153 && amd_event_mapping[i].unit_mask == unit_mask)
156 if (i == ARRAY_SIZE(amd_event_mapping))
157 return PERF_COUNT_HW_MAX;
159 return amd_event_mapping[i].event_type;
162 /* check if a PMC is enabled by comparing it against global_ctrl bits. Because
163 * AMD CPU doesn't have global_ctrl MSR, all PMCs are enabled (return TRUE).
165 static bool amd_pmc_is_enabled(struct kvm_pmc *pmc)
170 static struct kvm_pmc *amd_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx)
172 unsigned int base = get_msr_base(pmu, PMU_TYPE_COUNTER);
173 struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);
175 if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE)) {
177 * The idx is contiguous. The MSRs are not. The counter MSRs
178 * are interleaved with the event select MSRs.
183 return get_gp_pmc_amd(pmu, base + pmc_idx, PMU_TYPE_COUNTER);
186 static bool amd_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx)
188 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
192 return idx < pmu->nr_arch_gp_counters;
195 /* idx is the ECX register of RDPMC instruction */
196 static struct kvm_pmc *amd_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu,
197 unsigned int idx, u64 *mask)
199 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
200 struct kvm_pmc *counters;
203 if (idx >= pmu->nr_arch_gp_counters)
205 counters = pmu->gp_counters;
207 return &counters[idx];
210 static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
212 /* All MSRs refer to exactly one PMC, so msr_idx_to_pmc is enough. */
216 static struct kvm_pmc *amd_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr)
218 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
221 pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);
222 pmc = pmc ? pmc : get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);
227 static int amd_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
229 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
231 u32 msr = msr_info->index;
234 pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);
236 msr_info->data = pmc_read_counter(pmc);
240 pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);
242 msr_info->data = pmc->eventsel;
249 static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
251 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
253 u32 msr = msr_info->index;
254 u64 data = msr_info->data;
257 pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);
259 pmc->counter += data - pmc_read_counter(pmc);
263 pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);
265 if (data == pmc->eventsel)
267 if (!(data & pmu->reserved_bits)) {
268 reprogram_gp_counter(pmc, data);
276 static void amd_pmu_refresh(struct kvm_vcpu *vcpu)
278 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
280 if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE))
281 pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS_CORE;
283 pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS;
285 pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1;
286 pmu->reserved_bits = 0xfffffff000280000ull;
288 /* not applicable to AMD; but clean them to prevent any fall out */
289 pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
290 pmu->nr_arch_fixed_counters = 0;
291 pmu->global_status = 0;
292 bitmap_set(pmu->all_valid_pmc_idx, 0, pmu->nr_arch_gp_counters);
295 static void amd_pmu_init(struct kvm_vcpu *vcpu)
297 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
300 BUILD_BUG_ON(AMD64_NUM_COUNTERS_CORE > INTEL_PMC_MAX_GENERIC);
302 for (i = 0; i < AMD64_NUM_COUNTERS_CORE ; i++) {
303 pmu->gp_counters[i].type = KVM_PMC_GP;
304 pmu->gp_counters[i].vcpu = vcpu;
305 pmu->gp_counters[i].idx = i;
306 pmu->gp_counters[i].current_config = 0;
310 static void amd_pmu_reset(struct kvm_vcpu *vcpu)
312 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
315 for (i = 0; i < AMD64_NUM_COUNTERS_CORE; i++) {
316 struct kvm_pmc *pmc = &pmu->gp_counters[i];
318 pmc_stop_counter(pmc);
319 pmc->counter = pmc->eventsel = 0;
323 struct kvm_pmu_ops amd_pmu_ops = {
324 .pmc_perf_hw_id = amd_pmc_perf_hw_id,
325 .pmc_is_enabled = amd_pmc_is_enabled,
326 .pmc_idx_to_pmc = amd_pmc_idx_to_pmc,
327 .rdpmc_ecx_to_pmc = amd_rdpmc_ecx_to_pmc,
328 .msr_idx_to_pmc = amd_msr_idx_to_pmc,
329 .is_valid_rdpmc_ecx = amd_is_valid_rdpmc_ecx,
330 .is_valid_msr = amd_is_valid_msr,
331 .get_msr = amd_pmu_get_msr,
332 .set_msr = amd_pmu_set_msr,
333 .refresh = amd_pmu_refresh,
334 .init = amd_pmu_init,
335 .reset = amd_pmu_reset,