arch/x86/kvm/pmu.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __KVM_X86_PMU_H
   3 #define __KVM_X86_PMU_H
   4
   5 #include <linux/nospec.h>
   6
   7 #define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu)
   8 #define pmu_to_vcpu(pmu)  (container_of((pmu), struct kvm_vcpu, arch.pmu))
   9 #define pmc_to_pmu(pmc)   (&(pmc)->vcpu->arch.pmu)
  10
  11 #define MSR_IA32_MISC_ENABLE_PMU_RO_MASK (MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |   \
  12                                           MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)
  13
  14 /* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */
  15 #define fixed_ctrl_field(ctrl_reg, idx) (((ctrl_reg) >> ((idx)*4)) & 0xf)
  16
  17 #define VMWARE_BACKDOOR_PMC_HOST_TSC            0x10000
  18 #define VMWARE_BACKDOOR_PMC_REAL_TIME           0x10001
  19 #define VMWARE_BACKDOOR_PMC_APPARENT_TIME       0x10002
  20
  21 struct kvm_pmu_ops {
  22         bool (*hw_event_available)(struct kvm_pmc *pmc);
  23         bool (*pmc_is_enabled)(struct kvm_pmc *pmc);
  24         struct kvm_pmc *(*pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx);
  25         struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu,
  26                 unsigned int idx, u64 *mask);
  27         struct kvm_pmc *(*msr_idx_to_pmc)(struct kvm_vcpu *vcpu, u32 msr);
  28         bool (*is_valid_rdpmc_ecx)(struct kvm_vcpu *vcpu, unsigned int idx);
  29         bool (*is_valid_msr)(struct kvm_vcpu *vcpu, u32 msr);
  30         int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
  31         int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
  32         void (*refresh)(struct kvm_vcpu *vcpu);
  33         void (*init)(struct kvm_vcpu *vcpu);
  34         void (*reset)(struct kvm_vcpu *vcpu);
  35         void (*deliver_pmi)(struct kvm_vcpu *vcpu);
  36         void (*cleanup)(struct kvm_vcpu *vcpu);
  37
  38         const u64 EVENTSEL_EVENT;
  39         const int MAX_NR_GP_COUNTERS;
  40 };
  41
  42 void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops);
  43
  44 static inline u64 pmc_bitmask(struct kvm_pmc *pmc)
  45 {
  46         struct kvm_pmu *pmu = pmc_to_pmu(pmc);
  47
  48         return pmu->counter_bitmask[pmc->type];
  49 }
  50
  51 static inline u64 pmc_read_counter(struct kvm_pmc *pmc)
  52 {
  53         u64 counter, enabled, running;
  54
  55         counter = pmc->counter;
  56         if (pmc->perf_event && !pmc->is_paused)
  57                 counter += perf_event_read_value(pmc->perf_event,
  58                                                  &enabled, &running);
  59         /* FIXME: Scaling needed? */
  60         return counter & pmc_bitmask(pmc);
  61 }
  62
  63 static inline void pmc_release_perf_event(struct kvm_pmc *pmc)
  64 {
  65         if (pmc->perf_event) {
  66                 perf_event_release_kernel(pmc->perf_event);
  67                 pmc->perf_event = NULL;
  68                 pmc->current_config = 0;
  69                 pmc_to_pmu(pmc)->event_count--;
  70         }
  71 }
  72
  73 static inline void pmc_stop_counter(struct kvm_pmc *pmc)
  74 {
  75         if (pmc->perf_event) {
  76                 pmc->counter = pmc_read_counter(pmc);
  77                 pmc_release_perf_event(pmc);
  78         }
  79 }
  80
  81 static inline bool pmc_is_gp(struct kvm_pmc *pmc)
  82 {
  83         return pmc->type == KVM_PMC_GP;
  84 }
  85
  86 static inline bool pmc_is_fixed(struct kvm_pmc *pmc)
  87 {
  88         return pmc->type == KVM_PMC_FIXED;
  89 }
  90
  91 static inline bool kvm_valid_perf_global_ctrl(struct kvm_pmu *pmu,
  92                                                  u64 data)
  93 {
  94         return !(pmu->global_ctrl_mask & data);
  95 }
  96
  97 /* returns general purpose PMC with the specified MSR. Note that it can be
  98  * used for both PERFCTRn and EVNTSELn; that is why it accepts base as a
  99  * parameter to tell them apart.
 100  */
 101 static inline struct kvm_pmc *get_gp_pmc(struct kvm_pmu *pmu, u32 msr,
 102                                          u32 base)
 103 {
 104         if (msr >= base && msr < base + pmu->nr_arch_gp_counters) {
 105                 u32 index = array_index_nospec(msr - base,
 106                                                pmu->nr_arch_gp_counters);
 107
 108                 return &pmu->gp_counters[index];
 109         }
 110
 111         return NULL;
 112 }
 113
 114 /* returns fixed PMC with the specified MSR */
 115 static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr)
 116 {
 117         int base = MSR_CORE_PERF_FIXED_CTR0;
 118
 119         if (msr >= base && msr < base + pmu->nr_arch_fixed_counters) {
 120                 u32 index = array_index_nospec(msr - base,
 121                                                pmu->nr_arch_fixed_counters);
 122
 123                 return &pmu->fixed_counters[index];
 124         }
 125
 126         return NULL;
 127 }
 128
 129 static inline u64 get_sample_period(struct kvm_pmc *pmc, u64 counter_value)
 130 {
 131         u64 sample_period = (-counter_value) & pmc_bitmask(pmc);
 132
 133         if (!sample_period)
 134                 sample_period = pmc_bitmask(pmc) + 1;
 135         return sample_period;
 136 }
 137
 138 static inline void pmc_update_sample_period(struct kvm_pmc *pmc)
 139 {
 140         if (!pmc->perf_event || pmc->is_paused ||
 141             !is_sampling_event(pmc->perf_event))
 142                 return;
 143
 144         perf_event_period(pmc->perf_event,
 145                           get_sample_period(pmc, pmc->counter));
 146 }
 147
 148 static inline bool pmc_speculative_in_use(struct kvm_pmc *pmc)
 149 {
 150         struct kvm_pmu *pmu = pmc_to_pmu(pmc);
 151
 152         if (pmc_is_fixed(pmc))
 153                 return fixed_ctrl_field(pmu->fixed_ctr_ctrl,
 154                                         pmc->idx - INTEL_PMC_IDX_FIXED) & 0x3;
 155
 156         return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE;
 157 }
 158
 159 extern struct x86_pmu_capability kvm_pmu_cap;
 160
 161 static inline void kvm_init_pmu_capability(const struct kvm_pmu_ops *pmu_ops)
 162 {
 163         bool is_intel = boot_cpu_data.x86_vendor == X86_VENDOR_INTEL;
 164
 165         /*
 166          * Hybrid PMUs don't play nice with virtualization without careful
 167          * configuration by userspace, and KVM's APIs for reporting supported
 168          * vPMU features do not account for hybrid PMUs.  Disable vPMU support
 169          * for hybrid PMUs until KVM gains a way to let userspace opt-in.
 170          */
 171         if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
 172                 enable_pmu = false;
 173
 174         if (enable_pmu) {
 175                 perf_get_x86_pmu_capability(&kvm_pmu_cap);
 176
 177                 /*
 178                  * For Intel, only support guest architectural pmu
 179                  * on a host with architectural pmu.
 180                  */
 181                 if ((is_intel && !kvm_pmu_cap.version) ||
 182                     !kvm_pmu_cap.num_counters_gp)
 183                         enable_pmu = false;
 184         }
 185
 186         if (!enable_pmu) {
 187                 memset(&kvm_pmu_cap, 0, sizeof(kvm_pmu_cap));
 188                 return;
 189         }
 190
 191         kvm_pmu_cap.version = min(kvm_pmu_cap.version, 2);
 192         kvm_pmu_cap.num_counters_gp = min(kvm_pmu_cap.num_counters_gp,
 193                                           pmu_ops->MAX_NR_GP_COUNTERS);
 194         kvm_pmu_cap.num_counters_fixed = min(kvm_pmu_cap.num_counters_fixed,
 195                                              KVM_PMC_MAX_FIXED);
 196 }
 197
 198 static inline void kvm_pmu_request_counter_reprogram(struct kvm_pmc *pmc)
 199 {
 200         set_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi);
 201         kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
 202 }
 203
 204 void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu);
 205 void kvm_pmu_handle_event(struct kvm_vcpu *vcpu);
 206 int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data);
 207 bool kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx);
 208 bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr);
 209 int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
 210 int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
 211 void kvm_pmu_refresh(struct kvm_vcpu *vcpu);
 212 void kvm_pmu_reset(struct kvm_vcpu *vcpu);
 213 void kvm_pmu_init(struct kvm_vcpu *vcpu);
 214 void kvm_pmu_cleanup(struct kvm_vcpu *vcpu);
 215 void kvm_pmu_destroy(struct kvm_vcpu *vcpu);
 216 int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp);
 217 void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id);
 218
 219 bool is_vmware_backdoor_pmc(u32 pmc_idx);
 220
 221 extern struct kvm_pmu_ops intel_pmu_ops;
 222 extern struct kvm_pmu_ops amd_pmu_ops;
 223 #endif /* __KVM_X86_PMU_H */