1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
19 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
20 * so the code in this file is compiled twice, once per pte size.
24 #define pt_element_t u64
25 #define guest_walker guest_walker64
26 #define FNAME(name) paging##64_##name
27 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
28 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
29 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
30 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
31 #define PT_LEVEL_BITS PT64_LEVEL_BITS
32 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
33 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
34 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
36 #define PT_MAX_FULL_LEVELS 4
37 #define CMPXCHG cmpxchg
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
48 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
49 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
50 #define PT_LEVEL_BITS PT32_LEVEL_BITS
51 #define PT_MAX_FULL_LEVELS 2
52 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
53 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
54 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
55 #define CMPXCHG cmpxchg
56 #elif PTTYPE == PTTYPE_EPT
57 #define pt_element_t u64
58 #define guest_walker guest_walkerEPT
59 #define FNAME(name) ept_##name
60 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
61 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
62 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
63 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
64 #define PT_LEVEL_BITS PT64_LEVEL_BITS
65 #define PT_GUEST_DIRTY_SHIFT 9
66 #define PT_GUEST_ACCESSED_SHIFT 8
67 #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad)
68 #define CMPXCHG cmpxchg64
69 #define PT_MAX_FULL_LEVELS 4
71 #error Invalid PTTYPE value
74 #define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT)
75 #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT)
77 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
78 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
81 * The guest_walker structure emulates the behavior of the hardware page
87 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
88 pt_element_t ptes[PT_MAX_FULL_LEVELS];
89 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
90 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
91 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
92 bool pte_writable[PT_MAX_FULL_LEVELS];
96 struct x86_exception fault;
99 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
101 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
104 static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access,
109 /* dirty bit is not supported, so no need to track it */
110 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
113 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
115 mask = (unsigned)~ACC_WRITE_MASK;
116 /* Allow write access to dirty gptes */
117 mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
122 static inline int FNAME(is_present_gpte)(unsigned long pte)
124 #if PTTYPE != PTTYPE_EPT
125 return pte & PT_PRESENT_MASK;
131 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
132 pt_element_t __user *ptep_user, unsigned index,
133 pt_element_t orig_pte, pt_element_t new_pte)
140 npages = get_user_pages_fast((unsigned long)ptep_user, 1, FOLL_WRITE, &page);
141 if (likely(npages == 1)) {
142 table = kmap_atomic(page);
143 ret = CMPXCHG(&table[index], orig_pte, new_pte);
144 kunmap_atomic(table);
146 kvm_release_page_dirty(page);
148 struct vm_area_struct *vma;
149 unsigned long vaddr = (unsigned long)ptep_user & PAGE_MASK;
153 down_read(¤t->mm->mmap_sem);
154 vma = find_vma_intersection(current->mm, vaddr, vaddr + PAGE_SIZE);
155 if (!vma || !(vma->vm_flags & VM_PFNMAP)) {
156 up_read(¤t->mm->mmap_sem);
159 pfn = ((vaddr - vma->vm_start) >> PAGE_SHIFT) + vma->vm_pgoff;
160 paddr = pfn << PAGE_SHIFT;
161 table = memremap(paddr, PAGE_SIZE, MEMREMAP_WB);
163 up_read(¤t->mm->mmap_sem);
166 ret = CMPXCHG(&table[index], orig_pte, new_pte);
168 up_read(¤t->mm->mmap_sem);
171 return (ret != orig_pte);
174 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
175 struct kvm_mmu_page *sp, u64 *spte,
178 if (is_rsvd_bits_set(vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
181 if (!FNAME(is_present_gpte)(gpte))
184 /* if accessed bit is not supported prefetch non accessed gpte */
185 if (PT_HAVE_ACCESSED_DIRTY(vcpu->arch.mmu) &&
186 !(gpte & PT_GUEST_ACCESSED_MASK))
192 drop_spte(vcpu->kvm, spte);
197 * For PTTYPE_EPT, a page table can be executable but not readable
198 * on supported processors. Therefore, set_spte does not automatically
199 * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK
200 * to signify readability since it isn't used in the EPT case
202 static inline unsigned FNAME(gpte_access)(u64 gpte)
205 #if PTTYPE == PTTYPE_EPT
206 access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
207 ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
208 ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0);
210 BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK);
211 BUILD_BUG_ON(ACC_EXEC_MASK != 1);
212 access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK);
213 /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */
214 access ^= (gpte >> PT64_NX_SHIFT);
220 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
222 struct guest_walker *walker,
225 unsigned level, index;
226 pt_element_t pte, orig_pte;
227 pt_element_t __user *ptep_user;
231 /* dirty/accessed bits are not supported, so no need to update them */
232 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
235 for (level = walker->max_level; level >= walker->level; --level) {
236 pte = orig_pte = walker->ptes[level - 1];
237 table_gfn = walker->table_gfn[level - 1];
238 ptep_user = walker->ptep_user[level - 1];
239 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
240 if (!(pte & PT_GUEST_ACCESSED_MASK)) {
241 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
242 pte |= PT_GUEST_ACCESSED_MASK;
244 if (level == walker->level && write_fault &&
245 !(pte & PT_GUEST_DIRTY_MASK)) {
246 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
247 #if PTTYPE == PTTYPE_EPT
248 if (kvm_arch_write_log_dirty(vcpu))
251 pte |= PT_GUEST_DIRTY_MASK;
257 * If the slot is read-only, simply do not process the accessed
258 * and dirty bits. This is the correct thing to do if the slot
259 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
260 * are only supported if the accessed and dirty bits are already
261 * set in the ROM (so that MMIO writes are never needed).
263 * Note that NPT does not allow this at all and faults, since
264 * it always wants nested page table entries for the guest
265 * page tables to be writable. And EPT works but will simply
266 * overwrite the read-only memory to set the accessed and dirty
269 if (unlikely(!walker->pte_writable[level - 1]))
272 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
276 kvm_vcpu_mark_page_dirty(vcpu, table_gfn);
277 walker->ptes[level - 1] = pte;
282 static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte)
286 pte_t pte = {.pte = gpte};
288 pkeys = pte_flags_pkey(pte_flags(pte));
294 * Fetch a guest pte for a guest virtual address
296 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
297 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
298 gva_t addr, u32 access)
302 pt_element_t __user *uninitialized_var(ptep_user);
304 u64 pt_access, pte_access;
305 unsigned index, accessed_dirty, pte_pkey;
306 unsigned nested_access;
310 u64 walk_nx_mask = 0;
311 const int write_fault = access & PFERR_WRITE_MASK;
312 const int user_fault = access & PFERR_USER_MASK;
313 const int fetch_fault = access & PFERR_FETCH_MASK;
318 trace_kvm_mmu_pagetable_walk(addr, access);
320 walker->level = mmu->root_level;
321 pte = mmu->get_cr3(vcpu);
322 have_ad = PT_HAVE_ACCESSED_DIRTY(mmu);
325 walk_nx_mask = 1ULL << PT64_NX_SHIFT;
326 if (walker->level == PT32E_ROOT_LEVEL) {
327 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
328 trace_kvm_mmu_paging_element(pte, walker->level);
329 if (!FNAME(is_present_gpte)(pte))
334 walker->max_level = walker->level;
335 ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
338 * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging
339 * by the MOV to CR instruction are treated as reads and do not cause the
340 * processor to set the dirty flag in any EPT paging-structure entry.
342 nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK;
349 unsigned long host_addr;
351 pt_access = pte_access;
354 index = PT_INDEX(addr, walker->level);
355 table_gfn = gpte_to_gfn(pte);
356 offset = index * sizeof(pt_element_t);
357 pte_gpa = gfn_to_gpa(table_gfn) + offset;
359 BUG_ON(walker->level < 1);
360 walker->table_gfn[walker->level - 1] = table_gfn;
361 walker->pte_gpa[walker->level - 1] = pte_gpa;
363 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
368 * FIXME: This can happen if emulation (for of an INS/OUTS
369 * instruction) triggers a nested page fault. The exit
370 * qualification / exit info field will incorrectly have
371 * "guest page access" as the nested page fault's cause,
372 * instead of "guest page structure access". To fix this,
373 * the x86_exception struct should be augmented with enough
374 * information to fix the exit_qualification or exit_info_1
377 if (unlikely(real_gfn == UNMAPPED_GVA))
380 real_gfn = gpa_to_gfn(real_gfn);
382 host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn,
383 &walker->pte_writable[walker->level - 1]);
384 if (unlikely(kvm_is_error_hva(host_addr)))
387 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
388 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
390 walker->ptep_user[walker->level - 1] = ptep_user;
392 trace_kvm_mmu_paging_element(pte, walker->level);
395 * Inverting the NX it lets us AND it like other
398 pte_access = pt_access & (pte ^ walk_nx_mask);
400 if (unlikely(!FNAME(is_present_gpte)(pte)))
403 if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) {
404 errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
408 walker->ptes[walker->level - 1] = pte;
409 } while (!is_last_gpte(mmu, walker->level, pte));
411 pte_pkey = FNAME(gpte_pkeys)(vcpu, pte);
412 accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0;
414 /* Convert to ACC_*_MASK flags for struct guest_walker. */
415 walker->pt_access = FNAME(gpte_access)(pt_access ^ walk_nx_mask);
416 walker->pte_access = FNAME(gpte_access)(pte_access ^ walk_nx_mask);
417 errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access);
418 if (unlikely(errcode))
421 gfn = gpte_to_gfn_lvl(pte, walker->level);
422 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
424 if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
425 gfn += pse36_gfn_delta(pte);
427 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault);
428 if (real_gpa == UNMAPPED_GVA)
431 walker->gfn = real_gpa >> PAGE_SHIFT;
434 FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte);
437 * On a write fault, fold the dirty bit into accessed_dirty.
438 * For modes without A/D bits support accessed_dirty will be
441 accessed_dirty &= pte >>
442 (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
444 if (unlikely(!accessed_dirty)) {
445 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault);
446 if (unlikely(ret < 0))
452 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
453 __func__, (u64)pte, walker->pte_access, walker->pt_access);
457 errcode |= write_fault | user_fault;
458 if (fetch_fault && (mmu->nx ||
459 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
460 errcode |= PFERR_FETCH_MASK;
462 walker->fault.vector = PF_VECTOR;
463 walker->fault.error_code_valid = true;
464 walker->fault.error_code = errcode;
466 #if PTTYPE == PTTYPE_EPT
468 * Use PFERR_RSVD_MASK in error_code to to tell if EPT
469 * misconfiguration requires to be injected. The detection is
470 * done by is_rsvd_bits_set() above.
472 * We set up the value of exit_qualification to inject:
473 * [2:0] - Derive from the access bits. The exit_qualification might be
474 * out of date if it is serving an EPT misconfiguration.
475 * [5:3] - Calculated by the page walk of the guest EPT page tables
476 * [7:8] - Derived from [7:8] of real exit_qualification
478 * The other bits are set to 0.
480 if (!(errcode & PFERR_RSVD_MASK)) {
481 vcpu->arch.exit_qualification &= 0x180;
483 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_WRITE;
485 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_READ;
487 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_INSTR;
488 vcpu->arch.exit_qualification |= (pte_access & 0x7) << 3;
491 walker->fault.address = addr;
492 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
494 trace_kvm_mmu_walker_error(walker->fault.error_code);
498 static int FNAME(walk_addr)(struct guest_walker *walker,
499 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
501 return FNAME(walk_addr_generic)(walker, vcpu, vcpu->arch.mmu, addr,
505 #if PTTYPE != PTTYPE_EPT
506 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
507 struct kvm_vcpu *vcpu, gva_t addr,
510 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
516 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
517 u64 *spte, pt_element_t gpte, bool no_dirty_log)
523 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
526 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
528 gfn = gpte_to_gfn(gpte);
529 pte_access = sp->role.access & FNAME(gpte_access)(gpte);
530 FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte);
531 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
532 no_dirty_log && (pte_access & ACC_WRITE_MASK));
533 if (is_error_pfn(pfn))
537 * we call mmu_set_spte() with host_writable = true because
538 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
540 mmu_set_spte(vcpu, spte, pte_access, 0, PT_PAGE_TABLE_LEVEL, gfn, pfn,
546 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
547 u64 *spte, const void *pte)
549 pt_element_t gpte = *(const pt_element_t *)pte;
551 FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
554 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
555 struct guest_walker *gw, int level)
557 pt_element_t curr_pte;
558 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
562 if (level == PT_PAGE_TABLE_LEVEL) {
563 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
564 base_gpa = pte_gpa & ~mask;
565 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
567 r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa,
568 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
569 curr_pte = gw->prefetch_ptes[index];
571 r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa,
572 &curr_pte, sizeof(curr_pte));
574 return r || curr_pte != gw->ptes[level - 1];
577 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
580 struct kvm_mmu_page *sp;
581 pt_element_t *gptep = gw->prefetch_ptes;
585 sp = page_header(__pa(sptep));
587 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
591 return __direct_pte_prefetch(vcpu, sp, sptep);
593 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
596 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
600 if (is_shadow_present_pte(*spte))
603 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
609 * Fetch a shadow pte for a specific level in the paging hierarchy.
610 * If the guest tries to write a write-protected page, we need to
611 * emulate this operation, return 1 to indicate this case.
613 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
614 struct guest_walker *gw,
615 int write_fault, int hlevel,
616 kvm_pfn_t pfn, bool map_writable, bool prefault)
618 struct kvm_mmu_page *sp = NULL;
619 struct kvm_shadow_walk_iterator it;
620 unsigned direct_access, access = gw->pt_access;
623 direct_access = gw->pte_access;
625 top_level = vcpu->arch.mmu->root_level;
626 if (top_level == PT32E_ROOT_LEVEL)
627 top_level = PT32_ROOT_LEVEL;
629 * Verify that the top-level gpte is still there. Since the page
630 * is a root page, it is either write protected (and cannot be
631 * changed from now on) or it is invalid (in which case, we don't
632 * really care if it changes underneath us after this point).
634 if (FNAME(gpte_changed)(vcpu, gw, top_level))
635 goto out_gpte_changed;
637 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
638 goto out_gpte_changed;
640 for (shadow_walk_init(&it, vcpu, addr);
641 shadow_walk_okay(&it) && it.level > gw->level;
642 shadow_walk_next(&it)) {
645 clear_sp_write_flooding_count(it.sptep);
646 drop_large_spte(vcpu, it.sptep);
649 if (!is_shadow_present_pte(*it.sptep)) {
650 table_gfn = gw->table_gfn[it.level - 2];
651 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
656 * Verify that the gpte in the page we've just write
657 * protected is still there.
659 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
660 goto out_gpte_changed;
663 link_shadow_page(vcpu, it.sptep, sp);
667 shadow_walk_okay(&it) && it.level > hlevel;
668 shadow_walk_next(&it)) {
671 clear_sp_write_flooding_count(it.sptep);
672 validate_direct_spte(vcpu, it.sptep, direct_access);
674 drop_large_spte(vcpu, it.sptep);
676 if (is_shadow_present_pte(*it.sptep))
679 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
681 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
682 true, direct_access);
683 link_shadow_page(vcpu, it.sptep, sp);
686 clear_sp_write_flooding_count(it.sptep);
687 ret = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault,
688 it.level, gw->gfn, pfn, prefault, map_writable);
689 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
694 kvm_release_pfn_clean(pfn);
699 * To see whether the mapped gfn can write its page table in the current
702 * It is the helper function of FNAME(page_fault). When guest uses large page
703 * size to map the writable gfn which is used as current page table, we should
704 * force kvm to use small page size to map it because new shadow page will be
705 * created when kvm establishes shadow page table that stop kvm using large
706 * page size. Do it early can avoid unnecessary #PF and emulation.
708 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
709 * currently used as its page table.
711 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
712 * since the PDPT is always shadowed, that means, we can not use large page
713 * size to map the gfn which is used as PDPT.
716 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
717 struct guest_walker *walker, int user_fault,
718 bool *write_fault_to_shadow_pgtable)
721 gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
722 bool self_changed = false;
724 if (!(walker->pte_access & ACC_WRITE_MASK ||
725 (!is_write_protection(vcpu) && !user_fault)))
728 for (level = walker->level; level <= walker->max_level; level++) {
729 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
731 self_changed |= !(gfn & mask);
732 *write_fault_to_shadow_pgtable |= !gfn;
739 * Page fault handler. There are several causes for a page fault:
740 * - there is no shadow pte for the guest pte
741 * - write access through a shadow pte marked read only so that we can set
743 * - write access to a shadow pte marked read only so we can update the page
744 * dirty bitmap, when userspace requests it
745 * - mmio access; in this case we will never install a present shadow pte
746 * - normal guest page fault due to the guest pte marked not present, not
747 * writable, or not executable
749 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
750 * a negative value on error.
752 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
755 int write_fault = error_code & PFERR_WRITE_MASK;
756 int user_fault = error_code & PFERR_USER_MASK;
757 struct guest_walker walker;
760 int level = PT_PAGE_TABLE_LEVEL;
761 bool force_pt_level = false;
762 unsigned long mmu_seq;
763 bool map_writable, is_self_change_mapping;
765 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
767 r = mmu_topup_memory_caches(vcpu);
772 * If PFEC.RSVD is set, this is a shadow page fault.
773 * The bit needs to be cleared before walking guest page tables.
775 error_code &= ~PFERR_RSVD_MASK;
778 * Look up the guest pte for the faulting address.
780 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
783 * The page is not mapped by the guest. Let the guest handle it.
786 pgprintk("%s: guest page fault\n", __func__);
788 inject_page_fault(vcpu, &walker.fault);
793 if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) {
794 shadow_page_table_clear_flood(vcpu, addr);
795 return RET_PF_EMULATE;
798 vcpu->arch.write_fault_to_shadow_pgtable = false;
800 is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
801 &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
803 if (walker.level >= PT_DIRECTORY_LEVEL && !is_self_change_mapping) {
804 level = mapping_level(vcpu, walker.gfn, &force_pt_level);
805 if (likely(!force_pt_level)) {
806 level = min(walker.level, level);
807 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
810 force_pt_level = true;
812 mmu_seq = vcpu->kvm->mmu_notifier_seq;
815 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
819 if (handle_abnormal_pfn(vcpu, addr, walker.gfn, pfn, walker.pte_access, &r))
823 * Do not change pte_access if the pfn is a mmio page, otherwise
824 * we will cache the incorrect access into mmio spte.
826 if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
827 !is_write_protection(vcpu) && !user_fault &&
828 !is_noslot_pfn(pfn)) {
829 walker.pte_access |= ACC_WRITE_MASK;
830 walker.pte_access &= ~ACC_USER_MASK;
833 * If we converted a user page to a kernel page,
834 * so that the kernel can write to it when cr0.wp=0,
835 * then we should prevent the kernel from executing it
836 * if SMEP is enabled.
838 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
839 walker.pte_access &= ~ACC_EXEC_MASK;
842 spin_lock(&vcpu->kvm->mmu_lock);
843 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
846 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
847 if (make_mmu_pages_available(vcpu) < 0)
850 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
851 r = FNAME(fetch)(vcpu, addr, &walker, write_fault,
852 level, pfn, map_writable, prefault);
853 ++vcpu->stat.pf_fixed;
854 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
855 spin_unlock(&vcpu->kvm->mmu_lock);
860 spin_unlock(&vcpu->kvm->mmu_lock);
861 kvm_release_pfn_clean(pfn);
865 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
869 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
872 offset = sp->role.quadrant << PT64_LEVEL_BITS;
874 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
877 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa)
879 struct kvm_shadow_walk_iterator iterator;
880 struct kvm_mmu_page *sp;
884 vcpu_clear_mmio_info(vcpu, gva);
887 * No need to check return value here, rmap_can_add() can
888 * help us to skip pte prefetch later.
890 mmu_topup_memory_caches(vcpu);
892 if (!VALID_PAGE(root_hpa)) {
897 spin_lock(&vcpu->kvm->mmu_lock);
898 for_each_shadow_entry_using_root(vcpu, root_hpa, gva, iterator) {
899 level = iterator.level;
900 sptep = iterator.sptep;
902 sp = page_header(__pa(sptep));
903 if (is_last_spte(*sptep, level)) {
910 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
911 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
913 if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
914 kvm_flush_remote_tlbs_with_address(vcpu->kvm,
915 sp->gfn, KVM_PAGES_PER_HPAGE(sp->role.level));
917 if (!rmap_can_add(vcpu))
920 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
921 sizeof(pt_element_t)))
924 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
927 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
930 spin_unlock(&vcpu->kvm->mmu_lock);
933 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
934 struct x86_exception *exception)
936 struct guest_walker walker;
937 gpa_t gpa = UNMAPPED_GVA;
940 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
943 gpa = gfn_to_gpa(walker.gfn);
944 gpa |= vaddr & ~PAGE_MASK;
945 } else if (exception)
946 *exception = walker.fault;
951 #if PTTYPE != PTTYPE_EPT
952 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
954 struct x86_exception *exception)
956 struct guest_walker walker;
957 gpa_t gpa = UNMAPPED_GVA;
960 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
963 gpa = gfn_to_gpa(walker.gfn);
964 gpa |= vaddr & ~PAGE_MASK;
965 } else if (exception)
966 *exception = walker.fault;
973 * Using the cached information from sp->gfns is safe because:
974 * - The spte has a reference to the struct page, so the pfn for a given gfn
975 * can't change unless all sptes pointing to it are nuked first.
978 * We should flush all tlbs if spte is dropped even though guest is
979 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
980 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
981 * used by guest then tlbs are not flushed, so guest is allowed to access the
983 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
985 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
987 int i, nr_present = 0;
990 int set_spte_ret = 0;
992 /* direct kvm_mmu_page can not be unsync. */
993 BUG_ON(sp->role.direct);
995 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
997 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
1006 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
1008 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
1009 sizeof(pt_element_t)))
1012 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
1014 * Update spte before increasing tlbs_dirty to make
1015 * sure no tlb flush is lost after spte is zapped; see
1016 * the comments in kvm_flush_remote_tlbs().
1019 vcpu->kvm->tlbs_dirty++;
1023 gfn = gpte_to_gfn(gpte);
1024 pte_access = sp->role.access;
1025 pte_access &= FNAME(gpte_access)(gpte);
1026 FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte);
1028 if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access,
1032 if (gfn != sp->gfns[i]) {
1033 drop_spte(vcpu->kvm, &sp->spt[i]);
1035 * The same as above where we are doing
1036 * prefetch_invalid_gpte().
1039 vcpu->kvm->tlbs_dirty++;
1045 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
1047 set_spte_ret |= set_spte(vcpu, &sp->spt[i],
1048 pte_access, PT_PAGE_TABLE_LEVEL,
1049 gfn, spte_to_pfn(sp->spt[i]),
1050 true, false, host_writable);
1053 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH)
1054 kvm_flush_remote_tlbs(vcpu->kvm);
1062 #undef PT_BASE_ADDR_MASK
1064 #undef PT_LVL_ADDR_MASK
1065 #undef PT_LVL_OFFSET_MASK
1066 #undef PT_LEVEL_BITS
1067 #undef PT_MAX_FULL_LEVELS
1069 #undef gpte_to_gfn_lvl
1071 #undef PT_GUEST_ACCESSED_MASK
1072 #undef PT_GUEST_DIRTY_MASK
1073 #undef PT_GUEST_DIRTY_SHIFT
1074 #undef PT_GUEST_ACCESSED_SHIFT
1075 #undef PT_HAVE_ACCESSED_DIRTY