2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affilates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
35 #define PT_LEVEL_BITS PT64_LEVEL_BITS
37 #define PT_MAX_FULL_LEVELS 4
38 #define CMPXCHG cmpxchg
40 #define CMPXCHG cmpxchg64
41 #define PT_MAX_FULL_LEVELS 2
44 #define pt_element_t u32
45 #define guest_walker guest_walker32
46 #define FNAME(name) paging##32_##name
47 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
48 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
49 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
50 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
51 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
52 #define PT_LEVEL_BITS PT32_LEVEL_BITS
53 #define PT_MAX_FULL_LEVELS 2
54 #define CMPXCHG cmpxchg
56 #error Invalid PTTYPE value
59 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
60 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
63 * The guest_walker structure emulates the behavior of the hardware page
68 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
69 pt_element_t ptes[PT_MAX_FULL_LEVELS];
70 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
71 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
78 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
80 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
83 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
84 gfn_t table_gfn, unsigned index,
85 pt_element_t orig_pte, pt_element_t new_pte)
91 page = gfn_to_page(kvm, table_gfn);
93 table = kmap_atomic(page, KM_USER0);
94 ret = CMPXCHG(&table[index], orig_pte, new_pte);
95 kunmap_atomic(table, KM_USER0);
97 kvm_release_page_dirty(page);
99 return (ret != orig_pte);
102 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
106 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
109 access &= ~(gpte >> PT64_NX_SHIFT);
115 * Fetch a guest pte for a guest virtual address
117 static int FNAME(walk_addr)(struct guest_walker *walker,
118 struct kvm_vcpu *vcpu, gva_t addr,
119 int write_fault, int user_fault, int fetch_fault)
123 unsigned index, pt_access, uninitialized_var(pte_access);
125 bool eperm, present, rsvd_fault;
127 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
131 eperm = rsvd_fault = false;
132 walker->level = vcpu->arch.mmu.root_level;
133 pte = vcpu->arch.mmu.get_cr3(vcpu);
135 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
136 pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3);
137 trace_kvm_mmu_paging_element(pte, walker->level);
138 if (!is_present_gpte(pte)) {
145 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
146 (vcpu->arch.mmu.get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
151 index = PT_INDEX(addr, walker->level);
153 table_gfn = gpte_to_gfn(pte);
154 pte_gpa = gfn_to_gpa(table_gfn);
155 pte_gpa += index * sizeof(pt_element_t);
156 walker->table_gfn[walker->level - 1] = table_gfn;
157 walker->pte_gpa[walker->level - 1] = pte_gpa;
159 if (kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte))) {
164 trace_kvm_mmu_paging_element(pte, walker->level);
166 if (!is_present_gpte(pte)) {
171 if (is_rsvd_bits_set(&vcpu->arch.mmu, pte, walker->level)) {
176 if (write_fault && !is_writable_pte(pte))
177 if (user_fault || is_write_protection(vcpu))
180 if (user_fault && !(pte & PT_USER_MASK))
184 if (fetch_fault && (pte & PT64_NX_MASK))
188 if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) {
189 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
191 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
192 index, pte, pte|PT_ACCESSED_MASK))
194 mark_page_dirty(vcpu->kvm, table_gfn);
195 pte |= PT_ACCESSED_MASK;
198 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
200 walker->ptes[walker->level - 1] = pte;
202 if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
203 ((walker->level == PT_DIRECTORY_LEVEL) &&
205 (PTTYPE == 64 || is_pse(vcpu))) ||
206 ((walker->level == PT_PDPE_LEVEL) &&
208 vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL)) {
209 int lvl = walker->level;
211 walker->gfn = gpte_to_gfn_lvl(pte, lvl);
212 walker->gfn += (addr & PT_LVL_OFFSET_MASK(lvl))
216 walker->level == PT_DIRECTORY_LEVEL &&
218 walker->gfn += pse36_gfn_delta(pte);
223 pt_access = pte_access;
227 if (!present || eperm || rsvd_fault)
230 if (write_fault && !is_dirty_gpte(pte)) {
233 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
234 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
238 mark_page_dirty(vcpu->kvm, table_gfn);
239 pte |= PT_DIRTY_MASK;
240 walker->ptes[walker->level - 1] = pte;
243 walker->pt_access = pt_access;
244 walker->pte_access = pte_access;
245 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
246 __func__, (u64)pte, pte_access, pt_access);
250 walker->error_code = 0;
252 walker->error_code |= PFERR_PRESENT_MASK;
254 walker->error_code |= PFERR_WRITE_MASK;
256 walker->error_code |= PFERR_USER_MASK;
257 if (fetch_fault && is_nx(vcpu))
258 walker->error_code |= PFERR_FETCH_MASK;
260 walker->error_code |= PFERR_RSVD_MASK;
262 vcpu->arch.fault.address = addr;
263 vcpu->arch.fault.error_code = walker->error_code;
265 trace_kvm_mmu_walker_error(walker->error_code);
269 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
270 u64 *spte, const void *pte)
277 gpte = *(const pt_element_t *)pte;
278 if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
279 if (!is_present_gpte(gpte)) {
281 new_spte = shadow_trap_nonpresent_pte;
283 new_spte = shadow_notrap_nonpresent_pte;
284 __set_spte(spte, new_spte);
288 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
289 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
290 if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
292 pfn = vcpu->arch.update_pte.pfn;
293 if (is_error_pfn(pfn))
295 if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
299 * we call mmu_set_spte() with reset_host_protection = true beacuse that
300 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
302 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
303 is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL,
304 gpte_to_gfn(gpte), pfn, true, true);
307 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
308 struct guest_walker *gw, int level)
310 pt_element_t curr_pte;
311 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
315 if (level == PT_PAGE_TABLE_LEVEL) {
316 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
317 base_gpa = pte_gpa & ~mask;
318 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
320 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
321 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
322 curr_pte = gw->prefetch_ptes[index];
324 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
325 &curr_pte, sizeof(curr_pte));
327 return r || curr_pte != gw->ptes[level - 1];
330 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
333 struct kvm_mmu_page *sp;
334 struct kvm_mmu *mmu = &vcpu->arch.mmu;
335 pt_element_t *gptep = gw->prefetch_ptes;
339 sp = page_header(__pa(sptep));
341 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
345 return __direct_pte_prefetch(vcpu, sp, sptep);
347 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
350 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
360 if (*spte != shadow_trap_nonpresent_pte)
365 if (!is_present_gpte(gpte) ||
366 is_rsvd_bits_set(mmu, gpte, PT_PAGE_TABLE_LEVEL)) {
368 __set_spte(spte, shadow_notrap_nonpresent_pte);
372 if (!(gpte & PT_ACCESSED_MASK))
375 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
376 gfn = gpte_to_gfn(gpte);
377 dirty = is_dirty_gpte(gpte);
378 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
379 (pte_access & ACC_WRITE_MASK) && dirty);
380 if (is_error_pfn(pfn)) {
381 kvm_release_pfn_clean(pfn);
385 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
386 dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn,
392 * Fetch a shadow pte for a specific level in the paging hierarchy.
394 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
395 struct guest_walker *gw,
396 int user_fault, int write_fault, int hlevel,
397 int *ptwrite, pfn_t pfn)
399 unsigned access = gw->pt_access;
400 struct kvm_mmu_page *sp = NULL;
401 bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]);
403 unsigned direct_access;
404 struct kvm_shadow_walk_iterator it;
406 if (!is_present_gpte(gw->ptes[gw->level - 1]))
409 direct_access = gw->pt_access & gw->pte_access;
411 direct_access &= ~ACC_WRITE_MASK;
413 top_level = vcpu->arch.mmu.root_level;
414 if (top_level == PT32E_ROOT_LEVEL)
415 top_level = PT32_ROOT_LEVEL;
417 * Verify that the top-level gpte is still there. Since the page
418 * is a root page, it is either write protected (and cannot be
419 * changed from now on) or it is invalid (in which case, we don't
420 * really care if it changes underneath us after this point).
422 if (FNAME(gpte_changed)(vcpu, gw, top_level))
423 goto out_gpte_changed;
425 for (shadow_walk_init(&it, vcpu, addr);
426 shadow_walk_okay(&it) && it.level > gw->level;
427 shadow_walk_next(&it)) {
430 drop_large_spte(vcpu, it.sptep);
433 if (!is_shadow_present_pte(*it.sptep)) {
434 table_gfn = gw->table_gfn[it.level - 2];
435 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
436 false, access, it.sptep);
440 * Verify that the gpte in the page we've just write
441 * protected is still there.
443 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
444 goto out_gpte_changed;
447 link_shadow_page(it.sptep, sp);
451 shadow_walk_okay(&it) && it.level > hlevel;
452 shadow_walk_next(&it)) {
455 validate_direct_spte(vcpu, it.sptep, direct_access);
457 drop_large_spte(vcpu, it.sptep);
459 if (is_shadow_present_pte(*it.sptep))
462 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
464 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
465 true, direct_access, it.sptep);
466 link_shadow_page(it.sptep, sp);
469 mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access,
470 user_fault, write_fault, dirty, ptwrite, it.level,
471 gw->gfn, pfn, false, true);
472 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
478 kvm_mmu_put_page(sp, it.sptep);
479 kvm_release_pfn_clean(pfn);
484 * Page fault handler. There are several causes for a page fault:
485 * - there is no shadow pte for the guest pte
486 * - write access through a shadow pte marked read only so that we can set
488 * - write access to a shadow pte marked read only so we can update the page
489 * dirty bitmap, when userspace requests it
490 * - mmio access; in this case we will never install a present shadow pte
491 * - normal guest page fault due to the guest pte marked not present, not
492 * writable, or not executable
494 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
495 * a negative value on error.
497 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
500 int write_fault = error_code & PFERR_WRITE_MASK;
501 int user_fault = error_code & PFERR_USER_MASK;
502 int fetch_fault = error_code & PFERR_FETCH_MASK;
503 struct guest_walker walker;
508 int level = PT_PAGE_TABLE_LEVEL;
509 unsigned long mmu_seq;
511 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
513 r = mmu_topup_memory_caches(vcpu);
518 * Look up the guest pte for the faulting address.
520 r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
524 * The page is not mapped by the guest. Let the guest handle it.
527 pgprintk("%s: guest page fault\n", __func__);
528 inject_page_fault(vcpu);
529 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
533 if (walker.level >= PT_DIRECTORY_LEVEL) {
534 level = min(walker.level, mapping_level(vcpu, walker.gfn));
535 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
538 mmu_seq = vcpu->kvm->mmu_notifier_seq;
540 pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
543 if (is_error_pfn(pfn))
544 return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn);
546 spin_lock(&vcpu->kvm->mmu_lock);
547 if (mmu_notifier_retry(vcpu, mmu_seq))
550 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
551 kvm_mmu_free_some_pages(vcpu);
552 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
553 level, &write_pt, pfn);
555 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
556 sptep, *sptep, write_pt);
559 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
561 ++vcpu->stat.pf_fixed;
562 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
563 spin_unlock(&vcpu->kvm->mmu_lock);
568 spin_unlock(&vcpu->kvm->mmu_lock);
569 kvm_release_pfn_clean(pfn);
573 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
575 struct kvm_shadow_walk_iterator iterator;
576 struct kvm_mmu_page *sp;
582 spin_lock(&vcpu->kvm->mmu_lock);
584 for_each_shadow_entry(vcpu, gva, iterator) {
585 level = iterator.level;
586 sptep = iterator.sptep;
588 sp = page_header(__pa(sptep));
589 if (is_last_spte(*sptep, level)) {
596 (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
597 offset = sp->role.quadrant << shift;
599 pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
600 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
602 if (is_shadow_present_pte(*sptep)) {
603 if (is_large_pte(*sptep))
604 --vcpu->kvm->stat.lpages;
605 drop_spte(vcpu->kvm, sptep,
606 shadow_trap_nonpresent_pte);
609 __set_spte(sptep, shadow_trap_nonpresent_pte);
613 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
618 kvm_flush_remote_tlbs(vcpu->kvm);
620 atomic_inc(&vcpu->kvm->arch.invlpg_counter);
622 spin_unlock(&vcpu->kvm->mmu_lock);
627 if (mmu_topup_memory_caches(vcpu))
629 kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
632 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
635 struct guest_walker walker;
636 gpa_t gpa = UNMAPPED_GVA;
639 r = FNAME(walk_addr)(&walker, vcpu, vaddr,
640 !!(access & PFERR_WRITE_MASK),
641 !!(access & PFERR_USER_MASK),
642 !!(access & PFERR_FETCH_MASK));
645 gpa = gfn_to_gpa(walker.gfn);
646 gpa |= vaddr & ~PAGE_MASK;
648 *error = walker.error_code;
653 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
654 struct kvm_mmu_page *sp)
657 pt_element_t pt[256 / sizeof(pt_element_t)];
661 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
662 nonpaging_prefetch_page(vcpu, sp);
666 pte_gpa = gfn_to_gpa(sp->gfn);
668 offset = sp->role.quadrant << PT64_LEVEL_BITS;
669 pte_gpa += offset * sizeof(pt_element_t);
672 for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
673 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
674 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
675 for (j = 0; j < ARRAY_SIZE(pt); ++j)
676 if (r || is_present_gpte(pt[j]))
677 sp->spt[i+j] = shadow_trap_nonpresent_pte;
679 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
684 * Using the cached information from sp->gfns is safe because:
685 * - The spte has a reference to the struct page, so the pfn for a given gfn
686 * can't change unless all sptes pointing to it are nuked first.
688 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
691 int i, offset, nr_present;
692 bool reset_host_protection;
695 offset = nr_present = 0;
697 /* direct kvm_mmu_page can not be unsync. */
698 BUG_ON(sp->role.direct);
701 offset = sp->role.quadrant << PT64_LEVEL_BITS;
703 first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
705 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
711 if (!is_shadow_present_pte(sp->spt[i]))
714 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
716 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
717 sizeof(pt_element_t)))
720 gfn = gpte_to_gfn(gpte);
721 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)
722 || gfn != sp->gfns[i] || !is_present_gpte(gpte)
723 || !(gpte & PT_ACCESSED_MASK)) {
726 if (is_present_gpte(gpte) || !clear_unsync)
727 nonpresent = shadow_trap_nonpresent_pte;
729 nonpresent = shadow_notrap_nonpresent_pte;
730 drop_spte(vcpu->kvm, &sp->spt[i], nonpresent);
735 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
736 if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) {
737 pte_access &= ~ACC_WRITE_MASK;
738 reset_host_protection = 0;
740 reset_host_protection = 1;
742 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
743 is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
744 spte_to_pfn(sp->spt[i]), true, false,
745 reset_host_protection);
754 #undef PT_BASE_ADDR_MASK
757 #undef PT_LVL_ADDR_MASK
758 #undef PT_LVL_OFFSET_MASK
760 #undef PT_MAX_FULL_LEVELS
762 #undef gpte_to_gfn_lvl