2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/module.h>
33 #include <linux/swap.h>
34 #include <linux/hugetlb.h>
35 #include <linux/compiler.h>
36 #include <linux/srcu.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
41 #include <asm/cmpxchg.h>
44 #include <asm/kvm_page_track.h>
47 * When setting this variable to true it enables Two-Dimensional-Paging
48 * where the hardware walks 2 page tables:
49 * 1. the guest-virtual to guest-physical
50 * 2. while doing 1. it walks guest-physical to host-physical
51 * If the hardware supports that we don't need to do shadow paging.
53 bool tdp_enabled = false;
57 AUDIT_POST_PAGE_FAULT,
68 module_param(dbg, bool, 0644);
70 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
71 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
72 #define MMU_WARN_ON(x) WARN_ON(x)
74 #define pgprintk(x...) do { } while (0)
75 #define rmap_printk(x...) do { } while (0)
76 #define MMU_WARN_ON(x) do { } while (0)
79 #define PTE_PREFETCH_NUM 8
81 #define PT_FIRST_AVAIL_BITS_SHIFT 10
82 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
84 #define PT64_LEVEL_BITS 9
86 #define PT64_LEVEL_SHIFT(level) \
87 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
89 #define PT64_INDEX(address, level)\
90 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
93 #define PT32_LEVEL_BITS 10
95 #define PT32_LEVEL_SHIFT(level) \
96 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
98 #define PT32_LVL_OFFSET_MASK(level) \
99 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
100 * PT32_LEVEL_BITS))) - 1))
102 #define PT32_INDEX(address, level)\
103 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
106 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
107 #define PT64_DIR_BASE_ADDR_MASK \
108 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
109 #define PT64_LVL_ADDR_MASK(level) \
110 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
111 * PT64_LEVEL_BITS))) - 1))
112 #define PT64_LVL_OFFSET_MASK(level) \
113 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
114 * PT64_LEVEL_BITS))) - 1))
116 #define PT32_BASE_ADDR_MASK PAGE_MASK
117 #define PT32_DIR_BASE_ADDR_MASK \
118 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
119 #define PT32_LVL_ADDR_MASK(level) \
120 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
121 * PT32_LEVEL_BITS))) - 1))
123 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
124 | shadow_x_mask | shadow_nx_mask)
126 #define ACC_EXEC_MASK 1
127 #define ACC_WRITE_MASK PT_WRITABLE_MASK
128 #define ACC_USER_MASK PT_USER_MASK
129 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
131 #include <trace/events/kvm.h>
133 #define CREATE_TRACE_POINTS
134 #include "mmutrace.h"
136 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
137 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
139 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
141 /* make pte_list_desc fit well in cache line */
142 #define PTE_LIST_EXT 3
144 struct pte_list_desc {
145 u64 *sptes[PTE_LIST_EXT];
146 struct pte_list_desc *more;
149 struct kvm_shadow_walk_iterator {
157 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
158 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
159 shadow_walk_okay(&(_walker)); \
160 shadow_walk_next(&(_walker)))
162 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
163 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
164 shadow_walk_okay(&(_walker)) && \
165 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
166 __shadow_walk_next(&(_walker), spte))
168 static struct kmem_cache *pte_list_desc_cache;
169 static struct kmem_cache *mmu_page_header_cache;
170 static struct percpu_counter kvm_total_used_mmu_pages;
172 static u64 __read_mostly shadow_nx_mask;
173 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
174 static u64 __read_mostly shadow_user_mask;
175 static u64 __read_mostly shadow_accessed_mask;
176 static u64 __read_mostly shadow_dirty_mask;
177 static u64 __read_mostly shadow_mmio_mask;
179 static void mmu_spte_set(u64 *sptep, u64 spte);
180 static void mmu_free_roots(struct kvm_vcpu *vcpu);
182 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
184 shadow_mmio_mask = mmio_mask;
186 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
189 * the low bit of the generation number is always presumed to be zero.
190 * This disables mmio caching during memslot updates. The concept is
191 * similar to a seqcount but instead of retrying the access we just punt
192 * and ignore the cache.
194 * spte bits 3-11 are used as bits 1-9 of the generation number,
195 * the bits 52-61 are used as bits 10-19 of the generation number.
197 #define MMIO_SPTE_GEN_LOW_SHIFT 2
198 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
200 #define MMIO_GEN_SHIFT 20
201 #define MMIO_GEN_LOW_SHIFT 10
202 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
203 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
205 static u64 generation_mmio_spte_mask(unsigned int gen)
209 WARN_ON(gen & ~MMIO_GEN_MASK);
211 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
212 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
216 static unsigned int get_mmio_spte_generation(u64 spte)
220 spte &= ~shadow_mmio_mask;
222 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
223 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
227 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu)
229 return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK;
232 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
235 unsigned int gen = kvm_current_mmio_generation(vcpu);
236 u64 mask = generation_mmio_spte_mask(gen);
238 access &= ACC_WRITE_MASK | ACC_USER_MASK;
239 mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
241 trace_mark_mmio_spte(sptep, gfn, access, gen);
242 mmu_spte_set(sptep, mask);
245 static bool is_mmio_spte(u64 spte)
247 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
250 static gfn_t get_mmio_spte_gfn(u64 spte)
252 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
253 return (spte & ~mask) >> PAGE_SHIFT;
256 static unsigned get_mmio_spte_access(u64 spte)
258 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
259 return (spte & ~mask) & ~PAGE_MASK;
262 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
263 kvm_pfn_t pfn, unsigned access)
265 if (unlikely(is_noslot_pfn(pfn))) {
266 mark_mmio_spte(vcpu, sptep, gfn, access);
273 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
275 unsigned int kvm_gen, spte_gen;
277 kvm_gen = kvm_current_mmio_generation(vcpu);
278 spte_gen = get_mmio_spte_generation(spte);
280 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
281 return likely(kvm_gen == spte_gen);
284 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
285 u64 dirty_mask, u64 nx_mask, u64 x_mask)
287 shadow_user_mask = user_mask;
288 shadow_accessed_mask = accessed_mask;
289 shadow_dirty_mask = dirty_mask;
290 shadow_nx_mask = nx_mask;
291 shadow_x_mask = x_mask;
293 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
295 static int is_cpuid_PSE36(void)
300 static int is_nx(struct kvm_vcpu *vcpu)
302 return vcpu->arch.efer & EFER_NX;
305 static int is_shadow_present_pte(u64 pte)
307 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
310 static int is_large_pte(u64 pte)
312 return pte & PT_PAGE_SIZE_MASK;
315 static int is_last_spte(u64 pte, int level)
317 if (level == PT_PAGE_TABLE_LEVEL)
319 if (is_large_pte(pte))
324 static kvm_pfn_t spte_to_pfn(u64 pte)
326 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
329 static gfn_t pse36_gfn_delta(u32 gpte)
331 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
333 return (gpte & PT32_DIR_PSE36_MASK) << shift;
337 static void __set_spte(u64 *sptep, u64 spte)
342 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
347 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
349 return xchg(sptep, spte);
352 static u64 __get_spte_lockless(u64 *sptep)
354 return ACCESS_ONCE(*sptep);
365 static void count_spte_clear(u64 *sptep, u64 spte)
367 struct kvm_mmu_page *sp = page_header(__pa(sptep));
369 if (is_shadow_present_pte(spte))
372 /* Ensure the spte is completely set before we increase the count */
374 sp->clear_spte_count++;
377 static void __set_spte(u64 *sptep, u64 spte)
379 union split_spte *ssptep, sspte;
381 ssptep = (union split_spte *)sptep;
382 sspte = (union split_spte)spte;
384 ssptep->spte_high = sspte.spte_high;
387 * If we map the spte from nonpresent to present, We should store
388 * the high bits firstly, then set present bit, so cpu can not
389 * fetch this spte while we are setting the spte.
393 ssptep->spte_low = sspte.spte_low;
396 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
398 union split_spte *ssptep, sspte;
400 ssptep = (union split_spte *)sptep;
401 sspte = (union split_spte)spte;
403 ssptep->spte_low = sspte.spte_low;
406 * If we map the spte from present to nonpresent, we should clear
407 * present bit firstly to avoid vcpu fetch the old high bits.
411 ssptep->spte_high = sspte.spte_high;
412 count_spte_clear(sptep, spte);
415 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
417 union split_spte *ssptep, sspte, orig;
419 ssptep = (union split_spte *)sptep;
420 sspte = (union split_spte)spte;
422 /* xchg acts as a barrier before the setting of the high bits */
423 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
424 orig.spte_high = ssptep->spte_high;
425 ssptep->spte_high = sspte.spte_high;
426 count_spte_clear(sptep, spte);
432 * The idea using the light way get the spte on x86_32 guest is from
433 * gup_get_pte(arch/x86/mm/gup.c).
435 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
436 * coalesces them and we are running out of the MMU lock. Therefore
437 * we need to protect against in-progress updates of the spte.
439 * Reading the spte while an update is in progress may get the old value
440 * for the high part of the spte. The race is fine for a present->non-present
441 * change (because the high part of the spte is ignored for non-present spte),
442 * but for a present->present change we must reread the spte.
444 * All such changes are done in two steps (present->non-present and
445 * non-present->present), hence it is enough to count the number of
446 * present->non-present updates: if it changed while reading the spte,
447 * we might have hit the race. This is done using clear_spte_count.
449 static u64 __get_spte_lockless(u64 *sptep)
451 struct kvm_mmu_page *sp = page_header(__pa(sptep));
452 union split_spte spte, *orig = (union split_spte *)sptep;
456 count = sp->clear_spte_count;
459 spte.spte_low = orig->spte_low;
462 spte.spte_high = orig->spte_high;
465 if (unlikely(spte.spte_low != orig->spte_low ||
466 count != sp->clear_spte_count))
473 static bool spte_is_locklessly_modifiable(u64 spte)
475 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
476 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
479 static bool spte_has_volatile_bits(u64 spte)
482 * Always atomically update spte if it can be updated
483 * out of mmu-lock, it can ensure dirty bit is not lost,
484 * also, it can help us to get a stable is_writable_pte()
485 * to ensure tlb flush is not missed.
487 if (spte_is_locklessly_modifiable(spte))
490 if (!shadow_accessed_mask)
493 if (!is_shadow_present_pte(spte))
496 if ((spte & shadow_accessed_mask) &&
497 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
503 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
505 return (old_spte & bit_mask) && !(new_spte & bit_mask);
508 static bool spte_is_bit_changed(u64 old_spte, u64 new_spte, u64 bit_mask)
510 return (old_spte & bit_mask) != (new_spte & bit_mask);
513 /* Rules for using mmu_spte_set:
514 * Set the sptep from nonpresent to present.
515 * Note: the sptep being assigned *must* be either not present
516 * or in a state where the hardware will not attempt to update
519 static void mmu_spte_set(u64 *sptep, u64 new_spte)
521 WARN_ON(is_shadow_present_pte(*sptep));
522 __set_spte(sptep, new_spte);
525 /* Rules for using mmu_spte_update:
526 * Update the state bits, it means the mapped pfn is not changged.
528 * Whenever we overwrite a writable spte with a read-only one we
529 * should flush remote TLBs. Otherwise rmap_write_protect
530 * will find a read-only spte, even though the writable spte
531 * might be cached on a CPU's TLB, the return value indicates this
534 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
536 u64 old_spte = *sptep;
539 WARN_ON(!is_shadow_present_pte(new_spte));
541 if (!is_shadow_present_pte(old_spte)) {
542 mmu_spte_set(sptep, new_spte);
546 if (!spte_has_volatile_bits(old_spte))
547 __update_clear_spte_fast(sptep, new_spte);
549 old_spte = __update_clear_spte_slow(sptep, new_spte);
552 * For the spte updated out of mmu-lock is safe, since
553 * we always atomically update it, see the comments in
554 * spte_has_volatile_bits().
556 if (spte_is_locklessly_modifiable(old_spte) &&
557 !is_writable_pte(new_spte))
560 if (!shadow_accessed_mask) {
562 * We don't set page dirty when dropping non-writable spte.
563 * So do it now if the new spte is becoming non-writable.
566 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
571 * Flush TLB when accessed/dirty bits are changed in the page tables,
572 * to guarantee consistency between TLB and page tables.
574 if (spte_is_bit_changed(old_spte, new_spte,
575 shadow_accessed_mask | shadow_dirty_mask))
578 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
579 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
580 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
581 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
587 * Rules for using mmu_spte_clear_track_bits:
588 * It sets the sptep from present to nonpresent, and track the
589 * state bits, it is used to clear the last level sptep.
591 static int mmu_spte_clear_track_bits(u64 *sptep)
594 u64 old_spte = *sptep;
596 if (!spte_has_volatile_bits(old_spte))
597 __update_clear_spte_fast(sptep, 0ull);
599 old_spte = __update_clear_spte_slow(sptep, 0ull);
601 if (!is_shadow_present_pte(old_spte))
604 pfn = spte_to_pfn(old_spte);
607 * KVM does not hold the refcount of the page used by
608 * kvm mmu, before reclaiming the page, we should
609 * unmap it from mmu first.
611 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
613 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
614 kvm_set_pfn_accessed(pfn);
615 if (old_spte & (shadow_dirty_mask ? shadow_dirty_mask :
617 kvm_set_pfn_dirty(pfn);
622 * Rules for using mmu_spte_clear_no_track:
623 * Directly clear spte without caring the state bits of sptep,
624 * it is used to set the upper level spte.
626 static void mmu_spte_clear_no_track(u64 *sptep)
628 __update_clear_spte_fast(sptep, 0ull);
631 static u64 mmu_spte_get_lockless(u64 *sptep)
633 return __get_spte_lockless(sptep);
636 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
639 * Prevent page table teardown by making any free-er wait during
640 * kvm_flush_remote_tlbs() IPI to all active vcpus.
645 * Make sure a following spte read is not reordered ahead of the write
648 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
651 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
654 * Make sure the write to vcpu->mode is not reordered in front of
655 * reads to sptes. If it does, kvm_commit_zap_page() can see us
656 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
658 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
662 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
663 struct kmem_cache *base_cache, int min)
667 if (cache->nobjs >= min)
669 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
670 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
673 cache->objects[cache->nobjs++] = obj;
678 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
683 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
684 struct kmem_cache *cache)
687 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
690 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
695 if (cache->nobjs >= min)
697 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
698 page = (void *)__get_free_page(GFP_KERNEL);
701 cache->objects[cache->nobjs++] = page;
706 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
709 free_page((unsigned long)mc->objects[--mc->nobjs]);
712 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
716 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
717 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
720 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
723 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
724 mmu_page_header_cache, 4);
729 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
731 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
732 pte_list_desc_cache);
733 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
734 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
735 mmu_page_header_cache);
738 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
743 p = mc->objects[--mc->nobjs];
747 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
749 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
752 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
754 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
757 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
759 if (!sp->role.direct)
760 return sp->gfns[index];
762 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
765 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
768 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
770 sp->gfns[index] = gfn;
774 * Return the pointer to the large page information for a given gfn,
775 * handling slots that are not large page aligned.
777 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
778 struct kvm_memory_slot *slot,
783 idx = gfn_to_index(gfn, slot->base_gfn, level);
784 return &slot->arch.lpage_info[level - 2][idx];
787 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
788 gfn_t gfn, int count)
790 struct kvm_lpage_info *linfo;
793 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
794 linfo = lpage_info_slot(gfn, slot, i);
795 linfo->disallow_lpage += count;
796 WARN_ON(linfo->disallow_lpage < 0);
800 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
802 update_gfn_disallow_lpage_count(slot, gfn, 1);
805 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
807 update_gfn_disallow_lpage_count(slot, gfn, -1);
810 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
812 struct kvm_memslots *slots;
813 struct kvm_memory_slot *slot;
816 kvm->arch.indirect_shadow_pages++;
818 slots = kvm_memslots_for_spte_role(kvm, sp->role);
819 slot = __gfn_to_memslot(slots, gfn);
821 /* the non-leaf shadow pages are keeping readonly. */
822 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
823 return kvm_slot_page_track_add_page(kvm, slot, gfn,
824 KVM_PAGE_TRACK_WRITE);
826 kvm_mmu_gfn_disallow_lpage(slot, gfn);
829 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
831 struct kvm_memslots *slots;
832 struct kvm_memory_slot *slot;
835 kvm->arch.indirect_shadow_pages--;
837 slots = kvm_memslots_for_spte_role(kvm, sp->role);
838 slot = __gfn_to_memslot(slots, gfn);
839 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
840 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
841 KVM_PAGE_TRACK_WRITE);
843 kvm_mmu_gfn_allow_lpage(slot, gfn);
846 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
847 struct kvm_memory_slot *slot)
849 struct kvm_lpage_info *linfo;
852 linfo = lpage_info_slot(gfn, slot, level);
853 return !!linfo->disallow_lpage;
859 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
862 struct kvm_memory_slot *slot;
864 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
865 return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
868 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
870 unsigned long page_size;
873 page_size = kvm_host_page_size(kvm, gfn);
875 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
876 if (page_size >= KVM_HPAGE_SIZE(i))
885 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
888 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
890 if (no_dirty_log && slot->dirty_bitmap)
896 static struct kvm_memory_slot *
897 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
900 struct kvm_memory_slot *slot;
902 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
903 if (!memslot_valid_for_gpte(slot, no_dirty_log))
909 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
910 bool *force_pt_level)
912 int host_level, level, max_level;
913 struct kvm_memory_slot *slot;
915 if (unlikely(*force_pt_level))
916 return PT_PAGE_TABLE_LEVEL;
918 slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
919 *force_pt_level = !memslot_valid_for_gpte(slot, true);
920 if (unlikely(*force_pt_level))
921 return PT_PAGE_TABLE_LEVEL;
923 host_level = host_mapping_level(vcpu->kvm, large_gfn);
925 if (host_level == PT_PAGE_TABLE_LEVEL)
928 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
930 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
931 if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot))
938 * About rmap_head encoding:
940 * If the bit zero of rmap_head->val is clear, then it points to the only spte
941 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
942 * pte_list_desc containing more mappings.
946 * Returns the number of pointers in the rmap chain, not counting the new one.
948 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
949 struct kvm_rmap_head *rmap_head)
951 struct pte_list_desc *desc;
954 if (!rmap_head->val) {
955 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
956 rmap_head->val = (unsigned long)spte;
957 } else if (!(rmap_head->val & 1)) {
958 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
959 desc = mmu_alloc_pte_list_desc(vcpu);
960 desc->sptes[0] = (u64 *)rmap_head->val;
961 desc->sptes[1] = spte;
962 rmap_head->val = (unsigned long)desc | 1;
965 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
966 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
967 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
969 count += PTE_LIST_EXT;
971 if (desc->sptes[PTE_LIST_EXT-1]) {
972 desc->more = mmu_alloc_pte_list_desc(vcpu);
975 for (i = 0; desc->sptes[i]; ++i)
977 desc->sptes[i] = spte;
983 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
984 struct pte_list_desc *desc, int i,
985 struct pte_list_desc *prev_desc)
989 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
991 desc->sptes[i] = desc->sptes[j];
992 desc->sptes[j] = NULL;
995 if (!prev_desc && !desc->more)
996 rmap_head->val = (unsigned long)desc->sptes[0];
999 prev_desc->more = desc->more;
1001 rmap_head->val = (unsigned long)desc->more | 1;
1002 mmu_free_pte_list_desc(desc);
1005 static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1007 struct pte_list_desc *desc;
1008 struct pte_list_desc *prev_desc;
1011 if (!rmap_head->val) {
1012 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
1014 } else if (!(rmap_head->val & 1)) {
1015 rmap_printk("pte_list_remove: %p 1->0\n", spte);
1016 if ((u64 *)rmap_head->val != spte) {
1017 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
1022 rmap_printk("pte_list_remove: %p many->many\n", spte);
1023 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1026 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1027 if (desc->sptes[i] == spte) {
1028 pte_list_desc_remove_entry(rmap_head,
1029 desc, i, prev_desc);
1036 pr_err("pte_list_remove: %p many->many\n", spte);
1041 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1042 struct kvm_memory_slot *slot)
1046 idx = gfn_to_index(gfn, slot->base_gfn, level);
1047 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1050 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1051 struct kvm_mmu_page *sp)
1053 struct kvm_memslots *slots;
1054 struct kvm_memory_slot *slot;
1056 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1057 slot = __gfn_to_memslot(slots, gfn);
1058 return __gfn_to_rmap(gfn, sp->role.level, slot);
1061 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1063 struct kvm_mmu_memory_cache *cache;
1065 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1066 return mmu_memory_cache_free_objects(cache);
1069 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1071 struct kvm_mmu_page *sp;
1072 struct kvm_rmap_head *rmap_head;
1074 sp = page_header(__pa(spte));
1075 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1076 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1077 return pte_list_add(vcpu, spte, rmap_head);
1080 static void rmap_remove(struct kvm *kvm, u64 *spte)
1082 struct kvm_mmu_page *sp;
1084 struct kvm_rmap_head *rmap_head;
1086 sp = page_header(__pa(spte));
1087 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1088 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1089 pte_list_remove(spte, rmap_head);
1093 * Used by the following functions to iterate through the sptes linked by a
1094 * rmap. All fields are private and not assumed to be used outside.
1096 struct rmap_iterator {
1097 /* private fields */
1098 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1099 int pos; /* index of the sptep */
1103 * Iteration must be started by this function. This should also be used after
1104 * removing/dropping sptes from the rmap link because in such cases the
1105 * information in the itererator may not be valid.
1107 * Returns sptep if found, NULL otherwise.
1109 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1110 struct rmap_iterator *iter)
1114 if (!rmap_head->val)
1117 if (!(rmap_head->val & 1)) {
1119 sptep = (u64 *)rmap_head->val;
1123 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1125 sptep = iter->desc->sptes[iter->pos];
1127 BUG_ON(!is_shadow_present_pte(*sptep));
1132 * Must be used with a valid iterator: e.g. after rmap_get_first().
1134 * Returns sptep if found, NULL otherwise.
1136 static u64 *rmap_get_next(struct rmap_iterator *iter)
1141 if (iter->pos < PTE_LIST_EXT - 1) {
1143 sptep = iter->desc->sptes[iter->pos];
1148 iter->desc = iter->desc->more;
1152 /* desc->sptes[0] cannot be NULL */
1153 sptep = iter->desc->sptes[iter->pos];
1160 BUG_ON(!is_shadow_present_pte(*sptep));
1164 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1165 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1166 _spte_; _spte_ = rmap_get_next(_iter_))
1168 static void drop_spte(struct kvm *kvm, u64 *sptep)
1170 if (mmu_spte_clear_track_bits(sptep))
1171 rmap_remove(kvm, sptep);
1175 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1177 if (is_large_pte(*sptep)) {
1178 WARN_ON(page_header(__pa(sptep))->role.level ==
1179 PT_PAGE_TABLE_LEVEL);
1180 drop_spte(kvm, sptep);
1188 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1190 if (__drop_large_spte(vcpu->kvm, sptep))
1191 kvm_flush_remote_tlbs(vcpu->kvm);
1195 * Write-protect on the specified @sptep, @pt_protect indicates whether
1196 * spte write-protection is caused by protecting shadow page table.
1198 * Note: write protection is difference between dirty logging and spte
1200 * - for dirty logging, the spte can be set to writable at anytime if
1201 * its dirty bitmap is properly set.
1202 * - for spte protection, the spte can be writable only after unsync-ing
1205 * Return true if tlb need be flushed.
1207 static bool spte_write_protect(struct kvm *kvm, u64 *sptep, bool pt_protect)
1211 if (!is_writable_pte(spte) &&
1212 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1215 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1218 spte &= ~SPTE_MMU_WRITEABLE;
1219 spte = spte & ~PT_WRITABLE_MASK;
1221 return mmu_spte_update(sptep, spte);
1224 static bool __rmap_write_protect(struct kvm *kvm,
1225 struct kvm_rmap_head *rmap_head,
1229 struct rmap_iterator iter;
1232 for_each_rmap_spte(rmap_head, &iter, sptep)
1233 flush |= spte_write_protect(kvm, sptep, pt_protect);
1238 static bool spte_clear_dirty(struct kvm *kvm, u64 *sptep)
1242 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1244 spte &= ~shadow_dirty_mask;
1246 return mmu_spte_update(sptep, spte);
1249 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1252 struct rmap_iterator iter;
1255 for_each_rmap_spte(rmap_head, &iter, sptep)
1256 flush |= spte_clear_dirty(kvm, sptep);
1261 static bool spte_set_dirty(struct kvm *kvm, u64 *sptep)
1265 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1267 spte |= shadow_dirty_mask;
1269 return mmu_spte_update(sptep, spte);
1272 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1275 struct rmap_iterator iter;
1278 for_each_rmap_spte(rmap_head, &iter, sptep)
1279 flush |= spte_set_dirty(kvm, sptep);
1285 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1286 * @kvm: kvm instance
1287 * @slot: slot to protect
1288 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1289 * @mask: indicates which pages we should protect
1291 * Used when we do not need to care about huge page mappings: e.g. during dirty
1292 * logging we do not have any such mappings.
1294 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1295 struct kvm_memory_slot *slot,
1296 gfn_t gfn_offset, unsigned long mask)
1298 struct kvm_rmap_head *rmap_head;
1301 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1302 PT_PAGE_TABLE_LEVEL, slot);
1303 __rmap_write_protect(kvm, rmap_head, false);
1305 /* clear the first set bit */
1311 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages
1312 * @kvm: kvm instance
1313 * @slot: slot to clear D-bit
1314 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1315 * @mask: indicates which pages we should clear D-bit
1317 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1319 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1320 struct kvm_memory_slot *slot,
1321 gfn_t gfn_offset, unsigned long mask)
1323 struct kvm_rmap_head *rmap_head;
1326 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1327 PT_PAGE_TABLE_LEVEL, slot);
1328 __rmap_clear_dirty(kvm, rmap_head);
1330 /* clear the first set bit */
1334 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1337 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1340 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1341 * enable dirty logging for them.
1343 * Used when we do not need to care about huge page mappings: e.g. during dirty
1344 * logging we do not have any such mappings.
1346 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1347 struct kvm_memory_slot *slot,
1348 gfn_t gfn_offset, unsigned long mask)
1350 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1351 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1354 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1357 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1358 struct kvm_memory_slot *slot, u64 gfn)
1360 struct kvm_rmap_head *rmap_head;
1362 bool write_protected = false;
1364 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1365 rmap_head = __gfn_to_rmap(gfn, i, slot);
1366 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1369 return write_protected;
1372 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1374 struct kvm_memory_slot *slot;
1376 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1377 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1380 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1383 struct rmap_iterator iter;
1386 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1387 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1389 drop_spte(kvm, sptep);
1396 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1397 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1400 return kvm_zap_rmapp(kvm, rmap_head);
1403 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1404 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1408 struct rmap_iterator iter;
1411 pte_t *ptep = (pte_t *)data;
1414 WARN_ON(pte_huge(*ptep));
1415 new_pfn = pte_pfn(*ptep);
1418 for_each_rmap_spte(rmap_head, &iter, sptep) {
1419 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1420 sptep, *sptep, gfn, level);
1424 if (pte_write(*ptep)) {
1425 drop_spte(kvm, sptep);
1428 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1429 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1431 new_spte &= ~PT_WRITABLE_MASK;
1432 new_spte &= ~SPTE_HOST_WRITEABLE;
1433 new_spte &= ~shadow_accessed_mask;
1435 mmu_spte_clear_track_bits(sptep);
1436 mmu_spte_set(sptep, new_spte);
1441 kvm_flush_remote_tlbs(kvm);
1446 struct slot_rmap_walk_iterator {
1448 struct kvm_memory_slot *slot;
1454 /* output fields. */
1456 struct kvm_rmap_head *rmap;
1459 /* private field. */
1460 struct kvm_rmap_head *end_rmap;
1464 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1466 iterator->level = level;
1467 iterator->gfn = iterator->start_gfn;
1468 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1469 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1474 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1475 struct kvm_memory_slot *slot, int start_level,
1476 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1478 iterator->slot = slot;
1479 iterator->start_level = start_level;
1480 iterator->end_level = end_level;
1481 iterator->start_gfn = start_gfn;
1482 iterator->end_gfn = end_gfn;
1484 rmap_walk_init_level(iterator, iterator->start_level);
1487 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1489 return !!iterator->rmap;
1492 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1494 if (++iterator->rmap <= iterator->end_rmap) {
1495 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1499 if (++iterator->level > iterator->end_level) {
1500 iterator->rmap = NULL;
1504 rmap_walk_init_level(iterator, iterator->level);
1507 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1508 _start_gfn, _end_gfn, _iter_) \
1509 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1510 _end_level_, _start_gfn, _end_gfn); \
1511 slot_rmap_walk_okay(_iter_); \
1512 slot_rmap_walk_next(_iter_))
1514 static int kvm_handle_hva_range(struct kvm *kvm,
1515 unsigned long start,
1518 int (*handler)(struct kvm *kvm,
1519 struct kvm_rmap_head *rmap_head,
1520 struct kvm_memory_slot *slot,
1523 unsigned long data))
1525 struct kvm_memslots *slots;
1526 struct kvm_memory_slot *memslot;
1527 struct slot_rmap_walk_iterator iterator;
1531 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1532 slots = __kvm_memslots(kvm, i);
1533 kvm_for_each_memslot(memslot, slots) {
1534 unsigned long hva_start, hva_end;
1535 gfn_t gfn_start, gfn_end;
1537 hva_start = max(start, memslot->userspace_addr);
1538 hva_end = min(end, memslot->userspace_addr +
1539 (memslot->npages << PAGE_SHIFT));
1540 if (hva_start >= hva_end)
1543 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1544 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1546 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1547 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1549 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1550 PT_MAX_HUGEPAGE_LEVEL,
1551 gfn_start, gfn_end - 1,
1553 ret |= handler(kvm, iterator.rmap, memslot,
1554 iterator.gfn, iterator.level, data);
1561 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1563 int (*handler)(struct kvm *kvm,
1564 struct kvm_rmap_head *rmap_head,
1565 struct kvm_memory_slot *slot,
1566 gfn_t gfn, int level,
1567 unsigned long data))
1569 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1572 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1574 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1577 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1579 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1582 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1584 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1587 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1588 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1592 struct rmap_iterator uninitialized_var(iter);
1595 BUG_ON(!shadow_accessed_mask);
1597 for_each_rmap_spte(rmap_head, &iter, sptep) {
1598 if (*sptep & shadow_accessed_mask) {
1600 clear_bit((ffs(shadow_accessed_mask) - 1),
1601 (unsigned long *)sptep);
1605 trace_kvm_age_page(gfn, level, slot, young);
1609 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1610 struct kvm_memory_slot *slot, gfn_t gfn,
1611 int level, unsigned long data)
1614 struct rmap_iterator iter;
1618 * If there's no access bit in the secondary pte set by the
1619 * hardware it's up to gup-fast/gup to set the access bit in
1620 * the primary pte or in the page structure.
1622 if (!shadow_accessed_mask)
1625 for_each_rmap_spte(rmap_head, &iter, sptep) {
1626 if (*sptep & shadow_accessed_mask) {
1635 #define RMAP_RECYCLE_THRESHOLD 1000
1637 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1639 struct kvm_rmap_head *rmap_head;
1640 struct kvm_mmu_page *sp;
1642 sp = page_header(__pa(spte));
1644 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1646 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1647 kvm_flush_remote_tlbs(vcpu->kvm);
1650 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1653 * In case of absence of EPT Access and Dirty Bits supports,
1654 * emulate the accessed bit for EPT, by checking if this page has
1655 * an EPT mapping, and clearing it if it does. On the next access,
1656 * a new EPT mapping will be established.
1657 * This has some overhead, but not as much as the cost of swapping
1658 * out actively used pages or breaking up actively used hugepages.
1660 if (!shadow_accessed_mask) {
1662 * We are holding the kvm->mmu_lock, and we are blowing up
1663 * shadow PTEs. MMU notifier consumers need to be kept at bay.
1664 * This is correct as long as we don't decouple the mmu_lock
1665 * protected regions (like invalidate_range_start|end does).
1667 kvm->mmu_notifier_seq++;
1668 return kvm_handle_hva_range(kvm, start, end, 0,
1672 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1675 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1677 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1681 static int is_empty_shadow_page(u64 *spt)
1686 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1687 if (is_shadow_present_pte(*pos)) {
1688 printk(KERN_ERR "%s: %p %llx\n", __func__,
1697 * This value is the sum of all of the kvm instances's
1698 * kvm->arch.n_used_mmu_pages values. We need a global,
1699 * aggregate version in order to make the slab shrinker
1702 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1704 kvm->arch.n_used_mmu_pages += nr;
1705 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1708 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1710 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1711 hlist_del(&sp->hash_link);
1712 list_del(&sp->link);
1713 free_page((unsigned long)sp->spt);
1714 if (!sp->role.direct)
1715 free_page((unsigned long)sp->gfns);
1716 kmem_cache_free(mmu_page_header_cache, sp);
1719 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1721 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1724 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1725 struct kvm_mmu_page *sp, u64 *parent_pte)
1730 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1733 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1736 pte_list_remove(parent_pte, &sp->parent_ptes);
1739 static void drop_parent_pte(struct kvm_mmu_page *sp,
1742 mmu_page_remove_parent_pte(sp, parent_pte);
1743 mmu_spte_clear_no_track(parent_pte);
1746 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1748 struct kvm_mmu_page *sp;
1750 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1751 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1753 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1754 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1757 * The active_mmu_pages list is the FIFO list, do not move the
1758 * page until it is zapped. kvm_zap_obsolete_pages depends on
1759 * this feature. See the comments in kvm_zap_obsolete_pages().
1761 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1762 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1766 static void mark_unsync(u64 *spte);
1767 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1770 struct rmap_iterator iter;
1772 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1777 static void mark_unsync(u64 *spte)
1779 struct kvm_mmu_page *sp;
1782 sp = page_header(__pa(spte));
1783 index = spte - sp->spt;
1784 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1786 if (sp->unsync_children++)
1788 kvm_mmu_mark_parents_unsync(sp);
1791 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1792 struct kvm_mmu_page *sp)
1797 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1801 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1802 struct kvm_mmu_page *sp, u64 *spte,
1808 #define KVM_PAGE_ARRAY_NR 16
1810 struct kvm_mmu_pages {
1811 struct mmu_page_and_offset {
1812 struct kvm_mmu_page *sp;
1814 } page[KVM_PAGE_ARRAY_NR];
1818 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1824 for (i=0; i < pvec->nr; i++)
1825 if (pvec->page[i].sp == sp)
1828 pvec->page[pvec->nr].sp = sp;
1829 pvec->page[pvec->nr].idx = idx;
1831 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1834 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1836 --sp->unsync_children;
1837 WARN_ON((int)sp->unsync_children < 0);
1838 __clear_bit(idx, sp->unsync_child_bitmap);
1841 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1842 struct kvm_mmu_pages *pvec)
1844 int i, ret, nr_unsync_leaf = 0;
1846 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1847 struct kvm_mmu_page *child;
1848 u64 ent = sp->spt[i];
1850 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1851 clear_unsync_child_bit(sp, i);
1855 child = page_header(ent & PT64_BASE_ADDR_MASK);
1857 if (child->unsync_children) {
1858 if (mmu_pages_add(pvec, child, i))
1861 ret = __mmu_unsync_walk(child, pvec);
1863 clear_unsync_child_bit(sp, i);
1865 } else if (ret > 0) {
1866 nr_unsync_leaf += ret;
1869 } else if (child->unsync) {
1871 if (mmu_pages_add(pvec, child, i))
1874 clear_unsync_child_bit(sp, i);
1877 return nr_unsync_leaf;
1880 #define INVALID_INDEX (-1)
1882 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1883 struct kvm_mmu_pages *pvec)
1886 if (!sp->unsync_children)
1889 mmu_pages_add(pvec, sp, INVALID_INDEX);
1890 return __mmu_unsync_walk(sp, pvec);
1893 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1895 WARN_ON(!sp->unsync);
1896 trace_kvm_mmu_sync_page(sp);
1898 --kvm->stat.mmu_unsync;
1901 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1902 struct list_head *invalid_list);
1903 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1904 struct list_head *invalid_list);
1907 * NOTE: we should pay more attention on the zapped-obsolete page
1908 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1909 * since it has been deleted from active_mmu_pages but still can be found
1912 * for_each_gfn_indirect_valid_sp has skipped that kind of page and
1913 * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped
1914 * all the obsolete pages.
1916 #define for_each_gfn_sp(_kvm, _sp, _gfn) \
1917 hlist_for_each_entry(_sp, \
1918 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1919 if ((_sp)->gfn != (_gfn)) {} else
1921 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1922 for_each_gfn_sp(_kvm, _sp, _gfn) \
1923 if ((_sp)->role.direct || (_sp)->role.invalid) {} else
1925 /* @sp->gfn should be write-protected at the call site */
1926 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1927 struct list_head *invalid_list)
1929 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1930 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1934 if (vcpu->arch.mmu.sync_page(vcpu, sp) == 0) {
1935 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1942 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1943 struct list_head *invalid_list,
1944 bool remote_flush, bool local_flush)
1946 if (!list_empty(invalid_list)) {
1947 kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list);
1952 kvm_flush_remote_tlbs(vcpu->kvm);
1953 else if (local_flush)
1954 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1957 #ifdef CONFIG_KVM_MMU_AUDIT
1958 #include "mmu_audit.c"
1960 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1961 static void mmu_audit_disable(void) { }
1964 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1965 struct list_head *invalid_list)
1967 kvm_unlink_unsync_page(vcpu->kvm, sp);
1968 return __kvm_sync_page(vcpu, sp, invalid_list);
1971 /* @gfn should be write-protected at the call site */
1972 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
1973 struct list_head *invalid_list)
1975 struct kvm_mmu_page *s;
1978 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1982 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1983 ret |= kvm_sync_page(vcpu, s, invalid_list);
1989 struct mmu_page_path {
1990 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL];
1991 unsigned int idx[PT64_ROOT_LEVEL];
1994 #define for_each_sp(pvec, sp, parents, i) \
1995 for (i = mmu_pages_first(&pvec, &parents); \
1996 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1997 i = mmu_pages_next(&pvec, &parents, i))
1999 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2000 struct mmu_page_path *parents,
2005 for (n = i+1; n < pvec->nr; n++) {
2006 struct kvm_mmu_page *sp = pvec->page[n].sp;
2007 unsigned idx = pvec->page[n].idx;
2008 int level = sp->role.level;
2010 parents->idx[level-1] = idx;
2011 if (level == PT_PAGE_TABLE_LEVEL)
2014 parents->parent[level-2] = sp;
2020 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2021 struct mmu_page_path *parents)
2023 struct kvm_mmu_page *sp;
2029 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2031 sp = pvec->page[0].sp;
2032 level = sp->role.level;
2033 WARN_ON(level == PT_PAGE_TABLE_LEVEL);
2035 parents->parent[level-2] = sp;
2037 /* Also set up a sentinel. Further entries in pvec are all
2038 * children of sp, so this element is never overwritten.
2040 parents->parent[level-1] = NULL;
2041 return mmu_pages_next(pvec, parents, 0);
2044 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2046 struct kvm_mmu_page *sp;
2047 unsigned int level = 0;
2050 unsigned int idx = parents->idx[level];
2051 sp = parents->parent[level];
2055 WARN_ON(idx == INVALID_INDEX);
2056 clear_unsync_child_bit(sp, idx);
2058 } while (!sp->unsync_children);
2061 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2062 struct kvm_mmu_page *parent)
2065 struct kvm_mmu_page *sp;
2066 struct mmu_page_path parents;
2067 struct kvm_mmu_pages pages;
2068 LIST_HEAD(invalid_list);
2071 while (mmu_unsync_walk(parent, &pages)) {
2072 bool protected = false;
2074 for_each_sp(pages, sp, parents, i)
2075 protected |= rmap_write_protect(vcpu, sp->gfn);
2078 kvm_flush_remote_tlbs(vcpu->kvm);
2082 for_each_sp(pages, sp, parents, i) {
2083 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2084 mmu_pages_clear_parents(&parents);
2086 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2087 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2088 cond_resched_lock(&vcpu->kvm->mmu_lock);
2093 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2096 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2098 atomic_set(&sp->write_flooding_count, 0);
2101 static void clear_sp_write_flooding_count(u64 *spte)
2103 struct kvm_mmu_page *sp = page_header(__pa(spte));
2105 __clear_sp_write_flooding_count(sp);
2108 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
2110 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
2113 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2120 union kvm_mmu_page_role role;
2122 struct kvm_mmu_page *sp;
2123 bool need_sync = false;
2125 LIST_HEAD(invalid_list);
2127 role = vcpu->arch.mmu.base_role;
2129 role.direct = direct;
2132 role.access = access;
2133 if (!vcpu->arch.mmu.direct_map
2134 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
2135 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2136 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2137 role.quadrant = quadrant;
2139 for_each_gfn_sp(vcpu->kvm, sp, gfn) {
2140 if (is_obsolete_sp(vcpu->kvm, sp))
2143 if (!need_sync && sp->unsync)
2146 if (sp->role.word != role.word)
2150 /* The page is good, but __kvm_sync_page might still end
2151 * up zapping it. If so, break in order to rebuild it.
2153 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2156 WARN_ON(!list_empty(&invalid_list));
2157 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2160 if (sp->unsync_children)
2161 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2163 __clear_sp_write_flooding_count(sp);
2164 trace_kvm_mmu_get_page(sp, false);
2168 ++vcpu->kvm->stat.mmu_cache_miss;
2170 sp = kvm_mmu_alloc_page(vcpu, direct);
2174 hlist_add_head(&sp->hash_link,
2175 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2178 * we should do write protection before syncing pages
2179 * otherwise the content of the synced shadow page may
2180 * be inconsistent with guest page table.
2182 account_shadowed(vcpu->kvm, sp);
2183 if (level == PT_PAGE_TABLE_LEVEL &&
2184 rmap_write_protect(vcpu, gfn))
2185 kvm_flush_remote_tlbs(vcpu->kvm);
2187 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2188 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2190 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2191 clear_page(sp->spt);
2192 trace_kvm_mmu_get_page(sp, true);
2194 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2198 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2199 struct kvm_vcpu *vcpu, u64 addr)
2201 iterator->addr = addr;
2202 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
2203 iterator->level = vcpu->arch.mmu.shadow_root_level;
2205 if (iterator->level == PT64_ROOT_LEVEL &&
2206 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
2207 !vcpu->arch.mmu.direct_map)
2210 if (iterator->level == PT32E_ROOT_LEVEL) {
2211 iterator->shadow_addr
2212 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2213 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2215 if (!iterator->shadow_addr)
2216 iterator->level = 0;
2220 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2222 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2225 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2226 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2230 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2233 if (is_last_spte(spte, iterator->level)) {
2234 iterator->level = 0;
2238 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2242 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2244 return __shadow_walk_next(iterator, *iterator->sptep);
2247 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2248 struct kvm_mmu_page *sp)
2252 BUILD_BUG_ON(VMX_EPT_READABLE_MASK != PT_PRESENT_MASK ||
2253 VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2255 spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
2256 shadow_user_mask | shadow_x_mask | shadow_accessed_mask;
2258 mmu_spte_set(sptep, spte);
2260 mmu_page_add_parent_pte(vcpu, sp, sptep);
2262 if (sp->unsync_children || sp->unsync)
2266 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2267 unsigned direct_access)
2269 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2270 struct kvm_mmu_page *child;
2273 * For the direct sp, if the guest pte's dirty bit
2274 * changed form clean to dirty, it will corrupt the
2275 * sp's access: allow writable in the read-only sp,
2276 * so we should update the spte at this point to get
2277 * a new sp with the correct access.
2279 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2280 if (child->role.access == direct_access)
2283 drop_parent_pte(child, sptep);
2284 kvm_flush_remote_tlbs(vcpu->kvm);
2288 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2292 struct kvm_mmu_page *child;
2295 if (is_shadow_present_pte(pte)) {
2296 if (is_last_spte(pte, sp->role.level)) {
2297 drop_spte(kvm, spte);
2298 if (is_large_pte(pte))
2301 child = page_header(pte & PT64_BASE_ADDR_MASK);
2302 drop_parent_pte(child, spte);
2307 if (is_mmio_spte(pte))
2308 mmu_spte_clear_no_track(spte);
2313 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2314 struct kvm_mmu_page *sp)
2318 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2319 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2322 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2325 struct rmap_iterator iter;
2327 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2328 drop_parent_pte(sp, sptep);
2331 static int mmu_zap_unsync_children(struct kvm *kvm,
2332 struct kvm_mmu_page *parent,
2333 struct list_head *invalid_list)
2336 struct mmu_page_path parents;
2337 struct kvm_mmu_pages pages;
2339 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2342 while (mmu_unsync_walk(parent, &pages)) {
2343 struct kvm_mmu_page *sp;
2345 for_each_sp(pages, sp, parents, i) {
2346 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2347 mmu_pages_clear_parents(&parents);
2355 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2356 struct list_head *invalid_list)
2360 trace_kvm_mmu_prepare_zap_page(sp);
2361 ++kvm->stat.mmu_shadow_zapped;
2362 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2363 kvm_mmu_page_unlink_children(kvm, sp);
2364 kvm_mmu_unlink_parents(kvm, sp);
2366 if (!sp->role.invalid && !sp->role.direct)
2367 unaccount_shadowed(kvm, sp);
2370 kvm_unlink_unsync_page(kvm, sp);
2371 if (!sp->root_count) {
2374 list_move(&sp->link, invalid_list);
2375 kvm_mod_used_mmu_pages(kvm, -1);
2377 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2380 * The obsolete pages can not be used on any vcpus.
2381 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2383 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2384 kvm_reload_remote_mmus(kvm);
2387 sp->role.invalid = 1;
2391 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2392 struct list_head *invalid_list)
2394 struct kvm_mmu_page *sp, *nsp;
2396 if (list_empty(invalid_list))
2400 * We need to make sure everyone sees our modifications to
2401 * the page tables and see changes to vcpu->mode here. The barrier
2402 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2403 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2405 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2406 * guest mode and/or lockless shadow page table walks.
2408 kvm_flush_remote_tlbs(kvm);
2410 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2411 WARN_ON(!sp->role.invalid || sp->root_count);
2412 kvm_mmu_free_page(sp);
2416 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2417 struct list_head *invalid_list)
2419 struct kvm_mmu_page *sp;
2421 if (list_empty(&kvm->arch.active_mmu_pages))
2424 sp = list_last_entry(&kvm->arch.active_mmu_pages,
2425 struct kvm_mmu_page, link);
2426 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2432 * Changing the number of mmu pages allocated to the vm
2433 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2435 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2437 LIST_HEAD(invalid_list);
2439 spin_lock(&kvm->mmu_lock);
2441 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2442 /* Need to free some mmu pages to achieve the goal. */
2443 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2444 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2447 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2448 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2451 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2453 spin_unlock(&kvm->mmu_lock);
2456 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2458 struct kvm_mmu_page *sp;
2459 LIST_HEAD(invalid_list);
2462 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2464 spin_lock(&kvm->mmu_lock);
2465 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2466 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2469 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2471 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2472 spin_unlock(&kvm->mmu_lock);
2476 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2478 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2480 trace_kvm_mmu_unsync_page(sp);
2481 ++vcpu->kvm->stat.mmu_unsync;
2484 kvm_mmu_mark_parents_unsync(sp);
2487 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2490 struct kvm_mmu_page *sp;
2492 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2495 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2502 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
2503 kvm_unsync_page(vcpu, sp);
2509 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
2512 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn));
2517 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2518 unsigned pte_access, int level,
2519 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2520 bool can_unsync, bool host_writable)
2525 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2528 spte = PT_PRESENT_MASK;
2530 spte |= shadow_accessed_mask;
2532 if (pte_access & ACC_EXEC_MASK)
2533 spte |= shadow_x_mask;
2535 spte |= shadow_nx_mask;
2537 if (pte_access & ACC_USER_MASK)
2538 spte |= shadow_user_mask;
2540 if (level > PT_PAGE_TABLE_LEVEL)
2541 spte |= PT_PAGE_SIZE_MASK;
2543 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2544 kvm_is_mmio_pfn(pfn));
2547 spte |= SPTE_HOST_WRITEABLE;
2549 pte_access &= ~ACC_WRITE_MASK;
2551 spte |= (u64)pfn << PAGE_SHIFT;
2553 if (pte_access & ACC_WRITE_MASK) {
2556 * Other vcpu creates new sp in the window between
2557 * mapping_level() and acquiring mmu-lock. We can
2558 * allow guest to retry the access, the mapping can
2559 * be fixed if guest refault.
2561 if (level > PT_PAGE_TABLE_LEVEL &&
2562 mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
2565 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2568 * Optimization: for pte sync, if spte was writable the hash
2569 * lookup is unnecessary (and expensive). Write protection
2570 * is responsibility of mmu_get_page / kvm_sync_page.
2571 * Same reasoning can be applied to dirty page accounting.
2573 if (!can_unsync && is_writable_pte(*sptep))
2576 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2577 pgprintk("%s: found shadow page for %llx, marking ro\n",
2580 pte_access &= ~ACC_WRITE_MASK;
2581 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2585 if (pte_access & ACC_WRITE_MASK) {
2586 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2587 spte |= shadow_dirty_mask;
2591 if (mmu_spte_update(sptep, spte))
2592 kvm_flush_remote_tlbs(vcpu->kvm);
2597 static bool mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
2598 int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
2599 bool speculative, bool host_writable)
2601 int was_rmapped = 0;
2603 bool emulate = false;
2605 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2606 *sptep, write_fault, gfn);
2608 if (is_shadow_present_pte(*sptep)) {
2610 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2611 * the parent of the now unreachable PTE.
2613 if (level > PT_PAGE_TABLE_LEVEL &&
2614 !is_large_pte(*sptep)) {
2615 struct kvm_mmu_page *child;
2618 child = page_header(pte & PT64_BASE_ADDR_MASK);
2619 drop_parent_pte(child, sptep);
2620 kvm_flush_remote_tlbs(vcpu->kvm);
2621 } else if (pfn != spte_to_pfn(*sptep)) {
2622 pgprintk("hfn old %llx new %llx\n",
2623 spte_to_pfn(*sptep), pfn);
2624 drop_spte(vcpu->kvm, sptep);
2625 kvm_flush_remote_tlbs(vcpu->kvm);
2630 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2631 true, host_writable)) {
2634 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2637 if (unlikely(is_mmio_spte(*sptep)))
2640 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2641 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2642 is_large_pte(*sptep)? "2MB" : "4kB",
2643 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2645 if (!was_rmapped && is_large_pte(*sptep))
2646 ++vcpu->kvm->stat.lpages;
2648 if (is_shadow_present_pte(*sptep)) {
2650 rmap_count = rmap_add(vcpu, sptep, gfn);
2651 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2652 rmap_recycle(vcpu, sptep, gfn);
2656 kvm_release_pfn_clean(pfn);
2661 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2664 struct kvm_memory_slot *slot;
2666 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2668 return KVM_PFN_ERR_FAULT;
2670 return gfn_to_pfn_memslot_atomic(slot, gfn);
2673 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2674 struct kvm_mmu_page *sp,
2675 u64 *start, u64 *end)
2677 struct page *pages[PTE_PREFETCH_NUM];
2678 struct kvm_memory_slot *slot;
2679 unsigned access = sp->role.access;
2683 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2684 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2688 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2692 for (i = 0; i < ret; i++, gfn++, start++)
2693 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
2694 page_to_pfn(pages[i]), true, true);
2699 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2700 struct kvm_mmu_page *sp, u64 *sptep)
2702 u64 *spte, *start = NULL;
2705 WARN_ON(!sp->role.direct);
2707 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2710 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2711 if (is_shadow_present_pte(*spte) || spte == sptep) {
2714 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2722 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2724 struct kvm_mmu_page *sp;
2727 * Since it's no accessed bit on EPT, it's no way to
2728 * distinguish between actually accessed translations
2729 * and prefetched, so disable pte prefetch if EPT is
2732 if (!shadow_accessed_mask)
2735 sp = page_header(__pa(sptep));
2736 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2739 __direct_pte_prefetch(vcpu, sp, sptep);
2742 static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable,
2743 int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault)
2745 struct kvm_shadow_walk_iterator iterator;
2746 struct kvm_mmu_page *sp;
2750 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2753 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2754 if (iterator.level == level) {
2755 emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2756 write, level, gfn, pfn, prefault,
2758 direct_pte_prefetch(vcpu, iterator.sptep);
2759 ++vcpu->stat.pf_fixed;
2763 drop_large_spte(vcpu, iterator.sptep);
2764 if (!is_shadow_present_pte(*iterator.sptep)) {
2765 u64 base_addr = iterator.addr;
2767 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2768 pseudo_gfn = base_addr >> PAGE_SHIFT;
2769 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2770 iterator.level - 1, 1, ACC_ALL);
2772 link_shadow_page(vcpu, iterator.sptep, sp);
2778 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2782 info.si_signo = SIGBUS;
2784 info.si_code = BUS_MCEERR_AR;
2785 info.si_addr = (void __user *)address;
2786 info.si_addr_lsb = PAGE_SHIFT;
2788 send_sig_info(SIGBUS, &info, tsk);
2791 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2794 * Do not cache the mmio info caused by writing the readonly gfn
2795 * into the spte otherwise read access on readonly gfn also can
2796 * caused mmio page fault and treat it as mmio access.
2797 * Return 1 to tell kvm to emulate it.
2799 if (pfn == KVM_PFN_ERR_RO_FAULT)
2802 if (pfn == KVM_PFN_ERR_HWPOISON) {
2803 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2810 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2811 gfn_t *gfnp, kvm_pfn_t *pfnp,
2814 kvm_pfn_t pfn = *pfnp;
2816 int level = *levelp;
2819 * Check if it's a transparent hugepage. If this would be an
2820 * hugetlbfs page, level wouldn't be set to
2821 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2824 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
2825 level == PT_PAGE_TABLE_LEVEL &&
2826 PageTransCompound(pfn_to_page(pfn)) &&
2827 !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
2830 * mmu_notifier_retry was successful and we hold the
2831 * mmu_lock here, so the pmd can't become splitting
2832 * from under us, and in turn
2833 * __split_huge_page_refcount() can't run from under
2834 * us and we can safely transfer the refcount from
2835 * PG_tail to PG_head as we switch the pfn to tail to
2838 *levelp = level = PT_DIRECTORY_LEVEL;
2839 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2840 VM_BUG_ON((gfn & mask) != (pfn & mask));
2844 kvm_release_pfn_clean(pfn);
2852 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2853 kvm_pfn_t pfn, unsigned access, int *ret_val)
2855 /* The pfn is invalid, report the error! */
2856 if (unlikely(is_error_pfn(pfn))) {
2857 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2861 if (unlikely(is_noslot_pfn(pfn)))
2862 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2867 static bool page_fault_can_be_fast(u32 error_code)
2870 * Do not fix the mmio spte with invalid generation number which
2871 * need to be updated by slow page fault path.
2873 if (unlikely(error_code & PFERR_RSVD_MASK))
2877 * #PF can be fast only if the shadow page table is present and it
2878 * is caused by write-protect, that means we just need change the
2879 * W bit of the spte which can be done out of mmu-lock.
2881 if (!(error_code & PFERR_PRESENT_MASK) ||
2882 !(error_code & PFERR_WRITE_MASK))
2889 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2890 u64 *sptep, u64 spte)
2894 WARN_ON(!sp->role.direct);
2897 * The gfn of direct spte is stable since it is calculated
2900 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2903 * Theoretically we could also set dirty bit (and flush TLB) here in
2904 * order to eliminate unnecessary PML logging. See comments in
2905 * set_spte. But fast_page_fault is very unlikely to happen with PML
2906 * enabled, so we do not do this. This might result in the same GPA
2907 * to be logged in PML buffer again when the write really happens, and
2908 * eventually to be called by mark_page_dirty twice. But it's also no
2909 * harm. This also avoids the TLB flush needed after setting dirty bit
2910 * so non-PML cases won't be impacted.
2912 * Compare with set_spte where instead shadow_dirty_mask is set.
2914 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2915 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2922 * - true: let the vcpu to access on the same address again.
2923 * - false: let the real page fault path to fix it.
2925 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2928 struct kvm_shadow_walk_iterator iterator;
2929 struct kvm_mmu_page *sp;
2933 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2936 if (!page_fault_can_be_fast(error_code))
2939 walk_shadow_page_lockless_begin(vcpu);
2940 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2941 if (!is_shadow_present_pte(spte) || iterator.level < level)
2945 * If the mapping has been changed, let the vcpu fault on the
2946 * same address again.
2948 if (!is_shadow_present_pte(spte)) {
2953 sp = page_header(__pa(iterator.sptep));
2954 if (!is_last_spte(spte, sp->role.level))
2958 * Check if it is a spurious fault caused by TLB lazily flushed.
2960 * Need not check the access of upper level table entries since
2961 * they are always ACC_ALL.
2963 if (is_writable_pte(spte)) {
2969 * Currently, to simplify the code, only the spte write-protected
2970 * by dirty-log can be fast fixed.
2972 if (!spte_is_locklessly_modifiable(spte))
2976 * Do not fix write-permission on the large spte since we only dirty
2977 * the first page into the dirty-bitmap in fast_pf_fix_direct_spte()
2978 * that means other pages are missed if its slot is dirty-logged.
2980 * Instead, we let the slow page fault path create a normal spte to
2983 * See the comments in kvm_arch_commit_memory_region().
2985 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2989 * Currently, fast page fault only works for direct mapping since
2990 * the gfn is not stable for indirect shadow page.
2991 * See Documentation/virtual/kvm/locking.txt to get more detail.
2993 ret = fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte);
2995 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2997 walk_shadow_page_lockless_end(vcpu);
3002 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3003 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable);
3004 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
3006 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
3007 gfn_t gfn, bool prefault)
3011 bool force_pt_level = false;
3013 unsigned long mmu_seq;
3014 bool map_writable, write = error_code & PFERR_WRITE_MASK;
3016 level = mapping_level(vcpu, gfn, &force_pt_level);
3017 if (likely(!force_pt_level)) {
3019 * This path builds a PAE pagetable - so we can map
3020 * 2mb pages at maximum. Therefore check if the level
3021 * is larger than that.
3023 if (level > PT_DIRECTORY_LEVEL)
3024 level = PT_DIRECTORY_LEVEL;
3026 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3029 if (fast_page_fault(vcpu, v, level, error_code))
3032 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3035 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3038 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3041 spin_lock(&vcpu->kvm->mmu_lock);
3042 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3044 make_mmu_pages_available(vcpu);
3045 if (likely(!force_pt_level))
3046 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3047 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3048 spin_unlock(&vcpu->kvm->mmu_lock);
3053 spin_unlock(&vcpu->kvm->mmu_lock);
3054 kvm_release_pfn_clean(pfn);
3059 static void mmu_free_roots(struct kvm_vcpu *vcpu)
3062 struct kvm_mmu_page *sp;
3063 LIST_HEAD(invalid_list);
3065 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3068 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
3069 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
3070 vcpu->arch.mmu.direct_map)) {
3071 hpa_t root = vcpu->arch.mmu.root_hpa;
3073 spin_lock(&vcpu->kvm->mmu_lock);
3074 sp = page_header(root);
3076 if (!sp->root_count && sp->role.invalid) {
3077 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3078 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3080 spin_unlock(&vcpu->kvm->mmu_lock);
3081 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3085 spin_lock(&vcpu->kvm->mmu_lock);
3086 for (i = 0; i < 4; ++i) {
3087 hpa_t root = vcpu->arch.mmu.pae_root[i];
3090 root &= PT64_BASE_ADDR_MASK;
3091 sp = page_header(root);
3093 if (!sp->root_count && sp->role.invalid)
3094 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3097 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3099 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3100 spin_unlock(&vcpu->kvm->mmu_lock);
3101 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3104 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3108 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3109 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3116 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3118 struct kvm_mmu_page *sp;
3121 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3122 spin_lock(&vcpu->kvm->mmu_lock);
3123 make_mmu_pages_available(vcpu);
3124 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, 1, ACC_ALL);
3126 spin_unlock(&vcpu->kvm->mmu_lock);
3127 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3128 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3129 for (i = 0; i < 4; ++i) {
3130 hpa_t root = vcpu->arch.mmu.pae_root[i];
3132 MMU_WARN_ON(VALID_PAGE(root));
3133 spin_lock(&vcpu->kvm->mmu_lock);
3134 make_mmu_pages_available(vcpu);
3135 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3136 i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3137 root = __pa(sp->spt);
3139 spin_unlock(&vcpu->kvm->mmu_lock);
3140 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3142 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3149 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3151 struct kvm_mmu_page *sp;
3156 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3158 if (mmu_check_root(vcpu, root_gfn))
3162 * Do we shadow a long mode page table? If so we need to
3163 * write-protect the guests page table root.
3165 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3166 hpa_t root = vcpu->arch.mmu.root_hpa;
3168 MMU_WARN_ON(VALID_PAGE(root));
3170 spin_lock(&vcpu->kvm->mmu_lock);
3171 make_mmu_pages_available(vcpu);
3172 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3174 root = __pa(sp->spt);
3176 spin_unlock(&vcpu->kvm->mmu_lock);
3177 vcpu->arch.mmu.root_hpa = root;
3182 * We shadow a 32 bit page table. This may be a legacy 2-level
3183 * or a PAE 3-level page table. In either case we need to be aware that
3184 * the shadow page table may be a PAE or a long mode page table.
3186 pm_mask = PT_PRESENT_MASK;
3187 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3188 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3190 for (i = 0; i < 4; ++i) {
3191 hpa_t root = vcpu->arch.mmu.pae_root[i];
3193 MMU_WARN_ON(VALID_PAGE(root));
3194 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3195 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3196 if (!is_present_gpte(pdptr)) {
3197 vcpu->arch.mmu.pae_root[i] = 0;
3200 root_gfn = pdptr >> PAGE_SHIFT;
3201 if (mmu_check_root(vcpu, root_gfn))
3204 spin_lock(&vcpu->kvm->mmu_lock);
3205 make_mmu_pages_available(vcpu);
3206 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3208 root = __pa(sp->spt);
3210 spin_unlock(&vcpu->kvm->mmu_lock);
3212 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3214 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3217 * If we shadow a 32 bit page table with a long mode page
3218 * table we enter this path.
3220 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3221 if (vcpu->arch.mmu.lm_root == NULL) {
3223 * The additional page necessary for this is only
3224 * allocated on demand.
3229 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3230 if (lm_root == NULL)
3233 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3235 vcpu->arch.mmu.lm_root = lm_root;
3238 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3244 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3246 if (vcpu->arch.mmu.direct_map)
3247 return mmu_alloc_direct_roots(vcpu);
3249 return mmu_alloc_shadow_roots(vcpu);
3252 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3255 struct kvm_mmu_page *sp;
3257 if (vcpu->arch.mmu.direct_map)
3260 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3263 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3264 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3265 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3266 hpa_t root = vcpu->arch.mmu.root_hpa;
3267 sp = page_header(root);
3268 mmu_sync_children(vcpu, sp);
3269 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3272 for (i = 0; i < 4; ++i) {
3273 hpa_t root = vcpu->arch.mmu.pae_root[i];
3275 if (root && VALID_PAGE(root)) {
3276 root &= PT64_BASE_ADDR_MASK;
3277 sp = page_header(root);
3278 mmu_sync_children(vcpu, sp);
3281 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3284 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3286 spin_lock(&vcpu->kvm->mmu_lock);
3287 mmu_sync_roots(vcpu);
3288 spin_unlock(&vcpu->kvm->mmu_lock);
3290 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3292 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3293 u32 access, struct x86_exception *exception)
3296 exception->error_code = 0;
3300 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3302 struct x86_exception *exception)
3305 exception->error_code = 0;
3306 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3310 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3312 int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3314 return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3315 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3318 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3320 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3323 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3325 return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3328 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3331 return vcpu_match_mmio_gpa(vcpu, addr);
3333 return vcpu_match_mmio_gva(vcpu, addr);
3336 /* return true if reserved bit is detected on spte. */
3338 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3340 struct kvm_shadow_walk_iterator iterator;
3341 u64 sptes[PT64_ROOT_LEVEL], spte = 0ull;
3343 bool reserved = false;
3345 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3348 walk_shadow_page_lockless_begin(vcpu);
3350 for (shadow_walk_init(&iterator, vcpu, addr),
3351 leaf = root = iterator.level;
3352 shadow_walk_okay(&iterator);
3353 __shadow_walk_next(&iterator, spte)) {
3354 spte = mmu_spte_get_lockless(iterator.sptep);
3356 sptes[leaf - 1] = spte;
3359 if (!is_shadow_present_pte(spte))
3362 reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte,
3366 walk_shadow_page_lockless_end(vcpu);
3369 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3371 while (root > leaf) {
3372 pr_err("------ spte 0x%llx level %d.\n",
3373 sptes[root - 1], root);
3382 int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3387 if (mmio_info_in_cache(vcpu, addr, direct))
3388 return RET_MMIO_PF_EMULATE;
3390 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3391 if (WARN_ON(reserved))
3392 return RET_MMIO_PF_BUG;
3394 if (is_mmio_spte(spte)) {
3395 gfn_t gfn = get_mmio_spte_gfn(spte);
3396 unsigned access = get_mmio_spte_access(spte);
3398 if (!check_mmio_spte(vcpu, spte))
3399 return RET_MMIO_PF_INVALID;
3404 trace_handle_mmio_page_fault(addr, gfn, access);
3405 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3406 return RET_MMIO_PF_EMULATE;
3410 * If the page table is zapped by other cpus, let CPU fault again on
3413 return RET_MMIO_PF_RETRY;
3415 EXPORT_SYMBOL_GPL(handle_mmio_page_fault);
3417 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3418 u32 error_code, gfn_t gfn)
3420 if (unlikely(error_code & PFERR_RSVD_MASK))
3423 if (!(error_code & PFERR_PRESENT_MASK) ||
3424 !(error_code & PFERR_WRITE_MASK))
3428 * guest is writing the page which is write tracked which can
3429 * not be fixed by page fault handler.
3431 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3437 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3439 struct kvm_shadow_walk_iterator iterator;
3442 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3445 walk_shadow_page_lockless_begin(vcpu);
3446 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3447 clear_sp_write_flooding_count(iterator.sptep);
3448 if (!is_shadow_present_pte(spte))
3451 walk_shadow_page_lockless_end(vcpu);
3454 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3455 u32 error_code, bool prefault)
3457 gfn_t gfn = gva >> PAGE_SHIFT;
3460 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3462 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3465 r = mmu_topup_memory_caches(vcpu);
3469 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3472 return nonpaging_map(vcpu, gva & PAGE_MASK,
3473 error_code, gfn, prefault);
3476 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3478 struct kvm_arch_async_pf arch;
3480 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3482 arch.direct_map = vcpu->arch.mmu.direct_map;
3483 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3485 return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3488 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3490 if (unlikely(!lapic_in_kernel(vcpu) ||
3491 kvm_event_needs_reinjection(vcpu)))
3494 return kvm_x86_ops->interrupt_allowed(vcpu);
3497 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3498 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable)
3500 struct kvm_memory_slot *slot;
3503 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3505 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3507 return false; /* *pfn has correct page already */
3509 if (!prefault && can_do_async_pf(vcpu)) {
3510 trace_kvm_try_async_get_page(gva, gfn);
3511 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3512 trace_kvm_async_pf_doublefault(gva, gfn);
3513 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3515 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3519 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3524 check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
3526 int page_num = KVM_PAGES_PER_HPAGE(level);
3528 gfn &= ~(page_num - 1);
3530 return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
3533 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3539 bool force_pt_level;
3540 gfn_t gfn = gpa >> PAGE_SHIFT;
3541 unsigned long mmu_seq;
3542 int write = error_code & PFERR_WRITE_MASK;
3545 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3547 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3550 r = mmu_topup_memory_caches(vcpu);
3554 force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn,
3555 PT_DIRECTORY_LEVEL);
3556 level = mapping_level(vcpu, gfn, &force_pt_level);
3557 if (likely(!force_pt_level)) {
3558 if (level > PT_DIRECTORY_LEVEL &&
3559 !check_hugepage_cache_consistency(vcpu, gfn, level))
3560 level = PT_DIRECTORY_LEVEL;
3561 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3564 if (fast_page_fault(vcpu, gpa, level, error_code))
3567 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3570 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3573 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3576 spin_lock(&vcpu->kvm->mmu_lock);
3577 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3579 make_mmu_pages_available(vcpu);
3580 if (likely(!force_pt_level))
3581 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3582 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3583 spin_unlock(&vcpu->kvm->mmu_lock);
3588 spin_unlock(&vcpu->kvm->mmu_lock);
3589 kvm_release_pfn_clean(pfn);
3593 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3594 struct kvm_mmu *context)
3596 context->page_fault = nonpaging_page_fault;
3597 context->gva_to_gpa = nonpaging_gva_to_gpa;
3598 context->sync_page = nonpaging_sync_page;
3599 context->invlpg = nonpaging_invlpg;
3600 context->update_pte = nonpaging_update_pte;
3601 context->root_level = 0;
3602 context->shadow_root_level = PT32E_ROOT_LEVEL;
3603 context->root_hpa = INVALID_PAGE;
3604 context->direct_map = true;
3605 context->nx = false;
3608 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
3610 mmu_free_roots(vcpu);
3613 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3615 return kvm_read_cr3(vcpu);
3618 static void inject_page_fault(struct kvm_vcpu *vcpu,
3619 struct x86_exception *fault)
3621 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3624 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
3625 unsigned access, int *nr_present)
3627 if (unlikely(is_mmio_spte(*sptep))) {
3628 if (gfn != get_mmio_spte_gfn(*sptep)) {
3629 mmu_spte_clear_no_track(sptep);
3634 mark_mmio_spte(vcpu, sptep, gfn, access);
3641 static inline bool is_last_gpte(struct kvm_mmu *mmu,
3642 unsigned level, unsigned gpte)
3645 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
3646 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
3647 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
3649 gpte |= level - PT_PAGE_TABLE_LEVEL - 1;
3652 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3653 * If it is clear, there are no large pages at this level, so clear
3654 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3656 gpte &= level - mmu->last_nonleaf_level;
3658 return gpte & PT_PAGE_SIZE_MASK;
3661 #define PTTYPE_EPT 18 /* arbitrary */
3662 #define PTTYPE PTTYPE_EPT
3663 #include "paging_tmpl.h"
3667 #include "paging_tmpl.h"
3671 #include "paging_tmpl.h"
3675 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3676 struct rsvd_bits_validate *rsvd_check,
3677 int maxphyaddr, int level, bool nx, bool gbpages,
3680 u64 exb_bit_rsvd = 0;
3681 u64 gbpages_bit_rsvd = 0;
3682 u64 nonleaf_bit8_rsvd = 0;
3684 rsvd_check->bad_mt_xwr = 0;
3687 exb_bit_rsvd = rsvd_bits(63, 63);
3689 gbpages_bit_rsvd = rsvd_bits(7, 7);
3692 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3693 * leaf entries) on AMD CPUs only.
3696 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
3699 case PT32_ROOT_LEVEL:
3700 /* no rsvd bits for 2 level 4K page table entries */
3701 rsvd_check->rsvd_bits_mask[0][1] = 0;
3702 rsvd_check->rsvd_bits_mask[0][0] = 0;
3703 rsvd_check->rsvd_bits_mask[1][0] =
3704 rsvd_check->rsvd_bits_mask[0][0];
3707 rsvd_check->rsvd_bits_mask[1][1] = 0;
3711 if (is_cpuid_PSE36())
3712 /* 36bits PSE 4MB page */
3713 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3715 /* 32 bits PSE 4MB page */
3716 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3718 case PT32E_ROOT_LEVEL:
3719 rsvd_check->rsvd_bits_mask[0][2] =
3720 rsvd_bits(maxphyaddr, 63) |
3721 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3722 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3723 rsvd_bits(maxphyaddr, 62); /* PDE */
3724 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3725 rsvd_bits(maxphyaddr, 62); /* PTE */
3726 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3727 rsvd_bits(maxphyaddr, 62) |
3728 rsvd_bits(13, 20); /* large page */
3729 rsvd_check->rsvd_bits_mask[1][0] =
3730 rsvd_check->rsvd_bits_mask[0][0];
3732 case PT64_ROOT_LEVEL:
3733 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3734 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
3735 rsvd_bits(maxphyaddr, 51);
3736 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3737 nonleaf_bit8_rsvd | gbpages_bit_rsvd |
3738 rsvd_bits(maxphyaddr, 51);
3739 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3740 rsvd_bits(maxphyaddr, 51);
3741 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3742 rsvd_bits(maxphyaddr, 51);
3743 rsvd_check->rsvd_bits_mask[1][3] =
3744 rsvd_check->rsvd_bits_mask[0][3];
3745 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3746 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
3748 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3749 rsvd_bits(maxphyaddr, 51) |
3750 rsvd_bits(13, 20); /* large page */
3751 rsvd_check->rsvd_bits_mask[1][0] =
3752 rsvd_check->rsvd_bits_mask[0][0];
3757 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3758 struct kvm_mmu *context)
3760 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
3761 cpuid_maxphyaddr(vcpu), context->root_level,
3762 context->nx, guest_cpuid_has_gbpages(vcpu),
3763 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
3767 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
3768 int maxphyaddr, bool execonly)
3772 rsvd_check->rsvd_bits_mask[0][3] =
3773 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
3774 rsvd_check->rsvd_bits_mask[0][2] =
3775 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3776 rsvd_check->rsvd_bits_mask[0][1] =
3777 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3778 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
3781 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
3782 rsvd_check->rsvd_bits_mask[1][2] =
3783 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
3784 rsvd_check->rsvd_bits_mask[1][1] =
3785 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
3786 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
3788 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
3789 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
3790 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
3791 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
3792 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
3794 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
3795 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
3797 rsvd_check->bad_mt_xwr = bad_mt_xwr;
3800 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
3801 struct kvm_mmu *context, bool execonly)
3803 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
3804 cpuid_maxphyaddr(vcpu), execonly);
3808 * the page table on host is the shadow page table for the page
3809 * table in guest or amd nested guest, its mmu features completely
3810 * follow the features in guest.
3813 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3815 bool uses_nx = context->nx || context->base_role.smep_andnot_wp;
3818 * Passing "true" to the last argument is okay; it adds a check
3819 * on bit 8 of the SPTEs which KVM doesn't use anyway.
3821 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
3822 boot_cpu_data.x86_phys_bits,
3823 context->shadow_root_level, uses_nx,
3824 guest_cpuid_has_gbpages(vcpu), is_pse(vcpu),
3827 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
3829 static inline bool boot_cpu_is_amd(void)
3831 WARN_ON_ONCE(!tdp_enabled);
3832 return shadow_x_mask == 0;
3836 * the direct page table on host, use as much mmu features as
3837 * possible, however, kvm currently does not do execution-protection.
3840 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
3841 struct kvm_mmu *context)
3843 if (boot_cpu_is_amd())
3844 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
3845 boot_cpu_data.x86_phys_bits,
3846 context->shadow_root_level, false,
3847 boot_cpu_has(X86_FEATURE_GBPAGES),
3850 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
3851 boot_cpu_data.x86_phys_bits,
3857 * as the comments in reset_shadow_zero_bits_mask() except it
3858 * is the shadow page table for intel nested guest.
3861 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
3862 struct kvm_mmu *context, bool execonly)
3864 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
3865 boot_cpu_data.x86_phys_bits, execonly);
3868 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
3869 struct kvm_mmu *mmu, bool ept)
3871 unsigned bit, byte, pfec;
3873 bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0;
3875 cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3876 cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
3877 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3880 wf = pfec & PFERR_WRITE_MASK;
3881 uf = pfec & PFERR_USER_MASK;
3882 ff = pfec & PFERR_FETCH_MASK;
3884 * PFERR_RSVD_MASK bit is set in PFEC if the access is not
3885 * subject to SMAP restrictions, and cleared otherwise. The
3886 * bit is only meaningful if the SMAP bit is set in CR4.
3888 smapf = !(pfec & PFERR_RSVD_MASK);
3889 for (bit = 0; bit < 8; ++bit) {
3890 x = bit & ACC_EXEC_MASK;
3891 w = bit & ACC_WRITE_MASK;
3892 u = bit & ACC_USER_MASK;
3895 /* Not really needed: !nx will cause pte.nx to fault */
3897 /* Allow supervisor writes if !cr0.wp */
3898 w |= !is_write_protection(vcpu) && !uf;
3899 /* Disallow supervisor fetches of user code if cr4.smep */
3900 x &= !(cr4_smep && u && !uf);
3903 * SMAP:kernel-mode data accesses from user-mode
3904 * mappings should fault. A fault is considered
3905 * as a SMAP violation if all of the following
3906 * conditions are ture:
3907 * - X86_CR4_SMAP is set in CR4
3908 * - An user page is accessed
3909 * - Page fault in kernel mode
3910 * - if CPL = 3 or X86_EFLAGS_AC is clear
3912 * Here, we cover the first three conditions.
3913 * The fourth is computed dynamically in
3914 * permission_fault() and is in smapf.
3916 * Also, SMAP does not affect instruction
3917 * fetches, add the !ff check here to make it
3920 smap = cr4_smap && u && !uf && !ff;
3922 /* Not really needed: no U/S accesses on ept */
3925 fault = (ff && !x) || (uf && !u) || (wf && !w) ||
3927 map |= fault << bit;
3929 mmu->permissions[byte] = map;
3934 * PKU is an additional mechanism by which the paging controls access to
3935 * user-mode addresses based on the value in the PKRU register. Protection
3936 * key violations are reported through a bit in the page fault error code.
3937 * Unlike other bits of the error code, the PK bit is not known at the
3938 * call site of e.g. gva_to_gpa; it must be computed directly in
3939 * permission_fault based on two bits of PKRU, on some machine state (CR4,
3940 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
3942 * In particular the following conditions come from the error code, the
3943 * page tables and the machine state:
3944 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
3945 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
3946 * - PK is always zero if U=0 in the page tables
3947 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
3949 * The PKRU bitmask caches the result of these four conditions. The error
3950 * code (minus the P bit) and the page table's U bit form an index into the
3951 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
3952 * with the two bits of the PKRU register corresponding to the protection key.
3953 * For the first three conditions above the bits will be 00, thus masking
3954 * away both AD and WD. For all reads or if the last condition holds, WD
3955 * only will be masked away.
3957 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3968 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
3969 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
3974 wp = is_write_protection(vcpu);
3976 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
3977 unsigned pfec, pkey_bits;
3978 bool check_pkey, check_write, ff, uf, wf, pte_user;
3981 ff = pfec & PFERR_FETCH_MASK;
3982 uf = pfec & PFERR_USER_MASK;
3983 wf = pfec & PFERR_WRITE_MASK;
3985 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
3986 pte_user = pfec & PFERR_RSVD_MASK;
3989 * Only need to check the access which is not an
3990 * instruction fetch and is to a user page.
3992 check_pkey = (!ff && pte_user);
3994 * write access is controlled by PKRU if it is a
3995 * user access or CR0.WP = 1.
3997 check_write = check_pkey && wf && (uf || wp);
3999 /* PKRU.AD stops both read and write access. */
4000 pkey_bits = !!check_pkey;
4001 /* PKRU.WD stops write access. */
4002 pkey_bits |= (!!check_write) << 1;
4004 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4008 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4010 unsigned root_level = mmu->root_level;
4012 mmu->last_nonleaf_level = root_level;
4013 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4014 mmu->last_nonleaf_level++;
4017 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4018 struct kvm_mmu *context,
4021 context->nx = is_nx(vcpu);
4022 context->root_level = level;
4024 reset_rsvds_bits_mask(vcpu, context);
4025 update_permission_bitmask(vcpu, context, false);
4026 update_pkru_bitmask(vcpu, context, false);
4027 update_last_nonleaf_level(vcpu, context);
4029 MMU_WARN_ON(!is_pae(vcpu));
4030 context->page_fault = paging64_page_fault;
4031 context->gva_to_gpa = paging64_gva_to_gpa;
4032 context->sync_page = paging64_sync_page;
4033 context->invlpg = paging64_invlpg;
4034 context->update_pte = paging64_update_pte;
4035 context->shadow_root_level = level;
4036 context->root_hpa = INVALID_PAGE;
4037 context->direct_map = false;
4040 static void paging64_init_context(struct kvm_vcpu *vcpu,
4041 struct kvm_mmu *context)
4043 paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
4046 static void paging32_init_context(struct kvm_vcpu *vcpu,
4047 struct kvm_mmu *context)
4049 context->nx = false;
4050 context->root_level = PT32_ROOT_LEVEL;
4052 reset_rsvds_bits_mask(vcpu, context);
4053 update_permission_bitmask(vcpu, context, false);
4054 update_pkru_bitmask(vcpu, context, false);
4055 update_last_nonleaf_level(vcpu, context);
4057 context->page_fault = paging32_page_fault;
4058 context->gva_to_gpa = paging32_gva_to_gpa;
4059 context->sync_page = paging32_sync_page;
4060 context->invlpg = paging32_invlpg;
4061 context->update_pte = paging32_update_pte;
4062 context->shadow_root_level = PT32E_ROOT_LEVEL;
4063 context->root_hpa = INVALID_PAGE;
4064 context->direct_map = false;
4067 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4068 struct kvm_mmu *context)
4070 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4073 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4075 struct kvm_mmu *context = &vcpu->arch.mmu;
4077 context->base_role.word = 0;
4078 context->base_role.smm = is_smm(vcpu);
4079 context->page_fault = tdp_page_fault;
4080 context->sync_page = nonpaging_sync_page;
4081 context->invlpg = nonpaging_invlpg;
4082 context->update_pte = nonpaging_update_pte;
4083 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4084 context->root_hpa = INVALID_PAGE;
4085 context->direct_map = true;
4086 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
4087 context->get_cr3 = get_cr3;
4088 context->get_pdptr = kvm_pdptr_read;
4089 context->inject_page_fault = kvm_inject_page_fault;
4091 if (!is_paging(vcpu)) {
4092 context->nx = false;
4093 context->gva_to_gpa = nonpaging_gva_to_gpa;
4094 context->root_level = 0;
4095 } else if (is_long_mode(vcpu)) {
4096 context->nx = is_nx(vcpu);
4097 context->root_level = PT64_ROOT_LEVEL;
4098 reset_rsvds_bits_mask(vcpu, context);
4099 context->gva_to_gpa = paging64_gva_to_gpa;
4100 } else if (is_pae(vcpu)) {
4101 context->nx = is_nx(vcpu);
4102 context->root_level = PT32E_ROOT_LEVEL;
4103 reset_rsvds_bits_mask(vcpu, context);
4104 context->gva_to_gpa = paging64_gva_to_gpa;
4106 context->nx = false;
4107 context->root_level = PT32_ROOT_LEVEL;
4108 reset_rsvds_bits_mask(vcpu, context);
4109 context->gva_to_gpa = paging32_gva_to_gpa;
4112 update_permission_bitmask(vcpu, context, false);
4113 update_pkru_bitmask(vcpu, context, false);
4114 update_last_nonleaf_level(vcpu, context);
4115 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4118 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
4120 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4121 bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4122 struct kvm_mmu *context = &vcpu->arch.mmu;
4124 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4126 if (!is_paging(vcpu))
4127 nonpaging_init_context(vcpu, context);
4128 else if (is_long_mode(vcpu))
4129 paging64_init_context(vcpu, context);
4130 else if (is_pae(vcpu))
4131 paging32E_init_context(vcpu, context);
4133 paging32_init_context(vcpu, context);
4135 context->base_role.nxe = is_nx(vcpu);
4136 context->base_role.cr4_pae = !!is_pae(vcpu);
4137 context->base_role.cr0_wp = is_write_protection(vcpu);
4138 context->base_role.smep_andnot_wp
4139 = smep && !is_write_protection(vcpu);
4140 context->base_role.smap_andnot_wp
4141 = smap && !is_write_protection(vcpu);
4142 context->base_role.smm = is_smm(vcpu);
4143 reset_shadow_zero_bits_mask(vcpu, context);
4145 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4147 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly)
4149 struct kvm_mmu *context = &vcpu->arch.mmu;
4151 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4153 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4156 context->page_fault = ept_page_fault;
4157 context->gva_to_gpa = ept_gva_to_gpa;
4158 context->sync_page = ept_sync_page;
4159 context->invlpg = ept_invlpg;
4160 context->update_pte = ept_update_pte;
4161 context->root_level = context->shadow_root_level;
4162 context->root_hpa = INVALID_PAGE;
4163 context->direct_map = false;
4165 update_permission_bitmask(vcpu, context, true);
4166 update_pkru_bitmask(vcpu, context, true);
4167 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4168 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4170 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4172 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4174 struct kvm_mmu *context = &vcpu->arch.mmu;
4176 kvm_init_shadow_mmu(vcpu);
4177 context->set_cr3 = kvm_x86_ops->set_cr3;
4178 context->get_cr3 = get_cr3;
4179 context->get_pdptr = kvm_pdptr_read;
4180 context->inject_page_fault = kvm_inject_page_fault;
4183 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4185 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4187 g_context->get_cr3 = get_cr3;
4188 g_context->get_pdptr = kvm_pdptr_read;
4189 g_context->inject_page_fault = kvm_inject_page_fault;
4192 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4193 * L1's nested page tables (e.g. EPT12). The nested translation
4194 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4195 * L2's page tables as the first level of translation and L1's
4196 * nested page tables as the second level of translation. Basically
4197 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4199 if (!is_paging(vcpu)) {
4200 g_context->nx = false;
4201 g_context->root_level = 0;
4202 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4203 } else if (is_long_mode(vcpu)) {
4204 g_context->nx = is_nx(vcpu);
4205 g_context->root_level = PT64_ROOT_LEVEL;
4206 reset_rsvds_bits_mask(vcpu, g_context);
4207 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4208 } else if (is_pae(vcpu)) {
4209 g_context->nx = is_nx(vcpu);
4210 g_context->root_level = PT32E_ROOT_LEVEL;
4211 reset_rsvds_bits_mask(vcpu, g_context);
4212 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4214 g_context->nx = false;
4215 g_context->root_level = PT32_ROOT_LEVEL;
4216 reset_rsvds_bits_mask(vcpu, g_context);
4217 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4220 update_permission_bitmask(vcpu, g_context, false);
4221 update_pkru_bitmask(vcpu, g_context, false);
4222 update_last_nonleaf_level(vcpu, g_context);
4225 static void init_kvm_mmu(struct kvm_vcpu *vcpu)
4227 if (mmu_is_nested(vcpu))
4228 init_kvm_nested_mmu(vcpu);
4229 else if (tdp_enabled)
4230 init_kvm_tdp_mmu(vcpu);
4232 init_kvm_softmmu(vcpu);
4235 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4237 kvm_mmu_unload(vcpu);
4240 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4242 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4246 r = mmu_topup_memory_caches(vcpu);
4249 r = mmu_alloc_roots(vcpu);
4250 kvm_mmu_sync_roots(vcpu);
4253 /* set_cr3() should ensure TLB has been flushed */
4254 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
4258 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4260 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4262 mmu_free_roots(vcpu);
4263 WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4265 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4267 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4268 struct kvm_mmu_page *sp, u64 *spte,
4271 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
4272 ++vcpu->kvm->stat.mmu_pde_zapped;
4276 ++vcpu->kvm->stat.mmu_pte_updated;
4277 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
4280 static bool need_remote_flush(u64 old, u64 new)
4282 if (!is_shadow_present_pte(old))
4284 if (!is_shadow_present_pte(new))
4286 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4288 old ^= shadow_nx_mask;
4289 new ^= shadow_nx_mask;
4290 return (old & ~new & PT64_PERM_MASK) != 0;
4293 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4294 const u8 *new, int *bytes)
4300 * Assume that the pte write on a page table of the same type
4301 * as the current vcpu paging mode since we update the sptes only
4302 * when they have the same mode.
4304 if (is_pae(vcpu) && *bytes == 4) {
4305 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4308 r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8);
4311 new = (const u8 *)&gentry;
4316 gentry = *(const u32 *)new;
4319 gentry = *(const u64 *)new;
4330 * If we're seeing too many writes to a page, it may no longer be a page table,
4331 * or we may be forking, in which case it is better to unmap the page.
4333 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4336 * Skip write-flooding detected for the sp whose level is 1, because
4337 * it can become unsync, then the guest page is not write-protected.
4339 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
4342 atomic_inc(&sp->write_flooding_count);
4343 return atomic_read(&sp->write_flooding_count) >= 3;
4347 * Misaligned accesses are too much trouble to fix up; also, they usually
4348 * indicate a page is not used as a page table.
4350 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4353 unsigned offset, pte_size, misaligned;
4355 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4356 gpa, bytes, sp->role.word);
4358 offset = offset_in_page(gpa);
4359 pte_size = sp->role.cr4_pae ? 8 : 4;
4362 * Sometimes, the OS only writes the last one bytes to update status
4363 * bits, for example, in linux, andb instruction is used in clear_bit().
4365 if (!(offset & (pte_size - 1)) && bytes == 1)
4368 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4369 misaligned |= bytes < 4;
4374 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4376 unsigned page_offset, quadrant;
4380 page_offset = offset_in_page(gpa);
4381 level = sp->role.level;
4383 if (!sp->role.cr4_pae) {
4384 page_offset <<= 1; /* 32->64 */
4386 * A 32-bit pde maps 4MB while the shadow pdes map
4387 * only 2MB. So we need to double the offset again
4388 * and zap two pdes instead of one.
4390 if (level == PT32_ROOT_LEVEL) {
4391 page_offset &= ~7; /* kill rounding error */
4395 quadrant = page_offset >> PAGE_SHIFT;
4396 page_offset &= ~PAGE_MASK;
4397 if (quadrant != sp->role.quadrant)
4401 spte = &sp->spt[page_offset / sizeof(*spte)];
4405 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4406 const u8 *new, int bytes)
4408 gfn_t gfn = gpa >> PAGE_SHIFT;
4409 struct kvm_mmu_page *sp;
4410 LIST_HEAD(invalid_list);
4411 u64 entry, gentry, *spte;
4413 bool remote_flush, local_flush;
4414 union kvm_mmu_page_role mask = { };
4419 mask.smep_andnot_wp = 1;
4420 mask.smap_andnot_wp = 1;
4424 * If we don't have indirect shadow pages, it means no page is
4425 * write-protected, so we can exit simply.
4427 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4430 remote_flush = local_flush = false;
4432 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4434 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4437 * No need to care whether allocation memory is successful
4438 * or not since pte prefetch is skiped if it does not have
4439 * enough objects in the cache.
4441 mmu_topup_memory_caches(vcpu);
4443 spin_lock(&vcpu->kvm->mmu_lock);
4444 ++vcpu->kvm->stat.mmu_pte_write;
4445 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4447 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4448 if (detect_write_misaligned(sp, gpa, bytes) ||
4449 detect_write_flooding(sp)) {
4450 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4451 ++vcpu->kvm->stat.mmu_flooded;
4455 spte = get_written_sptes(sp, gpa, &npte);
4462 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4464 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4465 & mask.word) && rmap_can_add(vcpu))
4466 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4467 if (need_remote_flush(entry, *spte))
4468 remote_flush = true;
4472 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
4473 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4474 spin_unlock(&vcpu->kvm->mmu_lock);
4477 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4482 if (vcpu->arch.mmu.direct_map)
4485 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4487 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4491 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4493 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4495 LIST_HEAD(invalid_list);
4497 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4500 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4501 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4504 ++vcpu->kvm->stat.mmu_recycled;
4506 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4509 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4510 void *insn, int insn_len)
4512 int r, emulation_type = EMULTYPE_RETRY;
4513 enum emulation_result er;
4514 bool direct = vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu);
4516 if (unlikely(error_code & PFERR_RSVD_MASK)) {
4517 r = handle_mmio_page_fault(vcpu, cr2, direct);
4518 if (r == RET_MMIO_PF_EMULATE) {
4522 if (r == RET_MMIO_PF_RETRY)
4528 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4534 if (mmio_info_in_cache(vcpu, cr2, direct))
4537 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4542 case EMULATE_USER_EXIT:
4543 ++vcpu->stat.mmio_exits;
4551 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4553 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4555 vcpu->arch.mmu.invlpg(vcpu, gva);
4556 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4557 ++vcpu->stat.invlpg;
4559 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4561 void kvm_enable_tdp(void)
4565 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4567 void kvm_disable_tdp(void)
4569 tdp_enabled = false;
4571 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4573 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4575 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4576 if (vcpu->arch.mmu.lm_root != NULL)
4577 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4580 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4586 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4587 * Therefore we need to allocate shadow page tables in the first
4588 * 4GB of memory, which happens to fit the DMA32 zone.
4590 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4594 vcpu->arch.mmu.pae_root = page_address(page);
4595 for (i = 0; i < 4; ++i)
4596 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4601 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4603 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4604 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4605 vcpu->arch.mmu.translate_gpa = translate_gpa;
4606 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4608 return alloc_mmu_pages(vcpu);
4611 void kvm_mmu_setup(struct kvm_vcpu *vcpu)
4613 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4618 void kvm_mmu_init_vm(struct kvm *kvm)
4620 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
4622 node->track_write = kvm_mmu_pte_write;
4623 kvm_page_track_register_notifier(kvm, node);
4626 void kvm_mmu_uninit_vm(struct kvm *kvm)
4628 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
4630 kvm_page_track_unregister_notifier(kvm, node);
4633 /* The return value indicates if tlb flush on all vcpus is needed. */
4634 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
4636 /* The caller should hold mmu-lock before calling this function. */
4638 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
4639 slot_level_handler fn, int start_level, int end_level,
4640 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
4642 struct slot_rmap_walk_iterator iterator;
4645 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
4646 end_gfn, &iterator) {
4648 flush |= fn(kvm, iterator.rmap);
4650 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4651 if (flush && lock_flush_tlb) {
4652 kvm_flush_remote_tlbs(kvm);
4655 cond_resched_lock(&kvm->mmu_lock);
4659 if (flush && lock_flush_tlb) {
4660 kvm_flush_remote_tlbs(kvm);
4668 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4669 slot_level_handler fn, int start_level, int end_level,
4670 bool lock_flush_tlb)
4672 return slot_handle_level_range(kvm, memslot, fn, start_level,
4673 end_level, memslot->base_gfn,
4674 memslot->base_gfn + memslot->npages - 1,
4679 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4680 slot_level_handler fn, bool lock_flush_tlb)
4682 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4683 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4687 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4688 slot_level_handler fn, bool lock_flush_tlb)
4690 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
4691 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4695 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
4696 slot_level_handler fn, bool lock_flush_tlb)
4698 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4699 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
4702 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
4704 struct kvm_memslots *slots;
4705 struct kvm_memory_slot *memslot;
4708 spin_lock(&kvm->mmu_lock);
4709 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
4710 slots = __kvm_memslots(kvm, i);
4711 kvm_for_each_memslot(memslot, slots) {
4714 start = max(gfn_start, memslot->base_gfn);
4715 end = min(gfn_end, memslot->base_gfn + memslot->npages);
4719 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
4720 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
4721 start, end - 1, true);
4725 spin_unlock(&kvm->mmu_lock);
4728 static bool slot_rmap_write_protect(struct kvm *kvm,
4729 struct kvm_rmap_head *rmap_head)
4731 return __rmap_write_protect(kvm, rmap_head, false);
4734 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
4735 struct kvm_memory_slot *memslot)
4739 spin_lock(&kvm->mmu_lock);
4740 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
4742 spin_unlock(&kvm->mmu_lock);
4745 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
4746 * which do tlb flush out of mmu-lock should be serialized by
4747 * kvm->slots_lock otherwise tlb flush would be missed.
4749 lockdep_assert_held(&kvm->slots_lock);
4752 * We can flush all the TLBs out of the mmu lock without TLB
4753 * corruption since we just change the spte from writable to
4754 * readonly so that we only need to care the case of changing
4755 * spte from present to present (changing the spte from present
4756 * to nonpresent will flush all the TLBs immediately), in other
4757 * words, the only case we care is mmu_spte_update() where we
4758 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
4759 * instead of PT_WRITABLE_MASK, that means it does not depend
4760 * on PT_WRITABLE_MASK anymore.
4763 kvm_flush_remote_tlbs(kvm);
4766 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
4767 struct kvm_rmap_head *rmap_head)
4770 struct rmap_iterator iter;
4771 int need_tlb_flush = 0;
4773 struct kvm_mmu_page *sp;
4776 for_each_rmap_spte(rmap_head, &iter, sptep) {
4777 sp = page_header(__pa(sptep));
4778 pfn = spte_to_pfn(*sptep);
4781 * We cannot do huge page mapping for indirect shadow pages,
4782 * which are found on the last rmap (level = 1) when not using
4783 * tdp; such shadow pages are synced with the page table in
4784 * the guest, and the guest page table is using 4K page size
4785 * mapping if the indirect sp has level = 1.
4787 if (sp->role.direct &&
4788 !kvm_is_reserved_pfn(pfn) &&
4789 PageTransCompound(pfn_to_page(pfn))) {
4790 drop_spte(kvm, sptep);
4796 return need_tlb_flush;
4799 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
4800 const struct kvm_memory_slot *memslot)
4802 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
4803 spin_lock(&kvm->mmu_lock);
4804 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
4805 kvm_mmu_zap_collapsible_spte, true);
4806 spin_unlock(&kvm->mmu_lock);
4809 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
4810 struct kvm_memory_slot *memslot)
4814 spin_lock(&kvm->mmu_lock);
4815 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
4816 spin_unlock(&kvm->mmu_lock);
4818 lockdep_assert_held(&kvm->slots_lock);
4821 * It's also safe to flush TLBs out of mmu lock here as currently this
4822 * function is only used for dirty logging, in which case flushing TLB
4823 * out of mmu lock also guarantees no dirty pages will be lost in
4827 kvm_flush_remote_tlbs(kvm);
4829 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
4831 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
4832 struct kvm_memory_slot *memslot)
4836 spin_lock(&kvm->mmu_lock);
4837 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
4839 spin_unlock(&kvm->mmu_lock);
4841 /* see kvm_mmu_slot_remove_write_access */
4842 lockdep_assert_held(&kvm->slots_lock);
4845 kvm_flush_remote_tlbs(kvm);
4847 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
4849 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
4850 struct kvm_memory_slot *memslot)
4854 spin_lock(&kvm->mmu_lock);
4855 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
4856 spin_unlock(&kvm->mmu_lock);
4858 lockdep_assert_held(&kvm->slots_lock);
4860 /* see kvm_mmu_slot_leaf_clear_dirty */
4862 kvm_flush_remote_tlbs(kvm);
4864 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
4866 #define BATCH_ZAP_PAGES 10
4867 static void kvm_zap_obsolete_pages(struct kvm *kvm)
4869 struct kvm_mmu_page *sp, *node;
4873 list_for_each_entry_safe_reverse(sp, node,
4874 &kvm->arch.active_mmu_pages, link) {
4878 * No obsolete page exists before new created page since
4879 * active_mmu_pages is the FIFO list.
4881 if (!is_obsolete_sp(kvm, sp))
4885 * Since we are reversely walking the list and the invalid
4886 * list will be moved to the head, skip the invalid page
4887 * can help us to avoid the infinity list walking.
4889 if (sp->role.invalid)
4893 * Need not flush tlb since we only zap the sp with invalid
4894 * generation number.
4896 if (batch >= BATCH_ZAP_PAGES &&
4897 cond_resched_lock(&kvm->mmu_lock)) {
4902 ret = kvm_mmu_prepare_zap_page(kvm, sp,
4903 &kvm->arch.zapped_obsolete_pages);
4911 * Should flush tlb before free page tables since lockless-walking
4912 * may use the pages.
4914 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
4918 * Fast invalidate all shadow pages and use lock-break technique
4919 * to zap obsolete pages.
4921 * It's required when memslot is being deleted or VM is being
4922 * destroyed, in these cases, we should ensure that KVM MMU does
4923 * not use any resource of the being-deleted slot or all slots
4924 * after calling the function.
4926 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
4928 spin_lock(&kvm->mmu_lock);
4929 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
4930 kvm->arch.mmu_valid_gen++;
4933 * Notify all vcpus to reload its shadow page table
4934 * and flush TLB. Then all vcpus will switch to new
4935 * shadow page table with the new mmu_valid_gen.
4937 * Note: we should do this under the protection of
4938 * mmu-lock, otherwise, vcpu would purge shadow page
4939 * but miss tlb flush.
4941 kvm_reload_remote_mmus(kvm);
4943 kvm_zap_obsolete_pages(kvm);
4944 spin_unlock(&kvm->mmu_lock);
4947 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
4949 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
4952 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots)
4955 * The very rare case: if the generation-number is round,
4956 * zap all shadow pages.
4958 if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) {
4959 printk_ratelimited(KERN_DEBUG "kvm: zapping shadow pages for mmio generation wraparound\n");
4960 kvm_mmu_invalidate_zap_all_pages(kvm);
4964 static unsigned long
4965 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
4968 int nr_to_scan = sc->nr_to_scan;
4969 unsigned long freed = 0;
4971 spin_lock(&kvm_lock);
4973 list_for_each_entry(kvm, &vm_list, vm_list) {
4975 LIST_HEAD(invalid_list);
4978 * Never scan more than sc->nr_to_scan VM instances.
4979 * Will not hit this condition practically since we do not try
4980 * to shrink more than one VM and it is very unlikely to see
4981 * !n_used_mmu_pages so many times.
4986 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4987 * here. We may skip a VM instance errorneosly, but we do not
4988 * want to shrink a VM that only started to populate its MMU
4991 if (!kvm->arch.n_used_mmu_pages &&
4992 !kvm_has_zapped_obsolete_pages(kvm))
4995 idx = srcu_read_lock(&kvm->srcu);
4996 spin_lock(&kvm->mmu_lock);
4998 if (kvm_has_zapped_obsolete_pages(kvm)) {
4999 kvm_mmu_commit_zap_page(kvm,
5000 &kvm->arch.zapped_obsolete_pages);
5004 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
5006 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5009 spin_unlock(&kvm->mmu_lock);
5010 srcu_read_unlock(&kvm->srcu, idx);
5013 * unfair on small ones
5014 * per-vm shrinkers cry out
5015 * sadness comes quickly
5017 list_move_tail(&kvm->vm_list, &vm_list);
5021 spin_unlock(&kvm_lock);
5025 static unsigned long
5026 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5028 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5031 static struct shrinker mmu_shrinker = {
5032 .count_objects = mmu_shrink_count,
5033 .scan_objects = mmu_shrink_scan,
5034 .seeks = DEFAULT_SEEKS * 10,
5037 static void mmu_destroy_caches(void)
5039 if (pte_list_desc_cache)
5040 kmem_cache_destroy(pte_list_desc_cache);
5041 if (mmu_page_header_cache)
5042 kmem_cache_destroy(mmu_page_header_cache);
5045 int kvm_mmu_module_init(void)
5047 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5048 sizeof(struct pte_list_desc),
5050 if (!pte_list_desc_cache)
5053 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5054 sizeof(struct kvm_mmu_page),
5056 if (!mmu_page_header_cache)
5059 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5062 register_shrinker(&mmu_shrinker);
5067 mmu_destroy_caches();
5072 * Caculate mmu pages needed for kvm.
5074 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
5076 unsigned int nr_mmu_pages;
5077 unsigned int nr_pages = 0;
5078 struct kvm_memslots *slots;
5079 struct kvm_memory_slot *memslot;
5082 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5083 slots = __kvm_memslots(kvm, i);
5085 kvm_for_each_memslot(memslot, slots)
5086 nr_pages += memslot->npages;
5089 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5090 nr_mmu_pages = max(nr_mmu_pages,
5091 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
5093 return nr_mmu_pages;
5096 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5098 kvm_mmu_unload(vcpu);
5099 free_mmu_pages(vcpu);
5100 mmu_free_memory_caches(vcpu);
5103 void kvm_mmu_module_exit(void)
5105 mmu_destroy_caches();
5106 percpu_counter_destroy(&kvm_total_used_mmu_pages);
5107 unregister_shrinker(&mmu_shrinker);
5108 mmu_audit_disable();