2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/moduleparam.h>
33 #include <linux/export.h>
34 #include <linux/swap.h>
35 #include <linux/hugetlb.h>
36 #include <linux/compiler.h>
37 #include <linux/srcu.h>
38 #include <linux/slab.h>
39 #include <linux/sched/signal.h>
40 #include <linux/uaccess.h>
41 #include <linux/hash.h>
42 #include <linux/kern_levels.h>
46 #include <asm/cmpxchg.h>
49 #include <asm/kvm_page_track.h>
53 * When setting this variable to true it enables Two-Dimensional-Paging
54 * where the hardware walks 2 page tables:
55 * 1. the guest-virtual to guest-physical
56 * 2. while doing 1. it walks guest-physical to host-physical
57 * If the hardware supports that we don't need to do shadow paging.
59 bool tdp_enabled = false;
63 AUDIT_POST_PAGE_FAULT,
74 module_param(dbg, bool, 0644);
76 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
77 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
78 #define MMU_WARN_ON(x) WARN_ON(x)
80 #define pgprintk(x...) do { } while (0)
81 #define rmap_printk(x...) do { } while (0)
82 #define MMU_WARN_ON(x) do { } while (0)
85 #define PTE_PREFETCH_NUM 8
87 #define PT_FIRST_AVAIL_BITS_SHIFT 10
88 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
90 #define PT64_LEVEL_BITS 9
92 #define PT64_LEVEL_SHIFT(level) \
93 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
95 #define PT64_INDEX(address, level)\
96 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
99 #define PT32_LEVEL_BITS 10
101 #define PT32_LEVEL_SHIFT(level) \
102 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
104 #define PT32_LVL_OFFSET_MASK(level) \
105 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
106 * PT32_LEVEL_BITS))) - 1))
108 #define PT32_INDEX(address, level)\
109 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
112 #define PT64_BASE_ADDR_MASK __sme_clr((((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)))
113 #define PT64_DIR_BASE_ADDR_MASK \
114 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
115 #define PT64_LVL_ADDR_MASK(level) \
116 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
117 * PT64_LEVEL_BITS))) - 1))
118 #define PT64_LVL_OFFSET_MASK(level) \
119 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
120 * PT64_LEVEL_BITS))) - 1))
122 #define PT32_BASE_ADDR_MASK PAGE_MASK
123 #define PT32_DIR_BASE_ADDR_MASK \
124 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
125 #define PT32_LVL_ADDR_MASK(level) \
126 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
127 * PT32_LEVEL_BITS))) - 1))
129 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
130 | shadow_x_mask | shadow_nx_mask | shadow_me_mask)
132 #define ACC_EXEC_MASK 1
133 #define ACC_WRITE_MASK PT_WRITABLE_MASK
134 #define ACC_USER_MASK PT_USER_MASK
135 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
137 /* The mask for the R/X bits in EPT PTEs */
138 #define PT64_EPT_READABLE_MASK 0x1ull
139 #define PT64_EPT_EXECUTABLE_MASK 0x4ull
141 #include <trace/events/kvm.h>
143 #define CREATE_TRACE_POINTS
144 #include "mmutrace.h"
146 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
147 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
149 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
151 /* make pte_list_desc fit well in cache line */
152 #define PTE_LIST_EXT 3
155 * Return values of handle_mmio_page_fault and mmu.page_fault:
156 * RET_PF_RETRY: let CPU fault again on the address.
157 * RET_PF_EMULATE: mmio page fault, emulate the instruction directly.
159 * For handle_mmio_page_fault only:
160 * RET_PF_INVALID: the spte is invalid, let the real page fault path update it.
168 struct pte_list_desc {
169 u64 *sptes[PTE_LIST_EXT];
170 struct pte_list_desc *more;
173 struct kvm_shadow_walk_iterator {
181 static const union kvm_mmu_page_role mmu_base_role_mask = {
192 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
193 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
195 shadow_walk_okay(&(_walker)); \
196 shadow_walk_next(&(_walker)))
198 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
199 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
200 shadow_walk_okay(&(_walker)); \
201 shadow_walk_next(&(_walker)))
203 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
204 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
205 shadow_walk_okay(&(_walker)) && \
206 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
207 __shadow_walk_next(&(_walker), spte))
209 static struct kmem_cache *pte_list_desc_cache;
210 static struct kmem_cache *mmu_page_header_cache;
211 static struct percpu_counter kvm_total_used_mmu_pages;
213 static u64 __read_mostly shadow_nx_mask;
214 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
215 static u64 __read_mostly shadow_user_mask;
216 static u64 __read_mostly shadow_accessed_mask;
217 static u64 __read_mostly shadow_dirty_mask;
218 static u64 __read_mostly shadow_mmio_mask;
219 static u64 __read_mostly shadow_mmio_value;
220 static u64 __read_mostly shadow_present_mask;
221 static u64 __read_mostly shadow_me_mask;
224 * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value.
225 * Non-present SPTEs with shadow_acc_track_value set are in place for access
228 static u64 __read_mostly shadow_acc_track_mask;
229 static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK;
232 * The mask/shift to use for saving the original R/X bits when marking the PTE
233 * as not-present for access tracking purposes. We do not save the W bit as the
234 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
235 * restored only when a write is attempted to the page.
237 static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK |
238 PT64_EPT_EXECUTABLE_MASK;
239 static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT;
242 * This mask must be set on all non-zero Non-Present or Reserved SPTEs in order
243 * to guard against L1TF attacks.
245 static u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
248 * The number of high-order 1 bits to use in the mask above.
250 static const u64 shadow_nonpresent_or_rsvd_mask_len = 5;
252 static void mmu_spte_set(u64 *sptep, u64 spte);
253 static union kvm_mmu_page_role
254 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
256 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value)
258 BUG_ON((mmio_mask & mmio_value) != mmio_value);
259 shadow_mmio_value = mmio_value | SPTE_SPECIAL_MASK;
260 shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK;
262 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
264 static inline bool sp_ad_disabled(struct kvm_mmu_page *sp)
266 return sp->role.ad_disabled;
269 static inline bool spte_ad_enabled(u64 spte)
271 MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
272 return !(spte & shadow_acc_track_value);
275 static inline u64 spte_shadow_accessed_mask(u64 spte)
277 MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
278 return spte_ad_enabled(spte) ? shadow_accessed_mask : 0;
281 static inline u64 spte_shadow_dirty_mask(u64 spte)
283 MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
284 return spte_ad_enabled(spte) ? shadow_dirty_mask : 0;
287 static inline bool is_access_track_spte(u64 spte)
289 return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0;
293 * the low bit of the generation number is always presumed to be zero.
294 * This disables mmio caching during memslot updates. The concept is
295 * similar to a seqcount but instead of retrying the access we just punt
296 * and ignore the cache.
298 * spte bits 3-11 are used as bits 1-9 of the generation number,
299 * the bits 52-61 are used as bits 10-19 of the generation number.
301 #define MMIO_SPTE_GEN_LOW_SHIFT 2
302 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
304 #define MMIO_GEN_SHIFT 20
305 #define MMIO_GEN_LOW_SHIFT 10
306 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
307 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
309 static u64 generation_mmio_spte_mask(unsigned int gen)
313 WARN_ON(gen & ~MMIO_GEN_MASK);
315 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
316 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
320 static unsigned int get_mmio_spte_generation(u64 spte)
324 spte &= ~shadow_mmio_mask;
326 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
327 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
331 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu)
333 return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK;
336 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
339 unsigned int gen = kvm_current_mmio_generation(vcpu);
340 u64 mask = generation_mmio_spte_mask(gen);
341 u64 gpa = gfn << PAGE_SHIFT;
343 access &= ACC_WRITE_MASK | ACC_USER_MASK;
344 mask |= shadow_mmio_value | access;
345 mask |= gpa | shadow_nonpresent_or_rsvd_mask;
346 mask |= (gpa & shadow_nonpresent_or_rsvd_mask)
347 << shadow_nonpresent_or_rsvd_mask_len;
349 trace_mark_mmio_spte(sptep, gfn, access, gen);
350 mmu_spte_set(sptep, mask);
353 static bool is_mmio_spte(u64 spte)
355 return (spte & shadow_mmio_mask) == shadow_mmio_value;
358 static gfn_t get_mmio_spte_gfn(u64 spte)
360 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask |
361 shadow_nonpresent_or_rsvd_mask;
362 u64 gpa = spte & ~mask;
364 gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len)
365 & shadow_nonpresent_or_rsvd_mask;
367 return gpa >> PAGE_SHIFT;
370 static unsigned get_mmio_spte_access(u64 spte)
372 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
373 return (spte & ~mask) & ~PAGE_MASK;
376 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
377 kvm_pfn_t pfn, unsigned access)
379 if (unlikely(is_noslot_pfn(pfn))) {
380 mark_mmio_spte(vcpu, sptep, gfn, access);
387 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
389 unsigned int kvm_gen, spte_gen;
391 kvm_gen = kvm_current_mmio_generation(vcpu);
392 spte_gen = get_mmio_spte_generation(spte);
394 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
395 return likely(kvm_gen == spte_gen);
399 * Sets the shadow PTE masks used by the MMU.
402 * - Setting either @accessed_mask or @dirty_mask requires setting both
403 * - At least one of @accessed_mask or @acc_track_mask must be set
405 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
406 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
407 u64 acc_track_mask, u64 me_mask)
409 BUG_ON(!dirty_mask != !accessed_mask);
410 BUG_ON(!accessed_mask && !acc_track_mask);
411 BUG_ON(acc_track_mask & shadow_acc_track_value);
413 shadow_user_mask = user_mask;
414 shadow_accessed_mask = accessed_mask;
415 shadow_dirty_mask = dirty_mask;
416 shadow_nx_mask = nx_mask;
417 shadow_x_mask = x_mask;
418 shadow_present_mask = p_mask;
419 shadow_acc_track_mask = acc_track_mask;
420 shadow_me_mask = me_mask;
422 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
424 static void kvm_mmu_reset_all_pte_masks(void)
426 shadow_user_mask = 0;
427 shadow_accessed_mask = 0;
428 shadow_dirty_mask = 0;
431 shadow_mmio_mask = 0;
432 shadow_present_mask = 0;
433 shadow_acc_track_mask = 0;
436 * If the CPU has 46 or less physical address bits, then set an
437 * appropriate mask to guard against L1TF attacks. Otherwise, it is
438 * assumed that the CPU is not vulnerable to L1TF.
440 if (boot_cpu_data.x86_phys_bits <
441 52 - shadow_nonpresent_or_rsvd_mask_len)
442 shadow_nonpresent_or_rsvd_mask =
443 rsvd_bits(boot_cpu_data.x86_phys_bits -
444 shadow_nonpresent_or_rsvd_mask_len,
445 boot_cpu_data.x86_phys_bits - 1);
448 static int is_cpuid_PSE36(void)
453 static int is_nx(struct kvm_vcpu *vcpu)
455 return vcpu->arch.efer & EFER_NX;
458 static int is_shadow_present_pte(u64 pte)
460 return (pte != 0) && !is_mmio_spte(pte);
463 static int is_large_pte(u64 pte)
465 return pte & PT_PAGE_SIZE_MASK;
468 static int is_last_spte(u64 pte, int level)
470 if (level == PT_PAGE_TABLE_LEVEL)
472 if (is_large_pte(pte))
477 static bool is_executable_pte(u64 spte)
479 return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask;
482 static kvm_pfn_t spte_to_pfn(u64 pte)
484 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
487 static gfn_t pse36_gfn_delta(u32 gpte)
489 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
491 return (gpte & PT32_DIR_PSE36_MASK) << shift;
495 static void __set_spte(u64 *sptep, u64 spte)
497 WRITE_ONCE(*sptep, spte);
500 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
502 WRITE_ONCE(*sptep, spte);
505 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
507 return xchg(sptep, spte);
510 static u64 __get_spte_lockless(u64 *sptep)
512 return READ_ONCE(*sptep);
523 static void count_spte_clear(u64 *sptep, u64 spte)
525 struct kvm_mmu_page *sp = page_header(__pa(sptep));
527 if (is_shadow_present_pte(spte))
530 /* Ensure the spte is completely set before we increase the count */
532 sp->clear_spte_count++;
535 static void __set_spte(u64 *sptep, u64 spte)
537 union split_spte *ssptep, sspte;
539 ssptep = (union split_spte *)sptep;
540 sspte = (union split_spte)spte;
542 ssptep->spte_high = sspte.spte_high;
545 * If we map the spte from nonpresent to present, We should store
546 * the high bits firstly, then set present bit, so cpu can not
547 * fetch this spte while we are setting the spte.
551 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
554 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
556 union split_spte *ssptep, sspte;
558 ssptep = (union split_spte *)sptep;
559 sspte = (union split_spte)spte;
561 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
564 * If we map the spte from present to nonpresent, we should clear
565 * present bit firstly to avoid vcpu fetch the old high bits.
569 ssptep->spte_high = sspte.spte_high;
570 count_spte_clear(sptep, spte);
573 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
575 union split_spte *ssptep, sspte, orig;
577 ssptep = (union split_spte *)sptep;
578 sspte = (union split_spte)spte;
580 /* xchg acts as a barrier before the setting of the high bits */
581 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
582 orig.spte_high = ssptep->spte_high;
583 ssptep->spte_high = sspte.spte_high;
584 count_spte_clear(sptep, spte);
590 * The idea using the light way get the spte on x86_32 guest is from
591 * gup_get_pte(arch/x86/mm/gup.c).
593 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
594 * coalesces them and we are running out of the MMU lock. Therefore
595 * we need to protect against in-progress updates of the spte.
597 * Reading the spte while an update is in progress may get the old value
598 * for the high part of the spte. The race is fine for a present->non-present
599 * change (because the high part of the spte is ignored for non-present spte),
600 * but for a present->present change we must reread the spte.
602 * All such changes are done in two steps (present->non-present and
603 * non-present->present), hence it is enough to count the number of
604 * present->non-present updates: if it changed while reading the spte,
605 * we might have hit the race. This is done using clear_spte_count.
607 static u64 __get_spte_lockless(u64 *sptep)
609 struct kvm_mmu_page *sp = page_header(__pa(sptep));
610 union split_spte spte, *orig = (union split_spte *)sptep;
614 count = sp->clear_spte_count;
617 spte.spte_low = orig->spte_low;
620 spte.spte_high = orig->spte_high;
623 if (unlikely(spte.spte_low != orig->spte_low ||
624 count != sp->clear_spte_count))
631 static bool spte_can_locklessly_be_made_writable(u64 spte)
633 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
634 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
637 static bool spte_has_volatile_bits(u64 spte)
639 if (!is_shadow_present_pte(spte))
643 * Always atomically update spte if it can be updated
644 * out of mmu-lock, it can ensure dirty bit is not lost,
645 * also, it can help us to get a stable is_writable_pte()
646 * to ensure tlb flush is not missed.
648 if (spte_can_locklessly_be_made_writable(spte) ||
649 is_access_track_spte(spte))
652 if (spte_ad_enabled(spte)) {
653 if ((spte & shadow_accessed_mask) == 0 ||
654 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
661 static bool is_accessed_spte(u64 spte)
663 u64 accessed_mask = spte_shadow_accessed_mask(spte);
665 return accessed_mask ? spte & accessed_mask
666 : !is_access_track_spte(spte);
669 static bool is_dirty_spte(u64 spte)
671 u64 dirty_mask = spte_shadow_dirty_mask(spte);
673 return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK;
676 /* Rules for using mmu_spte_set:
677 * Set the sptep from nonpresent to present.
678 * Note: the sptep being assigned *must* be either not present
679 * or in a state where the hardware will not attempt to update
682 static void mmu_spte_set(u64 *sptep, u64 new_spte)
684 WARN_ON(is_shadow_present_pte(*sptep));
685 __set_spte(sptep, new_spte);
689 * Update the SPTE (excluding the PFN), but do not track changes in its
690 * accessed/dirty status.
692 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
694 u64 old_spte = *sptep;
696 WARN_ON(!is_shadow_present_pte(new_spte));
698 if (!is_shadow_present_pte(old_spte)) {
699 mmu_spte_set(sptep, new_spte);
703 if (!spte_has_volatile_bits(old_spte))
704 __update_clear_spte_fast(sptep, new_spte);
706 old_spte = __update_clear_spte_slow(sptep, new_spte);
708 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
713 /* Rules for using mmu_spte_update:
714 * Update the state bits, it means the mapped pfn is not changed.
716 * Whenever we overwrite a writable spte with a read-only one we
717 * should flush remote TLBs. Otherwise rmap_write_protect
718 * will find a read-only spte, even though the writable spte
719 * might be cached on a CPU's TLB, the return value indicates this
722 * Returns true if the TLB needs to be flushed
724 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
727 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
729 if (!is_shadow_present_pte(old_spte))
733 * For the spte updated out of mmu-lock is safe, since
734 * we always atomically update it, see the comments in
735 * spte_has_volatile_bits().
737 if (spte_can_locklessly_be_made_writable(old_spte) &&
738 !is_writable_pte(new_spte))
742 * Flush TLB when accessed/dirty states are changed in the page tables,
743 * to guarantee consistency between TLB and page tables.
746 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
748 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
751 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
753 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
760 * Rules for using mmu_spte_clear_track_bits:
761 * It sets the sptep from present to nonpresent, and track the
762 * state bits, it is used to clear the last level sptep.
763 * Returns non-zero if the PTE was previously valid.
765 static int mmu_spte_clear_track_bits(u64 *sptep)
768 u64 old_spte = *sptep;
770 if (!spte_has_volatile_bits(old_spte))
771 __update_clear_spte_fast(sptep, 0ull);
773 old_spte = __update_clear_spte_slow(sptep, 0ull);
775 if (!is_shadow_present_pte(old_spte))
778 pfn = spte_to_pfn(old_spte);
781 * KVM does not hold the refcount of the page used by
782 * kvm mmu, before reclaiming the page, we should
783 * unmap it from mmu first.
785 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
787 if (is_accessed_spte(old_spte))
788 kvm_set_pfn_accessed(pfn);
790 if (is_dirty_spte(old_spte))
791 kvm_set_pfn_dirty(pfn);
797 * Rules for using mmu_spte_clear_no_track:
798 * Directly clear spte without caring the state bits of sptep,
799 * it is used to set the upper level spte.
801 static void mmu_spte_clear_no_track(u64 *sptep)
803 __update_clear_spte_fast(sptep, 0ull);
806 static u64 mmu_spte_get_lockless(u64 *sptep)
808 return __get_spte_lockless(sptep);
811 static u64 mark_spte_for_access_track(u64 spte)
813 if (spte_ad_enabled(spte))
814 return spte & ~shadow_accessed_mask;
816 if (is_access_track_spte(spte))
820 * Making an Access Tracking PTE will result in removal of write access
821 * from the PTE. So, verify that we will be able to restore the write
822 * access in the fast page fault path later on.
824 WARN_ONCE((spte & PT_WRITABLE_MASK) &&
825 !spte_can_locklessly_be_made_writable(spte),
826 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
828 WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask <<
829 shadow_acc_track_saved_bits_shift),
830 "kvm: Access Tracking saved bit locations are not zero\n");
832 spte |= (spte & shadow_acc_track_saved_bits_mask) <<
833 shadow_acc_track_saved_bits_shift;
834 spte &= ~shadow_acc_track_mask;
839 /* Restore an acc-track PTE back to a regular PTE */
840 static u64 restore_acc_track_spte(u64 spte)
843 u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift)
844 & shadow_acc_track_saved_bits_mask;
846 WARN_ON_ONCE(spte_ad_enabled(spte));
847 WARN_ON_ONCE(!is_access_track_spte(spte));
849 new_spte &= ~shadow_acc_track_mask;
850 new_spte &= ~(shadow_acc_track_saved_bits_mask <<
851 shadow_acc_track_saved_bits_shift);
852 new_spte |= saved_bits;
857 /* Returns the Accessed status of the PTE and resets it at the same time. */
858 static bool mmu_spte_age(u64 *sptep)
860 u64 spte = mmu_spte_get_lockless(sptep);
862 if (!is_accessed_spte(spte))
865 if (spte_ad_enabled(spte)) {
866 clear_bit((ffs(shadow_accessed_mask) - 1),
867 (unsigned long *)sptep);
870 * Capture the dirty status of the page, so that it doesn't get
871 * lost when the SPTE is marked for access tracking.
873 if (is_writable_pte(spte))
874 kvm_set_pfn_dirty(spte_to_pfn(spte));
876 spte = mark_spte_for_access_track(spte);
877 mmu_spte_update_no_track(sptep, spte);
883 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
886 * Prevent page table teardown by making any free-er wait during
887 * kvm_flush_remote_tlbs() IPI to all active vcpus.
892 * Make sure a following spte read is not reordered ahead of the write
895 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
898 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
901 * Make sure the write to vcpu->mode is not reordered in front of
902 * reads to sptes. If it does, kvm_commit_zap_page() can see us
903 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
905 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
909 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
910 struct kmem_cache *base_cache, int min)
914 if (cache->nobjs >= min)
916 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
917 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
920 cache->objects[cache->nobjs++] = obj;
925 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
930 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
931 struct kmem_cache *cache)
934 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
937 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
942 if (cache->nobjs >= min)
944 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
945 page = (void *)__get_free_page(GFP_KERNEL_ACCOUNT);
948 cache->objects[cache->nobjs++] = page;
953 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
956 free_page((unsigned long)mc->objects[--mc->nobjs]);
959 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
963 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
964 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
967 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
970 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
971 mmu_page_header_cache, 4);
976 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
978 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
979 pte_list_desc_cache);
980 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
981 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
982 mmu_page_header_cache);
985 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
990 p = mc->objects[--mc->nobjs];
994 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
996 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
999 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
1001 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
1004 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
1006 if (!sp->role.direct)
1007 return sp->gfns[index];
1009 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
1012 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
1014 if (sp->role.direct)
1015 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
1017 sp->gfns[index] = gfn;
1021 * Return the pointer to the large page information for a given gfn,
1022 * handling slots that are not large page aligned.
1024 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
1025 struct kvm_memory_slot *slot,
1030 idx = gfn_to_index(gfn, slot->base_gfn, level);
1031 return &slot->arch.lpage_info[level - 2][idx];
1034 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
1035 gfn_t gfn, int count)
1037 struct kvm_lpage_info *linfo;
1040 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1041 linfo = lpage_info_slot(gfn, slot, i);
1042 linfo->disallow_lpage += count;
1043 WARN_ON(linfo->disallow_lpage < 0);
1047 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1049 update_gfn_disallow_lpage_count(slot, gfn, 1);
1052 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1054 update_gfn_disallow_lpage_count(slot, gfn, -1);
1057 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1059 struct kvm_memslots *slots;
1060 struct kvm_memory_slot *slot;
1063 kvm->arch.indirect_shadow_pages++;
1065 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1066 slot = __gfn_to_memslot(slots, gfn);
1068 /* the non-leaf shadow pages are keeping readonly. */
1069 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1070 return kvm_slot_page_track_add_page(kvm, slot, gfn,
1071 KVM_PAGE_TRACK_WRITE);
1073 kvm_mmu_gfn_disallow_lpage(slot, gfn);
1076 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1078 struct kvm_memslots *slots;
1079 struct kvm_memory_slot *slot;
1082 kvm->arch.indirect_shadow_pages--;
1084 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1085 slot = __gfn_to_memslot(slots, gfn);
1086 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1087 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
1088 KVM_PAGE_TRACK_WRITE);
1090 kvm_mmu_gfn_allow_lpage(slot, gfn);
1093 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
1094 struct kvm_memory_slot *slot)
1096 struct kvm_lpage_info *linfo;
1099 linfo = lpage_info_slot(gfn, slot, level);
1100 return !!linfo->disallow_lpage;
1106 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
1109 struct kvm_memory_slot *slot;
1111 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1112 return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
1115 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
1117 unsigned long page_size;
1120 page_size = kvm_host_page_size(kvm, gfn);
1122 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1123 if (page_size >= KVM_HPAGE_SIZE(i))
1132 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
1135 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
1137 if (no_dirty_log && slot->dirty_bitmap)
1143 static struct kvm_memory_slot *
1144 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
1147 struct kvm_memory_slot *slot;
1149 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1150 if (!memslot_valid_for_gpte(slot, no_dirty_log))
1156 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
1157 bool *force_pt_level)
1159 int host_level, level, max_level;
1160 struct kvm_memory_slot *slot;
1162 if (unlikely(*force_pt_level))
1163 return PT_PAGE_TABLE_LEVEL;
1165 slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
1166 *force_pt_level = !memslot_valid_for_gpte(slot, true);
1167 if (unlikely(*force_pt_level))
1168 return PT_PAGE_TABLE_LEVEL;
1170 host_level = host_mapping_level(vcpu->kvm, large_gfn);
1172 if (host_level == PT_PAGE_TABLE_LEVEL)
1175 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
1177 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
1178 if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot))
1185 * About rmap_head encoding:
1187 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1188 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1189 * pte_list_desc containing more mappings.
1193 * Returns the number of pointers in the rmap chain, not counting the new one.
1195 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
1196 struct kvm_rmap_head *rmap_head)
1198 struct pte_list_desc *desc;
1201 if (!rmap_head->val) {
1202 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
1203 rmap_head->val = (unsigned long)spte;
1204 } else if (!(rmap_head->val & 1)) {
1205 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
1206 desc = mmu_alloc_pte_list_desc(vcpu);
1207 desc->sptes[0] = (u64 *)rmap_head->val;
1208 desc->sptes[1] = spte;
1209 rmap_head->val = (unsigned long)desc | 1;
1212 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
1213 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1214 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
1216 count += PTE_LIST_EXT;
1218 if (desc->sptes[PTE_LIST_EXT-1]) {
1219 desc->more = mmu_alloc_pte_list_desc(vcpu);
1222 for (i = 0; desc->sptes[i]; ++i)
1224 desc->sptes[i] = spte;
1230 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
1231 struct pte_list_desc *desc, int i,
1232 struct pte_list_desc *prev_desc)
1236 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
1238 desc->sptes[i] = desc->sptes[j];
1239 desc->sptes[j] = NULL;
1242 if (!prev_desc && !desc->more)
1243 rmap_head->val = (unsigned long)desc->sptes[0];
1246 prev_desc->more = desc->more;
1248 rmap_head->val = (unsigned long)desc->more | 1;
1249 mmu_free_pte_list_desc(desc);
1252 static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1254 struct pte_list_desc *desc;
1255 struct pte_list_desc *prev_desc;
1258 if (!rmap_head->val) {
1259 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
1261 } else if (!(rmap_head->val & 1)) {
1262 rmap_printk("pte_list_remove: %p 1->0\n", spte);
1263 if ((u64 *)rmap_head->val != spte) {
1264 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
1269 rmap_printk("pte_list_remove: %p many->many\n", spte);
1270 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1273 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1274 if (desc->sptes[i] == spte) {
1275 pte_list_desc_remove_entry(rmap_head,
1276 desc, i, prev_desc);
1283 pr_err("pte_list_remove: %p many->many\n", spte);
1288 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1289 struct kvm_memory_slot *slot)
1293 idx = gfn_to_index(gfn, slot->base_gfn, level);
1294 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1297 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1298 struct kvm_mmu_page *sp)
1300 struct kvm_memslots *slots;
1301 struct kvm_memory_slot *slot;
1303 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1304 slot = __gfn_to_memslot(slots, gfn);
1305 return __gfn_to_rmap(gfn, sp->role.level, slot);
1308 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1310 struct kvm_mmu_memory_cache *cache;
1312 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1313 return mmu_memory_cache_free_objects(cache);
1316 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1318 struct kvm_mmu_page *sp;
1319 struct kvm_rmap_head *rmap_head;
1321 sp = page_header(__pa(spte));
1322 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1323 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1324 return pte_list_add(vcpu, spte, rmap_head);
1327 static void rmap_remove(struct kvm *kvm, u64 *spte)
1329 struct kvm_mmu_page *sp;
1331 struct kvm_rmap_head *rmap_head;
1333 sp = page_header(__pa(spte));
1334 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1335 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1336 pte_list_remove(spte, rmap_head);
1340 * Used by the following functions to iterate through the sptes linked by a
1341 * rmap. All fields are private and not assumed to be used outside.
1343 struct rmap_iterator {
1344 /* private fields */
1345 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1346 int pos; /* index of the sptep */
1350 * Iteration must be started by this function. This should also be used after
1351 * removing/dropping sptes from the rmap link because in such cases the
1352 * information in the itererator may not be valid.
1354 * Returns sptep if found, NULL otherwise.
1356 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1357 struct rmap_iterator *iter)
1361 if (!rmap_head->val)
1364 if (!(rmap_head->val & 1)) {
1366 sptep = (u64 *)rmap_head->val;
1370 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1372 sptep = iter->desc->sptes[iter->pos];
1374 BUG_ON(!is_shadow_present_pte(*sptep));
1379 * Must be used with a valid iterator: e.g. after rmap_get_first().
1381 * Returns sptep if found, NULL otherwise.
1383 static u64 *rmap_get_next(struct rmap_iterator *iter)
1388 if (iter->pos < PTE_LIST_EXT - 1) {
1390 sptep = iter->desc->sptes[iter->pos];
1395 iter->desc = iter->desc->more;
1399 /* desc->sptes[0] cannot be NULL */
1400 sptep = iter->desc->sptes[iter->pos];
1407 BUG_ON(!is_shadow_present_pte(*sptep));
1411 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1412 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1413 _spte_; _spte_ = rmap_get_next(_iter_))
1415 static void drop_spte(struct kvm *kvm, u64 *sptep)
1417 if (mmu_spte_clear_track_bits(sptep))
1418 rmap_remove(kvm, sptep);
1422 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1424 if (is_large_pte(*sptep)) {
1425 WARN_ON(page_header(__pa(sptep))->role.level ==
1426 PT_PAGE_TABLE_LEVEL);
1427 drop_spte(kvm, sptep);
1435 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1437 if (__drop_large_spte(vcpu->kvm, sptep))
1438 kvm_flush_remote_tlbs(vcpu->kvm);
1442 * Write-protect on the specified @sptep, @pt_protect indicates whether
1443 * spte write-protection is caused by protecting shadow page table.
1445 * Note: write protection is difference between dirty logging and spte
1447 * - for dirty logging, the spte can be set to writable at anytime if
1448 * its dirty bitmap is properly set.
1449 * - for spte protection, the spte can be writable only after unsync-ing
1452 * Return true if tlb need be flushed.
1454 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1458 if (!is_writable_pte(spte) &&
1459 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1462 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1465 spte &= ~SPTE_MMU_WRITEABLE;
1466 spte = spte & ~PT_WRITABLE_MASK;
1468 return mmu_spte_update(sptep, spte);
1471 static bool __rmap_write_protect(struct kvm *kvm,
1472 struct kvm_rmap_head *rmap_head,
1476 struct rmap_iterator iter;
1479 for_each_rmap_spte(rmap_head, &iter, sptep)
1480 flush |= spte_write_protect(sptep, pt_protect);
1485 static bool spte_clear_dirty(u64 *sptep)
1489 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1491 spte &= ~shadow_dirty_mask;
1493 return mmu_spte_update(sptep, spte);
1496 static bool wrprot_ad_disabled_spte(u64 *sptep)
1498 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1499 (unsigned long *)sptep);
1501 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1503 return was_writable;
1507 * Gets the GFN ready for another round of dirty logging by clearing the
1508 * - D bit on ad-enabled SPTEs, and
1509 * - W bit on ad-disabled SPTEs.
1510 * Returns true iff any D or W bits were cleared.
1512 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1515 struct rmap_iterator iter;
1518 for_each_rmap_spte(rmap_head, &iter, sptep)
1519 if (spte_ad_enabled(*sptep))
1520 flush |= spte_clear_dirty(sptep);
1522 flush |= wrprot_ad_disabled_spte(sptep);
1527 static bool spte_set_dirty(u64 *sptep)
1531 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1533 spte |= shadow_dirty_mask;
1535 return mmu_spte_update(sptep, spte);
1538 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1541 struct rmap_iterator iter;
1544 for_each_rmap_spte(rmap_head, &iter, sptep)
1545 if (spte_ad_enabled(*sptep))
1546 flush |= spte_set_dirty(sptep);
1552 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1553 * @kvm: kvm instance
1554 * @slot: slot to protect
1555 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1556 * @mask: indicates which pages we should protect
1558 * Used when we do not need to care about huge page mappings: e.g. during dirty
1559 * logging we do not have any such mappings.
1561 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1562 struct kvm_memory_slot *slot,
1563 gfn_t gfn_offset, unsigned long mask)
1565 struct kvm_rmap_head *rmap_head;
1568 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1569 PT_PAGE_TABLE_LEVEL, slot);
1570 __rmap_write_protect(kvm, rmap_head, false);
1572 /* clear the first set bit */
1578 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1579 * protect the page if the D-bit isn't supported.
1580 * @kvm: kvm instance
1581 * @slot: slot to clear D-bit
1582 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1583 * @mask: indicates which pages we should clear D-bit
1585 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1587 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1588 struct kvm_memory_slot *slot,
1589 gfn_t gfn_offset, unsigned long mask)
1591 struct kvm_rmap_head *rmap_head;
1594 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1595 PT_PAGE_TABLE_LEVEL, slot);
1596 __rmap_clear_dirty(kvm, rmap_head);
1598 /* clear the first set bit */
1602 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1605 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1608 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1609 * enable dirty logging for them.
1611 * Used when we do not need to care about huge page mappings: e.g. during dirty
1612 * logging we do not have any such mappings.
1614 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1615 struct kvm_memory_slot *slot,
1616 gfn_t gfn_offset, unsigned long mask)
1618 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1619 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1622 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1626 * kvm_arch_write_log_dirty - emulate dirty page logging
1627 * @vcpu: Guest mode vcpu
1629 * Emulate arch specific page modification logging for the
1632 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu)
1634 if (kvm_x86_ops->write_log_dirty)
1635 return kvm_x86_ops->write_log_dirty(vcpu);
1640 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1641 struct kvm_memory_slot *slot, u64 gfn)
1643 struct kvm_rmap_head *rmap_head;
1645 bool write_protected = false;
1647 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1648 rmap_head = __gfn_to_rmap(gfn, i, slot);
1649 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1652 return write_protected;
1655 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1657 struct kvm_memory_slot *slot;
1659 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1660 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1663 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1666 struct rmap_iterator iter;
1669 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1670 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1672 drop_spte(kvm, sptep);
1679 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1680 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1683 return kvm_zap_rmapp(kvm, rmap_head);
1686 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1687 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1691 struct rmap_iterator iter;
1694 pte_t *ptep = (pte_t *)data;
1697 WARN_ON(pte_huge(*ptep));
1698 new_pfn = pte_pfn(*ptep);
1701 for_each_rmap_spte(rmap_head, &iter, sptep) {
1702 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1703 sptep, *sptep, gfn, level);
1707 if (pte_write(*ptep)) {
1708 drop_spte(kvm, sptep);
1711 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1712 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1714 new_spte &= ~PT_WRITABLE_MASK;
1715 new_spte &= ~SPTE_HOST_WRITEABLE;
1717 new_spte = mark_spte_for_access_track(new_spte);
1719 mmu_spte_clear_track_bits(sptep);
1720 mmu_spte_set(sptep, new_spte);
1725 kvm_flush_remote_tlbs(kvm);
1730 struct slot_rmap_walk_iterator {
1732 struct kvm_memory_slot *slot;
1738 /* output fields. */
1740 struct kvm_rmap_head *rmap;
1743 /* private field. */
1744 struct kvm_rmap_head *end_rmap;
1748 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1750 iterator->level = level;
1751 iterator->gfn = iterator->start_gfn;
1752 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1753 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1758 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1759 struct kvm_memory_slot *slot, int start_level,
1760 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1762 iterator->slot = slot;
1763 iterator->start_level = start_level;
1764 iterator->end_level = end_level;
1765 iterator->start_gfn = start_gfn;
1766 iterator->end_gfn = end_gfn;
1768 rmap_walk_init_level(iterator, iterator->start_level);
1771 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1773 return !!iterator->rmap;
1776 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1778 if (++iterator->rmap <= iterator->end_rmap) {
1779 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1783 if (++iterator->level > iterator->end_level) {
1784 iterator->rmap = NULL;
1788 rmap_walk_init_level(iterator, iterator->level);
1791 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1792 _start_gfn, _end_gfn, _iter_) \
1793 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1794 _end_level_, _start_gfn, _end_gfn); \
1795 slot_rmap_walk_okay(_iter_); \
1796 slot_rmap_walk_next(_iter_))
1798 static int kvm_handle_hva_range(struct kvm *kvm,
1799 unsigned long start,
1802 int (*handler)(struct kvm *kvm,
1803 struct kvm_rmap_head *rmap_head,
1804 struct kvm_memory_slot *slot,
1807 unsigned long data))
1809 struct kvm_memslots *slots;
1810 struct kvm_memory_slot *memslot;
1811 struct slot_rmap_walk_iterator iterator;
1815 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1816 slots = __kvm_memslots(kvm, i);
1817 kvm_for_each_memslot(memslot, slots) {
1818 unsigned long hva_start, hva_end;
1819 gfn_t gfn_start, gfn_end;
1821 hva_start = max(start, memslot->userspace_addr);
1822 hva_end = min(end, memslot->userspace_addr +
1823 (memslot->npages << PAGE_SHIFT));
1824 if (hva_start >= hva_end)
1827 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1828 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1830 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1831 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1833 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1834 PT_MAX_HUGEPAGE_LEVEL,
1835 gfn_start, gfn_end - 1,
1837 ret |= handler(kvm, iterator.rmap, memslot,
1838 iterator.gfn, iterator.level, data);
1845 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1847 int (*handler)(struct kvm *kvm,
1848 struct kvm_rmap_head *rmap_head,
1849 struct kvm_memory_slot *slot,
1850 gfn_t gfn, int level,
1851 unsigned long data))
1853 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1856 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1858 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1861 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1863 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1866 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1867 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1871 struct rmap_iterator uninitialized_var(iter);
1874 for_each_rmap_spte(rmap_head, &iter, sptep)
1875 young |= mmu_spte_age(sptep);
1877 trace_kvm_age_page(gfn, level, slot, young);
1881 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1882 struct kvm_memory_slot *slot, gfn_t gfn,
1883 int level, unsigned long data)
1886 struct rmap_iterator iter;
1888 for_each_rmap_spte(rmap_head, &iter, sptep)
1889 if (is_accessed_spte(*sptep))
1894 #define RMAP_RECYCLE_THRESHOLD 1000
1896 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1898 struct kvm_rmap_head *rmap_head;
1899 struct kvm_mmu_page *sp;
1901 sp = page_header(__pa(spte));
1903 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1905 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1906 kvm_flush_remote_tlbs(vcpu->kvm);
1909 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1911 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1914 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1916 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1920 static int is_empty_shadow_page(u64 *spt)
1925 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1926 if (is_shadow_present_pte(*pos)) {
1927 printk(KERN_ERR "%s: %p %llx\n", __func__,
1936 * This value is the sum of all of the kvm instances's
1937 * kvm->arch.n_used_mmu_pages values. We need a global,
1938 * aggregate version in order to make the slab shrinker
1941 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1943 kvm->arch.n_used_mmu_pages += nr;
1944 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1947 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1949 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1950 hlist_del(&sp->hash_link);
1951 list_del(&sp->link);
1952 free_page((unsigned long)sp->spt);
1953 if (!sp->role.direct)
1954 free_page((unsigned long)sp->gfns);
1955 kmem_cache_free(mmu_page_header_cache, sp);
1958 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1960 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1963 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1964 struct kvm_mmu_page *sp, u64 *parent_pte)
1969 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1972 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1975 pte_list_remove(parent_pte, &sp->parent_ptes);
1978 static void drop_parent_pte(struct kvm_mmu_page *sp,
1981 mmu_page_remove_parent_pte(sp, parent_pte);
1982 mmu_spte_clear_no_track(parent_pte);
1985 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1987 struct kvm_mmu_page *sp;
1989 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1990 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1992 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1993 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1996 * The active_mmu_pages list is the FIFO list, do not move the
1997 * page until it is zapped. kvm_zap_obsolete_pages depends on
1998 * this feature. See the comments in kvm_zap_obsolete_pages().
2000 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
2001 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
2005 static void mark_unsync(u64 *spte);
2006 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
2009 struct rmap_iterator iter;
2011 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
2016 static void mark_unsync(u64 *spte)
2018 struct kvm_mmu_page *sp;
2021 sp = page_header(__pa(spte));
2022 index = spte - sp->spt;
2023 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
2025 if (sp->unsync_children++)
2027 kvm_mmu_mark_parents_unsync(sp);
2030 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
2031 struct kvm_mmu_page *sp)
2036 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root)
2040 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
2041 struct kvm_mmu_page *sp, u64 *spte,
2047 #define KVM_PAGE_ARRAY_NR 16
2049 struct kvm_mmu_pages {
2050 struct mmu_page_and_offset {
2051 struct kvm_mmu_page *sp;
2053 } page[KVM_PAGE_ARRAY_NR];
2057 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
2063 for (i=0; i < pvec->nr; i++)
2064 if (pvec->page[i].sp == sp)
2067 pvec->page[pvec->nr].sp = sp;
2068 pvec->page[pvec->nr].idx = idx;
2070 return (pvec->nr == KVM_PAGE_ARRAY_NR);
2073 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
2075 --sp->unsync_children;
2076 WARN_ON((int)sp->unsync_children < 0);
2077 __clear_bit(idx, sp->unsync_child_bitmap);
2080 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
2081 struct kvm_mmu_pages *pvec)
2083 int i, ret, nr_unsync_leaf = 0;
2085 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
2086 struct kvm_mmu_page *child;
2087 u64 ent = sp->spt[i];
2089 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
2090 clear_unsync_child_bit(sp, i);
2094 child = page_header(ent & PT64_BASE_ADDR_MASK);
2096 if (child->unsync_children) {
2097 if (mmu_pages_add(pvec, child, i))
2100 ret = __mmu_unsync_walk(child, pvec);
2102 clear_unsync_child_bit(sp, i);
2104 } else if (ret > 0) {
2105 nr_unsync_leaf += ret;
2108 } else if (child->unsync) {
2110 if (mmu_pages_add(pvec, child, i))
2113 clear_unsync_child_bit(sp, i);
2116 return nr_unsync_leaf;
2119 #define INVALID_INDEX (-1)
2121 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
2122 struct kvm_mmu_pages *pvec)
2125 if (!sp->unsync_children)
2128 mmu_pages_add(pvec, sp, INVALID_INDEX);
2129 return __mmu_unsync_walk(sp, pvec);
2132 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
2134 WARN_ON(!sp->unsync);
2135 trace_kvm_mmu_sync_page(sp);
2137 --kvm->stat.mmu_unsync;
2140 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2141 struct list_head *invalid_list);
2142 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2143 struct list_head *invalid_list);
2146 * NOTE: we should pay more attention on the zapped-obsolete page
2147 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
2148 * since it has been deleted from active_mmu_pages but still can be found
2151 * for_each_valid_sp() has skipped that kind of pages.
2153 #define for_each_valid_sp(_kvm, _sp, _gfn) \
2154 hlist_for_each_entry(_sp, \
2155 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2156 if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \
2159 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
2160 for_each_valid_sp(_kvm, _sp, _gfn) \
2161 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2163 /* @sp->gfn should be write-protected at the call site */
2164 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2165 struct list_head *invalid_list)
2167 if (sp->role.cr4_pae != !!is_pae(vcpu)
2168 || vcpu->arch.mmu.sync_page(vcpu, sp) == 0) {
2169 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
2176 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
2177 struct list_head *invalid_list,
2178 bool remote_flush, bool local_flush)
2180 if (!list_empty(invalid_list)) {
2181 kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list);
2186 kvm_flush_remote_tlbs(vcpu->kvm);
2187 else if (local_flush)
2188 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2191 #ifdef CONFIG_KVM_MMU_AUDIT
2192 #include "mmu_audit.c"
2194 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
2195 static void mmu_audit_disable(void) { }
2198 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
2200 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
2203 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2204 struct list_head *invalid_list)
2206 kvm_unlink_unsync_page(vcpu->kvm, sp);
2207 return __kvm_sync_page(vcpu, sp, invalid_list);
2210 /* @gfn should be write-protected at the call site */
2211 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
2212 struct list_head *invalid_list)
2214 struct kvm_mmu_page *s;
2217 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2221 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2222 ret |= kvm_sync_page(vcpu, s, invalid_list);
2228 struct mmu_page_path {
2229 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
2230 unsigned int idx[PT64_ROOT_MAX_LEVEL];
2233 #define for_each_sp(pvec, sp, parents, i) \
2234 for (i = mmu_pages_first(&pvec, &parents); \
2235 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2236 i = mmu_pages_next(&pvec, &parents, i))
2238 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2239 struct mmu_page_path *parents,
2244 for (n = i+1; n < pvec->nr; n++) {
2245 struct kvm_mmu_page *sp = pvec->page[n].sp;
2246 unsigned idx = pvec->page[n].idx;
2247 int level = sp->role.level;
2249 parents->idx[level-1] = idx;
2250 if (level == PT_PAGE_TABLE_LEVEL)
2253 parents->parent[level-2] = sp;
2259 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2260 struct mmu_page_path *parents)
2262 struct kvm_mmu_page *sp;
2268 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2270 sp = pvec->page[0].sp;
2271 level = sp->role.level;
2272 WARN_ON(level == PT_PAGE_TABLE_LEVEL);
2274 parents->parent[level-2] = sp;
2276 /* Also set up a sentinel. Further entries in pvec are all
2277 * children of sp, so this element is never overwritten.
2279 parents->parent[level-1] = NULL;
2280 return mmu_pages_next(pvec, parents, 0);
2283 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2285 struct kvm_mmu_page *sp;
2286 unsigned int level = 0;
2289 unsigned int idx = parents->idx[level];
2290 sp = parents->parent[level];
2294 WARN_ON(idx == INVALID_INDEX);
2295 clear_unsync_child_bit(sp, idx);
2297 } while (!sp->unsync_children);
2300 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2301 struct kvm_mmu_page *parent)
2304 struct kvm_mmu_page *sp;
2305 struct mmu_page_path parents;
2306 struct kvm_mmu_pages pages;
2307 LIST_HEAD(invalid_list);
2310 while (mmu_unsync_walk(parent, &pages)) {
2311 bool protected = false;
2313 for_each_sp(pages, sp, parents, i)
2314 protected |= rmap_write_protect(vcpu, sp->gfn);
2317 kvm_flush_remote_tlbs(vcpu->kvm);
2321 for_each_sp(pages, sp, parents, i) {
2322 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2323 mmu_pages_clear_parents(&parents);
2325 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2326 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2327 cond_resched_lock(&vcpu->kvm->mmu_lock);
2332 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2335 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2337 atomic_set(&sp->write_flooding_count, 0);
2340 static void clear_sp_write_flooding_count(u64 *spte)
2342 struct kvm_mmu_page *sp = page_header(__pa(spte));
2344 __clear_sp_write_flooding_count(sp);
2347 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2354 union kvm_mmu_page_role role;
2356 struct kvm_mmu_page *sp;
2357 bool need_sync = false;
2360 LIST_HEAD(invalid_list);
2362 role = vcpu->arch.mmu.base_role;
2364 role.direct = direct;
2367 role.access = access;
2368 if (!vcpu->arch.mmu.direct_map
2369 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
2370 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2371 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2372 role.quadrant = quadrant;
2374 for_each_valid_sp(vcpu->kvm, sp, gfn) {
2375 if (sp->gfn != gfn) {
2380 if (!need_sync && sp->unsync)
2383 if (sp->role.word != role.word)
2387 /* The page is good, but __kvm_sync_page might still end
2388 * up zapping it. If so, break in order to rebuild it.
2390 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2393 WARN_ON(!list_empty(&invalid_list));
2394 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2397 if (sp->unsync_children)
2398 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2400 __clear_sp_write_flooding_count(sp);
2401 trace_kvm_mmu_get_page(sp, false);
2405 ++vcpu->kvm->stat.mmu_cache_miss;
2407 sp = kvm_mmu_alloc_page(vcpu, direct);
2411 hlist_add_head(&sp->hash_link,
2412 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2415 * we should do write protection before syncing pages
2416 * otherwise the content of the synced shadow page may
2417 * be inconsistent with guest page table.
2419 account_shadowed(vcpu->kvm, sp);
2420 if (level == PT_PAGE_TABLE_LEVEL &&
2421 rmap_write_protect(vcpu, gfn))
2422 kvm_flush_remote_tlbs(vcpu->kvm);
2424 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2425 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2427 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2428 clear_page(sp->spt);
2429 trace_kvm_mmu_get_page(sp, true);
2431 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2433 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2434 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2438 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2439 struct kvm_vcpu *vcpu, hpa_t root,
2442 iterator->addr = addr;
2443 iterator->shadow_addr = root;
2444 iterator->level = vcpu->arch.mmu.shadow_root_level;
2446 if (iterator->level == PT64_ROOT_4LEVEL &&
2447 vcpu->arch.mmu.root_level < PT64_ROOT_4LEVEL &&
2448 !vcpu->arch.mmu.direct_map)
2451 if (iterator->level == PT32E_ROOT_LEVEL) {
2453 * prev_root is currently only used for 64-bit hosts. So only
2454 * the active root_hpa is valid here.
2456 BUG_ON(root != vcpu->arch.mmu.root_hpa);
2458 iterator->shadow_addr
2459 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2460 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2462 if (!iterator->shadow_addr)
2463 iterator->level = 0;
2467 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2468 struct kvm_vcpu *vcpu, u64 addr)
2470 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu.root_hpa,
2474 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2476 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2479 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2480 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2484 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2487 if (is_last_spte(spte, iterator->level)) {
2488 iterator->level = 0;
2492 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2496 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2498 __shadow_walk_next(iterator, *iterator->sptep);
2501 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2502 struct kvm_mmu_page *sp)
2506 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2508 spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK |
2509 shadow_user_mask | shadow_x_mask | shadow_me_mask;
2511 if (sp_ad_disabled(sp))
2512 spte |= shadow_acc_track_value;
2514 spte |= shadow_accessed_mask;
2516 mmu_spte_set(sptep, spte);
2518 mmu_page_add_parent_pte(vcpu, sp, sptep);
2520 if (sp->unsync_children || sp->unsync)
2524 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2525 unsigned direct_access)
2527 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2528 struct kvm_mmu_page *child;
2531 * For the direct sp, if the guest pte's dirty bit
2532 * changed form clean to dirty, it will corrupt the
2533 * sp's access: allow writable in the read-only sp,
2534 * so we should update the spte at this point to get
2535 * a new sp with the correct access.
2537 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2538 if (child->role.access == direct_access)
2541 drop_parent_pte(child, sptep);
2542 kvm_flush_remote_tlbs(vcpu->kvm);
2546 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2550 struct kvm_mmu_page *child;
2553 if (is_shadow_present_pte(pte)) {
2554 if (is_last_spte(pte, sp->role.level)) {
2555 drop_spte(kvm, spte);
2556 if (is_large_pte(pte))
2559 child = page_header(pte & PT64_BASE_ADDR_MASK);
2560 drop_parent_pte(child, spte);
2565 if (is_mmio_spte(pte))
2566 mmu_spte_clear_no_track(spte);
2571 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2572 struct kvm_mmu_page *sp)
2576 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2577 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2580 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2583 struct rmap_iterator iter;
2585 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2586 drop_parent_pte(sp, sptep);
2589 static int mmu_zap_unsync_children(struct kvm *kvm,
2590 struct kvm_mmu_page *parent,
2591 struct list_head *invalid_list)
2594 struct mmu_page_path parents;
2595 struct kvm_mmu_pages pages;
2597 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2600 while (mmu_unsync_walk(parent, &pages)) {
2601 struct kvm_mmu_page *sp;
2603 for_each_sp(pages, sp, parents, i) {
2604 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2605 mmu_pages_clear_parents(&parents);
2613 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2614 struct list_head *invalid_list)
2618 trace_kvm_mmu_prepare_zap_page(sp);
2619 ++kvm->stat.mmu_shadow_zapped;
2620 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2621 kvm_mmu_page_unlink_children(kvm, sp);
2622 kvm_mmu_unlink_parents(kvm, sp);
2624 if (!sp->role.invalid && !sp->role.direct)
2625 unaccount_shadowed(kvm, sp);
2628 kvm_unlink_unsync_page(kvm, sp);
2629 if (!sp->root_count) {
2632 list_move(&sp->link, invalid_list);
2633 kvm_mod_used_mmu_pages(kvm, -1);
2635 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2638 * The obsolete pages can not be used on any vcpus.
2639 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2641 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2642 kvm_reload_remote_mmus(kvm);
2645 sp->role.invalid = 1;
2649 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2650 struct list_head *invalid_list)
2652 struct kvm_mmu_page *sp, *nsp;
2654 if (list_empty(invalid_list))
2658 * We need to make sure everyone sees our modifications to
2659 * the page tables and see changes to vcpu->mode here. The barrier
2660 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2661 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2663 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2664 * guest mode and/or lockless shadow page table walks.
2666 kvm_flush_remote_tlbs(kvm);
2668 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2669 WARN_ON(!sp->role.invalid || sp->root_count);
2670 kvm_mmu_free_page(sp);
2674 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2675 struct list_head *invalid_list)
2677 struct kvm_mmu_page *sp;
2679 if (list_empty(&kvm->arch.active_mmu_pages))
2682 sp = list_last_entry(&kvm->arch.active_mmu_pages,
2683 struct kvm_mmu_page, link);
2684 return kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2688 * Changing the number of mmu pages allocated to the vm
2689 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2691 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2693 LIST_HEAD(invalid_list);
2695 spin_lock(&kvm->mmu_lock);
2697 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2698 /* Need to free some mmu pages to achieve the goal. */
2699 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2700 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2703 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2704 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2707 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2709 spin_unlock(&kvm->mmu_lock);
2712 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2714 struct kvm_mmu_page *sp;
2715 LIST_HEAD(invalid_list);
2718 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2720 spin_lock(&kvm->mmu_lock);
2721 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2722 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2725 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2727 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2728 spin_unlock(&kvm->mmu_lock);
2732 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2734 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2736 trace_kvm_mmu_unsync_page(sp);
2737 ++vcpu->kvm->stat.mmu_unsync;
2740 kvm_mmu_mark_parents_unsync(sp);
2743 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2746 struct kvm_mmu_page *sp;
2748 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2751 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2758 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
2759 kvm_unsync_page(vcpu, sp);
2763 * We need to ensure that the marking of unsync pages is visible
2764 * before the SPTE is updated to allow writes because
2765 * kvm_mmu_sync_roots() checks the unsync flags without holding
2766 * the MMU lock and so can race with this. If the SPTE was updated
2767 * before the page had been marked as unsync-ed, something like the
2768 * following could happen:
2771 * ---------------------------------------------------------------------
2772 * 1.2 Host updates SPTE
2774 * 2.1 Guest writes a GPTE for GVA X.
2775 * (GPTE being in the guest page table shadowed
2776 * by the SP from CPU 1.)
2777 * This reads SPTE during the page table walk.
2778 * Since SPTE.W is read as 1, there is no
2781 * 2.2 Guest issues TLB flush.
2782 * That causes a VM Exit.
2784 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
2785 * Since it is false, so it just returns.
2787 * 2.4 Guest accesses GVA X.
2788 * Since the mapping in the SP was not updated,
2789 * so the old mapping for GVA X incorrectly
2793 * (sp->unsync = true)
2795 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2796 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2797 * pairs with this write barrier.
2804 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
2807 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) &&
2809 * Some reserved pages, such as those from NVDIMM
2810 * DAX devices, are not for MMIO, and can be mapped
2811 * with cached memory type for better performance.
2812 * However, the above check misconceives those pages
2813 * as MMIO, and results in KVM mapping them with UC
2814 * memory type, which would hurt the performance.
2815 * Therefore, we check the host memory type in addition
2816 * and only treat UC/UC-/WC pages as MMIO.
2818 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn));
2823 /* Bits which may be returned by set_spte() */
2824 #define SET_SPTE_WRITE_PROTECTED_PT BIT(0)
2825 #define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1)
2827 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2828 unsigned pte_access, int level,
2829 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2830 bool can_unsync, bool host_writable)
2834 struct kvm_mmu_page *sp;
2836 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2839 sp = page_header(__pa(sptep));
2840 if (sp_ad_disabled(sp))
2841 spte |= shadow_acc_track_value;
2844 * For the EPT case, shadow_present_mask is 0 if hardware
2845 * supports exec-only page table entries. In that case,
2846 * ACC_USER_MASK and shadow_user_mask are used to represent
2847 * read access. See FNAME(gpte_access) in paging_tmpl.h.
2849 spte |= shadow_present_mask;
2851 spte |= spte_shadow_accessed_mask(spte);
2853 if (pte_access & ACC_EXEC_MASK)
2854 spte |= shadow_x_mask;
2856 spte |= shadow_nx_mask;
2858 if (pte_access & ACC_USER_MASK)
2859 spte |= shadow_user_mask;
2861 if (level > PT_PAGE_TABLE_LEVEL)
2862 spte |= PT_PAGE_SIZE_MASK;
2864 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2865 kvm_is_mmio_pfn(pfn));
2868 spte |= SPTE_HOST_WRITEABLE;
2870 pte_access &= ~ACC_WRITE_MASK;
2872 if (!kvm_is_mmio_pfn(pfn))
2873 spte |= shadow_me_mask;
2875 spte |= (u64)pfn << PAGE_SHIFT;
2877 if (pte_access & ACC_WRITE_MASK) {
2880 * Other vcpu creates new sp in the window between
2881 * mapping_level() and acquiring mmu-lock. We can
2882 * allow guest to retry the access, the mapping can
2883 * be fixed if guest refault.
2885 if (level > PT_PAGE_TABLE_LEVEL &&
2886 mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
2889 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2892 * Optimization: for pte sync, if spte was writable the hash
2893 * lookup is unnecessary (and expensive). Write protection
2894 * is responsibility of mmu_get_page / kvm_sync_page.
2895 * Same reasoning can be applied to dirty page accounting.
2897 if (!can_unsync && is_writable_pte(*sptep))
2900 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2901 pgprintk("%s: found shadow page for %llx, marking ro\n",
2903 ret |= SET_SPTE_WRITE_PROTECTED_PT;
2904 pte_access &= ~ACC_WRITE_MASK;
2905 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2909 if (pte_access & ACC_WRITE_MASK) {
2910 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2911 spte |= spte_shadow_dirty_mask(spte);
2915 spte = mark_spte_for_access_track(spte);
2918 if (mmu_spte_update(sptep, spte))
2919 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2924 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
2925 int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
2926 bool speculative, bool host_writable)
2928 int was_rmapped = 0;
2931 int ret = RET_PF_RETRY;
2934 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2935 *sptep, write_fault, gfn);
2937 if (is_shadow_present_pte(*sptep)) {
2939 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2940 * the parent of the now unreachable PTE.
2942 if (level > PT_PAGE_TABLE_LEVEL &&
2943 !is_large_pte(*sptep)) {
2944 struct kvm_mmu_page *child;
2947 child = page_header(pte & PT64_BASE_ADDR_MASK);
2948 drop_parent_pte(child, sptep);
2950 } else if (pfn != spte_to_pfn(*sptep)) {
2951 pgprintk("hfn old %llx new %llx\n",
2952 spte_to_pfn(*sptep), pfn);
2953 drop_spte(vcpu->kvm, sptep);
2959 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
2960 speculative, true, host_writable);
2961 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
2963 ret = RET_PF_EMULATE;
2964 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2966 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
2967 kvm_flush_remote_tlbs(vcpu->kvm);
2969 if (unlikely(is_mmio_spte(*sptep)))
2970 ret = RET_PF_EMULATE;
2972 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2973 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2974 is_large_pte(*sptep)? "2MB" : "4kB",
2975 *sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn,
2977 if (!was_rmapped && is_large_pte(*sptep))
2978 ++vcpu->kvm->stat.lpages;
2980 if (is_shadow_present_pte(*sptep)) {
2982 rmap_count = rmap_add(vcpu, sptep, gfn);
2983 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2984 rmap_recycle(vcpu, sptep, gfn);
2988 kvm_release_pfn_clean(pfn);
2993 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2996 struct kvm_memory_slot *slot;
2998 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
3000 return KVM_PFN_ERR_FAULT;
3002 return gfn_to_pfn_memslot_atomic(slot, gfn);
3005 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
3006 struct kvm_mmu_page *sp,
3007 u64 *start, u64 *end)
3009 struct page *pages[PTE_PREFETCH_NUM];
3010 struct kvm_memory_slot *slot;
3011 unsigned access = sp->role.access;
3015 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
3016 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
3020 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
3024 for (i = 0; i < ret; i++, gfn++, start++)
3025 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
3026 page_to_pfn(pages[i]), true, true);
3031 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
3032 struct kvm_mmu_page *sp, u64 *sptep)
3034 u64 *spte, *start = NULL;
3037 WARN_ON(!sp->role.direct);
3039 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
3042 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
3043 if (is_shadow_present_pte(*spte) || spte == sptep) {
3046 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
3054 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
3056 struct kvm_mmu_page *sp;
3058 sp = page_header(__pa(sptep));
3061 * Without accessed bits, there's no way to distinguish between
3062 * actually accessed translations and prefetched, so disable pte
3063 * prefetch if accessed bits aren't available.
3065 if (sp_ad_disabled(sp))
3068 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3071 __direct_pte_prefetch(vcpu, sp, sptep);
3074 static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable,
3075 int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault)
3077 struct kvm_shadow_walk_iterator iterator;
3078 struct kvm_mmu_page *sp;
3082 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3085 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
3086 if (iterator.level == level) {
3087 emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
3088 write, level, gfn, pfn, prefault,
3090 direct_pte_prefetch(vcpu, iterator.sptep);
3091 ++vcpu->stat.pf_fixed;
3095 drop_large_spte(vcpu, iterator.sptep);
3096 if (!is_shadow_present_pte(*iterator.sptep)) {
3097 u64 base_addr = iterator.addr;
3099 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
3100 pseudo_gfn = base_addr >> PAGE_SHIFT;
3101 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
3102 iterator.level - 1, 1, ACC_ALL);
3104 link_shadow_page(vcpu, iterator.sptep, sp);
3110 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
3114 clear_siginfo(&info);
3115 info.si_signo = SIGBUS;
3117 info.si_code = BUS_MCEERR_AR;
3118 info.si_addr = (void __user *)address;
3119 info.si_addr_lsb = PAGE_SHIFT;
3121 send_sig_info(SIGBUS, &info, tsk);
3124 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
3127 * Do not cache the mmio info caused by writing the readonly gfn
3128 * into the spte otherwise read access on readonly gfn also can
3129 * caused mmio page fault and treat it as mmio access.
3131 if (pfn == KVM_PFN_ERR_RO_FAULT)
3132 return RET_PF_EMULATE;
3134 if (pfn == KVM_PFN_ERR_HWPOISON) {
3135 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
3136 return RET_PF_RETRY;
3142 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
3143 gfn_t *gfnp, kvm_pfn_t *pfnp,
3146 kvm_pfn_t pfn = *pfnp;
3148 int level = *levelp;
3151 * Check if it's a transparent hugepage. If this would be an
3152 * hugetlbfs page, level wouldn't be set to
3153 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
3156 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
3157 level == PT_PAGE_TABLE_LEVEL &&
3158 PageTransCompoundMap(pfn_to_page(pfn)) &&
3159 !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
3162 * mmu_notifier_retry was successful and we hold the
3163 * mmu_lock here, so the pmd can't become splitting
3164 * from under us, and in turn
3165 * __split_huge_page_refcount() can't run from under
3166 * us and we can safely transfer the refcount from
3167 * PG_tail to PG_head as we switch the pfn to tail to
3170 *levelp = level = PT_DIRECTORY_LEVEL;
3171 mask = KVM_PAGES_PER_HPAGE(level) - 1;
3172 VM_BUG_ON((gfn & mask) != (pfn & mask));
3176 kvm_release_pfn_clean(pfn);
3184 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
3185 kvm_pfn_t pfn, unsigned access, int *ret_val)
3187 /* The pfn is invalid, report the error! */
3188 if (unlikely(is_error_pfn(pfn))) {
3189 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
3193 if (unlikely(is_noslot_pfn(pfn)))
3194 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
3199 static bool page_fault_can_be_fast(u32 error_code)
3202 * Do not fix the mmio spte with invalid generation number which
3203 * need to be updated by slow page fault path.
3205 if (unlikely(error_code & PFERR_RSVD_MASK))
3208 /* See if the page fault is due to an NX violation */
3209 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3210 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3214 * #PF can be fast if:
3215 * 1. The shadow page table entry is not present, which could mean that
3216 * the fault is potentially caused by access tracking (if enabled).
3217 * 2. The shadow page table entry is present and the fault
3218 * is caused by write-protect, that means we just need change the W
3219 * bit of the spte which can be done out of mmu-lock.
3221 * However, if access tracking is disabled we know that a non-present
3222 * page must be a genuine page fault where we have to create a new SPTE.
3223 * So, if access tracking is disabled, we return true only for write
3224 * accesses to a present page.
3227 return shadow_acc_track_mask != 0 ||
3228 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3229 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3233 * Returns true if the SPTE was fixed successfully. Otherwise,
3234 * someone else modified the SPTE from its original value.
3237 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3238 u64 *sptep, u64 old_spte, u64 new_spte)
3242 WARN_ON(!sp->role.direct);
3245 * Theoretically we could also set dirty bit (and flush TLB) here in
3246 * order to eliminate unnecessary PML logging. See comments in
3247 * set_spte. But fast_page_fault is very unlikely to happen with PML
3248 * enabled, so we do not do this. This might result in the same GPA
3249 * to be logged in PML buffer again when the write really happens, and
3250 * eventually to be called by mark_page_dirty twice. But it's also no
3251 * harm. This also avoids the TLB flush needed after setting dirty bit
3252 * so non-PML cases won't be impacted.
3254 * Compare with set_spte where instead shadow_dirty_mask is set.
3256 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3259 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3261 * The gfn of direct spte is stable since it is
3262 * calculated by sp->gfn.
3264 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3265 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3271 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3273 if (fault_err_code & PFERR_FETCH_MASK)
3274 return is_executable_pte(spte);
3276 if (fault_err_code & PFERR_WRITE_MASK)
3277 return is_writable_pte(spte);
3279 /* Fault was on Read access */
3280 return spte & PT_PRESENT_MASK;
3285 * - true: let the vcpu to access on the same address again.
3286 * - false: let the real page fault path to fix it.
3288 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
3291 struct kvm_shadow_walk_iterator iterator;
3292 struct kvm_mmu_page *sp;
3293 bool fault_handled = false;
3295 uint retry_count = 0;
3297 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3300 if (!page_fault_can_be_fast(error_code))
3303 walk_shadow_page_lockless_begin(vcpu);
3308 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
3309 if (!is_shadow_present_pte(spte) ||
3310 iterator.level < level)
3313 sp = page_header(__pa(iterator.sptep));
3314 if (!is_last_spte(spte, sp->role.level))
3318 * Check whether the memory access that caused the fault would
3319 * still cause it if it were to be performed right now. If not,
3320 * then this is a spurious fault caused by TLB lazily flushed,
3321 * or some other CPU has already fixed the PTE after the
3322 * current CPU took the fault.
3324 * Need not check the access of upper level table entries since
3325 * they are always ACC_ALL.
3327 if (is_access_allowed(error_code, spte)) {
3328 fault_handled = true;
3334 if (is_access_track_spte(spte))
3335 new_spte = restore_acc_track_spte(new_spte);
3338 * Currently, to simplify the code, write-protection can
3339 * be removed in the fast path only if the SPTE was
3340 * write-protected for dirty-logging or access tracking.
3342 if ((error_code & PFERR_WRITE_MASK) &&
3343 spte_can_locklessly_be_made_writable(spte))
3345 new_spte |= PT_WRITABLE_MASK;
3348 * Do not fix write-permission on the large spte. Since
3349 * we only dirty the first page into the dirty-bitmap in
3350 * fast_pf_fix_direct_spte(), other pages are missed
3351 * if its slot has dirty logging enabled.
3353 * Instead, we let the slow page fault path create a
3354 * normal spte to fix the access.
3356 * See the comments in kvm_arch_commit_memory_region().
3358 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3362 /* Verify that the fault can be handled in the fast path */
3363 if (new_spte == spte ||
3364 !is_access_allowed(error_code, new_spte))
3368 * Currently, fast page fault only works for direct mapping
3369 * since the gfn is not stable for indirect shadow page. See
3370 * Documentation/virtual/kvm/locking.txt to get more detail.
3372 fault_handled = fast_pf_fix_direct_spte(vcpu, sp,
3373 iterator.sptep, spte,
3378 if (++retry_count > 4) {
3379 printk_once(KERN_WARNING
3380 "kvm: Fast #PF retrying more than 4 times.\n");
3386 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
3387 spte, fault_handled);
3388 walk_shadow_page_lockless_end(vcpu);
3390 return fault_handled;
3393 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3394 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable);
3395 static int make_mmu_pages_available(struct kvm_vcpu *vcpu);
3397 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
3398 gfn_t gfn, bool prefault)
3402 bool force_pt_level = false;
3404 unsigned long mmu_seq;
3405 bool map_writable, write = error_code & PFERR_WRITE_MASK;
3407 level = mapping_level(vcpu, gfn, &force_pt_level);
3408 if (likely(!force_pt_level)) {
3410 * This path builds a PAE pagetable - so we can map
3411 * 2mb pages at maximum. Therefore check if the level
3412 * is larger than that.
3414 if (level > PT_DIRECTORY_LEVEL)
3415 level = PT_DIRECTORY_LEVEL;
3417 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3420 if (fast_page_fault(vcpu, v, level, error_code))
3421 return RET_PF_RETRY;
3423 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3426 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3427 return RET_PF_RETRY;
3429 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3432 spin_lock(&vcpu->kvm->mmu_lock);
3433 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3435 if (make_mmu_pages_available(vcpu) < 0)
3437 if (likely(!force_pt_level))
3438 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3439 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3440 spin_unlock(&vcpu->kvm->mmu_lock);
3445 spin_unlock(&vcpu->kvm->mmu_lock);
3446 kvm_release_pfn_clean(pfn);
3447 return RET_PF_RETRY;
3450 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3451 struct list_head *invalid_list)
3453 struct kvm_mmu_page *sp;
3455 if (!VALID_PAGE(*root_hpa))
3458 sp = page_header(*root_hpa & PT64_BASE_ADDR_MASK);
3460 if (!sp->root_count && sp->role.invalid)
3461 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3463 *root_hpa = INVALID_PAGE;
3466 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3467 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, ulong roots_to_free)
3470 LIST_HEAD(invalid_list);
3471 struct kvm_mmu *mmu = &vcpu->arch.mmu;
3472 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3474 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3476 /* Before acquiring the MMU lock, see if we need to do any real work. */
3477 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3478 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3479 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3480 VALID_PAGE(mmu->prev_roots[i].hpa))
3483 if (i == KVM_MMU_NUM_PREV_ROOTS)
3487 spin_lock(&vcpu->kvm->mmu_lock);
3489 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3490 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3491 mmu_free_root_page(vcpu->kvm, &mmu->prev_roots[i].hpa,
3494 if (free_active_root) {
3495 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3496 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3497 mmu_free_root_page(vcpu->kvm, &mmu->root_hpa,
3500 for (i = 0; i < 4; ++i)
3501 if (mmu->pae_root[i] != 0)
3502 mmu_free_root_page(vcpu->kvm,
3505 mmu->root_hpa = INVALID_PAGE;
3509 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3510 spin_unlock(&vcpu->kvm->mmu_lock);
3512 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3514 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3518 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3519 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3526 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3528 struct kvm_mmu_page *sp;
3531 if (vcpu->arch.mmu.shadow_root_level >= PT64_ROOT_4LEVEL) {
3532 spin_lock(&vcpu->kvm->mmu_lock);
3533 if(make_mmu_pages_available(vcpu) < 0) {
3534 spin_unlock(&vcpu->kvm->mmu_lock);
3537 sp = kvm_mmu_get_page(vcpu, 0, 0,
3538 vcpu->arch.mmu.shadow_root_level, 1, ACC_ALL);
3540 spin_unlock(&vcpu->kvm->mmu_lock);
3541 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3542 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3543 for (i = 0; i < 4; ++i) {
3544 hpa_t root = vcpu->arch.mmu.pae_root[i];
3546 MMU_WARN_ON(VALID_PAGE(root));
3547 spin_lock(&vcpu->kvm->mmu_lock);
3548 if (make_mmu_pages_available(vcpu) < 0) {
3549 spin_unlock(&vcpu->kvm->mmu_lock);
3552 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3553 i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3554 root = __pa(sp->spt);
3556 spin_unlock(&vcpu->kvm->mmu_lock);
3557 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3559 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3566 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3568 struct kvm_mmu_page *sp;
3573 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3575 if (mmu_check_root(vcpu, root_gfn))
3579 * Do we shadow a long mode page table? If so we need to
3580 * write-protect the guests page table root.
3582 if (vcpu->arch.mmu.root_level >= PT64_ROOT_4LEVEL) {
3583 hpa_t root = vcpu->arch.mmu.root_hpa;
3585 MMU_WARN_ON(VALID_PAGE(root));
3587 spin_lock(&vcpu->kvm->mmu_lock);
3588 if (make_mmu_pages_available(vcpu) < 0) {
3589 spin_unlock(&vcpu->kvm->mmu_lock);
3592 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
3593 vcpu->arch.mmu.shadow_root_level, 0, ACC_ALL);
3594 root = __pa(sp->spt);
3596 spin_unlock(&vcpu->kvm->mmu_lock);
3597 vcpu->arch.mmu.root_hpa = root;
3602 * We shadow a 32 bit page table. This may be a legacy 2-level
3603 * or a PAE 3-level page table. In either case we need to be aware that
3604 * the shadow page table may be a PAE or a long mode page table.
3606 pm_mask = PT_PRESENT_MASK;
3607 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_4LEVEL)
3608 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3610 for (i = 0; i < 4; ++i) {
3611 hpa_t root = vcpu->arch.mmu.pae_root[i];
3613 MMU_WARN_ON(VALID_PAGE(root));
3614 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3615 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3616 if (!(pdptr & PT_PRESENT_MASK)) {
3617 vcpu->arch.mmu.pae_root[i] = 0;
3620 root_gfn = pdptr >> PAGE_SHIFT;
3621 if (mmu_check_root(vcpu, root_gfn))
3624 spin_lock(&vcpu->kvm->mmu_lock);
3625 if (make_mmu_pages_available(vcpu) < 0) {
3626 spin_unlock(&vcpu->kvm->mmu_lock);
3629 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3631 root = __pa(sp->spt);
3633 spin_unlock(&vcpu->kvm->mmu_lock);
3635 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3637 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3640 * If we shadow a 32 bit page table with a long mode page
3641 * table we enter this path.
3643 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_4LEVEL) {
3644 if (vcpu->arch.mmu.lm_root == NULL) {
3646 * The additional page necessary for this is only
3647 * allocated on demand.
3652 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3653 if (lm_root == NULL)
3656 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3658 vcpu->arch.mmu.lm_root = lm_root;
3661 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3667 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3669 if (vcpu->arch.mmu.direct_map)
3670 return mmu_alloc_direct_roots(vcpu);
3672 return mmu_alloc_shadow_roots(vcpu);
3675 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3678 struct kvm_mmu_page *sp;
3680 if (vcpu->arch.mmu.direct_map)
3683 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3686 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3688 if (vcpu->arch.mmu.root_level >= PT64_ROOT_4LEVEL) {
3689 hpa_t root = vcpu->arch.mmu.root_hpa;
3691 sp = page_header(root);
3694 * Even if another CPU was marking the SP as unsync-ed
3695 * simultaneously, any guest page table changes are not
3696 * guaranteed to be visible anyway until this VCPU issues a TLB
3697 * flush strictly after those changes are made. We only need to
3698 * ensure that the other CPU sets these flags before any actual
3699 * changes to the page tables are made. The comments in
3700 * mmu_need_write_protect() describe what could go wrong if this
3701 * requirement isn't satisfied.
3703 if (!smp_load_acquire(&sp->unsync) &&
3704 !smp_load_acquire(&sp->unsync_children))
3707 spin_lock(&vcpu->kvm->mmu_lock);
3708 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3710 mmu_sync_children(vcpu, sp);
3712 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3713 spin_unlock(&vcpu->kvm->mmu_lock);
3717 spin_lock(&vcpu->kvm->mmu_lock);
3718 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3720 for (i = 0; i < 4; ++i) {
3721 hpa_t root = vcpu->arch.mmu.pae_root[i];
3723 if (root && VALID_PAGE(root)) {
3724 root &= PT64_BASE_ADDR_MASK;
3725 sp = page_header(root);
3726 mmu_sync_children(vcpu, sp);
3730 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3731 spin_unlock(&vcpu->kvm->mmu_lock);
3733 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3735 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3736 u32 access, struct x86_exception *exception)
3739 exception->error_code = 0;
3743 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3745 struct x86_exception *exception)
3748 exception->error_code = 0;
3749 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3753 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3755 int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3757 return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3758 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3761 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3763 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3766 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3768 return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3771 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3774 * A nested guest cannot use the MMIO cache if it is using nested
3775 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3777 if (mmu_is_nested(vcpu))
3781 return vcpu_match_mmio_gpa(vcpu, addr);
3783 return vcpu_match_mmio_gva(vcpu, addr);
3786 /* return true if reserved bit is detected on spte. */
3788 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3790 struct kvm_shadow_walk_iterator iterator;
3791 u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull;
3793 bool reserved = false;
3795 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3798 walk_shadow_page_lockless_begin(vcpu);
3800 for (shadow_walk_init(&iterator, vcpu, addr),
3801 leaf = root = iterator.level;
3802 shadow_walk_okay(&iterator);
3803 __shadow_walk_next(&iterator, spte)) {
3804 spte = mmu_spte_get_lockless(iterator.sptep);
3806 sptes[leaf - 1] = spte;
3809 if (!is_shadow_present_pte(spte))
3812 reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte,
3816 walk_shadow_page_lockless_end(vcpu);
3819 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3821 while (root > leaf) {
3822 pr_err("------ spte 0x%llx level %d.\n",
3823 sptes[root - 1], root);
3832 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3837 if (mmio_info_in_cache(vcpu, addr, direct))
3838 return RET_PF_EMULATE;
3840 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3841 if (WARN_ON(reserved))
3844 if (is_mmio_spte(spte)) {
3845 gfn_t gfn = get_mmio_spte_gfn(spte);
3846 unsigned access = get_mmio_spte_access(spte);
3848 if (!check_mmio_spte(vcpu, spte))
3849 return RET_PF_INVALID;
3854 trace_handle_mmio_page_fault(addr, gfn, access);
3855 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3856 return RET_PF_EMULATE;
3860 * If the page table is zapped by other cpus, let CPU fault again on
3863 return RET_PF_RETRY;
3866 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3867 u32 error_code, gfn_t gfn)
3869 if (unlikely(error_code & PFERR_RSVD_MASK))
3872 if (!(error_code & PFERR_PRESENT_MASK) ||
3873 !(error_code & PFERR_WRITE_MASK))
3877 * guest is writing the page which is write tracked which can
3878 * not be fixed by page fault handler.
3880 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3886 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3888 struct kvm_shadow_walk_iterator iterator;
3891 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3894 walk_shadow_page_lockless_begin(vcpu);
3895 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3896 clear_sp_write_flooding_count(iterator.sptep);
3897 if (!is_shadow_present_pte(spte))
3900 walk_shadow_page_lockless_end(vcpu);
3903 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3904 u32 error_code, bool prefault)
3906 gfn_t gfn = gva >> PAGE_SHIFT;
3909 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3911 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3912 return RET_PF_EMULATE;
3914 r = mmu_topup_memory_caches(vcpu);
3918 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3921 return nonpaging_map(vcpu, gva & PAGE_MASK,
3922 error_code, gfn, prefault);
3925 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3927 struct kvm_arch_async_pf arch;
3929 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3931 arch.direct_map = vcpu->arch.mmu.direct_map;
3932 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3934 return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3937 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
3939 if (unlikely(!lapic_in_kernel(vcpu) ||
3940 kvm_event_needs_reinjection(vcpu) ||
3941 vcpu->arch.exception.pending))
3944 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
3947 return kvm_x86_ops->interrupt_allowed(vcpu);
3950 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3951 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable)
3953 struct kvm_memory_slot *slot;
3957 * Don't expose private memslots to L2.
3959 if (is_guest_mode(vcpu) && !kvm_is_visible_gfn(vcpu->kvm, gfn)) {
3960 *pfn = KVM_PFN_NOSLOT;
3964 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3966 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3968 return false; /* *pfn has correct page already */
3970 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3971 trace_kvm_try_async_get_page(gva, gfn);
3972 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3973 trace_kvm_async_pf_doublefault(gva, gfn);
3974 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3976 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3980 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3984 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3985 u64 fault_address, char *insn, int insn_len)
3989 vcpu->arch.l1tf_flush_l1d = true;
3990 switch (vcpu->arch.apf.host_apf_reason) {
3992 trace_kvm_page_fault(fault_address, error_code);
3994 if (kvm_event_needs_reinjection(vcpu))
3995 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3996 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3999 case KVM_PV_REASON_PAGE_NOT_PRESENT:
4000 vcpu->arch.apf.host_apf_reason = 0;
4001 local_irq_disable();
4002 kvm_async_pf_task_wait(fault_address, 0);
4005 case KVM_PV_REASON_PAGE_READY:
4006 vcpu->arch.apf.host_apf_reason = 0;
4007 local_irq_disable();
4008 kvm_async_pf_task_wake(fault_address);
4014 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
4017 check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
4019 int page_num = KVM_PAGES_PER_HPAGE(level);
4021 gfn &= ~(page_num - 1);
4023 return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
4026 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
4032 bool force_pt_level;
4033 gfn_t gfn = gpa >> PAGE_SHIFT;
4034 unsigned long mmu_seq;
4035 int write = error_code & PFERR_WRITE_MASK;
4038 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
4040 if (page_fault_handle_page_track(vcpu, error_code, gfn))
4041 return RET_PF_EMULATE;
4043 r = mmu_topup_memory_caches(vcpu);
4047 force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn,
4048 PT_DIRECTORY_LEVEL);
4049 level = mapping_level(vcpu, gfn, &force_pt_level);
4050 if (likely(!force_pt_level)) {
4051 if (level > PT_DIRECTORY_LEVEL &&
4052 !check_hugepage_cache_consistency(vcpu, gfn, level))
4053 level = PT_DIRECTORY_LEVEL;
4054 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
4057 if (fast_page_fault(vcpu, gpa, level, error_code))
4058 return RET_PF_RETRY;
4060 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4063 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
4064 return RET_PF_RETRY;
4066 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
4069 spin_lock(&vcpu->kvm->mmu_lock);
4070 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
4072 if (make_mmu_pages_available(vcpu) < 0)
4074 if (likely(!force_pt_level))
4075 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
4076 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
4077 spin_unlock(&vcpu->kvm->mmu_lock);
4082 spin_unlock(&vcpu->kvm->mmu_lock);
4083 kvm_release_pfn_clean(pfn);
4084 return RET_PF_RETRY;
4087 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
4088 struct kvm_mmu *context)
4090 context->page_fault = nonpaging_page_fault;
4091 context->gva_to_gpa = nonpaging_gva_to_gpa;
4092 context->sync_page = nonpaging_sync_page;
4093 context->invlpg = nonpaging_invlpg;
4094 context->update_pte = nonpaging_update_pte;
4095 context->root_level = 0;
4096 context->shadow_root_level = PT32E_ROOT_LEVEL;
4097 context->direct_map = true;
4098 context->nx = false;
4102 * Find out if a previously cached root matching the new CR3/role is available.
4103 * The current root is also inserted into the cache.
4104 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
4106 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
4107 * false is returned. This root should now be freed by the caller.
4109 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4110 union kvm_mmu_page_role new_role)
4113 struct kvm_mmu_root_info root;
4114 struct kvm_mmu *mmu = &vcpu->arch.mmu;
4116 root.cr3 = mmu->get_cr3(vcpu);
4117 root.hpa = mmu->root_hpa;
4119 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
4120 swap(root, mmu->prev_roots[i]);
4122 if (new_cr3 == root.cr3 && VALID_PAGE(root.hpa) &&
4123 page_header(root.hpa) != NULL &&
4124 new_role.word == page_header(root.hpa)->role.word)
4128 mmu->root_hpa = root.hpa;
4130 return i < KVM_MMU_NUM_PREV_ROOTS;
4133 static bool fast_cr3_switch(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4134 union kvm_mmu_page_role new_role,
4135 bool skip_tlb_flush)
4137 struct kvm_mmu *mmu = &vcpu->arch.mmu;
4140 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4141 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4142 * later if necessary.
4144 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
4145 mmu->root_level >= PT64_ROOT_4LEVEL) {
4146 if (mmu_check_root(vcpu, new_cr3 >> PAGE_SHIFT))
4149 if (cached_root_available(vcpu, new_cr3, new_role)) {
4151 * It is possible that the cached previous root page is
4152 * obsolete because of a change in the MMU
4153 * generation number. However, that is accompanied by
4154 * KVM_REQ_MMU_RELOAD, which will free the root that we
4155 * have set here and allocate a new one.
4158 kvm_make_request(KVM_REQ_LOAD_CR3, vcpu);
4159 if (!skip_tlb_flush) {
4160 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
4161 kvm_x86_ops->tlb_flush(vcpu, true);
4165 * The last MMIO access's GVA and GPA are cached in the
4166 * VCPU. When switching to a new CR3, that GVA->GPA
4167 * mapping may no longer be valid. So clear any cached
4168 * MMIO info even when we don't need to sync the shadow
4171 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4173 __clear_sp_write_flooding_count(
4174 page_header(mmu->root_hpa));
4183 static void __kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4184 union kvm_mmu_page_role new_role,
4185 bool skip_tlb_flush)
4187 if (!fast_cr3_switch(vcpu, new_cr3, new_role, skip_tlb_flush))
4188 kvm_mmu_free_roots(vcpu, KVM_MMU_ROOT_CURRENT);
4191 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush)
4193 __kvm_mmu_new_cr3(vcpu, new_cr3, kvm_mmu_calc_root_page_role(vcpu),
4196 EXPORT_SYMBOL_GPL(kvm_mmu_new_cr3);
4198 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4200 return kvm_read_cr3(vcpu);
4203 static void inject_page_fault(struct kvm_vcpu *vcpu,
4204 struct x86_exception *fault)
4206 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
4209 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4210 unsigned access, int *nr_present)
4212 if (unlikely(is_mmio_spte(*sptep))) {
4213 if (gfn != get_mmio_spte_gfn(*sptep)) {
4214 mmu_spte_clear_no_track(sptep);
4219 mark_mmio_spte(vcpu, sptep, gfn, access);
4226 static inline bool is_last_gpte(struct kvm_mmu *mmu,
4227 unsigned level, unsigned gpte)
4230 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
4231 * If it is clear, there are no large pages at this level, so clear
4232 * PT_PAGE_SIZE_MASK in gpte if that is the case.
4234 gpte &= level - mmu->last_nonleaf_level;
4237 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
4238 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
4239 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
4241 gpte |= level - PT_PAGE_TABLE_LEVEL - 1;
4243 return gpte & PT_PAGE_SIZE_MASK;
4246 #define PTTYPE_EPT 18 /* arbitrary */
4247 #define PTTYPE PTTYPE_EPT
4248 #include "paging_tmpl.h"
4252 #include "paging_tmpl.h"
4256 #include "paging_tmpl.h"
4260 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4261 struct rsvd_bits_validate *rsvd_check,
4262 int maxphyaddr, int level, bool nx, bool gbpages,
4265 u64 exb_bit_rsvd = 0;
4266 u64 gbpages_bit_rsvd = 0;
4267 u64 nonleaf_bit8_rsvd = 0;
4269 rsvd_check->bad_mt_xwr = 0;
4272 exb_bit_rsvd = rsvd_bits(63, 63);
4274 gbpages_bit_rsvd = rsvd_bits(7, 7);
4277 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4278 * leaf entries) on AMD CPUs only.
4281 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4284 case PT32_ROOT_LEVEL:
4285 /* no rsvd bits for 2 level 4K page table entries */
4286 rsvd_check->rsvd_bits_mask[0][1] = 0;
4287 rsvd_check->rsvd_bits_mask[0][0] = 0;
4288 rsvd_check->rsvd_bits_mask[1][0] =
4289 rsvd_check->rsvd_bits_mask[0][0];
4292 rsvd_check->rsvd_bits_mask[1][1] = 0;
4296 if (is_cpuid_PSE36())
4297 /* 36bits PSE 4MB page */
4298 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4300 /* 32 bits PSE 4MB page */
4301 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4303 case PT32E_ROOT_LEVEL:
4304 rsvd_check->rsvd_bits_mask[0][2] =
4305 rsvd_bits(maxphyaddr, 63) |
4306 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
4307 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4308 rsvd_bits(maxphyaddr, 62); /* PDE */
4309 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4310 rsvd_bits(maxphyaddr, 62); /* PTE */
4311 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4312 rsvd_bits(maxphyaddr, 62) |
4313 rsvd_bits(13, 20); /* large page */
4314 rsvd_check->rsvd_bits_mask[1][0] =
4315 rsvd_check->rsvd_bits_mask[0][0];
4317 case PT64_ROOT_5LEVEL:
4318 rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd |
4319 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4320 rsvd_bits(maxphyaddr, 51);
4321 rsvd_check->rsvd_bits_mask[1][4] =
4322 rsvd_check->rsvd_bits_mask[0][4];
4323 case PT64_ROOT_4LEVEL:
4324 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
4325 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4326 rsvd_bits(maxphyaddr, 51);
4327 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
4328 nonleaf_bit8_rsvd | gbpages_bit_rsvd |
4329 rsvd_bits(maxphyaddr, 51);
4330 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4331 rsvd_bits(maxphyaddr, 51);
4332 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4333 rsvd_bits(maxphyaddr, 51);
4334 rsvd_check->rsvd_bits_mask[1][3] =
4335 rsvd_check->rsvd_bits_mask[0][3];
4336 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
4337 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
4339 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4340 rsvd_bits(maxphyaddr, 51) |
4341 rsvd_bits(13, 20); /* large page */
4342 rsvd_check->rsvd_bits_mask[1][0] =
4343 rsvd_check->rsvd_bits_mask[0][0];
4348 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4349 struct kvm_mmu *context)
4351 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4352 cpuid_maxphyaddr(vcpu), context->root_level,
4354 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4355 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
4359 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4360 int maxphyaddr, bool execonly)
4364 rsvd_check->rsvd_bits_mask[0][4] =
4365 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4366 rsvd_check->rsvd_bits_mask[0][3] =
4367 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4368 rsvd_check->rsvd_bits_mask[0][2] =
4369 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4370 rsvd_check->rsvd_bits_mask[0][1] =
4371 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4372 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
4375 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4376 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4377 rsvd_check->rsvd_bits_mask[1][2] =
4378 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
4379 rsvd_check->rsvd_bits_mask[1][1] =
4380 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
4381 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4383 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4384 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4385 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4386 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4387 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4389 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4390 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4392 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4395 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4396 struct kvm_mmu *context, bool execonly)
4398 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4399 cpuid_maxphyaddr(vcpu), execonly);
4403 * the page table on host is the shadow page table for the page
4404 * table in guest or amd nested guest, its mmu features completely
4405 * follow the features in guest.
4408 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4410 bool uses_nx = context->nx || context->base_role.smep_andnot_wp;
4411 struct rsvd_bits_validate *shadow_zero_check;
4415 * Passing "true" to the last argument is okay; it adds a check
4416 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4418 shadow_zero_check = &context->shadow_zero_check;
4419 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4420 boot_cpu_data.x86_phys_bits,
4421 context->shadow_root_level, uses_nx,
4422 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4423 is_pse(vcpu), true);
4425 if (!shadow_me_mask)
4428 for (i = context->shadow_root_level; --i >= 0;) {
4429 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4430 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4434 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4436 static inline bool boot_cpu_is_amd(void)
4438 WARN_ON_ONCE(!tdp_enabled);
4439 return shadow_x_mask == 0;
4443 * the direct page table on host, use as much mmu features as
4444 * possible, however, kvm currently does not do execution-protection.
4447 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4448 struct kvm_mmu *context)
4450 struct rsvd_bits_validate *shadow_zero_check;
4453 shadow_zero_check = &context->shadow_zero_check;
4455 if (boot_cpu_is_amd())
4456 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4457 boot_cpu_data.x86_phys_bits,
4458 context->shadow_root_level, false,
4459 boot_cpu_has(X86_FEATURE_GBPAGES),
4462 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4463 boot_cpu_data.x86_phys_bits,
4466 if (!shadow_me_mask)
4469 for (i = context->shadow_root_level; --i >= 0;) {
4470 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4471 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4476 * as the comments in reset_shadow_zero_bits_mask() except it
4477 * is the shadow page table for intel nested guest.
4480 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4481 struct kvm_mmu *context, bool execonly)
4483 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4484 boot_cpu_data.x86_phys_bits, execonly);
4487 #define BYTE_MASK(access) \
4488 ((1 & (access) ? 2 : 0) | \
4489 (2 & (access) ? 4 : 0) | \
4490 (3 & (access) ? 8 : 0) | \
4491 (4 & (access) ? 16 : 0) | \
4492 (5 & (access) ? 32 : 0) | \
4493 (6 & (access) ? 64 : 0) | \
4494 (7 & (access) ? 128 : 0))
4497 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4498 struct kvm_mmu *mmu, bool ept)
4502 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4503 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4504 const u8 u = BYTE_MASK(ACC_USER_MASK);
4506 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4507 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4508 bool cr0_wp = is_write_protection(vcpu);
4510 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4511 unsigned pfec = byte << 1;
4514 * Each "*f" variable has a 1 bit for each UWX value
4515 * that causes a fault with the given PFEC.
4518 /* Faults from writes to non-writable pages */
4519 u8 wf = (pfec & PFERR_WRITE_MASK) ? ~w : 0;
4520 /* Faults from user mode accesses to supervisor pages */
4521 u8 uf = (pfec & PFERR_USER_MASK) ? ~u : 0;
4522 /* Faults from fetches of non-executable pages*/
4523 u8 ff = (pfec & PFERR_FETCH_MASK) ? ~x : 0;
4524 /* Faults from kernel mode fetches of user pages */
4526 /* Faults from kernel mode accesses of user pages */
4530 /* Faults from kernel mode accesses to user pages */
4531 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4533 /* Not really needed: !nx will cause pte.nx to fault */
4537 /* Allow supervisor writes if !cr0.wp */
4539 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4541 /* Disallow supervisor fetches of user code if cr4.smep */
4543 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4546 * SMAP:kernel-mode data accesses from user-mode
4547 * mappings should fault. A fault is considered
4548 * as a SMAP violation if all of the following
4549 * conditions are ture:
4550 * - X86_CR4_SMAP is set in CR4
4551 * - A user page is accessed
4552 * - The access is not a fetch
4553 * - Page fault in kernel mode
4554 * - if CPL = 3 or X86_EFLAGS_AC is clear
4556 * Here, we cover the first three conditions.
4557 * The fourth is computed dynamically in permission_fault();
4558 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4559 * *not* subject to SMAP restrictions.
4562 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4565 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4570 * PKU is an additional mechanism by which the paging controls access to
4571 * user-mode addresses based on the value in the PKRU register. Protection
4572 * key violations are reported through a bit in the page fault error code.
4573 * Unlike other bits of the error code, the PK bit is not known at the
4574 * call site of e.g. gva_to_gpa; it must be computed directly in
4575 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4576 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4578 * In particular the following conditions come from the error code, the
4579 * page tables and the machine state:
4580 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4581 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4582 * - PK is always zero if U=0 in the page tables
4583 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4585 * The PKRU bitmask caches the result of these four conditions. The error
4586 * code (minus the P bit) and the page table's U bit form an index into the
4587 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4588 * with the two bits of the PKRU register corresponding to the protection key.
4589 * For the first three conditions above the bits will be 00, thus masking
4590 * away both AD and WD. For all reads or if the last condition holds, WD
4591 * only will be masked away.
4593 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4604 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4605 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4610 wp = is_write_protection(vcpu);
4612 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4613 unsigned pfec, pkey_bits;
4614 bool check_pkey, check_write, ff, uf, wf, pte_user;
4617 ff = pfec & PFERR_FETCH_MASK;
4618 uf = pfec & PFERR_USER_MASK;
4619 wf = pfec & PFERR_WRITE_MASK;
4621 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4622 pte_user = pfec & PFERR_RSVD_MASK;
4625 * Only need to check the access which is not an
4626 * instruction fetch and is to a user page.
4628 check_pkey = (!ff && pte_user);
4630 * write access is controlled by PKRU if it is a
4631 * user access or CR0.WP = 1.
4633 check_write = check_pkey && wf && (uf || wp);
4635 /* PKRU.AD stops both read and write access. */
4636 pkey_bits = !!check_pkey;
4637 /* PKRU.WD stops write access. */
4638 pkey_bits |= (!!check_write) << 1;
4640 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4644 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4646 unsigned root_level = mmu->root_level;
4648 mmu->last_nonleaf_level = root_level;
4649 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4650 mmu->last_nonleaf_level++;
4653 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4654 struct kvm_mmu *context,
4657 context->nx = is_nx(vcpu);
4658 context->root_level = level;
4660 reset_rsvds_bits_mask(vcpu, context);
4661 update_permission_bitmask(vcpu, context, false);
4662 update_pkru_bitmask(vcpu, context, false);
4663 update_last_nonleaf_level(vcpu, context);
4665 MMU_WARN_ON(!is_pae(vcpu));
4666 context->page_fault = paging64_page_fault;
4667 context->gva_to_gpa = paging64_gva_to_gpa;
4668 context->sync_page = paging64_sync_page;
4669 context->invlpg = paging64_invlpg;
4670 context->update_pte = paging64_update_pte;
4671 context->shadow_root_level = level;
4672 context->direct_map = false;
4675 static void paging64_init_context(struct kvm_vcpu *vcpu,
4676 struct kvm_mmu *context)
4678 int root_level = is_la57_mode(vcpu) ?
4679 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4681 paging64_init_context_common(vcpu, context, root_level);
4684 static void paging32_init_context(struct kvm_vcpu *vcpu,
4685 struct kvm_mmu *context)
4687 context->nx = false;
4688 context->root_level = PT32_ROOT_LEVEL;
4690 reset_rsvds_bits_mask(vcpu, context);
4691 update_permission_bitmask(vcpu, context, false);
4692 update_pkru_bitmask(vcpu, context, false);
4693 update_last_nonleaf_level(vcpu, context);
4695 context->page_fault = paging32_page_fault;
4696 context->gva_to_gpa = paging32_gva_to_gpa;
4697 context->sync_page = paging32_sync_page;
4698 context->invlpg = paging32_invlpg;
4699 context->update_pte = paging32_update_pte;
4700 context->shadow_root_level = PT32E_ROOT_LEVEL;
4701 context->direct_map = false;
4704 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4705 struct kvm_mmu *context)
4707 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4710 static union kvm_mmu_page_role
4711 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu)
4713 union kvm_mmu_page_role role = {0};
4715 role.guest_mode = is_guest_mode(vcpu);
4716 role.smm = is_smm(vcpu);
4717 role.ad_disabled = (shadow_accessed_mask == 0);
4718 role.level = kvm_x86_ops->get_tdp_level(vcpu);
4720 role.access = ACC_ALL;
4725 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4727 struct kvm_mmu *context = &vcpu->arch.mmu;
4729 context->base_role.word = mmu_base_role_mask.word &
4730 kvm_calc_tdp_mmu_root_page_role(vcpu).word;
4731 context->page_fault = tdp_page_fault;
4732 context->sync_page = nonpaging_sync_page;
4733 context->invlpg = nonpaging_invlpg;
4734 context->update_pte = nonpaging_update_pte;
4735 context->shadow_root_level = kvm_x86_ops->get_tdp_level(vcpu);
4736 context->direct_map = true;
4737 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
4738 context->get_cr3 = get_cr3;
4739 context->get_pdptr = kvm_pdptr_read;
4740 context->inject_page_fault = kvm_inject_page_fault;
4742 if (!is_paging(vcpu)) {
4743 context->nx = false;
4744 context->gva_to_gpa = nonpaging_gva_to_gpa;
4745 context->root_level = 0;
4746 } else if (is_long_mode(vcpu)) {
4747 context->nx = is_nx(vcpu);
4748 context->root_level = is_la57_mode(vcpu) ?
4749 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4750 reset_rsvds_bits_mask(vcpu, context);
4751 context->gva_to_gpa = paging64_gva_to_gpa;
4752 } else if (is_pae(vcpu)) {
4753 context->nx = is_nx(vcpu);
4754 context->root_level = PT32E_ROOT_LEVEL;
4755 reset_rsvds_bits_mask(vcpu, context);
4756 context->gva_to_gpa = paging64_gva_to_gpa;
4758 context->nx = false;
4759 context->root_level = PT32_ROOT_LEVEL;
4760 reset_rsvds_bits_mask(vcpu, context);
4761 context->gva_to_gpa = paging32_gva_to_gpa;
4764 update_permission_bitmask(vcpu, context, false);
4765 update_pkru_bitmask(vcpu, context, false);
4766 update_last_nonleaf_level(vcpu, context);
4767 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4770 static union kvm_mmu_page_role
4771 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu)
4773 union kvm_mmu_page_role role = {0};
4774 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4775 bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4777 role.nxe = is_nx(vcpu);
4778 role.cr4_pae = !!is_pae(vcpu);
4779 role.cr0_wp = is_write_protection(vcpu);
4780 role.smep_andnot_wp = smep && !is_write_protection(vcpu);
4781 role.smap_andnot_wp = smap && !is_write_protection(vcpu);
4782 role.guest_mode = is_guest_mode(vcpu);
4783 role.smm = is_smm(vcpu);
4784 role.direct = !is_paging(vcpu);
4785 role.access = ACC_ALL;
4787 if (!is_long_mode(vcpu))
4788 role.level = PT32E_ROOT_LEVEL;
4789 else if (is_la57_mode(vcpu))
4790 role.level = PT64_ROOT_5LEVEL;
4792 role.level = PT64_ROOT_4LEVEL;
4797 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
4799 struct kvm_mmu *context = &vcpu->arch.mmu;
4801 if (!is_paging(vcpu))
4802 nonpaging_init_context(vcpu, context);
4803 else if (is_long_mode(vcpu))
4804 paging64_init_context(vcpu, context);
4805 else if (is_pae(vcpu))
4806 paging32E_init_context(vcpu, context);
4808 paging32_init_context(vcpu, context);
4810 context->base_role.word = mmu_base_role_mask.word &
4811 kvm_calc_shadow_mmu_root_page_role(vcpu).word;
4812 reset_shadow_zero_bits_mask(vcpu, context);
4814 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4816 static union kvm_mmu_page_role
4817 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty)
4819 union kvm_mmu_page_role role = vcpu->arch.mmu.base_role;
4821 role.level = PT64_ROOT_4LEVEL;
4822 role.direct = false;
4823 role.ad_disabled = !accessed_dirty;
4824 role.guest_mode = true;
4825 role.access = ACC_ALL;
4830 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4831 bool accessed_dirty, gpa_t new_eptp)
4833 struct kvm_mmu *context = &vcpu->arch.mmu;
4834 union kvm_mmu_page_role root_page_role =
4835 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty);
4837 __kvm_mmu_new_cr3(vcpu, new_eptp, root_page_role, false);
4838 context->shadow_root_level = PT64_ROOT_4LEVEL;
4841 context->ept_ad = accessed_dirty;
4842 context->page_fault = ept_page_fault;
4843 context->gva_to_gpa = ept_gva_to_gpa;
4844 context->sync_page = ept_sync_page;
4845 context->invlpg = ept_invlpg;
4846 context->update_pte = ept_update_pte;
4847 context->root_level = PT64_ROOT_4LEVEL;
4848 context->direct_map = false;
4849 context->base_role.word = root_page_role.word & mmu_base_role_mask.word;
4850 update_permission_bitmask(vcpu, context, true);
4851 update_pkru_bitmask(vcpu, context, true);
4852 update_last_nonleaf_level(vcpu, context);
4853 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4854 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4856 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4858 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4860 struct kvm_mmu *context = &vcpu->arch.mmu;
4862 kvm_init_shadow_mmu(vcpu);
4863 context->set_cr3 = kvm_x86_ops->set_cr3;
4864 context->get_cr3 = get_cr3;
4865 context->get_pdptr = kvm_pdptr_read;
4866 context->inject_page_fault = kvm_inject_page_fault;
4869 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4871 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4873 g_context->get_cr3 = get_cr3;
4874 g_context->get_pdptr = kvm_pdptr_read;
4875 g_context->inject_page_fault = kvm_inject_page_fault;
4878 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4879 * L1's nested page tables (e.g. EPT12). The nested translation
4880 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4881 * L2's page tables as the first level of translation and L1's
4882 * nested page tables as the second level of translation. Basically
4883 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4885 if (!is_paging(vcpu)) {
4886 g_context->nx = false;
4887 g_context->root_level = 0;
4888 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4889 } else if (is_long_mode(vcpu)) {
4890 g_context->nx = is_nx(vcpu);
4891 g_context->root_level = is_la57_mode(vcpu) ?
4892 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4893 reset_rsvds_bits_mask(vcpu, g_context);
4894 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4895 } else if (is_pae(vcpu)) {
4896 g_context->nx = is_nx(vcpu);
4897 g_context->root_level = PT32E_ROOT_LEVEL;
4898 reset_rsvds_bits_mask(vcpu, g_context);
4899 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4901 g_context->nx = false;
4902 g_context->root_level = PT32_ROOT_LEVEL;
4903 reset_rsvds_bits_mask(vcpu, g_context);
4904 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4907 update_permission_bitmask(vcpu, g_context, false);
4908 update_pkru_bitmask(vcpu, g_context, false);
4909 update_last_nonleaf_level(vcpu, g_context);
4912 void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots)
4917 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4919 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
4920 vcpu->arch.mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
4923 if (mmu_is_nested(vcpu))
4924 init_kvm_nested_mmu(vcpu);
4925 else if (tdp_enabled)
4926 init_kvm_tdp_mmu(vcpu);
4928 init_kvm_softmmu(vcpu);
4930 EXPORT_SYMBOL_GPL(kvm_init_mmu);
4932 static union kvm_mmu_page_role
4933 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
4936 return kvm_calc_tdp_mmu_root_page_role(vcpu);
4938 return kvm_calc_shadow_mmu_root_page_role(vcpu);
4941 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4943 kvm_mmu_unload(vcpu);
4944 kvm_init_mmu(vcpu, true);
4946 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4948 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4952 r = mmu_topup_memory_caches(vcpu);
4955 r = mmu_alloc_roots(vcpu);
4956 kvm_mmu_sync_roots(vcpu);
4959 kvm_mmu_load_cr3(vcpu);
4960 kvm_x86_ops->tlb_flush(vcpu, true);
4964 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4966 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4968 kvm_mmu_free_roots(vcpu, KVM_MMU_ROOTS_ALL);
4969 WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4971 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4973 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4974 struct kvm_mmu_page *sp, u64 *spte,
4977 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
4978 ++vcpu->kvm->stat.mmu_pde_zapped;
4982 ++vcpu->kvm->stat.mmu_pte_updated;
4983 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
4986 static bool need_remote_flush(u64 old, u64 new)
4988 if (!is_shadow_present_pte(old))
4990 if (!is_shadow_present_pte(new))
4992 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4994 old ^= shadow_nx_mask;
4995 new ^= shadow_nx_mask;
4996 return (old & ~new & PT64_PERM_MASK) != 0;
4999 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
5000 const u8 *new, int *bytes)
5006 * Assume that the pte write on a page table of the same type
5007 * as the current vcpu paging mode since we update the sptes only
5008 * when they have the same mode.
5010 if (is_pae(vcpu) && *bytes == 4) {
5011 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
5014 r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8);
5017 new = (const u8 *)&gentry;
5022 gentry = *(const u32 *)new;
5025 gentry = *(const u64 *)new;
5036 * If we're seeing too many writes to a page, it may no longer be a page table,
5037 * or we may be forking, in which case it is better to unmap the page.
5039 static bool detect_write_flooding(struct kvm_mmu_page *sp)
5042 * Skip write-flooding detected for the sp whose level is 1, because
5043 * it can become unsync, then the guest page is not write-protected.
5045 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
5048 atomic_inc(&sp->write_flooding_count);
5049 return atomic_read(&sp->write_flooding_count) >= 3;
5053 * Misaligned accesses are too much trouble to fix up; also, they usually
5054 * indicate a page is not used as a page table.
5056 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5059 unsigned offset, pte_size, misaligned;
5061 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5062 gpa, bytes, sp->role.word);
5064 offset = offset_in_page(gpa);
5065 pte_size = sp->role.cr4_pae ? 8 : 4;
5068 * Sometimes, the OS only writes the last one bytes to update status
5069 * bits, for example, in linux, andb instruction is used in clear_bit().
5071 if (!(offset & (pte_size - 1)) && bytes == 1)
5074 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5075 misaligned |= bytes < 4;
5080 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5082 unsigned page_offset, quadrant;
5086 page_offset = offset_in_page(gpa);
5087 level = sp->role.level;
5089 if (!sp->role.cr4_pae) {
5090 page_offset <<= 1; /* 32->64 */
5092 * A 32-bit pde maps 4MB while the shadow pdes map
5093 * only 2MB. So we need to double the offset again
5094 * and zap two pdes instead of one.
5096 if (level == PT32_ROOT_LEVEL) {
5097 page_offset &= ~7; /* kill rounding error */
5101 quadrant = page_offset >> PAGE_SHIFT;
5102 page_offset &= ~PAGE_MASK;
5103 if (quadrant != sp->role.quadrant)
5107 spte = &sp->spt[page_offset / sizeof(*spte)];
5111 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5112 const u8 *new, int bytes,
5113 struct kvm_page_track_notifier_node *node)
5115 gfn_t gfn = gpa >> PAGE_SHIFT;
5116 struct kvm_mmu_page *sp;
5117 LIST_HEAD(invalid_list);
5118 u64 entry, gentry, *spte;
5120 bool remote_flush, local_flush;
5123 * If we don't have indirect shadow pages, it means no page is
5124 * write-protected, so we can exit simply.
5126 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5129 remote_flush = local_flush = false;
5131 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5133 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
5136 * No need to care whether allocation memory is successful
5137 * or not since pte prefetch is skiped if it does not have
5138 * enough objects in the cache.
5140 mmu_topup_memory_caches(vcpu);
5142 spin_lock(&vcpu->kvm->mmu_lock);
5143 ++vcpu->kvm->stat.mmu_pte_write;
5144 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5146 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5147 if (detect_write_misaligned(sp, gpa, bytes) ||
5148 detect_write_flooding(sp)) {
5149 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5150 ++vcpu->kvm->stat.mmu_flooded;
5154 spte = get_written_sptes(sp, gpa, &npte);
5161 mmu_page_zap_pte(vcpu->kvm, sp, spte);
5163 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
5164 & mmu_base_role_mask.word) && rmap_can_add(vcpu))
5165 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
5166 if (need_remote_flush(entry, *spte))
5167 remote_flush = true;
5171 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5172 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5173 spin_unlock(&vcpu->kvm->mmu_lock);
5176 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
5181 if (vcpu->arch.mmu.direct_map)
5184 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
5186 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
5190 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
5192 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
5194 LIST_HEAD(invalid_list);
5196 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
5199 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
5200 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
5203 ++vcpu->kvm->stat.mmu_recycled;
5205 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
5207 if (!kvm_mmu_available_pages(vcpu->kvm))
5212 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code,
5213 void *insn, int insn_len)
5215 int r, emulation_type = 0;
5216 enum emulation_result er;
5217 bool direct = vcpu->arch.mmu.direct_map;
5219 /* With shadow page tables, fault_address contains a GVA or nGPA. */
5220 if (vcpu->arch.mmu.direct_map) {
5221 vcpu->arch.gpa_available = true;
5222 vcpu->arch.gpa_val = cr2;
5226 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5227 r = handle_mmio_page_fault(vcpu, cr2, direct);
5228 if (r == RET_PF_EMULATE)
5232 if (r == RET_PF_INVALID) {
5233 r = vcpu->arch.mmu.page_fault(vcpu, cr2, lower_32_bits(error_code),
5235 WARN_ON(r == RET_PF_INVALID);
5238 if (r == RET_PF_RETRY)
5244 * Before emulating the instruction, check if the error code
5245 * was due to a RO violation while translating the guest page.
5246 * This can occur when using nested virtualization with nested
5247 * paging in both guests. If true, we simply unprotect the page
5248 * and resume the guest.
5250 if (vcpu->arch.mmu.direct_map &&
5251 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5252 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2));
5257 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5258 * optimistically try to just unprotect the page and let the processor
5259 * re-execute the instruction that caused the page fault. Do not allow
5260 * retrying MMIO emulation, as it's not only pointless but could also
5261 * cause us to enter an infinite loop because the processor will keep
5262 * faulting on the non-existent MMIO address. Retrying an instruction
5263 * from a nested guest is also pointless and dangerous as we are only
5264 * explicitly shadowing L1's page tables, i.e. unprotecting something
5265 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5267 if (!mmio_info_in_cache(vcpu, cr2, direct) && !is_guest_mode(vcpu))
5268 emulation_type = EMULTYPE_ALLOW_RETRY;
5271 * On AMD platforms, under certain conditions insn_len may be zero on #NPF.
5272 * This can happen if a guest gets a page-fault on data access but the HW
5273 * table walker is not able to read the instruction page (e.g instruction
5274 * page is not present in memory). In those cases we simply restart the
5277 if (unlikely(insn && !insn_len))
5280 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
5285 case EMULATE_USER_EXIT:
5286 ++vcpu->stat.mmio_exits;
5294 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5296 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5298 struct kvm_mmu *mmu = &vcpu->arch.mmu;
5301 /* INVLPG on a * non-canonical address is a NOP according to the SDM. */
5302 if (is_noncanonical_address(gva, vcpu))
5305 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5308 * INVLPG is required to invalidate any global mappings for the VA,
5309 * irrespective of PCID. Since it would take us roughly similar amount
5310 * of work to determine whether any of the prev_root mappings of the VA
5311 * is marked global, or to just sync it blindly, so we might as well
5312 * just always sync it.
5314 * Mappings not reachable via the current cr3 or the prev_roots will be
5315 * synced when switching to that cr3, so nothing needs to be done here
5318 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5319 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5320 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5322 kvm_x86_ops->tlb_flush_gva(vcpu, gva);
5323 ++vcpu->stat.invlpg;
5325 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5327 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5329 struct kvm_mmu *mmu = &vcpu->arch.mmu;
5330 bool tlb_flush = false;
5333 if (pcid == kvm_get_active_pcid(vcpu)) {
5334 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5338 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5339 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5340 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].cr3)) {
5341 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5347 kvm_x86_ops->tlb_flush_gva(vcpu, gva);
5349 ++vcpu->stat.invlpg;
5352 * Mappings not reachable via the current cr3 or the prev_roots will be
5353 * synced when switching to that cr3, so nothing needs to be done here
5357 EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva);
5359 void kvm_enable_tdp(void)
5363 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
5365 void kvm_disable_tdp(void)
5367 tdp_enabled = false;
5369 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
5371 static void free_mmu_pages(struct kvm_vcpu *vcpu)
5373 free_page((unsigned long)vcpu->arch.mmu.pae_root);
5374 free_page((unsigned long)vcpu->arch.mmu.lm_root);
5377 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
5386 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
5387 * Therefore we need to allocate shadow page tables in the first
5388 * 4GB of memory, which happens to fit the DMA32 zone.
5390 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
5394 vcpu->arch.mmu.pae_root = page_address(page);
5395 for (i = 0; i < 4; ++i)
5396 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
5401 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5405 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
5406 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
5407 vcpu->arch.mmu.translate_gpa = translate_gpa;
5408 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5410 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5411 vcpu->arch.mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5413 return alloc_mmu_pages(vcpu);
5416 void kvm_mmu_setup(struct kvm_vcpu *vcpu)
5418 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
5420 kvm_init_mmu(vcpu, true);
5423 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5424 struct kvm_memory_slot *slot,
5425 struct kvm_page_track_notifier_node *node)
5427 kvm_mmu_invalidate_zap_all_pages(kvm);
5430 void kvm_mmu_init_vm(struct kvm *kvm)
5432 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5434 node->track_write = kvm_mmu_pte_write;
5435 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5436 kvm_page_track_register_notifier(kvm, node);
5439 void kvm_mmu_uninit_vm(struct kvm *kvm)
5441 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5443 kvm_page_track_unregister_notifier(kvm, node);
5446 /* The return value indicates if tlb flush on all vcpus is needed. */
5447 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
5449 /* The caller should hold mmu-lock before calling this function. */
5450 static __always_inline bool
5451 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5452 slot_level_handler fn, int start_level, int end_level,
5453 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
5455 struct slot_rmap_walk_iterator iterator;
5458 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5459 end_gfn, &iterator) {
5461 flush |= fn(kvm, iterator.rmap);
5463 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5464 if (flush && lock_flush_tlb) {
5465 kvm_flush_remote_tlbs(kvm);
5468 cond_resched_lock(&kvm->mmu_lock);
5472 if (flush && lock_flush_tlb) {
5473 kvm_flush_remote_tlbs(kvm);
5480 static __always_inline bool
5481 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5482 slot_level_handler fn, int start_level, int end_level,
5483 bool lock_flush_tlb)
5485 return slot_handle_level_range(kvm, memslot, fn, start_level,
5486 end_level, memslot->base_gfn,
5487 memslot->base_gfn + memslot->npages - 1,
5491 static __always_inline bool
5492 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5493 slot_level_handler fn, bool lock_flush_tlb)
5495 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5496 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5499 static __always_inline bool
5500 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5501 slot_level_handler fn, bool lock_flush_tlb)
5503 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
5504 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5507 static __always_inline bool
5508 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5509 slot_level_handler fn, bool lock_flush_tlb)
5511 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5512 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
5515 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5517 struct kvm_memslots *slots;
5518 struct kvm_memory_slot *memslot;
5521 spin_lock(&kvm->mmu_lock);
5522 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5523 slots = __kvm_memslots(kvm, i);
5524 kvm_for_each_memslot(memslot, slots) {
5527 start = max(gfn_start, memslot->base_gfn);
5528 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5532 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5533 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
5534 start, end - 1, true);
5538 spin_unlock(&kvm->mmu_lock);
5541 static bool slot_rmap_write_protect(struct kvm *kvm,
5542 struct kvm_rmap_head *rmap_head)
5544 return __rmap_write_protect(kvm, rmap_head, false);
5547 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5548 struct kvm_memory_slot *memslot)
5552 spin_lock(&kvm->mmu_lock);
5553 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
5555 spin_unlock(&kvm->mmu_lock);
5558 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
5559 * which do tlb flush out of mmu-lock should be serialized by
5560 * kvm->slots_lock otherwise tlb flush would be missed.
5562 lockdep_assert_held(&kvm->slots_lock);
5565 * We can flush all the TLBs out of the mmu lock without TLB
5566 * corruption since we just change the spte from writable to
5567 * readonly so that we only need to care the case of changing
5568 * spte from present to present (changing the spte from present
5569 * to nonpresent will flush all the TLBs immediately), in other
5570 * words, the only case we care is mmu_spte_update() where we
5571 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5572 * instead of PT_WRITABLE_MASK, that means it does not depend
5573 * on PT_WRITABLE_MASK anymore.
5576 kvm_flush_remote_tlbs(kvm);
5579 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5580 struct kvm_rmap_head *rmap_head)
5583 struct rmap_iterator iter;
5584 int need_tlb_flush = 0;
5586 struct kvm_mmu_page *sp;
5589 for_each_rmap_spte(rmap_head, &iter, sptep) {
5590 sp = page_header(__pa(sptep));
5591 pfn = spte_to_pfn(*sptep);
5594 * We cannot do huge page mapping for indirect shadow pages,
5595 * which are found on the last rmap (level = 1) when not using
5596 * tdp; such shadow pages are synced with the page table in
5597 * the guest, and the guest page table is using 4K page size
5598 * mapping if the indirect sp has level = 1.
5600 if (sp->role.direct &&
5601 !kvm_is_reserved_pfn(pfn) &&
5602 PageTransCompoundMap(pfn_to_page(pfn))) {
5603 drop_spte(kvm, sptep);
5609 return need_tlb_flush;
5612 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5613 const struct kvm_memory_slot *memslot)
5615 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5616 spin_lock(&kvm->mmu_lock);
5617 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
5618 kvm_mmu_zap_collapsible_spte, true);
5619 spin_unlock(&kvm->mmu_lock);
5622 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5623 struct kvm_memory_slot *memslot)
5627 spin_lock(&kvm->mmu_lock);
5628 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
5629 spin_unlock(&kvm->mmu_lock);
5631 lockdep_assert_held(&kvm->slots_lock);
5634 * It's also safe to flush TLBs out of mmu lock here as currently this
5635 * function is only used for dirty logging, in which case flushing TLB
5636 * out of mmu lock also guarantees no dirty pages will be lost in
5640 kvm_flush_remote_tlbs(kvm);
5642 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
5644 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
5645 struct kvm_memory_slot *memslot)
5649 spin_lock(&kvm->mmu_lock);
5650 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
5652 spin_unlock(&kvm->mmu_lock);
5654 /* see kvm_mmu_slot_remove_write_access */
5655 lockdep_assert_held(&kvm->slots_lock);
5658 kvm_flush_remote_tlbs(kvm);
5660 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
5662 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
5663 struct kvm_memory_slot *memslot)
5667 spin_lock(&kvm->mmu_lock);
5668 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
5669 spin_unlock(&kvm->mmu_lock);
5671 lockdep_assert_held(&kvm->slots_lock);
5673 /* see kvm_mmu_slot_leaf_clear_dirty */
5675 kvm_flush_remote_tlbs(kvm);
5677 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
5679 #define BATCH_ZAP_PAGES 10
5680 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5682 struct kvm_mmu_page *sp, *node;
5686 list_for_each_entry_safe_reverse(sp, node,
5687 &kvm->arch.active_mmu_pages, link) {
5691 * No obsolete page exists before new created page since
5692 * active_mmu_pages is the FIFO list.
5694 if (!is_obsolete_sp(kvm, sp))
5698 * Since we are reversely walking the list and the invalid
5699 * list will be moved to the head, skip the invalid page
5700 * can help us to avoid the infinity list walking.
5702 if (sp->role.invalid)
5706 * Need not flush tlb since we only zap the sp with invalid
5707 * generation number.
5709 if (batch >= BATCH_ZAP_PAGES &&
5710 cond_resched_lock(&kvm->mmu_lock)) {
5715 ret = kvm_mmu_prepare_zap_page(kvm, sp,
5716 &kvm->arch.zapped_obsolete_pages);
5724 * Should flush tlb before free page tables since lockless-walking
5725 * may use the pages.
5727 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5731 * Fast invalidate all shadow pages and use lock-break technique
5732 * to zap obsolete pages.
5734 * It's required when memslot is being deleted or VM is being
5735 * destroyed, in these cases, we should ensure that KVM MMU does
5736 * not use any resource of the being-deleted slot or all slots
5737 * after calling the function.
5739 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
5741 spin_lock(&kvm->mmu_lock);
5742 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
5743 kvm->arch.mmu_valid_gen++;
5746 * Notify all vcpus to reload its shadow page table
5747 * and flush TLB. Then all vcpus will switch to new
5748 * shadow page table with the new mmu_valid_gen.
5750 * Note: we should do this under the protection of
5751 * mmu-lock, otherwise, vcpu would purge shadow page
5752 * but miss tlb flush.
5754 kvm_reload_remote_mmus(kvm);
5756 kvm_zap_obsolete_pages(kvm);
5757 spin_unlock(&kvm->mmu_lock);
5760 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5762 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5765 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots)
5768 * The very rare case: if the generation-number is round,
5769 * zap all shadow pages.
5771 if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) {
5772 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5773 kvm_mmu_invalidate_zap_all_pages(kvm);
5777 static unsigned long
5778 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5781 int nr_to_scan = sc->nr_to_scan;
5782 unsigned long freed = 0;
5784 spin_lock(&kvm_lock);
5786 list_for_each_entry(kvm, &vm_list, vm_list) {
5788 LIST_HEAD(invalid_list);
5791 * Never scan more than sc->nr_to_scan VM instances.
5792 * Will not hit this condition practically since we do not try
5793 * to shrink more than one VM and it is very unlikely to see
5794 * !n_used_mmu_pages so many times.
5799 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5800 * here. We may skip a VM instance errorneosly, but we do not
5801 * want to shrink a VM that only started to populate its MMU
5804 if (!kvm->arch.n_used_mmu_pages &&
5805 !kvm_has_zapped_obsolete_pages(kvm))
5808 idx = srcu_read_lock(&kvm->srcu);
5809 spin_lock(&kvm->mmu_lock);
5811 if (kvm_has_zapped_obsolete_pages(kvm)) {
5812 kvm_mmu_commit_zap_page(kvm,
5813 &kvm->arch.zapped_obsolete_pages);
5817 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
5819 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5822 spin_unlock(&kvm->mmu_lock);
5823 srcu_read_unlock(&kvm->srcu, idx);
5826 * unfair on small ones
5827 * per-vm shrinkers cry out
5828 * sadness comes quickly
5830 list_move_tail(&kvm->vm_list, &vm_list);
5834 spin_unlock(&kvm_lock);
5838 static unsigned long
5839 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5841 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5844 static struct shrinker mmu_shrinker = {
5845 .count_objects = mmu_shrink_count,
5846 .scan_objects = mmu_shrink_scan,
5847 .seeks = DEFAULT_SEEKS * 10,
5850 static void mmu_destroy_caches(void)
5852 kmem_cache_destroy(pte_list_desc_cache);
5853 kmem_cache_destroy(mmu_page_header_cache);
5856 int kvm_mmu_module_init(void)
5860 kvm_mmu_reset_all_pte_masks();
5862 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5863 sizeof(struct pte_list_desc),
5864 0, SLAB_ACCOUNT, NULL);
5865 if (!pte_list_desc_cache)
5868 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5869 sizeof(struct kvm_mmu_page),
5870 0, SLAB_ACCOUNT, NULL);
5871 if (!mmu_page_header_cache)
5874 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5877 ret = register_shrinker(&mmu_shrinker);
5884 mmu_destroy_caches();
5889 * Caculate mmu pages needed for kvm.
5891 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
5893 unsigned int nr_mmu_pages;
5894 unsigned int nr_pages = 0;
5895 struct kvm_memslots *slots;
5896 struct kvm_memory_slot *memslot;
5899 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5900 slots = __kvm_memslots(kvm, i);
5902 kvm_for_each_memslot(memslot, slots)
5903 nr_pages += memslot->npages;
5906 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5907 nr_mmu_pages = max(nr_mmu_pages,
5908 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
5910 return nr_mmu_pages;
5913 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5915 kvm_mmu_unload(vcpu);
5916 free_mmu_pages(vcpu);
5917 mmu_free_memory_caches(vcpu);
5920 void kvm_mmu_module_exit(void)
5922 mmu_destroy_caches();
5923 percpu_counter_destroy(&kvm_total_used_mmu_pages);
5924 unregister_shrinker(&mmu_shrinker);
5925 mmu_audit_disable();