2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/moduleparam.h>
33 #include <linux/export.h>
34 #include <linux/swap.h>
35 #include <linux/hugetlb.h>
36 #include <linux/compiler.h>
37 #include <linux/srcu.h>
38 #include <linux/slab.h>
39 #include <linux/sched/signal.h>
40 #include <linux/uaccess.h>
41 #include <linux/hash.h>
42 #include <linux/kern_levels.h>
45 #include <asm/cmpxchg.h>
48 #include <asm/kvm_page_track.h>
51 * When setting this variable to true it enables Two-Dimensional-Paging
52 * where the hardware walks 2 page tables:
53 * 1. the guest-virtual to guest-physical
54 * 2. while doing 1. it walks guest-physical to host-physical
55 * If the hardware supports that we don't need to do shadow paging.
57 bool tdp_enabled = false;
61 AUDIT_POST_PAGE_FAULT,
72 module_param(dbg, bool, 0644);
74 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
75 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
76 #define MMU_WARN_ON(x) WARN_ON(x)
78 #define pgprintk(x...) do { } while (0)
79 #define rmap_printk(x...) do { } while (0)
80 #define MMU_WARN_ON(x) do { } while (0)
83 #define PTE_PREFETCH_NUM 8
85 #define PT_FIRST_AVAIL_BITS_SHIFT 10
86 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
88 #define PT64_LEVEL_BITS 9
90 #define PT64_LEVEL_SHIFT(level) \
91 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
93 #define PT64_INDEX(address, level)\
94 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
97 #define PT32_LEVEL_BITS 10
99 #define PT32_LEVEL_SHIFT(level) \
100 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
102 #define PT32_LVL_OFFSET_MASK(level) \
103 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
104 * PT32_LEVEL_BITS))) - 1))
106 #define PT32_INDEX(address, level)\
107 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
110 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
111 #define PT64_DIR_BASE_ADDR_MASK \
112 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
113 #define PT64_LVL_ADDR_MASK(level) \
114 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
115 * PT64_LEVEL_BITS))) - 1))
116 #define PT64_LVL_OFFSET_MASK(level) \
117 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
118 * PT64_LEVEL_BITS))) - 1))
120 #define PT32_BASE_ADDR_MASK PAGE_MASK
121 #define PT32_DIR_BASE_ADDR_MASK \
122 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
123 #define PT32_LVL_ADDR_MASK(level) \
124 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
125 * PT32_LEVEL_BITS))) - 1))
127 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
128 | shadow_x_mask | shadow_nx_mask)
130 #define ACC_EXEC_MASK 1
131 #define ACC_WRITE_MASK PT_WRITABLE_MASK
132 #define ACC_USER_MASK PT_USER_MASK
133 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
135 /* The mask for the R/X bits in EPT PTEs */
136 #define PT64_EPT_READABLE_MASK 0x1ull
137 #define PT64_EPT_EXECUTABLE_MASK 0x4ull
139 #include <trace/events/kvm.h>
141 #define CREATE_TRACE_POINTS
142 #include "mmutrace.h"
144 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
145 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
147 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
149 /* make pte_list_desc fit well in cache line */
150 #define PTE_LIST_EXT 3
152 struct pte_list_desc {
153 u64 *sptes[PTE_LIST_EXT];
154 struct pte_list_desc *more;
157 struct kvm_shadow_walk_iterator {
165 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
166 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
167 shadow_walk_okay(&(_walker)); \
168 shadow_walk_next(&(_walker)))
170 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
171 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
172 shadow_walk_okay(&(_walker)) && \
173 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
174 __shadow_walk_next(&(_walker), spte))
176 static struct kmem_cache *pte_list_desc_cache;
177 static struct kmem_cache *mmu_page_header_cache;
178 static struct percpu_counter kvm_total_used_mmu_pages;
180 static u64 __read_mostly shadow_nx_mask;
181 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
182 static u64 __read_mostly shadow_user_mask;
183 static u64 __read_mostly shadow_accessed_mask;
184 static u64 __read_mostly shadow_dirty_mask;
185 static u64 __read_mostly shadow_mmio_mask;
186 static u64 __read_mostly shadow_present_mask;
189 * The mask/value to distinguish a PTE that has been marked not-present for
190 * access tracking purposes.
191 * The mask would be either 0 if access tracking is disabled, or
192 * SPTE_SPECIAL_MASK|VMX_EPT_RWX_MASK if access tracking is enabled.
194 static u64 __read_mostly shadow_acc_track_mask;
195 static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK;
198 * The mask/shift to use for saving the original R/X bits when marking the PTE
199 * as not-present for access tracking purposes. We do not save the W bit as the
200 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
201 * restored only when a write is attempted to the page.
203 static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK |
204 PT64_EPT_EXECUTABLE_MASK;
205 static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT;
207 static void mmu_spte_set(u64 *sptep, u64 spte);
208 static void mmu_free_roots(struct kvm_vcpu *vcpu);
210 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
212 shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK;
214 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
216 static inline bool is_access_track_spte(u64 spte)
218 /* Always false if shadow_acc_track_mask is zero. */
219 return (spte & shadow_acc_track_mask) == shadow_acc_track_value;
223 * the low bit of the generation number is always presumed to be zero.
224 * This disables mmio caching during memslot updates. The concept is
225 * similar to a seqcount but instead of retrying the access we just punt
226 * and ignore the cache.
228 * spte bits 3-11 are used as bits 1-9 of the generation number,
229 * the bits 52-61 are used as bits 10-19 of the generation number.
231 #define MMIO_SPTE_GEN_LOW_SHIFT 2
232 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
234 #define MMIO_GEN_SHIFT 20
235 #define MMIO_GEN_LOW_SHIFT 10
236 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
237 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
239 static u64 generation_mmio_spte_mask(unsigned int gen)
243 WARN_ON(gen & ~MMIO_GEN_MASK);
245 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
246 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
250 static unsigned int get_mmio_spte_generation(u64 spte)
254 spte &= ~shadow_mmio_mask;
256 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
257 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
261 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu)
263 return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK;
266 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
269 unsigned int gen = kvm_current_mmio_generation(vcpu);
270 u64 mask = generation_mmio_spte_mask(gen);
272 access &= ACC_WRITE_MASK | ACC_USER_MASK;
273 mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
275 trace_mark_mmio_spte(sptep, gfn, access, gen);
276 mmu_spte_set(sptep, mask);
279 static bool is_mmio_spte(u64 spte)
281 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
284 static gfn_t get_mmio_spte_gfn(u64 spte)
286 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
287 return (spte & ~mask) >> PAGE_SHIFT;
290 static unsigned get_mmio_spte_access(u64 spte)
292 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
293 return (spte & ~mask) & ~PAGE_MASK;
296 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
297 kvm_pfn_t pfn, unsigned access)
299 if (unlikely(is_noslot_pfn(pfn))) {
300 mark_mmio_spte(vcpu, sptep, gfn, access);
307 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
309 unsigned int kvm_gen, spte_gen;
311 kvm_gen = kvm_current_mmio_generation(vcpu);
312 spte_gen = get_mmio_spte_generation(spte);
314 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
315 return likely(kvm_gen == spte_gen);
318 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
319 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
322 if (acc_track_mask != 0)
323 acc_track_mask |= SPTE_SPECIAL_MASK;
325 shadow_user_mask = user_mask;
326 shadow_accessed_mask = accessed_mask;
327 shadow_dirty_mask = dirty_mask;
328 shadow_nx_mask = nx_mask;
329 shadow_x_mask = x_mask;
330 shadow_present_mask = p_mask;
331 shadow_acc_track_mask = acc_track_mask;
332 WARN_ON(shadow_accessed_mask != 0 && shadow_acc_track_mask != 0);
334 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
336 void kvm_mmu_clear_all_pte_masks(void)
338 shadow_user_mask = 0;
339 shadow_accessed_mask = 0;
340 shadow_dirty_mask = 0;
343 shadow_mmio_mask = 0;
344 shadow_present_mask = 0;
345 shadow_acc_track_mask = 0;
348 static int is_cpuid_PSE36(void)
353 static int is_nx(struct kvm_vcpu *vcpu)
355 return vcpu->arch.efer & EFER_NX;
358 static int is_shadow_present_pte(u64 pte)
360 return (pte != 0) && !is_mmio_spte(pte);
363 static int is_large_pte(u64 pte)
365 return pte & PT_PAGE_SIZE_MASK;
368 static int is_last_spte(u64 pte, int level)
370 if (level == PT_PAGE_TABLE_LEVEL)
372 if (is_large_pte(pte))
377 static bool is_executable_pte(u64 spte)
379 return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask;
382 static kvm_pfn_t spte_to_pfn(u64 pte)
384 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
387 static gfn_t pse36_gfn_delta(u32 gpte)
389 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
391 return (gpte & PT32_DIR_PSE36_MASK) << shift;
395 static void __set_spte(u64 *sptep, u64 spte)
397 WRITE_ONCE(*sptep, spte);
400 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
402 WRITE_ONCE(*sptep, spte);
405 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
407 return xchg(sptep, spte);
410 static u64 __get_spte_lockless(u64 *sptep)
412 return ACCESS_ONCE(*sptep);
423 static void count_spte_clear(u64 *sptep, u64 spte)
425 struct kvm_mmu_page *sp = page_header(__pa(sptep));
427 if (is_shadow_present_pte(spte))
430 /* Ensure the spte is completely set before we increase the count */
432 sp->clear_spte_count++;
435 static void __set_spte(u64 *sptep, u64 spte)
437 union split_spte *ssptep, sspte;
439 ssptep = (union split_spte *)sptep;
440 sspte = (union split_spte)spte;
442 ssptep->spte_high = sspte.spte_high;
445 * If we map the spte from nonpresent to present, We should store
446 * the high bits firstly, then set present bit, so cpu can not
447 * fetch this spte while we are setting the spte.
451 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
454 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
456 union split_spte *ssptep, sspte;
458 ssptep = (union split_spte *)sptep;
459 sspte = (union split_spte)spte;
461 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
464 * If we map the spte from present to nonpresent, we should clear
465 * present bit firstly to avoid vcpu fetch the old high bits.
469 ssptep->spte_high = sspte.spte_high;
470 count_spte_clear(sptep, spte);
473 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
475 union split_spte *ssptep, sspte, orig;
477 ssptep = (union split_spte *)sptep;
478 sspte = (union split_spte)spte;
480 /* xchg acts as a barrier before the setting of the high bits */
481 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
482 orig.spte_high = ssptep->spte_high;
483 ssptep->spte_high = sspte.spte_high;
484 count_spte_clear(sptep, spte);
490 * The idea using the light way get the spte on x86_32 guest is from
491 * gup_get_pte(arch/x86/mm/gup.c).
493 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
494 * coalesces them and we are running out of the MMU lock. Therefore
495 * we need to protect against in-progress updates of the spte.
497 * Reading the spte while an update is in progress may get the old value
498 * for the high part of the spte. The race is fine for a present->non-present
499 * change (because the high part of the spte is ignored for non-present spte),
500 * but for a present->present change we must reread the spte.
502 * All such changes are done in two steps (present->non-present and
503 * non-present->present), hence it is enough to count the number of
504 * present->non-present updates: if it changed while reading the spte,
505 * we might have hit the race. This is done using clear_spte_count.
507 static u64 __get_spte_lockless(u64 *sptep)
509 struct kvm_mmu_page *sp = page_header(__pa(sptep));
510 union split_spte spte, *orig = (union split_spte *)sptep;
514 count = sp->clear_spte_count;
517 spte.spte_low = orig->spte_low;
520 spte.spte_high = orig->spte_high;
523 if (unlikely(spte.spte_low != orig->spte_low ||
524 count != sp->clear_spte_count))
531 static bool spte_can_locklessly_be_made_writable(u64 spte)
533 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
534 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
537 static bool spte_has_volatile_bits(u64 spte)
539 if (!is_shadow_present_pte(spte))
543 * Always atomically update spte if it can be updated
544 * out of mmu-lock, it can ensure dirty bit is not lost,
545 * also, it can help us to get a stable is_writable_pte()
546 * to ensure tlb flush is not missed.
548 if (spte_can_locklessly_be_made_writable(spte) ||
549 is_access_track_spte(spte))
552 if (shadow_accessed_mask) {
553 if ((spte & shadow_accessed_mask) == 0 ||
554 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
561 static bool is_accessed_spte(u64 spte)
563 return shadow_accessed_mask ? spte & shadow_accessed_mask
564 : !is_access_track_spte(spte);
567 static bool is_dirty_spte(u64 spte)
569 return shadow_dirty_mask ? spte & shadow_dirty_mask
570 : spte & PT_WRITABLE_MASK;
573 /* Rules for using mmu_spte_set:
574 * Set the sptep from nonpresent to present.
575 * Note: the sptep being assigned *must* be either not present
576 * or in a state where the hardware will not attempt to update
579 static void mmu_spte_set(u64 *sptep, u64 new_spte)
581 WARN_ON(is_shadow_present_pte(*sptep));
582 __set_spte(sptep, new_spte);
586 * Update the SPTE (excluding the PFN), but do not track changes in its
587 * accessed/dirty status.
589 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
591 u64 old_spte = *sptep;
593 WARN_ON(!is_shadow_present_pte(new_spte));
595 if (!is_shadow_present_pte(old_spte)) {
596 mmu_spte_set(sptep, new_spte);
600 if (!spte_has_volatile_bits(old_spte))
601 __update_clear_spte_fast(sptep, new_spte);
603 old_spte = __update_clear_spte_slow(sptep, new_spte);
605 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
610 /* Rules for using mmu_spte_update:
611 * Update the state bits, it means the mapped pfn is not changed.
613 * Whenever we overwrite a writable spte with a read-only one we
614 * should flush remote TLBs. Otherwise rmap_write_protect
615 * will find a read-only spte, even though the writable spte
616 * might be cached on a CPU's TLB, the return value indicates this
619 * Returns true if the TLB needs to be flushed
621 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
624 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
626 if (!is_shadow_present_pte(old_spte))
630 * For the spte updated out of mmu-lock is safe, since
631 * we always atomically update it, see the comments in
632 * spte_has_volatile_bits().
634 if (spte_can_locklessly_be_made_writable(old_spte) &&
635 !is_writable_pte(new_spte))
639 * Flush TLB when accessed/dirty states are changed in the page tables,
640 * to guarantee consistency between TLB and page tables.
643 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
645 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
648 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
650 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
657 * Rules for using mmu_spte_clear_track_bits:
658 * It sets the sptep from present to nonpresent, and track the
659 * state bits, it is used to clear the last level sptep.
660 * Returns non-zero if the PTE was previously valid.
662 static int mmu_spte_clear_track_bits(u64 *sptep)
665 u64 old_spte = *sptep;
667 if (!spte_has_volatile_bits(old_spte))
668 __update_clear_spte_fast(sptep, 0ull);
670 old_spte = __update_clear_spte_slow(sptep, 0ull);
672 if (!is_shadow_present_pte(old_spte))
675 pfn = spte_to_pfn(old_spte);
678 * KVM does not hold the refcount of the page used by
679 * kvm mmu, before reclaiming the page, we should
680 * unmap it from mmu first.
682 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
684 if (is_accessed_spte(old_spte))
685 kvm_set_pfn_accessed(pfn);
687 if (is_dirty_spte(old_spte))
688 kvm_set_pfn_dirty(pfn);
694 * Rules for using mmu_spte_clear_no_track:
695 * Directly clear spte without caring the state bits of sptep,
696 * it is used to set the upper level spte.
698 static void mmu_spte_clear_no_track(u64 *sptep)
700 __update_clear_spte_fast(sptep, 0ull);
703 static u64 mmu_spte_get_lockless(u64 *sptep)
705 return __get_spte_lockless(sptep);
708 static u64 mark_spte_for_access_track(u64 spte)
710 if (shadow_accessed_mask != 0)
711 return spte & ~shadow_accessed_mask;
713 if (shadow_acc_track_mask == 0 || is_access_track_spte(spte))
717 * Making an Access Tracking PTE will result in removal of write access
718 * from the PTE. So, verify that we will be able to restore the write
719 * access in the fast page fault path later on.
721 WARN_ONCE((spte & PT_WRITABLE_MASK) &&
722 !spte_can_locklessly_be_made_writable(spte),
723 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
725 WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask <<
726 shadow_acc_track_saved_bits_shift),
727 "kvm: Access Tracking saved bit locations are not zero\n");
729 spte |= (spte & shadow_acc_track_saved_bits_mask) <<
730 shadow_acc_track_saved_bits_shift;
731 spte &= ~shadow_acc_track_mask;
732 spte |= shadow_acc_track_value;
737 /* Restore an acc-track PTE back to a regular PTE */
738 static u64 restore_acc_track_spte(u64 spte)
741 u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift)
742 & shadow_acc_track_saved_bits_mask;
744 WARN_ON_ONCE(!is_access_track_spte(spte));
746 new_spte &= ~shadow_acc_track_mask;
747 new_spte &= ~(shadow_acc_track_saved_bits_mask <<
748 shadow_acc_track_saved_bits_shift);
749 new_spte |= saved_bits;
754 /* Returns the Accessed status of the PTE and resets it at the same time. */
755 static bool mmu_spte_age(u64 *sptep)
757 u64 spte = mmu_spte_get_lockless(sptep);
759 if (!is_accessed_spte(spte))
762 if (shadow_accessed_mask) {
763 clear_bit((ffs(shadow_accessed_mask) - 1),
764 (unsigned long *)sptep);
767 * Capture the dirty status of the page, so that it doesn't get
768 * lost when the SPTE is marked for access tracking.
770 if (is_writable_pte(spte))
771 kvm_set_pfn_dirty(spte_to_pfn(spte));
773 spte = mark_spte_for_access_track(spte);
774 mmu_spte_update_no_track(sptep, spte);
780 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
783 * Prevent page table teardown by making any free-er wait during
784 * kvm_flush_remote_tlbs() IPI to all active vcpus.
789 * Make sure a following spte read is not reordered ahead of the write
792 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
795 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
798 * Make sure the write to vcpu->mode is not reordered in front of
799 * reads to sptes. If it does, kvm_commit_zap_page() can see us
800 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
802 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
806 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
807 struct kmem_cache *base_cache, int min)
811 if (cache->nobjs >= min)
813 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
814 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
817 cache->objects[cache->nobjs++] = obj;
822 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
827 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
828 struct kmem_cache *cache)
831 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
834 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
839 if (cache->nobjs >= min)
841 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
842 page = (void *)__get_free_page(GFP_KERNEL);
845 cache->objects[cache->nobjs++] = page;
850 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
853 free_page((unsigned long)mc->objects[--mc->nobjs]);
856 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
860 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
861 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
864 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
867 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
868 mmu_page_header_cache, 4);
873 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
875 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
876 pte_list_desc_cache);
877 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
878 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
879 mmu_page_header_cache);
882 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
887 p = mc->objects[--mc->nobjs];
891 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
893 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
896 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
898 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
901 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
903 if (!sp->role.direct)
904 return sp->gfns[index];
906 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
909 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
912 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
914 sp->gfns[index] = gfn;
918 * Return the pointer to the large page information for a given gfn,
919 * handling slots that are not large page aligned.
921 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
922 struct kvm_memory_slot *slot,
927 idx = gfn_to_index(gfn, slot->base_gfn, level);
928 return &slot->arch.lpage_info[level - 2][idx];
931 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
932 gfn_t gfn, int count)
934 struct kvm_lpage_info *linfo;
937 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
938 linfo = lpage_info_slot(gfn, slot, i);
939 linfo->disallow_lpage += count;
940 WARN_ON(linfo->disallow_lpage < 0);
944 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
946 update_gfn_disallow_lpage_count(slot, gfn, 1);
949 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
951 update_gfn_disallow_lpage_count(slot, gfn, -1);
954 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
956 struct kvm_memslots *slots;
957 struct kvm_memory_slot *slot;
960 kvm->arch.indirect_shadow_pages++;
962 slots = kvm_memslots_for_spte_role(kvm, sp->role);
963 slot = __gfn_to_memslot(slots, gfn);
965 /* the non-leaf shadow pages are keeping readonly. */
966 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
967 return kvm_slot_page_track_add_page(kvm, slot, gfn,
968 KVM_PAGE_TRACK_WRITE);
970 kvm_mmu_gfn_disallow_lpage(slot, gfn);
973 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
975 struct kvm_memslots *slots;
976 struct kvm_memory_slot *slot;
979 kvm->arch.indirect_shadow_pages--;
981 slots = kvm_memslots_for_spte_role(kvm, sp->role);
982 slot = __gfn_to_memslot(slots, gfn);
983 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
984 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
985 KVM_PAGE_TRACK_WRITE);
987 kvm_mmu_gfn_allow_lpage(slot, gfn);
990 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
991 struct kvm_memory_slot *slot)
993 struct kvm_lpage_info *linfo;
996 linfo = lpage_info_slot(gfn, slot, level);
997 return !!linfo->disallow_lpage;
1003 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
1006 struct kvm_memory_slot *slot;
1008 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1009 return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
1012 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
1014 unsigned long page_size;
1017 page_size = kvm_host_page_size(kvm, gfn);
1019 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1020 if (page_size >= KVM_HPAGE_SIZE(i))
1029 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
1032 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
1034 if (no_dirty_log && slot->dirty_bitmap)
1040 static struct kvm_memory_slot *
1041 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
1044 struct kvm_memory_slot *slot;
1046 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1047 if (!memslot_valid_for_gpte(slot, no_dirty_log))
1053 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
1054 bool *force_pt_level)
1056 int host_level, level, max_level;
1057 struct kvm_memory_slot *slot;
1059 if (unlikely(*force_pt_level))
1060 return PT_PAGE_TABLE_LEVEL;
1062 slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
1063 *force_pt_level = !memslot_valid_for_gpte(slot, true);
1064 if (unlikely(*force_pt_level))
1065 return PT_PAGE_TABLE_LEVEL;
1067 host_level = host_mapping_level(vcpu->kvm, large_gfn);
1069 if (host_level == PT_PAGE_TABLE_LEVEL)
1072 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
1074 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
1075 if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot))
1082 * About rmap_head encoding:
1084 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1085 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1086 * pte_list_desc containing more mappings.
1090 * Returns the number of pointers in the rmap chain, not counting the new one.
1092 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
1093 struct kvm_rmap_head *rmap_head)
1095 struct pte_list_desc *desc;
1098 if (!rmap_head->val) {
1099 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
1100 rmap_head->val = (unsigned long)spte;
1101 } else if (!(rmap_head->val & 1)) {
1102 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
1103 desc = mmu_alloc_pte_list_desc(vcpu);
1104 desc->sptes[0] = (u64 *)rmap_head->val;
1105 desc->sptes[1] = spte;
1106 rmap_head->val = (unsigned long)desc | 1;
1109 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
1110 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1111 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
1113 count += PTE_LIST_EXT;
1115 if (desc->sptes[PTE_LIST_EXT-1]) {
1116 desc->more = mmu_alloc_pte_list_desc(vcpu);
1119 for (i = 0; desc->sptes[i]; ++i)
1121 desc->sptes[i] = spte;
1127 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
1128 struct pte_list_desc *desc, int i,
1129 struct pte_list_desc *prev_desc)
1133 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
1135 desc->sptes[i] = desc->sptes[j];
1136 desc->sptes[j] = NULL;
1139 if (!prev_desc && !desc->more)
1140 rmap_head->val = (unsigned long)desc->sptes[0];
1143 prev_desc->more = desc->more;
1145 rmap_head->val = (unsigned long)desc->more | 1;
1146 mmu_free_pte_list_desc(desc);
1149 static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1151 struct pte_list_desc *desc;
1152 struct pte_list_desc *prev_desc;
1155 if (!rmap_head->val) {
1156 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
1158 } else if (!(rmap_head->val & 1)) {
1159 rmap_printk("pte_list_remove: %p 1->0\n", spte);
1160 if ((u64 *)rmap_head->val != spte) {
1161 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
1166 rmap_printk("pte_list_remove: %p many->many\n", spte);
1167 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1170 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1171 if (desc->sptes[i] == spte) {
1172 pte_list_desc_remove_entry(rmap_head,
1173 desc, i, prev_desc);
1180 pr_err("pte_list_remove: %p many->many\n", spte);
1185 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1186 struct kvm_memory_slot *slot)
1190 idx = gfn_to_index(gfn, slot->base_gfn, level);
1191 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1194 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1195 struct kvm_mmu_page *sp)
1197 struct kvm_memslots *slots;
1198 struct kvm_memory_slot *slot;
1200 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1201 slot = __gfn_to_memslot(slots, gfn);
1202 return __gfn_to_rmap(gfn, sp->role.level, slot);
1205 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1207 struct kvm_mmu_memory_cache *cache;
1209 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1210 return mmu_memory_cache_free_objects(cache);
1213 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1215 struct kvm_mmu_page *sp;
1216 struct kvm_rmap_head *rmap_head;
1218 sp = page_header(__pa(spte));
1219 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1220 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1221 return pte_list_add(vcpu, spte, rmap_head);
1224 static void rmap_remove(struct kvm *kvm, u64 *spte)
1226 struct kvm_mmu_page *sp;
1228 struct kvm_rmap_head *rmap_head;
1230 sp = page_header(__pa(spte));
1231 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1232 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1233 pte_list_remove(spte, rmap_head);
1237 * Used by the following functions to iterate through the sptes linked by a
1238 * rmap. All fields are private and not assumed to be used outside.
1240 struct rmap_iterator {
1241 /* private fields */
1242 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1243 int pos; /* index of the sptep */
1247 * Iteration must be started by this function. This should also be used after
1248 * removing/dropping sptes from the rmap link because in such cases the
1249 * information in the itererator may not be valid.
1251 * Returns sptep if found, NULL otherwise.
1253 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1254 struct rmap_iterator *iter)
1258 if (!rmap_head->val)
1261 if (!(rmap_head->val & 1)) {
1263 sptep = (u64 *)rmap_head->val;
1267 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1269 sptep = iter->desc->sptes[iter->pos];
1271 BUG_ON(!is_shadow_present_pte(*sptep));
1276 * Must be used with a valid iterator: e.g. after rmap_get_first().
1278 * Returns sptep if found, NULL otherwise.
1280 static u64 *rmap_get_next(struct rmap_iterator *iter)
1285 if (iter->pos < PTE_LIST_EXT - 1) {
1287 sptep = iter->desc->sptes[iter->pos];
1292 iter->desc = iter->desc->more;
1296 /* desc->sptes[0] cannot be NULL */
1297 sptep = iter->desc->sptes[iter->pos];
1304 BUG_ON(!is_shadow_present_pte(*sptep));
1308 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1309 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1310 _spte_; _spte_ = rmap_get_next(_iter_))
1312 static void drop_spte(struct kvm *kvm, u64 *sptep)
1314 if (mmu_spte_clear_track_bits(sptep))
1315 rmap_remove(kvm, sptep);
1319 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1321 if (is_large_pte(*sptep)) {
1322 WARN_ON(page_header(__pa(sptep))->role.level ==
1323 PT_PAGE_TABLE_LEVEL);
1324 drop_spte(kvm, sptep);
1332 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1334 if (__drop_large_spte(vcpu->kvm, sptep))
1335 kvm_flush_remote_tlbs(vcpu->kvm);
1339 * Write-protect on the specified @sptep, @pt_protect indicates whether
1340 * spte write-protection is caused by protecting shadow page table.
1342 * Note: write protection is difference between dirty logging and spte
1344 * - for dirty logging, the spte can be set to writable at anytime if
1345 * its dirty bitmap is properly set.
1346 * - for spte protection, the spte can be writable only after unsync-ing
1349 * Return true if tlb need be flushed.
1351 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1355 if (!is_writable_pte(spte) &&
1356 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1359 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1362 spte &= ~SPTE_MMU_WRITEABLE;
1363 spte = spte & ~PT_WRITABLE_MASK;
1365 return mmu_spte_update(sptep, spte);
1368 static bool __rmap_write_protect(struct kvm *kvm,
1369 struct kvm_rmap_head *rmap_head,
1373 struct rmap_iterator iter;
1376 for_each_rmap_spte(rmap_head, &iter, sptep)
1377 flush |= spte_write_protect(sptep, pt_protect);
1382 static bool spte_clear_dirty(u64 *sptep)
1386 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1388 spte &= ~shadow_dirty_mask;
1390 return mmu_spte_update(sptep, spte);
1393 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1396 struct rmap_iterator iter;
1399 for_each_rmap_spte(rmap_head, &iter, sptep)
1400 flush |= spte_clear_dirty(sptep);
1405 static bool spte_set_dirty(u64 *sptep)
1409 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1411 spte |= shadow_dirty_mask;
1413 return mmu_spte_update(sptep, spte);
1416 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1419 struct rmap_iterator iter;
1422 for_each_rmap_spte(rmap_head, &iter, sptep)
1423 flush |= spte_set_dirty(sptep);
1429 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1430 * @kvm: kvm instance
1431 * @slot: slot to protect
1432 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1433 * @mask: indicates which pages we should protect
1435 * Used when we do not need to care about huge page mappings: e.g. during dirty
1436 * logging we do not have any such mappings.
1438 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1439 struct kvm_memory_slot *slot,
1440 gfn_t gfn_offset, unsigned long mask)
1442 struct kvm_rmap_head *rmap_head;
1445 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1446 PT_PAGE_TABLE_LEVEL, slot);
1447 __rmap_write_protect(kvm, rmap_head, false);
1449 /* clear the first set bit */
1455 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages
1456 * @kvm: kvm instance
1457 * @slot: slot to clear D-bit
1458 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1459 * @mask: indicates which pages we should clear D-bit
1461 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1463 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1464 struct kvm_memory_slot *slot,
1465 gfn_t gfn_offset, unsigned long mask)
1467 struct kvm_rmap_head *rmap_head;
1470 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1471 PT_PAGE_TABLE_LEVEL, slot);
1472 __rmap_clear_dirty(kvm, rmap_head);
1474 /* clear the first set bit */
1478 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1481 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1484 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1485 * enable dirty logging for them.
1487 * Used when we do not need to care about huge page mappings: e.g. during dirty
1488 * logging we do not have any such mappings.
1490 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1491 struct kvm_memory_slot *slot,
1492 gfn_t gfn_offset, unsigned long mask)
1494 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1495 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1498 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1502 * kvm_arch_write_log_dirty - emulate dirty page logging
1503 * @vcpu: Guest mode vcpu
1505 * Emulate arch specific page modification logging for the
1508 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu)
1510 if (kvm_x86_ops->write_log_dirty)
1511 return kvm_x86_ops->write_log_dirty(vcpu);
1516 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1517 struct kvm_memory_slot *slot, u64 gfn)
1519 struct kvm_rmap_head *rmap_head;
1521 bool write_protected = false;
1523 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1524 rmap_head = __gfn_to_rmap(gfn, i, slot);
1525 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1528 return write_protected;
1531 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1533 struct kvm_memory_slot *slot;
1535 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1536 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1539 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1542 struct rmap_iterator iter;
1545 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1546 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1548 drop_spte(kvm, sptep);
1555 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1556 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1559 return kvm_zap_rmapp(kvm, rmap_head);
1562 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1563 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1567 struct rmap_iterator iter;
1570 pte_t *ptep = (pte_t *)data;
1573 WARN_ON(pte_huge(*ptep));
1574 new_pfn = pte_pfn(*ptep);
1577 for_each_rmap_spte(rmap_head, &iter, sptep) {
1578 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1579 sptep, *sptep, gfn, level);
1583 if (pte_write(*ptep)) {
1584 drop_spte(kvm, sptep);
1587 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1588 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1590 new_spte &= ~PT_WRITABLE_MASK;
1591 new_spte &= ~SPTE_HOST_WRITEABLE;
1593 new_spte = mark_spte_for_access_track(new_spte);
1595 mmu_spte_clear_track_bits(sptep);
1596 mmu_spte_set(sptep, new_spte);
1601 kvm_flush_remote_tlbs(kvm);
1606 struct slot_rmap_walk_iterator {
1608 struct kvm_memory_slot *slot;
1614 /* output fields. */
1616 struct kvm_rmap_head *rmap;
1619 /* private field. */
1620 struct kvm_rmap_head *end_rmap;
1624 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1626 iterator->level = level;
1627 iterator->gfn = iterator->start_gfn;
1628 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1629 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1634 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1635 struct kvm_memory_slot *slot, int start_level,
1636 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1638 iterator->slot = slot;
1639 iterator->start_level = start_level;
1640 iterator->end_level = end_level;
1641 iterator->start_gfn = start_gfn;
1642 iterator->end_gfn = end_gfn;
1644 rmap_walk_init_level(iterator, iterator->start_level);
1647 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1649 return !!iterator->rmap;
1652 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1654 if (++iterator->rmap <= iterator->end_rmap) {
1655 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1659 if (++iterator->level > iterator->end_level) {
1660 iterator->rmap = NULL;
1664 rmap_walk_init_level(iterator, iterator->level);
1667 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1668 _start_gfn, _end_gfn, _iter_) \
1669 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1670 _end_level_, _start_gfn, _end_gfn); \
1671 slot_rmap_walk_okay(_iter_); \
1672 slot_rmap_walk_next(_iter_))
1674 static int kvm_handle_hva_range(struct kvm *kvm,
1675 unsigned long start,
1678 int (*handler)(struct kvm *kvm,
1679 struct kvm_rmap_head *rmap_head,
1680 struct kvm_memory_slot *slot,
1683 unsigned long data))
1685 struct kvm_memslots *slots;
1686 struct kvm_memory_slot *memslot;
1687 struct slot_rmap_walk_iterator iterator;
1691 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1692 slots = __kvm_memslots(kvm, i);
1693 kvm_for_each_memslot(memslot, slots) {
1694 unsigned long hva_start, hva_end;
1695 gfn_t gfn_start, gfn_end;
1697 hva_start = max(start, memslot->userspace_addr);
1698 hva_end = min(end, memslot->userspace_addr +
1699 (memslot->npages << PAGE_SHIFT));
1700 if (hva_start >= hva_end)
1703 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1704 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1706 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1707 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1709 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1710 PT_MAX_HUGEPAGE_LEVEL,
1711 gfn_start, gfn_end - 1,
1713 ret |= handler(kvm, iterator.rmap, memslot,
1714 iterator.gfn, iterator.level, data);
1721 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1723 int (*handler)(struct kvm *kvm,
1724 struct kvm_rmap_head *rmap_head,
1725 struct kvm_memory_slot *slot,
1726 gfn_t gfn, int level,
1727 unsigned long data))
1729 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1732 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1734 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1737 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1739 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1742 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1744 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1747 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1748 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1752 struct rmap_iterator uninitialized_var(iter);
1755 for_each_rmap_spte(rmap_head, &iter, sptep)
1756 young |= mmu_spte_age(sptep);
1758 trace_kvm_age_page(gfn, level, slot, young);
1762 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1763 struct kvm_memory_slot *slot, gfn_t gfn,
1764 int level, unsigned long data)
1767 struct rmap_iterator iter;
1770 * If there's no access bit in the secondary pte set by the hardware and
1771 * fast access tracking is also not enabled, it's up to gup-fast/gup to
1772 * set the access bit in the primary pte or in the page structure.
1774 if (!shadow_accessed_mask && !shadow_acc_track_mask)
1777 for_each_rmap_spte(rmap_head, &iter, sptep)
1778 if (is_accessed_spte(*sptep))
1784 #define RMAP_RECYCLE_THRESHOLD 1000
1786 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1788 struct kvm_rmap_head *rmap_head;
1789 struct kvm_mmu_page *sp;
1791 sp = page_header(__pa(spte));
1793 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1795 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1796 kvm_flush_remote_tlbs(vcpu->kvm);
1799 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1802 * In case of absence of EPT Access and Dirty Bits supports,
1803 * emulate the accessed bit for EPT, by checking if this page has
1804 * an EPT mapping, and clearing it if it does. On the next access,
1805 * a new EPT mapping will be established.
1806 * This has some overhead, but not as much as the cost of swapping
1807 * out actively used pages or breaking up actively used hugepages.
1809 if (!shadow_accessed_mask && !shadow_acc_track_mask)
1810 return kvm_handle_hva_range(kvm, start, end, 0,
1813 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1816 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1818 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1822 static int is_empty_shadow_page(u64 *spt)
1827 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1828 if (is_shadow_present_pte(*pos)) {
1829 printk(KERN_ERR "%s: %p %llx\n", __func__,
1838 * This value is the sum of all of the kvm instances's
1839 * kvm->arch.n_used_mmu_pages values. We need a global,
1840 * aggregate version in order to make the slab shrinker
1843 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1845 kvm->arch.n_used_mmu_pages += nr;
1846 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1849 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1851 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1852 hlist_del(&sp->hash_link);
1853 list_del(&sp->link);
1854 free_page((unsigned long)sp->spt);
1855 if (!sp->role.direct)
1856 free_page((unsigned long)sp->gfns);
1857 kmem_cache_free(mmu_page_header_cache, sp);
1860 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1862 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1865 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1866 struct kvm_mmu_page *sp, u64 *parent_pte)
1871 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1874 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1877 pte_list_remove(parent_pte, &sp->parent_ptes);
1880 static void drop_parent_pte(struct kvm_mmu_page *sp,
1883 mmu_page_remove_parent_pte(sp, parent_pte);
1884 mmu_spte_clear_no_track(parent_pte);
1887 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1889 struct kvm_mmu_page *sp;
1891 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1892 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1894 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1895 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1898 * The active_mmu_pages list is the FIFO list, do not move the
1899 * page until it is zapped. kvm_zap_obsolete_pages depends on
1900 * this feature. See the comments in kvm_zap_obsolete_pages().
1902 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1903 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1907 static void mark_unsync(u64 *spte);
1908 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1911 struct rmap_iterator iter;
1913 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1918 static void mark_unsync(u64 *spte)
1920 struct kvm_mmu_page *sp;
1923 sp = page_header(__pa(spte));
1924 index = spte - sp->spt;
1925 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1927 if (sp->unsync_children++)
1929 kvm_mmu_mark_parents_unsync(sp);
1932 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1933 struct kvm_mmu_page *sp)
1938 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1942 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1943 struct kvm_mmu_page *sp, u64 *spte,
1949 #define KVM_PAGE_ARRAY_NR 16
1951 struct kvm_mmu_pages {
1952 struct mmu_page_and_offset {
1953 struct kvm_mmu_page *sp;
1955 } page[KVM_PAGE_ARRAY_NR];
1959 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1965 for (i=0; i < pvec->nr; i++)
1966 if (pvec->page[i].sp == sp)
1969 pvec->page[pvec->nr].sp = sp;
1970 pvec->page[pvec->nr].idx = idx;
1972 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1975 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1977 --sp->unsync_children;
1978 WARN_ON((int)sp->unsync_children < 0);
1979 __clear_bit(idx, sp->unsync_child_bitmap);
1982 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1983 struct kvm_mmu_pages *pvec)
1985 int i, ret, nr_unsync_leaf = 0;
1987 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1988 struct kvm_mmu_page *child;
1989 u64 ent = sp->spt[i];
1991 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1992 clear_unsync_child_bit(sp, i);
1996 child = page_header(ent & PT64_BASE_ADDR_MASK);
1998 if (child->unsync_children) {
1999 if (mmu_pages_add(pvec, child, i))
2002 ret = __mmu_unsync_walk(child, pvec);
2004 clear_unsync_child_bit(sp, i);
2006 } else if (ret > 0) {
2007 nr_unsync_leaf += ret;
2010 } else if (child->unsync) {
2012 if (mmu_pages_add(pvec, child, i))
2015 clear_unsync_child_bit(sp, i);
2018 return nr_unsync_leaf;
2021 #define INVALID_INDEX (-1)
2023 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
2024 struct kvm_mmu_pages *pvec)
2027 if (!sp->unsync_children)
2030 mmu_pages_add(pvec, sp, INVALID_INDEX);
2031 return __mmu_unsync_walk(sp, pvec);
2034 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
2036 WARN_ON(!sp->unsync);
2037 trace_kvm_mmu_sync_page(sp);
2039 --kvm->stat.mmu_unsync;
2042 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2043 struct list_head *invalid_list);
2044 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2045 struct list_head *invalid_list);
2048 * NOTE: we should pay more attention on the zapped-obsolete page
2049 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
2050 * since it has been deleted from active_mmu_pages but still can be found
2053 * for_each_valid_sp() has skipped that kind of pages.
2055 #define for_each_valid_sp(_kvm, _sp, _gfn) \
2056 hlist_for_each_entry(_sp, \
2057 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2058 if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \
2061 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
2062 for_each_valid_sp(_kvm, _sp, _gfn) \
2063 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2065 /* @sp->gfn should be write-protected at the call site */
2066 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2067 struct list_head *invalid_list)
2069 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
2070 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
2074 if (vcpu->arch.mmu.sync_page(vcpu, sp) == 0) {
2075 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
2082 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
2083 struct list_head *invalid_list,
2084 bool remote_flush, bool local_flush)
2086 if (!list_empty(invalid_list)) {
2087 kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list);
2092 kvm_flush_remote_tlbs(vcpu->kvm);
2093 else if (local_flush)
2094 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2097 #ifdef CONFIG_KVM_MMU_AUDIT
2098 #include "mmu_audit.c"
2100 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
2101 static void mmu_audit_disable(void) { }
2104 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
2106 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
2109 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2110 struct list_head *invalid_list)
2112 kvm_unlink_unsync_page(vcpu->kvm, sp);
2113 return __kvm_sync_page(vcpu, sp, invalid_list);
2116 /* @gfn should be write-protected at the call site */
2117 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
2118 struct list_head *invalid_list)
2120 struct kvm_mmu_page *s;
2123 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2127 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2128 ret |= kvm_sync_page(vcpu, s, invalid_list);
2134 struct mmu_page_path {
2135 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL];
2136 unsigned int idx[PT64_ROOT_LEVEL];
2139 #define for_each_sp(pvec, sp, parents, i) \
2140 for (i = mmu_pages_first(&pvec, &parents); \
2141 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2142 i = mmu_pages_next(&pvec, &parents, i))
2144 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2145 struct mmu_page_path *parents,
2150 for (n = i+1; n < pvec->nr; n++) {
2151 struct kvm_mmu_page *sp = pvec->page[n].sp;
2152 unsigned idx = pvec->page[n].idx;
2153 int level = sp->role.level;
2155 parents->idx[level-1] = idx;
2156 if (level == PT_PAGE_TABLE_LEVEL)
2159 parents->parent[level-2] = sp;
2165 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2166 struct mmu_page_path *parents)
2168 struct kvm_mmu_page *sp;
2174 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2176 sp = pvec->page[0].sp;
2177 level = sp->role.level;
2178 WARN_ON(level == PT_PAGE_TABLE_LEVEL);
2180 parents->parent[level-2] = sp;
2182 /* Also set up a sentinel. Further entries in pvec are all
2183 * children of sp, so this element is never overwritten.
2185 parents->parent[level-1] = NULL;
2186 return mmu_pages_next(pvec, parents, 0);
2189 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2191 struct kvm_mmu_page *sp;
2192 unsigned int level = 0;
2195 unsigned int idx = parents->idx[level];
2196 sp = parents->parent[level];
2200 WARN_ON(idx == INVALID_INDEX);
2201 clear_unsync_child_bit(sp, idx);
2203 } while (!sp->unsync_children);
2206 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2207 struct kvm_mmu_page *parent)
2210 struct kvm_mmu_page *sp;
2211 struct mmu_page_path parents;
2212 struct kvm_mmu_pages pages;
2213 LIST_HEAD(invalid_list);
2216 while (mmu_unsync_walk(parent, &pages)) {
2217 bool protected = false;
2219 for_each_sp(pages, sp, parents, i)
2220 protected |= rmap_write_protect(vcpu, sp->gfn);
2223 kvm_flush_remote_tlbs(vcpu->kvm);
2227 for_each_sp(pages, sp, parents, i) {
2228 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2229 mmu_pages_clear_parents(&parents);
2231 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2232 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2233 cond_resched_lock(&vcpu->kvm->mmu_lock);
2238 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2241 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2243 atomic_set(&sp->write_flooding_count, 0);
2246 static void clear_sp_write_flooding_count(u64 *spte)
2248 struct kvm_mmu_page *sp = page_header(__pa(spte));
2250 __clear_sp_write_flooding_count(sp);
2253 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2260 union kvm_mmu_page_role role;
2262 struct kvm_mmu_page *sp;
2263 bool need_sync = false;
2266 LIST_HEAD(invalid_list);
2268 role = vcpu->arch.mmu.base_role;
2270 role.direct = direct;
2273 role.access = access;
2274 if (!vcpu->arch.mmu.direct_map
2275 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
2276 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2277 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2278 role.quadrant = quadrant;
2280 for_each_valid_sp(vcpu->kvm, sp, gfn) {
2281 if (sp->gfn != gfn) {
2286 if (!need_sync && sp->unsync)
2289 if (sp->role.word != role.word)
2293 /* The page is good, but __kvm_sync_page might still end
2294 * up zapping it. If so, break in order to rebuild it.
2296 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2299 WARN_ON(!list_empty(&invalid_list));
2300 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2303 if (sp->unsync_children)
2304 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2306 __clear_sp_write_flooding_count(sp);
2307 trace_kvm_mmu_get_page(sp, false);
2311 ++vcpu->kvm->stat.mmu_cache_miss;
2313 sp = kvm_mmu_alloc_page(vcpu, direct);
2317 hlist_add_head(&sp->hash_link,
2318 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2321 * we should do write protection before syncing pages
2322 * otherwise the content of the synced shadow page may
2323 * be inconsistent with guest page table.
2325 account_shadowed(vcpu->kvm, sp);
2326 if (level == PT_PAGE_TABLE_LEVEL &&
2327 rmap_write_protect(vcpu, gfn))
2328 kvm_flush_remote_tlbs(vcpu->kvm);
2330 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2331 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2333 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2334 clear_page(sp->spt);
2335 trace_kvm_mmu_get_page(sp, true);
2337 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2339 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2340 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2344 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2345 struct kvm_vcpu *vcpu, u64 addr)
2347 iterator->addr = addr;
2348 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
2349 iterator->level = vcpu->arch.mmu.shadow_root_level;
2351 if (iterator->level == PT64_ROOT_LEVEL &&
2352 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
2353 !vcpu->arch.mmu.direct_map)
2356 if (iterator->level == PT32E_ROOT_LEVEL) {
2357 iterator->shadow_addr
2358 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2359 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2361 if (!iterator->shadow_addr)
2362 iterator->level = 0;
2366 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2368 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2371 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2372 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2376 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2379 if (is_last_spte(spte, iterator->level)) {
2380 iterator->level = 0;
2384 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2388 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2390 return __shadow_walk_next(iterator, *iterator->sptep);
2393 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2394 struct kvm_mmu_page *sp)
2398 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2400 spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK |
2401 shadow_user_mask | shadow_x_mask | shadow_accessed_mask;
2403 mmu_spte_set(sptep, spte);
2405 mmu_page_add_parent_pte(vcpu, sp, sptep);
2407 if (sp->unsync_children || sp->unsync)
2411 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2412 unsigned direct_access)
2414 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2415 struct kvm_mmu_page *child;
2418 * For the direct sp, if the guest pte's dirty bit
2419 * changed form clean to dirty, it will corrupt the
2420 * sp's access: allow writable in the read-only sp,
2421 * so we should update the spte at this point to get
2422 * a new sp with the correct access.
2424 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2425 if (child->role.access == direct_access)
2428 drop_parent_pte(child, sptep);
2429 kvm_flush_remote_tlbs(vcpu->kvm);
2433 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2437 struct kvm_mmu_page *child;
2440 if (is_shadow_present_pte(pte)) {
2441 if (is_last_spte(pte, sp->role.level)) {
2442 drop_spte(kvm, spte);
2443 if (is_large_pte(pte))
2446 child = page_header(pte & PT64_BASE_ADDR_MASK);
2447 drop_parent_pte(child, spte);
2452 if (is_mmio_spte(pte))
2453 mmu_spte_clear_no_track(spte);
2458 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2459 struct kvm_mmu_page *sp)
2463 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2464 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2467 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2470 struct rmap_iterator iter;
2472 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2473 drop_parent_pte(sp, sptep);
2476 static int mmu_zap_unsync_children(struct kvm *kvm,
2477 struct kvm_mmu_page *parent,
2478 struct list_head *invalid_list)
2481 struct mmu_page_path parents;
2482 struct kvm_mmu_pages pages;
2484 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2487 while (mmu_unsync_walk(parent, &pages)) {
2488 struct kvm_mmu_page *sp;
2490 for_each_sp(pages, sp, parents, i) {
2491 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2492 mmu_pages_clear_parents(&parents);
2500 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2501 struct list_head *invalid_list)
2505 trace_kvm_mmu_prepare_zap_page(sp);
2506 ++kvm->stat.mmu_shadow_zapped;
2507 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2508 kvm_mmu_page_unlink_children(kvm, sp);
2509 kvm_mmu_unlink_parents(kvm, sp);
2511 if (!sp->role.invalid && !sp->role.direct)
2512 unaccount_shadowed(kvm, sp);
2515 kvm_unlink_unsync_page(kvm, sp);
2516 if (!sp->root_count) {
2519 list_move(&sp->link, invalid_list);
2520 kvm_mod_used_mmu_pages(kvm, -1);
2522 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2525 * The obsolete pages can not be used on any vcpus.
2526 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2528 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2529 kvm_reload_remote_mmus(kvm);
2532 sp->role.invalid = 1;
2536 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2537 struct list_head *invalid_list)
2539 struct kvm_mmu_page *sp, *nsp;
2541 if (list_empty(invalid_list))
2545 * We need to make sure everyone sees our modifications to
2546 * the page tables and see changes to vcpu->mode here. The barrier
2547 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2548 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2550 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2551 * guest mode and/or lockless shadow page table walks.
2553 kvm_flush_remote_tlbs(kvm);
2555 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2556 WARN_ON(!sp->role.invalid || sp->root_count);
2557 kvm_mmu_free_page(sp);
2561 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2562 struct list_head *invalid_list)
2564 struct kvm_mmu_page *sp;
2566 if (list_empty(&kvm->arch.active_mmu_pages))
2569 sp = list_last_entry(&kvm->arch.active_mmu_pages,
2570 struct kvm_mmu_page, link);
2571 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2577 * Changing the number of mmu pages allocated to the vm
2578 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2580 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2582 LIST_HEAD(invalid_list);
2584 spin_lock(&kvm->mmu_lock);
2586 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2587 /* Need to free some mmu pages to achieve the goal. */
2588 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2589 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2592 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2593 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2596 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2598 spin_unlock(&kvm->mmu_lock);
2601 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2603 struct kvm_mmu_page *sp;
2604 LIST_HEAD(invalid_list);
2607 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2609 spin_lock(&kvm->mmu_lock);
2610 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2611 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2614 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2616 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2617 spin_unlock(&kvm->mmu_lock);
2621 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2623 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2625 trace_kvm_mmu_unsync_page(sp);
2626 ++vcpu->kvm->stat.mmu_unsync;
2629 kvm_mmu_mark_parents_unsync(sp);
2632 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2635 struct kvm_mmu_page *sp;
2637 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2640 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2647 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
2648 kvm_unsync_page(vcpu, sp);
2654 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
2657 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn));
2662 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2663 unsigned pte_access, int level,
2664 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2665 bool can_unsync, bool host_writable)
2670 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2674 * For the EPT case, shadow_present_mask is 0 if hardware
2675 * supports exec-only page table entries. In that case,
2676 * ACC_USER_MASK and shadow_user_mask are used to represent
2677 * read access. See FNAME(gpte_access) in paging_tmpl.h.
2679 spte |= shadow_present_mask;
2681 spte |= shadow_accessed_mask;
2683 if (pte_access & ACC_EXEC_MASK)
2684 spte |= shadow_x_mask;
2686 spte |= shadow_nx_mask;
2688 if (pte_access & ACC_USER_MASK)
2689 spte |= shadow_user_mask;
2691 if (level > PT_PAGE_TABLE_LEVEL)
2692 spte |= PT_PAGE_SIZE_MASK;
2694 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2695 kvm_is_mmio_pfn(pfn));
2698 spte |= SPTE_HOST_WRITEABLE;
2700 pte_access &= ~ACC_WRITE_MASK;
2702 spte |= (u64)pfn << PAGE_SHIFT;
2704 if (pte_access & ACC_WRITE_MASK) {
2707 * Other vcpu creates new sp in the window between
2708 * mapping_level() and acquiring mmu-lock. We can
2709 * allow guest to retry the access, the mapping can
2710 * be fixed if guest refault.
2712 if (level > PT_PAGE_TABLE_LEVEL &&
2713 mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
2716 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2719 * Optimization: for pte sync, if spte was writable the hash
2720 * lookup is unnecessary (and expensive). Write protection
2721 * is responsibility of mmu_get_page / kvm_sync_page.
2722 * Same reasoning can be applied to dirty page accounting.
2724 if (!can_unsync && is_writable_pte(*sptep))
2727 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2728 pgprintk("%s: found shadow page for %llx, marking ro\n",
2731 pte_access &= ~ACC_WRITE_MASK;
2732 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2736 if (pte_access & ACC_WRITE_MASK) {
2737 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2738 spte |= shadow_dirty_mask;
2742 spte = mark_spte_for_access_track(spte);
2745 if (mmu_spte_update(sptep, spte))
2746 kvm_flush_remote_tlbs(vcpu->kvm);
2751 static bool mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
2752 int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
2753 bool speculative, bool host_writable)
2755 int was_rmapped = 0;
2757 bool emulate = false;
2759 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2760 *sptep, write_fault, gfn);
2762 if (is_shadow_present_pte(*sptep)) {
2764 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2765 * the parent of the now unreachable PTE.
2767 if (level > PT_PAGE_TABLE_LEVEL &&
2768 !is_large_pte(*sptep)) {
2769 struct kvm_mmu_page *child;
2772 child = page_header(pte & PT64_BASE_ADDR_MASK);
2773 drop_parent_pte(child, sptep);
2774 kvm_flush_remote_tlbs(vcpu->kvm);
2775 } else if (pfn != spte_to_pfn(*sptep)) {
2776 pgprintk("hfn old %llx new %llx\n",
2777 spte_to_pfn(*sptep), pfn);
2778 drop_spte(vcpu->kvm, sptep);
2779 kvm_flush_remote_tlbs(vcpu->kvm);
2784 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2785 true, host_writable)) {
2788 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2791 if (unlikely(is_mmio_spte(*sptep)))
2794 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2795 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2796 is_large_pte(*sptep)? "2MB" : "4kB",
2797 *sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn,
2799 if (!was_rmapped && is_large_pte(*sptep))
2800 ++vcpu->kvm->stat.lpages;
2802 if (is_shadow_present_pte(*sptep)) {
2804 rmap_count = rmap_add(vcpu, sptep, gfn);
2805 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2806 rmap_recycle(vcpu, sptep, gfn);
2810 kvm_release_pfn_clean(pfn);
2815 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2818 struct kvm_memory_slot *slot;
2820 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2822 return KVM_PFN_ERR_FAULT;
2824 return gfn_to_pfn_memslot_atomic(slot, gfn);
2827 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2828 struct kvm_mmu_page *sp,
2829 u64 *start, u64 *end)
2831 struct page *pages[PTE_PREFETCH_NUM];
2832 struct kvm_memory_slot *slot;
2833 unsigned access = sp->role.access;
2837 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2838 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2842 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2846 for (i = 0; i < ret; i++, gfn++, start++)
2847 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
2848 page_to_pfn(pages[i]), true, true);
2853 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2854 struct kvm_mmu_page *sp, u64 *sptep)
2856 u64 *spte, *start = NULL;
2859 WARN_ON(!sp->role.direct);
2861 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2864 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2865 if (is_shadow_present_pte(*spte) || spte == sptep) {
2868 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2876 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2878 struct kvm_mmu_page *sp;
2881 * Since it's no accessed bit on EPT, it's no way to
2882 * distinguish between actually accessed translations
2883 * and prefetched, so disable pte prefetch if EPT is
2886 if (!shadow_accessed_mask)
2889 sp = page_header(__pa(sptep));
2890 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2893 __direct_pte_prefetch(vcpu, sp, sptep);
2896 static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable,
2897 int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault)
2899 struct kvm_shadow_walk_iterator iterator;
2900 struct kvm_mmu_page *sp;
2904 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2907 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2908 if (iterator.level == level) {
2909 emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2910 write, level, gfn, pfn, prefault,
2912 direct_pte_prefetch(vcpu, iterator.sptep);
2913 ++vcpu->stat.pf_fixed;
2917 drop_large_spte(vcpu, iterator.sptep);
2918 if (!is_shadow_present_pte(*iterator.sptep)) {
2919 u64 base_addr = iterator.addr;
2921 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2922 pseudo_gfn = base_addr >> PAGE_SHIFT;
2923 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2924 iterator.level - 1, 1, ACC_ALL);
2926 link_shadow_page(vcpu, iterator.sptep, sp);
2932 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2936 info.si_signo = SIGBUS;
2938 info.si_code = BUS_MCEERR_AR;
2939 info.si_addr = (void __user *)address;
2940 info.si_addr_lsb = PAGE_SHIFT;
2942 send_sig_info(SIGBUS, &info, tsk);
2945 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2948 * Do not cache the mmio info caused by writing the readonly gfn
2949 * into the spte otherwise read access on readonly gfn also can
2950 * caused mmio page fault and treat it as mmio access.
2951 * Return 1 to tell kvm to emulate it.
2953 if (pfn == KVM_PFN_ERR_RO_FAULT)
2956 if (pfn == KVM_PFN_ERR_HWPOISON) {
2957 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2964 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2965 gfn_t *gfnp, kvm_pfn_t *pfnp,
2968 kvm_pfn_t pfn = *pfnp;
2970 int level = *levelp;
2973 * Check if it's a transparent hugepage. If this would be an
2974 * hugetlbfs page, level wouldn't be set to
2975 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2978 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
2979 level == PT_PAGE_TABLE_LEVEL &&
2980 PageTransCompoundMap(pfn_to_page(pfn)) &&
2981 !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
2984 * mmu_notifier_retry was successful and we hold the
2985 * mmu_lock here, so the pmd can't become splitting
2986 * from under us, and in turn
2987 * __split_huge_page_refcount() can't run from under
2988 * us and we can safely transfer the refcount from
2989 * PG_tail to PG_head as we switch the pfn to tail to
2992 *levelp = level = PT_DIRECTORY_LEVEL;
2993 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2994 VM_BUG_ON((gfn & mask) != (pfn & mask));
2998 kvm_release_pfn_clean(pfn);
3006 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
3007 kvm_pfn_t pfn, unsigned access, int *ret_val)
3009 /* The pfn is invalid, report the error! */
3010 if (unlikely(is_error_pfn(pfn))) {
3011 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
3015 if (unlikely(is_noslot_pfn(pfn)))
3016 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
3021 static bool page_fault_can_be_fast(u32 error_code)
3024 * Do not fix the mmio spte with invalid generation number which
3025 * need to be updated by slow page fault path.
3027 if (unlikely(error_code & PFERR_RSVD_MASK))
3030 /* See if the page fault is due to an NX violation */
3031 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3032 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3036 * #PF can be fast if:
3037 * 1. The shadow page table entry is not present, which could mean that
3038 * the fault is potentially caused by access tracking (if enabled).
3039 * 2. The shadow page table entry is present and the fault
3040 * is caused by write-protect, that means we just need change the W
3041 * bit of the spte which can be done out of mmu-lock.
3043 * However, if access tracking is disabled we know that a non-present
3044 * page must be a genuine page fault where we have to create a new SPTE.
3045 * So, if access tracking is disabled, we return true only for write
3046 * accesses to a present page.
3049 return shadow_acc_track_mask != 0 ||
3050 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3051 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3055 * Returns true if the SPTE was fixed successfully. Otherwise,
3056 * someone else modified the SPTE from its original value.
3059 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3060 u64 *sptep, u64 old_spte, u64 new_spte)
3064 WARN_ON(!sp->role.direct);
3067 * Theoretically we could also set dirty bit (and flush TLB) here in
3068 * order to eliminate unnecessary PML logging. See comments in
3069 * set_spte. But fast_page_fault is very unlikely to happen with PML
3070 * enabled, so we do not do this. This might result in the same GPA
3071 * to be logged in PML buffer again when the write really happens, and
3072 * eventually to be called by mark_page_dirty twice. But it's also no
3073 * harm. This also avoids the TLB flush needed after setting dirty bit
3074 * so non-PML cases won't be impacted.
3076 * Compare with set_spte where instead shadow_dirty_mask is set.
3078 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3081 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3083 * The gfn of direct spte is stable since it is
3084 * calculated by sp->gfn.
3086 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3087 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3093 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3095 if (fault_err_code & PFERR_FETCH_MASK)
3096 return is_executable_pte(spte);
3098 if (fault_err_code & PFERR_WRITE_MASK)
3099 return is_writable_pte(spte);
3101 /* Fault was on Read access */
3102 return spte & PT_PRESENT_MASK;
3107 * - true: let the vcpu to access on the same address again.
3108 * - false: let the real page fault path to fix it.
3110 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
3113 struct kvm_shadow_walk_iterator iterator;
3114 struct kvm_mmu_page *sp;
3115 bool fault_handled = false;
3117 uint retry_count = 0;
3119 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3122 if (!page_fault_can_be_fast(error_code))
3125 walk_shadow_page_lockless_begin(vcpu);
3130 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
3131 if (!is_shadow_present_pte(spte) ||
3132 iterator.level < level)
3135 sp = page_header(__pa(iterator.sptep));
3136 if (!is_last_spte(spte, sp->role.level))
3140 * Check whether the memory access that caused the fault would
3141 * still cause it if it were to be performed right now. If not,
3142 * then this is a spurious fault caused by TLB lazily flushed,
3143 * or some other CPU has already fixed the PTE after the
3144 * current CPU took the fault.
3146 * Need not check the access of upper level table entries since
3147 * they are always ACC_ALL.
3149 if (is_access_allowed(error_code, spte)) {
3150 fault_handled = true;
3156 if (is_access_track_spte(spte))
3157 new_spte = restore_acc_track_spte(new_spte);
3160 * Currently, to simplify the code, write-protection can
3161 * be removed in the fast path only if the SPTE was
3162 * write-protected for dirty-logging or access tracking.
3164 if ((error_code & PFERR_WRITE_MASK) &&
3165 spte_can_locklessly_be_made_writable(spte))
3167 new_spte |= PT_WRITABLE_MASK;
3170 * Do not fix write-permission on the large spte. Since
3171 * we only dirty the first page into the dirty-bitmap in
3172 * fast_pf_fix_direct_spte(), other pages are missed
3173 * if its slot has dirty logging enabled.
3175 * Instead, we let the slow page fault path create a
3176 * normal spte to fix the access.
3178 * See the comments in kvm_arch_commit_memory_region().
3180 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3184 /* Verify that the fault can be handled in the fast path */
3185 if (new_spte == spte ||
3186 !is_access_allowed(error_code, new_spte))
3190 * Currently, fast page fault only works for direct mapping
3191 * since the gfn is not stable for indirect shadow page. See
3192 * Documentation/virtual/kvm/locking.txt to get more detail.
3194 fault_handled = fast_pf_fix_direct_spte(vcpu, sp,
3195 iterator.sptep, spte,
3200 if (++retry_count > 4) {
3201 printk_once(KERN_WARNING
3202 "kvm: Fast #PF retrying more than 4 times.\n");
3208 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
3209 spte, fault_handled);
3210 walk_shadow_page_lockless_end(vcpu);
3212 return fault_handled;
3215 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3216 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable);
3217 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
3219 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
3220 gfn_t gfn, bool prefault)
3224 bool force_pt_level = false;
3226 unsigned long mmu_seq;
3227 bool map_writable, write = error_code & PFERR_WRITE_MASK;
3229 level = mapping_level(vcpu, gfn, &force_pt_level);
3230 if (likely(!force_pt_level)) {
3232 * This path builds a PAE pagetable - so we can map
3233 * 2mb pages at maximum. Therefore check if the level
3234 * is larger than that.
3236 if (level > PT_DIRECTORY_LEVEL)
3237 level = PT_DIRECTORY_LEVEL;
3239 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3242 if (fast_page_fault(vcpu, v, level, error_code))
3245 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3248 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3251 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3254 spin_lock(&vcpu->kvm->mmu_lock);
3255 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3257 make_mmu_pages_available(vcpu);
3258 if (likely(!force_pt_level))
3259 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3260 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3261 spin_unlock(&vcpu->kvm->mmu_lock);
3266 spin_unlock(&vcpu->kvm->mmu_lock);
3267 kvm_release_pfn_clean(pfn);
3272 static void mmu_free_roots(struct kvm_vcpu *vcpu)
3275 struct kvm_mmu_page *sp;
3276 LIST_HEAD(invalid_list);
3278 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3281 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
3282 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
3283 vcpu->arch.mmu.direct_map)) {
3284 hpa_t root = vcpu->arch.mmu.root_hpa;
3286 spin_lock(&vcpu->kvm->mmu_lock);
3287 sp = page_header(root);
3289 if (!sp->root_count && sp->role.invalid) {
3290 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3291 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3293 spin_unlock(&vcpu->kvm->mmu_lock);
3294 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3298 spin_lock(&vcpu->kvm->mmu_lock);
3299 for (i = 0; i < 4; ++i) {
3300 hpa_t root = vcpu->arch.mmu.pae_root[i];
3303 root &= PT64_BASE_ADDR_MASK;
3304 sp = page_header(root);
3306 if (!sp->root_count && sp->role.invalid)
3307 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3310 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3312 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3313 spin_unlock(&vcpu->kvm->mmu_lock);
3314 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3317 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3321 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3322 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3329 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3331 struct kvm_mmu_page *sp;
3334 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3335 spin_lock(&vcpu->kvm->mmu_lock);
3336 make_mmu_pages_available(vcpu);
3337 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, 1, ACC_ALL);
3339 spin_unlock(&vcpu->kvm->mmu_lock);
3340 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3341 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3342 for (i = 0; i < 4; ++i) {
3343 hpa_t root = vcpu->arch.mmu.pae_root[i];
3345 MMU_WARN_ON(VALID_PAGE(root));
3346 spin_lock(&vcpu->kvm->mmu_lock);
3347 make_mmu_pages_available(vcpu);
3348 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3349 i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3350 root = __pa(sp->spt);
3352 spin_unlock(&vcpu->kvm->mmu_lock);
3353 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3355 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3362 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3364 struct kvm_mmu_page *sp;
3369 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3371 if (mmu_check_root(vcpu, root_gfn))
3375 * Do we shadow a long mode page table? If so we need to
3376 * write-protect the guests page table root.
3378 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3379 hpa_t root = vcpu->arch.mmu.root_hpa;
3381 MMU_WARN_ON(VALID_PAGE(root));
3383 spin_lock(&vcpu->kvm->mmu_lock);
3384 make_mmu_pages_available(vcpu);
3385 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3387 root = __pa(sp->spt);
3389 spin_unlock(&vcpu->kvm->mmu_lock);
3390 vcpu->arch.mmu.root_hpa = root;
3395 * We shadow a 32 bit page table. This may be a legacy 2-level
3396 * or a PAE 3-level page table. In either case we need to be aware that
3397 * the shadow page table may be a PAE or a long mode page table.
3399 pm_mask = PT_PRESENT_MASK;
3400 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3401 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3403 for (i = 0; i < 4; ++i) {
3404 hpa_t root = vcpu->arch.mmu.pae_root[i];
3406 MMU_WARN_ON(VALID_PAGE(root));
3407 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3408 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3409 if (!(pdptr & PT_PRESENT_MASK)) {
3410 vcpu->arch.mmu.pae_root[i] = 0;
3413 root_gfn = pdptr >> PAGE_SHIFT;
3414 if (mmu_check_root(vcpu, root_gfn))
3417 spin_lock(&vcpu->kvm->mmu_lock);
3418 make_mmu_pages_available(vcpu);
3419 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3421 root = __pa(sp->spt);
3423 spin_unlock(&vcpu->kvm->mmu_lock);
3425 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3427 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3430 * If we shadow a 32 bit page table with a long mode page
3431 * table we enter this path.
3433 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3434 if (vcpu->arch.mmu.lm_root == NULL) {
3436 * The additional page necessary for this is only
3437 * allocated on demand.
3442 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3443 if (lm_root == NULL)
3446 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3448 vcpu->arch.mmu.lm_root = lm_root;
3451 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3457 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3459 if (vcpu->arch.mmu.direct_map)
3460 return mmu_alloc_direct_roots(vcpu);
3462 return mmu_alloc_shadow_roots(vcpu);
3465 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3468 struct kvm_mmu_page *sp;
3470 if (vcpu->arch.mmu.direct_map)
3473 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3476 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3477 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3478 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3479 hpa_t root = vcpu->arch.mmu.root_hpa;
3480 sp = page_header(root);
3481 mmu_sync_children(vcpu, sp);
3482 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3485 for (i = 0; i < 4; ++i) {
3486 hpa_t root = vcpu->arch.mmu.pae_root[i];
3488 if (root && VALID_PAGE(root)) {
3489 root &= PT64_BASE_ADDR_MASK;
3490 sp = page_header(root);
3491 mmu_sync_children(vcpu, sp);
3494 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3497 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3499 spin_lock(&vcpu->kvm->mmu_lock);
3500 mmu_sync_roots(vcpu);
3501 spin_unlock(&vcpu->kvm->mmu_lock);
3503 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3505 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3506 u32 access, struct x86_exception *exception)
3509 exception->error_code = 0;
3513 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3515 struct x86_exception *exception)
3518 exception->error_code = 0;
3519 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3523 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3525 int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3527 return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3528 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3531 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3533 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3536 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3538 return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3541 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3544 return vcpu_match_mmio_gpa(vcpu, addr);
3546 return vcpu_match_mmio_gva(vcpu, addr);
3549 /* return true if reserved bit is detected on spte. */
3551 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3553 struct kvm_shadow_walk_iterator iterator;
3554 u64 sptes[PT64_ROOT_LEVEL], spte = 0ull;
3556 bool reserved = false;
3558 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3561 walk_shadow_page_lockless_begin(vcpu);
3563 for (shadow_walk_init(&iterator, vcpu, addr),
3564 leaf = root = iterator.level;
3565 shadow_walk_okay(&iterator);
3566 __shadow_walk_next(&iterator, spte)) {
3567 spte = mmu_spte_get_lockless(iterator.sptep);
3569 sptes[leaf - 1] = spte;
3572 if (!is_shadow_present_pte(spte))
3575 reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte,
3579 walk_shadow_page_lockless_end(vcpu);
3582 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3584 while (root > leaf) {
3585 pr_err("------ spte 0x%llx level %d.\n",
3586 sptes[root - 1], root);
3595 int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3600 if (mmio_info_in_cache(vcpu, addr, direct))
3601 return RET_MMIO_PF_EMULATE;
3603 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3604 if (WARN_ON(reserved))
3605 return RET_MMIO_PF_BUG;
3607 if (is_mmio_spte(spte)) {
3608 gfn_t gfn = get_mmio_spte_gfn(spte);
3609 unsigned access = get_mmio_spte_access(spte);
3611 if (!check_mmio_spte(vcpu, spte))
3612 return RET_MMIO_PF_INVALID;
3617 trace_handle_mmio_page_fault(addr, gfn, access);
3618 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3619 return RET_MMIO_PF_EMULATE;
3623 * If the page table is zapped by other cpus, let CPU fault again on
3626 return RET_MMIO_PF_RETRY;
3628 EXPORT_SYMBOL_GPL(handle_mmio_page_fault);
3630 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3631 u32 error_code, gfn_t gfn)
3633 if (unlikely(error_code & PFERR_RSVD_MASK))
3636 if (!(error_code & PFERR_PRESENT_MASK) ||
3637 !(error_code & PFERR_WRITE_MASK))
3641 * guest is writing the page which is write tracked which can
3642 * not be fixed by page fault handler.
3644 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3650 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3652 struct kvm_shadow_walk_iterator iterator;
3655 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3658 walk_shadow_page_lockless_begin(vcpu);
3659 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3660 clear_sp_write_flooding_count(iterator.sptep);
3661 if (!is_shadow_present_pte(spte))
3664 walk_shadow_page_lockless_end(vcpu);
3667 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3668 u32 error_code, bool prefault)
3670 gfn_t gfn = gva >> PAGE_SHIFT;
3673 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3675 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3678 r = mmu_topup_memory_caches(vcpu);
3682 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3685 return nonpaging_map(vcpu, gva & PAGE_MASK,
3686 error_code, gfn, prefault);
3689 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3691 struct kvm_arch_async_pf arch;
3693 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3695 arch.direct_map = vcpu->arch.mmu.direct_map;
3696 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3698 return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3701 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
3703 if (unlikely(!lapic_in_kernel(vcpu) ||
3704 kvm_event_needs_reinjection(vcpu)))
3707 if (is_guest_mode(vcpu))
3710 return kvm_x86_ops->interrupt_allowed(vcpu);
3713 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3714 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable)
3716 struct kvm_memory_slot *slot;
3719 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3721 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3723 return false; /* *pfn has correct page already */
3725 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3726 trace_kvm_try_async_get_page(gva, gfn);
3727 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3728 trace_kvm_async_pf_doublefault(gva, gfn);
3729 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3731 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3735 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3740 check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
3742 int page_num = KVM_PAGES_PER_HPAGE(level);
3744 gfn &= ~(page_num - 1);
3746 return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
3749 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3755 bool force_pt_level;
3756 gfn_t gfn = gpa >> PAGE_SHIFT;
3757 unsigned long mmu_seq;
3758 int write = error_code & PFERR_WRITE_MASK;
3761 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3763 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3766 r = mmu_topup_memory_caches(vcpu);
3770 force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn,
3771 PT_DIRECTORY_LEVEL);
3772 level = mapping_level(vcpu, gfn, &force_pt_level);
3773 if (likely(!force_pt_level)) {
3774 if (level > PT_DIRECTORY_LEVEL &&
3775 !check_hugepage_cache_consistency(vcpu, gfn, level))
3776 level = PT_DIRECTORY_LEVEL;
3777 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3780 if (fast_page_fault(vcpu, gpa, level, error_code))
3783 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3786 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3789 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3792 spin_lock(&vcpu->kvm->mmu_lock);
3793 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3795 make_mmu_pages_available(vcpu);
3796 if (likely(!force_pt_level))
3797 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3798 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3799 spin_unlock(&vcpu->kvm->mmu_lock);
3804 spin_unlock(&vcpu->kvm->mmu_lock);
3805 kvm_release_pfn_clean(pfn);
3809 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3810 struct kvm_mmu *context)
3812 context->page_fault = nonpaging_page_fault;
3813 context->gva_to_gpa = nonpaging_gva_to_gpa;
3814 context->sync_page = nonpaging_sync_page;
3815 context->invlpg = nonpaging_invlpg;
3816 context->update_pte = nonpaging_update_pte;
3817 context->root_level = 0;
3818 context->shadow_root_level = PT32E_ROOT_LEVEL;
3819 context->root_hpa = INVALID_PAGE;
3820 context->direct_map = true;
3821 context->nx = false;
3824 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
3826 mmu_free_roots(vcpu);
3829 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3831 return kvm_read_cr3(vcpu);
3834 static void inject_page_fault(struct kvm_vcpu *vcpu,
3835 struct x86_exception *fault)
3837 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3840 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
3841 unsigned access, int *nr_present)
3843 if (unlikely(is_mmio_spte(*sptep))) {
3844 if (gfn != get_mmio_spte_gfn(*sptep)) {
3845 mmu_spte_clear_no_track(sptep);
3850 mark_mmio_spte(vcpu, sptep, gfn, access);
3857 static inline bool is_last_gpte(struct kvm_mmu *mmu,
3858 unsigned level, unsigned gpte)
3861 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
3862 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
3863 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
3865 gpte |= level - PT_PAGE_TABLE_LEVEL - 1;
3868 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3869 * If it is clear, there are no large pages at this level, so clear
3870 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3872 gpte &= level - mmu->last_nonleaf_level;
3874 return gpte & PT_PAGE_SIZE_MASK;
3877 #define PTTYPE_EPT 18 /* arbitrary */
3878 #define PTTYPE PTTYPE_EPT
3879 #include "paging_tmpl.h"
3883 #include "paging_tmpl.h"
3887 #include "paging_tmpl.h"
3891 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3892 struct rsvd_bits_validate *rsvd_check,
3893 int maxphyaddr, int level, bool nx, bool gbpages,
3896 u64 exb_bit_rsvd = 0;
3897 u64 gbpages_bit_rsvd = 0;
3898 u64 nonleaf_bit8_rsvd = 0;
3900 rsvd_check->bad_mt_xwr = 0;
3903 exb_bit_rsvd = rsvd_bits(63, 63);
3905 gbpages_bit_rsvd = rsvd_bits(7, 7);
3908 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3909 * leaf entries) on AMD CPUs only.
3912 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
3915 case PT32_ROOT_LEVEL:
3916 /* no rsvd bits for 2 level 4K page table entries */
3917 rsvd_check->rsvd_bits_mask[0][1] = 0;
3918 rsvd_check->rsvd_bits_mask[0][0] = 0;
3919 rsvd_check->rsvd_bits_mask[1][0] =
3920 rsvd_check->rsvd_bits_mask[0][0];
3923 rsvd_check->rsvd_bits_mask[1][1] = 0;
3927 if (is_cpuid_PSE36())
3928 /* 36bits PSE 4MB page */
3929 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3931 /* 32 bits PSE 4MB page */
3932 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3934 case PT32E_ROOT_LEVEL:
3935 rsvd_check->rsvd_bits_mask[0][2] =
3936 rsvd_bits(maxphyaddr, 63) |
3937 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3938 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3939 rsvd_bits(maxphyaddr, 62); /* PDE */
3940 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3941 rsvd_bits(maxphyaddr, 62); /* PTE */
3942 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3943 rsvd_bits(maxphyaddr, 62) |
3944 rsvd_bits(13, 20); /* large page */
3945 rsvd_check->rsvd_bits_mask[1][0] =
3946 rsvd_check->rsvd_bits_mask[0][0];
3948 case PT64_ROOT_LEVEL:
3949 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3950 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
3951 rsvd_bits(maxphyaddr, 51);
3952 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3953 nonleaf_bit8_rsvd | gbpages_bit_rsvd |
3954 rsvd_bits(maxphyaddr, 51);
3955 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3956 rsvd_bits(maxphyaddr, 51);
3957 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3958 rsvd_bits(maxphyaddr, 51);
3959 rsvd_check->rsvd_bits_mask[1][3] =
3960 rsvd_check->rsvd_bits_mask[0][3];
3961 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3962 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
3964 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3965 rsvd_bits(maxphyaddr, 51) |
3966 rsvd_bits(13, 20); /* large page */
3967 rsvd_check->rsvd_bits_mask[1][0] =
3968 rsvd_check->rsvd_bits_mask[0][0];
3973 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3974 struct kvm_mmu *context)
3976 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
3977 cpuid_maxphyaddr(vcpu), context->root_level,
3978 context->nx, guest_cpuid_has_gbpages(vcpu),
3979 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
3983 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
3984 int maxphyaddr, bool execonly)
3988 rsvd_check->rsvd_bits_mask[0][3] =
3989 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
3990 rsvd_check->rsvd_bits_mask[0][2] =
3991 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3992 rsvd_check->rsvd_bits_mask[0][1] =
3993 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3994 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
3997 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
3998 rsvd_check->rsvd_bits_mask[1][2] =
3999 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
4000 rsvd_check->rsvd_bits_mask[1][1] =
4001 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
4002 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4004 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4005 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4006 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4007 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4008 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4010 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4011 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4013 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4016 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4017 struct kvm_mmu *context, bool execonly)
4019 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4020 cpuid_maxphyaddr(vcpu), execonly);
4024 * the page table on host is the shadow page table for the page
4025 * table in guest or amd nested guest, its mmu features completely
4026 * follow the features in guest.
4029 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4031 bool uses_nx = context->nx || context->base_role.smep_andnot_wp;
4034 * Passing "true" to the last argument is okay; it adds a check
4035 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4037 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
4038 boot_cpu_data.x86_phys_bits,
4039 context->shadow_root_level, uses_nx,
4040 guest_cpuid_has_gbpages(vcpu), is_pse(vcpu),
4043 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4045 static inline bool boot_cpu_is_amd(void)
4047 WARN_ON_ONCE(!tdp_enabled);
4048 return shadow_x_mask == 0;
4052 * the direct page table on host, use as much mmu features as
4053 * possible, however, kvm currently does not do execution-protection.
4056 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4057 struct kvm_mmu *context)
4059 if (boot_cpu_is_amd())
4060 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
4061 boot_cpu_data.x86_phys_bits,
4062 context->shadow_root_level, false,
4063 boot_cpu_has(X86_FEATURE_GBPAGES),
4066 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4067 boot_cpu_data.x86_phys_bits,
4073 * as the comments in reset_shadow_zero_bits_mask() except it
4074 * is the shadow page table for intel nested guest.
4077 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4078 struct kvm_mmu *context, bool execonly)
4080 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4081 boot_cpu_data.x86_phys_bits, execonly);
4084 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4085 struct kvm_mmu *mmu, bool ept)
4087 unsigned bit, byte, pfec;
4089 bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0;
4091 cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4092 cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4093 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4096 wf = pfec & PFERR_WRITE_MASK;
4097 uf = pfec & PFERR_USER_MASK;
4098 ff = pfec & PFERR_FETCH_MASK;
4100 * PFERR_RSVD_MASK bit is set in PFEC if the access is not
4101 * subject to SMAP restrictions, and cleared otherwise. The
4102 * bit is only meaningful if the SMAP bit is set in CR4.
4104 smapf = !(pfec & PFERR_RSVD_MASK);
4105 for (bit = 0; bit < 8; ++bit) {
4106 x = bit & ACC_EXEC_MASK;
4107 w = bit & ACC_WRITE_MASK;
4108 u = bit & ACC_USER_MASK;
4111 /* Not really needed: !nx will cause pte.nx to fault */
4113 /* Allow supervisor writes if !cr0.wp */
4114 w |= !is_write_protection(vcpu) && !uf;
4115 /* Disallow supervisor fetches of user code if cr4.smep */
4116 x &= !(cr4_smep && u && !uf);
4119 * SMAP:kernel-mode data accesses from user-mode
4120 * mappings should fault. A fault is considered
4121 * as a SMAP violation if all of the following
4122 * conditions are ture:
4123 * - X86_CR4_SMAP is set in CR4
4124 * - A user page is accessed
4125 * - Page fault in kernel mode
4126 * - if CPL = 3 or X86_EFLAGS_AC is clear
4128 * Here, we cover the first three conditions.
4129 * The fourth is computed dynamically in
4130 * permission_fault() and is in smapf.
4132 * Also, SMAP does not affect instruction
4133 * fetches, add the !ff check here to make it
4136 smap = cr4_smap && u && !uf && !ff;
4139 fault = (ff && !x) || (uf && !u) || (wf && !w) ||
4141 map |= fault << bit;
4143 mmu->permissions[byte] = map;
4148 * PKU is an additional mechanism by which the paging controls access to
4149 * user-mode addresses based on the value in the PKRU register. Protection
4150 * key violations are reported through a bit in the page fault error code.
4151 * Unlike other bits of the error code, the PK bit is not known at the
4152 * call site of e.g. gva_to_gpa; it must be computed directly in
4153 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4154 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4156 * In particular the following conditions come from the error code, the
4157 * page tables and the machine state:
4158 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4159 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4160 * - PK is always zero if U=0 in the page tables
4161 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4163 * The PKRU bitmask caches the result of these four conditions. The error
4164 * code (minus the P bit) and the page table's U bit form an index into the
4165 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4166 * with the two bits of the PKRU register corresponding to the protection key.
4167 * For the first three conditions above the bits will be 00, thus masking
4168 * away both AD and WD. For all reads or if the last condition holds, WD
4169 * only will be masked away.
4171 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4182 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4183 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4188 wp = is_write_protection(vcpu);
4190 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4191 unsigned pfec, pkey_bits;
4192 bool check_pkey, check_write, ff, uf, wf, pte_user;
4195 ff = pfec & PFERR_FETCH_MASK;
4196 uf = pfec & PFERR_USER_MASK;
4197 wf = pfec & PFERR_WRITE_MASK;
4199 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4200 pte_user = pfec & PFERR_RSVD_MASK;
4203 * Only need to check the access which is not an
4204 * instruction fetch and is to a user page.
4206 check_pkey = (!ff && pte_user);
4208 * write access is controlled by PKRU if it is a
4209 * user access or CR0.WP = 1.
4211 check_write = check_pkey && wf && (uf || wp);
4213 /* PKRU.AD stops both read and write access. */
4214 pkey_bits = !!check_pkey;
4215 /* PKRU.WD stops write access. */
4216 pkey_bits |= (!!check_write) << 1;
4218 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4222 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4224 unsigned root_level = mmu->root_level;
4226 mmu->last_nonleaf_level = root_level;
4227 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4228 mmu->last_nonleaf_level++;
4231 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4232 struct kvm_mmu *context,
4235 context->nx = is_nx(vcpu);
4236 context->root_level = level;
4238 reset_rsvds_bits_mask(vcpu, context);
4239 update_permission_bitmask(vcpu, context, false);
4240 update_pkru_bitmask(vcpu, context, false);
4241 update_last_nonleaf_level(vcpu, context);
4243 MMU_WARN_ON(!is_pae(vcpu));
4244 context->page_fault = paging64_page_fault;
4245 context->gva_to_gpa = paging64_gva_to_gpa;
4246 context->sync_page = paging64_sync_page;
4247 context->invlpg = paging64_invlpg;
4248 context->update_pte = paging64_update_pte;
4249 context->shadow_root_level = level;
4250 context->root_hpa = INVALID_PAGE;
4251 context->direct_map = false;
4254 static void paging64_init_context(struct kvm_vcpu *vcpu,
4255 struct kvm_mmu *context)
4257 paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
4260 static void paging32_init_context(struct kvm_vcpu *vcpu,
4261 struct kvm_mmu *context)
4263 context->nx = false;
4264 context->root_level = PT32_ROOT_LEVEL;
4266 reset_rsvds_bits_mask(vcpu, context);
4267 update_permission_bitmask(vcpu, context, false);
4268 update_pkru_bitmask(vcpu, context, false);
4269 update_last_nonleaf_level(vcpu, context);
4271 context->page_fault = paging32_page_fault;
4272 context->gva_to_gpa = paging32_gva_to_gpa;
4273 context->sync_page = paging32_sync_page;
4274 context->invlpg = paging32_invlpg;
4275 context->update_pte = paging32_update_pte;
4276 context->shadow_root_level = PT32E_ROOT_LEVEL;
4277 context->root_hpa = INVALID_PAGE;
4278 context->direct_map = false;
4281 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4282 struct kvm_mmu *context)
4284 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4287 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4289 struct kvm_mmu *context = &vcpu->arch.mmu;
4291 context->base_role.word = 0;
4292 context->base_role.smm = is_smm(vcpu);
4293 context->page_fault = tdp_page_fault;
4294 context->sync_page = nonpaging_sync_page;
4295 context->invlpg = nonpaging_invlpg;
4296 context->update_pte = nonpaging_update_pte;
4297 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4298 context->root_hpa = INVALID_PAGE;
4299 context->direct_map = true;
4300 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
4301 context->get_cr3 = get_cr3;
4302 context->get_pdptr = kvm_pdptr_read;
4303 context->inject_page_fault = kvm_inject_page_fault;
4305 if (!is_paging(vcpu)) {
4306 context->nx = false;
4307 context->gva_to_gpa = nonpaging_gva_to_gpa;
4308 context->root_level = 0;
4309 } else if (is_long_mode(vcpu)) {
4310 context->nx = is_nx(vcpu);
4311 context->root_level = PT64_ROOT_LEVEL;
4312 reset_rsvds_bits_mask(vcpu, context);
4313 context->gva_to_gpa = paging64_gva_to_gpa;
4314 } else if (is_pae(vcpu)) {
4315 context->nx = is_nx(vcpu);
4316 context->root_level = PT32E_ROOT_LEVEL;
4317 reset_rsvds_bits_mask(vcpu, context);
4318 context->gva_to_gpa = paging64_gva_to_gpa;
4320 context->nx = false;
4321 context->root_level = PT32_ROOT_LEVEL;
4322 reset_rsvds_bits_mask(vcpu, context);
4323 context->gva_to_gpa = paging32_gva_to_gpa;
4326 update_permission_bitmask(vcpu, context, false);
4327 update_pkru_bitmask(vcpu, context, false);
4328 update_last_nonleaf_level(vcpu, context);
4329 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4332 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
4334 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4335 bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4336 struct kvm_mmu *context = &vcpu->arch.mmu;
4338 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4340 if (!is_paging(vcpu))
4341 nonpaging_init_context(vcpu, context);
4342 else if (is_long_mode(vcpu))
4343 paging64_init_context(vcpu, context);
4344 else if (is_pae(vcpu))
4345 paging32E_init_context(vcpu, context);
4347 paging32_init_context(vcpu, context);
4349 context->base_role.nxe = is_nx(vcpu);
4350 context->base_role.cr4_pae = !!is_pae(vcpu);
4351 context->base_role.cr0_wp = is_write_protection(vcpu);
4352 context->base_role.smep_andnot_wp
4353 = smep && !is_write_protection(vcpu);
4354 context->base_role.smap_andnot_wp
4355 = smap && !is_write_protection(vcpu);
4356 context->base_role.smm = is_smm(vcpu);
4357 reset_shadow_zero_bits_mask(vcpu, context);
4359 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4361 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4362 bool accessed_dirty)
4364 struct kvm_mmu *context = &vcpu->arch.mmu;
4366 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4368 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4371 context->ept_ad = accessed_dirty;
4372 context->page_fault = ept_page_fault;
4373 context->gva_to_gpa = ept_gva_to_gpa;
4374 context->sync_page = ept_sync_page;
4375 context->invlpg = ept_invlpg;
4376 context->update_pte = ept_update_pte;
4377 context->root_level = context->shadow_root_level;
4378 context->root_hpa = INVALID_PAGE;
4379 context->direct_map = false;
4381 update_permission_bitmask(vcpu, context, true);
4382 update_pkru_bitmask(vcpu, context, true);
4383 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4384 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4386 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4388 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4390 struct kvm_mmu *context = &vcpu->arch.mmu;
4392 kvm_init_shadow_mmu(vcpu);
4393 context->set_cr3 = kvm_x86_ops->set_cr3;
4394 context->get_cr3 = get_cr3;
4395 context->get_pdptr = kvm_pdptr_read;
4396 context->inject_page_fault = kvm_inject_page_fault;
4399 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4401 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4403 g_context->get_cr3 = get_cr3;
4404 g_context->get_pdptr = kvm_pdptr_read;
4405 g_context->inject_page_fault = kvm_inject_page_fault;
4408 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4409 * L1's nested page tables (e.g. EPT12). The nested translation
4410 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4411 * L2's page tables as the first level of translation and L1's
4412 * nested page tables as the second level of translation. Basically
4413 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4415 if (!is_paging(vcpu)) {
4416 g_context->nx = false;
4417 g_context->root_level = 0;
4418 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4419 } else if (is_long_mode(vcpu)) {
4420 g_context->nx = is_nx(vcpu);
4421 g_context->root_level = PT64_ROOT_LEVEL;
4422 reset_rsvds_bits_mask(vcpu, g_context);
4423 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4424 } else if (is_pae(vcpu)) {
4425 g_context->nx = is_nx(vcpu);
4426 g_context->root_level = PT32E_ROOT_LEVEL;
4427 reset_rsvds_bits_mask(vcpu, g_context);
4428 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4430 g_context->nx = false;
4431 g_context->root_level = PT32_ROOT_LEVEL;
4432 reset_rsvds_bits_mask(vcpu, g_context);
4433 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4436 update_permission_bitmask(vcpu, g_context, false);
4437 update_pkru_bitmask(vcpu, g_context, false);
4438 update_last_nonleaf_level(vcpu, g_context);
4441 static void init_kvm_mmu(struct kvm_vcpu *vcpu)
4443 if (mmu_is_nested(vcpu))
4444 init_kvm_nested_mmu(vcpu);
4445 else if (tdp_enabled)
4446 init_kvm_tdp_mmu(vcpu);
4448 init_kvm_softmmu(vcpu);
4451 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4453 kvm_mmu_unload(vcpu);
4456 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4458 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4462 r = mmu_topup_memory_caches(vcpu);
4465 r = mmu_alloc_roots(vcpu);
4466 kvm_mmu_sync_roots(vcpu);
4469 /* set_cr3() should ensure TLB has been flushed */
4470 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
4474 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4476 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4478 mmu_free_roots(vcpu);
4479 WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4481 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4483 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4484 struct kvm_mmu_page *sp, u64 *spte,
4487 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
4488 ++vcpu->kvm->stat.mmu_pde_zapped;
4492 ++vcpu->kvm->stat.mmu_pte_updated;
4493 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
4496 static bool need_remote_flush(u64 old, u64 new)
4498 if (!is_shadow_present_pte(old))
4500 if (!is_shadow_present_pte(new))
4502 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4504 old ^= shadow_nx_mask;
4505 new ^= shadow_nx_mask;
4506 return (old & ~new & PT64_PERM_MASK) != 0;
4509 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4510 const u8 *new, int *bytes)
4516 * Assume that the pte write on a page table of the same type
4517 * as the current vcpu paging mode since we update the sptes only
4518 * when they have the same mode.
4520 if (is_pae(vcpu) && *bytes == 4) {
4521 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4524 r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8);
4527 new = (const u8 *)&gentry;
4532 gentry = *(const u32 *)new;
4535 gentry = *(const u64 *)new;
4546 * If we're seeing too many writes to a page, it may no longer be a page table,
4547 * or we may be forking, in which case it is better to unmap the page.
4549 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4552 * Skip write-flooding detected for the sp whose level is 1, because
4553 * it can become unsync, then the guest page is not write-protected.
4555 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
4558 atomic_inc(&sp->write_flooding_count);
4559 return atomic_read(&sp->write_flooding_count) >= 3;
4563 * Misaligned accesses are too much trouble to fix up; also, they usually
4564 * indicate a page is not used as a page table.
4566 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4569 unsigned offset, pte_size, misaligned;
4571 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4572 gpa, bytes, sp->role.word);
4574 offset = offset_in_page(gpa);
4575 pte_size = sp->role.cr4_pae ? 8 : 4;
4578 * Sometimes, the OS only writes the last one bytes to update status
4579 * bits, for example, in linux, andb instruction is used in clear_bit().
4581 if (!(offset & (pte_size - 1)) && bytes == 1)
4584 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4585 misaligned |= bytes < 4;
4590 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4592 unsigned page_offset, quadrant;
4596 page_offset = offset_in_page(gpa);
4597 level = sp->role.level;
4599 if (!sp->role.cr4_pae) {
4600 page_offset <<= 1; /* 32->64 */
4602 * A 32-bit pde maps 4MB while the shadow pdes map
4603 * only 2MB. So we need to double the offset again
4604 * and zap two pdes instead of one.
4606 if (level == PT32_ROOT_LEVEL) {
4607 page_offset &= ~7; /* kill rounding error */
4611 quadrant = page_offset >> PAGE_SHIFT;
4612 page_offset &= ~PAGE_MASK;
4613 if (quadrant != sp->role.quadrant)
4617 spte = &sp->spt[page_offset / sizeof(*spte)];
4621 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4622 const u8 *new, int bytes,
4623 struct kvm_page_track_notifier_node *node)
4625 gfn_t gfn = gpa >> PAGE_SHIFT;
4626 struct kvm_mmu_page *sp;
4627 LIST_HEAD(invalid_list);
4628 u64 entry, gentry, *spte;
4630 bool remote_flush, local_flush;
4631 union kvm_mmu_page_role mask = { };
4636 mask.smep_andnot_wp = 1;
4637 mask.smap_andnot_wp = 1;
4641 * If we don't have indirect shadow pages, it means no page is
4642 * write-protected, so we can exit simply.
4644 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4647 remote_flush = local_flush = false;
4649 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4651 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4654 * No need to care whether allocation memory is successful
4655 * or not since pte prefetch is skiped if it does not have
4656 * enough objects in the cache.
4658 mmu_topup_memory_caches(vcpu);
4660 spin_lock(&vcpu->kvm->mmu_lock);
4661 ++vcpu->kvm->stat.mmu_pte_write;
4662 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4664 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4665 if (detect_write_misaligned(sp, gpa, bytes) ||
4666 detect_write_flooding(sp)) {
4667 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4668 ++vcpu->kvm->stat.mmu_flooded;
4672 spte = get_written_sptes(sp, gpa, &npte);
4679 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4681 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4682 & mask.word) && rmap_can_add(vcpu))
4683 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4684 if (need_remote_flush(entry, *spte))
4685 remote_flush = true;
4689 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
4690 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4691 spin_unlock(&vcpu->kvm->mmu_lock);
4694 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4699 if (vcpu->arch.mmu.direct_map)
4702 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4704 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4708 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4710 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4712 LIST_HEAD(invalid_list);
4714 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4717 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4718 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4721 ++vcpu->kvm->stat.mmu_recycled;
4723 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4726 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code,
4727 void *insn, int insn_len)
4729 int r, emulation_type = EMULTYPE_RETRY;
4730 enum emulation_result er;
4731 bool direct = vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu);
4733 if (unlikely(error_code & PFERR_RSVD_MASK)) {
4734 r = handle_mmio_page_fault(vcpu, cr2, direct);
4735 if (r == RET_MMIO_PF_EMULATE) {
4739 if (r == RET_MMIO_PF_RETRY)
4745 r = vcpu->arch.mmu.page_fault(vcpu, cr2, lower_32_bits(error_code),
4753 * Before emulating the instruction, check if the error code
4754 * was due to a RO violation while translating the guest page.
4755 * This can occur when using nested virtualization with nested
4756 * paging in both guests. If true, we simply unprotect the page
4757 * and resume the guest.
4759 * Note: AMD only (since it supports the PFERR_GUEST_PAGE_MASK used
4760 * in PFERR_NEXT_GUEST_PAGE)
4762 if (error_code == PFERR_NESTED_GUEST_PAGE) {
4763 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2));
4767 if (mmio_info_in_cache(vcpu, cr2, direct))
4770 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4775 case EMULATE_USER_EXIT:
4776 ++vcpu->stat.mmio_exits;
4784 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4786 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4788 vcpu->arch.mmu.invlpg(vcpu, gva);
4789 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4790 ++vcpu->stat.invlpg;
4792 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4794 void kvm_enable_tdp(void)
4798 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4800 void kvm_disable_tdp(void)
4802 tdp_enabled = false;
4804 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4806 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4808 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4809 if (vcpu->arch.mmu.lm_root != NULL)
4810 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4813 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4819 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4820 * Therefore we need to allocate shadow page tables in the first
4821 * 4GB of memory, which happens to fit the DMA32 zone.
4823 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4827 vcpu->arch.mmu.pae_root = page_address(page);
4828 for (i = 0; i < 4; ++i)
4829 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4834 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4836 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4837 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4838 vcpu->arch.mmu.translate_gpa = translate_gpa;
4839 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4841 return alloc_mmu_pages(vcpu);
4844 void kvm_mmu_setup(struct kvm_vcpu *vcpu)
4846 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4851 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
4852 struct kvm_memory_slot *slot,
4853 struct kvm_page_track_notifier_node *node)
4855 kvm_mmu_invalidate_zap_all_pages(kvm);
4858 void kvm_mmu_init_vm(struct kvm *kvm)
4860 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
4862 node->track_write = kvm_mmu_pte_write;
4863 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
4864 kvm_page_track_register_notifier(kvm, node);
4867 void kvm_mmu_uninit_vm(struct kvm *kvm)
4869 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
4871 kvm_page_track_unregister_notifier(kvm, node);
4874 /* The return value indicates if tlb flush on all vcpus is needed. */
4875 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
4877 /* The caller should hold mmu-lock before calling this function. */
4879 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
4880 slot_level_handler fn, int start_level, int end_level,
4881 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
4883 struct slot_rmap_walk_iterator iterator;
4886 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
4887 end_gfn, &iterator) {
4889 flush |= fn(kvm, iterator.rmap);
4891 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4892 if (flush && lock_flush_tlb) {
4893 kvm_flush_remote_tlbs(kvm);
4896 cond_resched_lock(&kvm->mmu_lock);
4900 if (flush && lock_flush_tlb) {
4901 kvm_flush_remote_tlbs(kvm);
4909 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4910 slot_level_handler fn, int start_level, int end_level,
4911 bool lock_flush_tlb)
4913 return slot_handle_level_range(kvm, memslot, fn, start_level,
4914 end_level, memslot->base_gfn,
4915 memslot->base_gfn + memslot->npages - 1,
4920 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4921 slot_level_handler fn, bool lock_flush_tlb)
4923 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4924 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4928 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4929 slot_level_handler fn, bool lock_flush_tlb)
4931 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
4932 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4936 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
4937 slot_level_handler fn, bool lock_flush_tlb)
4939 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4940 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
4943 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
4945 struct kvm_memslots *slots;
4946 struct kvm_memory_slot *memslot;
4949 spin_lock(&kvm->mmu_lock);
4950 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
4951 slots = __kvm_memslots(kvm, i);
4952 kvm_for_each_memslot(memslot, slots) {
4955 start = max(gfn_start, memslot->base_gfn);
4956 end = min(gfn_end, memslot->base_gfn + memslot->npages);
4960 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
4961 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
4962 start, end - 1, true);
4966 spin_unlock(&kvm->mmu_lock);
4969 static bool slot_rmap_write_protect(struct kvm *kvm,
4970 struct kvm_rmap_head *rmap_head)
4972 return __rmap_write_protect(kvm, rmap_head, false);
4975 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
4976 struct kvm_memory_slot *memslot)
4980 spin_lock(&kvm->mmu_lock);
4981 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
4983 spin_unlock(&kvm->mmu_lock);
4986 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
4987 * which do tlb flush out of mmu-lock should be serialized by
4988 * kvm->slots_lock otherwise tlb flush would be missed.
4990 lockdep_assert_held(&kvm->slots_lock);
4993 * We can flush all the TLBs out of the mmu lock without TLB
4994 * corruption since we just change the spte from writable to
4995 * readonly so that we only need to care the case of changing
4996 * spte from present to present (changing the spte from present
4997 * to nonpresent will flush all the TLBs immediately), in other
4998 * words, the only case we care is mmu_spte_update() where we
4999 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5000 * instead of PT_WRITABLE_MASK, that means it does not depend
5001 * on PT_WRITABLE_MASK anymore.
5004 kvm_flush_remote_tlbs(kvm);
5007 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5008 struct kvm_rmap_head *rmap_head)
5011 struct rmap_iterator iter;
5012 int need_tlb_flush = 0;
5014 struct kvm_mmu_page *sp;
5017 for_each_rmap_spte(rmap_head, &iter, sptep) {
5018 sp = page_header(__pa(sptep));
5019 pfn = spte_to_pfn(*sptep);
5022 * We cannot do huge page mapping for indirect shadow pages,
5023 * which are found on the last rmap (level = 1) when not using
5024 * tdp; such shadow pages are synced with the page table in
5025 * the guest, and the guest page table is using 4K page size
5026 * mapping if the indirect sp has level = 1.
5028 if (sp->role.direct &&
5029 !kvm_is_reserved_pfn(pfn) &&
5030 PageTransCompoundMap(pfn_to_page(pfn))) {
5031 drop_spte(kvm, sptep);
5037 return need_tlb_flush;
5040 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5041 const struct kvm_memory_slot *memslot)
5043 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5044 spin_lock(&kvm->mmu_lock);
5045 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
5046 kvm_mmu_zap_collapsible_spte, true);
5047 spin_unlock(&kvm->mmu_lock);
5050 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5051 struct kvm_memory_slot *memslot)
5055 spin_lock(&kvm->mmu_lock);
5056 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
5057 spin_unlock(&kvm->mmu_lock);
5059 lockdep_assert_held(&kvm->slots_lock);
5062 * It's also safe to flush TLBs out of mmu lock here as currently this
5063 * function is only used for dirty logging, in which case flushing TLB
5064 * out of mmu lock also guarantees no dirty pages will be lost in
5068 kvm_flush_remote_tlbs(kvm);
5070 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
5072 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
5073 struct kvm_memory_slot *memslot)
5077 spin_lock(&kvm->mmu_lock);
5078 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
5080 spin_unlock(&kvm->mmu_lock);
5082 /* see kvm_mmu_slot_remove_write_access */
5083 lockdep_assert_held(&kvm->slots_lock);
5086 kvm_flush_remote_tlbs(kvm);
5088 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
5090 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
5091 struct kvm_memory_slot *memslot)
5095 spin_lock(&kvm->mmu_lock);
5096 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
5097 spin_unlock(&kvm->mmu_lock);
5099 lockdep_assert_held(&kvm->slots_lock);
5101 /* see kvm_mmu_slot_leaf_clear_dirty */
5103 kvm_flush_remote_tlbs(kvm);
5105 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
5107 #define BATCH_ZAP_PAGES 10
5108 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5110 struct kvm_mmu_page *sp, *node;
5114 list_for_each_entry_safe_reverse(sp, node,
5115 &kvm->arch.active_mmu_pages, link) {
5119 * No obsolete page exists before new created page since
5120 * active_mmu_pages is the FIFO list.
5122 if (!is_obsolete_sp(kvm, sp))
5126 * Since we are reversely walking the list and the invalid
5127 * list will be moved to the head, skip the invalid page
5128 * can help us to avoid the infinity list walking.
5130 if (sp->role.invalid)
5134 * Need not flush tlb since we only zap the sp with invalid
5135 * generation number.
5137 if (batch >= BATCH_ZAP_PAGES &&
5138 cond_resched_lock(&kvm->mmu_lock)) {
5143 ret = kvm_mmu_prepare_zap_page(kvm, sp,
5144 &kvm->arch.zapped_obsolete_pages);
5152 * Should flush tlb before free page tables since lockless-walking
5153 * may use the pages.
5155 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5159 * Fast invalidate all shadow pages and use lock-break technique
5160 * to zap obsolete pages.
5162 * It's required when memslot is being deleted or VM is being
5163 * destroyed, in these cases, we should ensure that KVM MMU does
5164 * not use any resource of the being-deleted slot or all slots
5165 * after calling the function.
5167 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
5169 spin_lock(&kvm->mmu_lock);
5170 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
5171 kvm->arch.mmu_valid_gen++;
5174 * Notify all vcpus to reload its shadow page table
5175 * and flush TLB. Then all vcpus will switch to new
5176 * shadow page table with the new mmu_valid_gen.
5178 * Note: we should do this under the protection of
5179 * mmu-lock, otherwise, vcpu would purge shadow page
5180 * but miss tlb flush.
5182 kvm_reload_remote_mmus(kvm);
5184 kvm_zap_obsolete_pages(kvm);
5185 spin_unlock(&kvm->mmu_lock);
5188 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5190 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5193 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots)
5196 * The very rare case: if the generation-number is round,
5197 * zap all shadow pages.
5199 if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) {
5200 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5201 kvm_mmu_invalidate_zap_all_pages(kvm);
5205 static unsigned long
5206 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5209 int nr_to_scan = sc->nr_to_scan;
5210 unsigned long freed = 0;
5212 spin_lock(&kvm_lock);
5214 list_for_each_entry(kvm, &vm_list, vm_list) {
5216 LIST_HEAD(invalid_list);
5219 * Never scan more than sc->nr_to_scan VM instances.
5220 * Will not hit this condition practically since we do not try
5221 * to shrink more than one VM and it is very unlikely to see
5222 * !n_used_mmu_pages so many times.
5227 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5228 * here. We may skip a VM instance errorneosly, but we do not
5229 * want to shrink a VM that only started to populate its MMU
5232 if (!kvm->arch.n_used_mmu_pages &&
5233 !kvm_has_zapped_obsolete_pages(kvm))
5236 idx = srcu_read_lock(&kvm->srcu);
5237 spin_lock(&kvm->mmu_lock);
5239 if (kvm_has_zapped_obsolete_pages(kvm)) {
5240 kvm_mmu_commit_zap_page(kvm,
5241 &kvm->arch.zapped_obsolete_pages);
5245 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
5247 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5250 spin_unlock(&kvm->mmu_lock);
5251 srcu_read_unlock(&kvm->srcu, idx);
5254 * unfair on small ones
5255 * per-vm shrinkers cry out
5256 * sadness comes quickly
5258 list_move_tail(&kvm->vm_list, &vm_list);
5262 spin_unlock(&kvm_lock);
5266 static unsigned long
5267 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5269 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5272 static struct shrinker mmu_shrinker = {
5273 .count_objects = mmu_shrink_count,
5274 .scan_objects = mmu_shrink_scan,
5275 .seeks = DEFAULT_SEEKS * 10,
5278 static void mmu_destroy_caches(void)
5280 if (pte_list_desc_cache)
5281 kmem_cache_destroy(pte_list_desc_cache);
5282 if (mmu_page_header_cache)
5283 kmem_cache_destroy(mmu_page_header_cache);
5286 int kvm_mmu_module_init(void)
5288 kvm_mmu_clear_all_pte_masks();
5290 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5291 sizeof(struct pte_list_desc),
5293 if (!pte_list_desc_cache)
5296 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5297 sizeof(struct kvm_mmu_page),
5299 if (!mmu_page_header_cache)
5302 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5305 register_shrinker(&mmu_shrinker);
5310 mmu_destroy_caches();
5315 * Caculate mmu pages needed for kvm.
5317 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
5319 unsigned int nr_mmu_pages;
5320 unsigned int nr_pages = 0;
5321 struct kvm_memslots *slots;
5322 struct kvm_memory_slot *memslot;
5325 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5326 slots = __kvm_memslots(kvm, i);
5328 kvm_for_each_memslot(memslot, slots)
5329 nr_pages += memslot->npages;
5332 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5333 nr_mmu_pages = max(nr_mmu_pages,
5334 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
5336 return nr_mmu_pages;
5339 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5341 kvm_mmu_unload(vcpu);
5342 free_mmu_pages(vcpu);
5343 mmu_free_memory_caches(vcpu);
5346 void kvm_mmu_module_exit(void)
5348 mmu_destroy_caches();
5349 percpu_counter_destroy(&kvm_total_used_mmu_pages);
5350 unregister_shrinker(&mmu_shrinker);
5351 mmu_audit_disable();