1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "kvm_cache_regs.h"
24 #include <linux/kvm_host.h>
25 #include <linux/types.h>
26 #include <linux/string.h>
28 #include <linux/highmem.h>
29 #include <linux/moduleparam.h>
30 #include <linux/export.h>
31 #include <linux/swap.h>
32 #include <linux/hugetlb.h>
33 #include <linux/compiler.h>
34 #include <linux/srcu.h>
35 #include <linux/slab.h>
36 #include <linux/sched/signal.h>
37 #include <linux/uaccess.h>
38 #include <linux/hash.h>
39 #include <linux/kern_levels.h>
43 #include <asm/cmpxchg.h>
44 #include <asm/e820/api.h>
47 #include <asm/kvm_page_track.h>
51 * When setting this variable to true it enables Two-Dimensional-Paging
52 * where the hardware walks 2 page tables:
53 * 1. the guest-virtual to guest-physical
54 * 2. while doing 1. it walks guest-physical to host-physical
55 * If the hardware supports that we don't need to do shadow paging.
57 bool tdp_enabled = false;
61 AUDIT_POST_PAGE_FAULT,
72 module_param(dbg, bool, 0644);
74 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
75 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
76 #define MMU_WARN_ON(x) WARN_ON(x)
78 #define pgprintk(x...) do { } while (0)
79 #define rmap_printk(x...) do { } while (0)
80 #define MMU_WARN_ON(x) do { } while (0)
83 #define PTE_PREFETCH_NUM 8
85 #define PT_FIRST_AVAIL_BITS_SHIFT 10
86 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
88 #define PT64_LEVEL_BITS 9
90 #define PT64_LEVEL_SHIFT(level) \
91 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
93 #define PT64_INDEX(address, level)\
94 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
97 #define PT32_LEVEL_BITS 10
99 #define PT32_LEVEL_SHIFT(level) \
100 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
102 #define PT32_LVL_OFFSET_MASK(level) \
103 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
104 * PT32_LEVEL_BITS))) - 1))
106 #define PT32_INDEX(address, level)\
107 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
110 #ifdef CONFIG_DYNAMIC_PHYSICAL_MASK
111 #define PT64_BASE_ADDR_MASK (physical_mask & ~(u64)(PAGE_SIZE-1))
113 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
115 #define PT64_LVL_ADDR_MASK(level) \
116 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
117 * PT64_LEVEL_BITS))) - 1))
118 #define PT64_LVL_OFFSET_MASK(level) \
119 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
120 * PT64_LEVEL_BITS))) - 1))
122 #define PT32_BASE_ADDR_MASK PAGE_MASK
123 #define PT32_DIR_BASE_ADDR_MASK \
124 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
125 #define PT32_LVL_ADDR_MASK(level) \
126 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
127 * PT32_LEVEL_BITS))) - 1))
129 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
130 | shadow_x_mask | shadow_nx_mask | shadow_me_mask)
132 #define ACC_EXEC_MASK 1
133 #define ACC_WRITE_MASK PT_WRITABLE_MASK
134 #define ACC_USER_MASK PT_USER_MASK
135 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
137 /* The mask for the R/X bits in EPT PTEs */
138 #define PT64_EPT_READABLE_MASK 0x1ull
139 #define PT64_EPT_EXECUTABLE_MASK 0x4ull
141 #include <trace/events/kvm.h>
143 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
144 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
146 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
148 /* make pte_list_desc fit well in cache line */
149 #define PTE_LIST_EXT 3
152 * Return values of handle_mmio_page_fault and mmu.page_fault:
153 * RET_PF_RETRY: let CPU fault again on the address.
154 * RET_PF_EMULATE: mmio page fault, emulate the instruction directly.
156 * For handle_mmio_page_fault only:
157 * RET_PF_INVALID: the spte is invalid, let the real page fault path update it.
165 struct pte_list_desc {
166 u64 *sptes[PTE_LIST_EXT];
167 struct pte_list_desc *more;
170 struct kvm_shadow_walk_iterator {
178 static const union kvm_mmu_page_role mmu_base_role_mask = {
180 .gpte_is_8_bytes = 1,
189 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
190 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
192 shadow_walk_okay(&(_walker)); \
193 shadow_walk_next(&(_walker)))
195 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
196 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
197 shadow_walk_okay(&(_walker)); \
198 shadow_walk_next(&(_walker)))
200 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
201 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
202 shadow_walk_okay(&(_walker)) && \
203 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
204 __shadow_walk_next(&(_walker), spte))
206 static struct kmem_cache *pte_list_desc_cache;
207 static struct kmem_cache *mmu_page_header_cache;
208 static struct percpu_counter kvm_total_used_mmu_pages;
210 static u64 __read_mostly shadow_nx_mask;
211 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
212 static u64 __read_mostly shadow_user_mask;
213 static u64 __read_mostly shadow_accessed_mask;
214 static u64 __read_mostly shadow_dirty_mask;
215 static u64 __read_mostly shadow_mmio_mask;
216 static u64 __read_mostly shadow_mmio_value;
217 static u64 __read_mostly shadow_present_mask;
218 static u64 __read_mostly shadow_me_mask;
221 * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value.
222 * Non-present SPTEs with shadow_acc_track_value set are in place for access
225 static u64 __read_mostly shadow_acc_track_mask;
226 static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK;
229 * The mask/shift to use for saving the original R/X bits when marking the PTE
230 * as not-present for access tracking purposes. We do not save the W bit as the
231 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
232 * restored only when a write is attempted to the page.
234 static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK |
235 PT64_EPT_EXECUTABLE_MASK;
236 static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT;
239 * This mask must be set on all non-zero Non-Present or Reserved SPTEs in order
240 * to guard against L1TF attacks.
242 static u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
245 * The number of high-order 1 bits to use in the mask above.
247 static const u64 shadow_nonpresent_or_rsvd_mask_len = 5;
250 * In some cases, we need to preserve the GFN of a non-present or reserved
251 * SPTE when we usurp the upper five bits of the physical address space to
252 * defend against L1TF, e.g. for MMIO SPTEs. To preserve the GFN, we'll
253 * shift bits of the GFN that overlap with shadow_nonpresent_or_rsvd_mask
254 * left into the reserved bits, i.e. the GFN in the SPTE will be split into
255 * high and low parts. This mask covers the lower bits of the GFN.
257 static u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask;
260 * The number of non-reserved physical address bits irrespective of features
261 * that repurpose legal bits, e.g. MKTME.
263 static u8 __read_mostly shadow_phys_bits;
265 static void mmu_spte_set(u64 *sptep, u64 spte);
266 static bool is_executable_pte(u64 spte);
267 static union kvm_mmu_page_role
268 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
270 #define CREATE_TRACE_POINTS
271 #include "mmutrace.h"
274 static inline bool kvm_available_flush_tlb_with_range(void)
276 return kvm_x86_ops->tlb_remote_flush_with_range;
279 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
280 struct kvm_tlb_range *range)
284 if (range && kvm_x86_ops->tlb_remote_flush_with_range)
285 ret = kvm_x86_ops->tlb_remote_flush_with_range(kvm, range);
288 kvm_flush_remote_tlbs(kvm);
291 static void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
292 u64 start_gfn, u64 pages)
294 struct kvm_tlb_range range;
296 range.start_gfn = start_gfn;
299 kvm_flush_remote_tlbs_with_range(kvm, &range);
302 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value)
304 BUG_ON((mmio_mask & mmio_value) != mmio_value);
305 shadow_mmio_value = mmio_value | SPTE_SPECIAL_MASK;
306 shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK;
308 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
310 static inline bool sp_ad_disabled(struct kvm_mmu_page *sp)
312 return sp->role.ad_disabled;
315 static inline bool spte_ad_enabled(u64 spte)
317 MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
318 return !(spte & shadow_acc_track_value);
321 static inline u64 spte_shadow_accessed_mask(u64 spte)
323 MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
324 return spte_ad_enabled(spte) ? shadow_accessed_mask : 0;
327 static inline u64 spte_shadow_dirty_mask(u64 spte)
329 MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
330 return spte_ad_enabled(spte) ? shadow_dirty_mask : 0;
333 static inline bool is_access_track_spte(u64 spte)
335 return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0;
339 * Due to limited space in PTEs, the MMIO generation is a 19 bit subset of
340 * the memslots generation and is derived as follows:
342 * Bits 0-8 of the MMIO generation are propagated to spte bits 3-11
343 * Bits 9-18 of the MMIO generation are propagated to spte bits 52-61
345 * The KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS flag is intentionally not included in
346 * the MMIO generation number, as doing so would require stealing a bit from
347 * the "real" generation number and thus effectively halve the maximum number
348 * of MMIO generations that can be handled before encountering a wrap (which
349 * requires a full MMU zap). The flag is instead explicitly queried when
350 * checking for MMIO spte cache hits.
352 #define MMIO_SPTE_GEN_MASK GENMASK_ULL(18, 0)
354 #define MMIO_SPTE_GEN_LOW_START 3
355 #define MMIO_SPTE_GEN_LOW_END 11
356 #define MMIO_SPTE_GEN_LOW_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \
357 MMIO_SPTE_GEN_LOW_START)
359 #define MMIO_SPTE_GEN_HIGH_START 52
360 #define MMIO_SPTE_GEN_HIGH_END 61
361 #define MMIO_SPTE_GEN_HIGH_MASK GENMASK_ULL(MMIO_SPTE_GEN_HIGH_END, \
362 MMIO_SPTE_GEN_HIGH_START)
363 static u64 generation_mmio_spte_mask(u64 gen)
367 WARN_ON(gen & ~MMIO_SPTE_GEN_MASK);
369 mask = (gen << MMIO_SPTE_GEN_LOW_START) & MMIO_SPTE_GEN_LOW_MASK;
370 mask |= (gen << MMIO_SPTE_GEN_HIGH_START) & MMIO_SPTE_GEN_HIGH_MASK;
374 static u64 get_mmio_spte_generation(u64 spte)
378 spte &= ~shadow_mmio_mask;
380 gen = (spte & MMIO_SPTE_GEN_LOW_MASK) >> MMIO_SPTE_GEN_LOW_START;
381 gen |= (spte & MMIO_SPTE_GEN_HIGH_MASK) >> MMIO_SPTE_GEN_HIGH_START;
385 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
388 u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK;
389 u64 mask = generation_mmio_spte_mask(gen);
390 u64 gpa = gfn << PAGE_SHIFT;
392 access &= ACC_WRITE_MASK | ACC_USER_MASK;
393 mask |= shadow_mmio_value | access;
394 mask |= gpa | shadow_nonpresent_or_rsvd_mask;
395 mask |= (gpa & shadow_nonpresent_or_rsvd_mask)
396 << shadow_nonpresent_or_rsvd_mask_len;
398 page_header(__pa(sptep))->mmio_cached = true;
400 trace_mark_mmio_spte(sptep, gfn, access, gen);
401 mmu_spte_set(sptep, mask);
404 static bool is_mmio_spte(u64 spte)
406 return (spte & shadow_mmio_mask) == shadow_mmio_value;
409 static gfn_t get_mmio_spte_gfn(u64 spte)
411 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
413 gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len)
414 & shadow_nonpresent_or_rsvd_mask;
416 return gpa >> PAGE_SHIFT;
419 static unsigned get_mmio_spte_access(u64 spte)
421 u64 mask = generation_mmio_spte_mask(MMIO_SPTE_GEN_MASK) | shadow_mmio_mask;
422 return (spte & ~mask) & ~PAGE_MASK;
425 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
426 kvm_pfn_t pfn, unsigned access)
428 if (unlikely(is_noslot_pfn(pfn))) {
429 mark_mmio_spte(vcpu, sptep, gfn, access);
436 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
438 u64 kvm_gen, spte_gen, gen;
440 gen = kvm_vcpu_memslots(vcpu)->generation;
441 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
444 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
445 spte_gen = get_mmio_spte_generation(spte);
447 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
448 return likely(kvm_gen == spte_gen);
452 * Sets the shadow PTE masks used by the MMU.
455 * - Setting either @accessed_mask or @dirty_mask requires setting both
456 * - At least one of @accessed_mask or @acc_track_mask must be set
458 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
459 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
460 u64 acc_track_mask, u64 me_mask)
462 BUG_ON(!dirty_mask != !accessed_mask);
463 BUG_ON(!accessed_mask && !acc_track_mask);
464 BUG_ON(acc_track_mask & shadow_acc_track_value);
466 shadow_user_mask = user_mask;
467 shadow_accessed_mask = accessed_mask;
468 shadow_dirty_mask = dirty_mask;
469 shadow_nx_mask = nx_mask;
470 shadow_x_mask = x_mask;
471 shadow_present_mask = p_mask;
472 shadow_acc_track_mask = acc_track_mask;
473 shadow_me_mask = me_mask;
475 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
477 static u8 kvm_get_shadow_phys_bits(void)
480 * boot_cpu_data.x86_phys_bits is reduced when MKTME is detected
481 * in CPU detection code, but MKTME treats those reduced bits as
482 * 'keyID' thus they are not reserved bits. Therefore for MKTME
483 * we should still return physical address bits reported by CPUID.
485 if (!boot_cpu_has(X86_FEATURE_TME) ||
486 WARN_ON_ONCE(boot_cpu_data.extended_cpuid_level < 0x80000008))
487 return boot_cpu_data.x86_phys_bits;
489 return cpuid_eax(0x80000008) & 0xff;
492 static void kvm_mmu_reset_all_pte_masks(void)
496 shadow_user_mask = 0;
497 shadow_accessed_mask = 0;
498 shadow_dirty_mask = 0;
501 shadow_mmio_mask = 0;
502 shadow_present_mask = 0;
503 shadow_acc_track_mask = 0;
505 shadow_phys_bits = kvm_get_shadow_phys_bits();
508 * If the CPU has 46 or less physical address bits, then set an
509 * appropriate mask to guard against L1TF attacks. Otherwise, it is
510 * assumed that the CPU is not vulnerable to L1TF.
512 * Some Intel CPUs address the L1 cache using more PA bits than are
513 * reported by CPUID. Use the PA width of the L1 cache when possible
514 * to achieve more effective mitigation, e.g. if system RAM overlaps
515 * the most significant bits of legal physical address space.
517 shadow_nonpresent_or_rsvd_mask = 0;
518 low_phys_bits = boot_cpu_data.x86_cache_bits;
519 if (boot_cpu_data.x86_cache_bits <
520 52 - shadow_nonpresent_or_rsvd_mask_len) {
521 shadow_nonpresent_or_rsvd_mask =
522 rsvd_bits(boot_cpu_data.x86_cache_bits -
523 shadow_nonpresent_or_rsvd_mask_len,
524 boot_cpu_data.x86_cache_bits - 1);
525 low_phys_bits -= shadow_nonpresent_or_rsvd_mask_len;
527 WARN_ON_ONCE(boot_cpu_has_bug(X86_BUG_L1TF));
529 shadow_nonpresent_or_rsvd_lower_gfn_mask =
530 GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT);
533 static int is_cpuid_PSE36(void)
538 static int is_nx(struct kvm_vcpu *vcpu)
540 return vcpu->arch.efer & EFER_NX;
543 static int is_shadow_present_pte(u64 pte)
545 return (pte != 0) && !is_mmio_spte(pte);
548 static int is_large_pte(u64 pte)
550 return pte & PT_PAGE_SIZE_MASK;
553 static int is_last_spte(u64 pte, int level)
555 if (level == PT_PAGE_TABLE_LEVEL)
557 if (is_large_pte(pte))
562 static bool is_executable_pte(u64 spte)
564 return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask;
567 static kvm_pfn_t spte_to_pfn(u64 pte)
569 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
572 static gfn_t pse36_gfn_delta(u32 gpte)
574 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
576 return (gpte & PT32_DIR_PSE36_MASK) << shift;
580 static void __set_spte(u64 *sptep, u64 spte)
582 WRITE_ONCE(*sptep, spte);
585 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
587 WRITE_ONCE(*sptep, spte);
590 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
592 return xchg(sptep, spte);
595 static u64 __get_spte_lockless(u64 *sptep)
597 return READ_ONCE(*sptep);
608 static void count_spte_clear(u64 *sptep, u64 spte)
610 struct kvm_mmu_page *sp = page_header(__pa(sptep));
612 if (is_shadow_present_pte(spte))
615 /* Ensure the spte is completely set before we increase the count */
617 sp->clear_spte_count++;
620 static void __set_spte(u64 *sptep, u64 spte)
622 union split_spte *ssptep, sspte;
624 ssptep = (union split_spte *)sptep;
625 sspte = (union split_spte)spte;
627 ssptep->spte_high = sspte.spte_high;
630 * If we map the spte from nonpresent to present, We should store
631 * the high bits firstly, then set present bit, so cpu can not
632 * fetch this spte while we are setting the spte.
636 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
639 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
641 union split_spte *ssptep, sspte;
643 ssptep = (union split_spte *)sptep;
644 sspte = (union split_spte)spte;
646 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
649 * If we map the spte from present to nonpresent, we should clear
650 * present bit firstly to avoid vcpu fetch the old high bits.
654 ssptep->spte_high = sspte.spte_high;
655 count_spte_clear(sptep, spte);
658 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
660 union split_spte *ssptep, sspte, orig;
662 ssptep = (union split_spte *)sptep;
663 sspte = (union split_spte)spte;
665 /* xchg acts as a barrier before the setting of the high bits */
666 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
667 orig.spte_high = ssptep->spte_high;
668 ssptep->spte_high = sspte.spte_high;
669 count_spte_clear(sptep, spte);
675 * The idea using the light way get the spte on x86_32 guest is from
676 * gup_get_pte (mm/gup.c).
678 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
679 * coalesces them and we are running out of the MMU lock. Therefore
680 * we need to protect against in-progress updates of the spte.
682 * Reading the spte while an update is in progress may get the old value
683 * for the high part of the spte. The race is fine for a present->non-present
684 * change (because the high part of the spte is ignored for non-present spte),
685 * but for a present->present change we must reread the spte.
687 * All such changes are done in two steps (present->non-present and
688 * non-present->present), hence it is enough to count the number of
689 * present->non-present updates: if it changed while reading the spte,
690 * we might have hit the race. This is done using clear_spte_count.
692 static u64 __get_spte_lockless(u64 *sptep)
694 struct kvm_mmu_page *sp = page_header(__pa(sptep));
695 union split_spte spte, *orig = (union split_spte *)sptep;
699 count = sp->clear_spte_count;
702 spte.spte_low = orig->spte_low;
705 spte.spte_high = orig->spte_high;
708 if (unlikely(spte.spte_low != orig->spte_low ||
709 count != sp->clear_spte_count))
716 static bool spte_can_locklessly_be_made_writable(u64 spte)
718 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
719 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
722 static bool spte_has_volatile_bits(u64 spte)
724 if (!is_shadow_present_pte(spte))
728 * Always atomically update spte if it can be updated
729 * out of mmu-lock, it can ensure dirty bit is not lost,
730 * also, it can help us to get a stable is_writable_pte()
731 * to ensure tlb flush is not missed.
733 if (spte_can_locklessly_be_made_writable(spte) ||
734 is_access_track_spte(spte))
737 if (spte_ad_enabled(spte)) {
738 if ((spte & shadow_accessed_mask) == 0 ||
739 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
746 static bool is_accessed_spte(u64 spte)
748 u64 accessed_mask = spte_shadow_accessed_mask(spte);
750 return accessed_mask ? spte & accessed_mask
751 : !is_access_track_spte(spte);
754 static bool is_dirty_spte(u64 spte)
756 u64 dirty_mask = spte_shadow_dirty_mask(spte);
758 return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK;
761 /* Rules for using mmu_spte_set:
762 * Set the sptep from nonpresent to present.
763 * Note: the sptep being assigned *must* be either not present
764 * or in a state where the hardware will not attempt to update
767 static void mmu_spte_set(u64 *sptep, u64 new_spte)
769 WARN_ON(is_shadow_present_pte(*sptep));
770 __set_spte(sptep, new_spte);
774 * Update the SPTE (excluding the PFN), but do not track changes in its
775 * accessed/dirty status.
777 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
779 u64 old_spte = *sptep;
781 WARN_ON(!is_shadow_present_pte(new_spte));
783 if (!is_shadow_present_pte(old_spte)) {
784 mmu_spte_set(sptep, new_spte);
788 if (!spte_has_volatile_bits(old_spte))
789 __update_clear_spte_fast(sptep, new_spte);
791 old_spte = __update_clear_spte_slow(sptep, new_spte);
793 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
798 /* Rules for using mmu_spte_update:
799 * Update the state bits, it means the mapped pfn is not changed.
801 * Whenever we overwrite a writable spte with a read-only one we
802 * should flush remote TLBs. Otherwise rmap_write_protect
803 * will find a read-only spte, even though the writable spte
804 * might be cached on a CPU's TLB, the return value indicates this
807 * Returns true if the TLB needs to be flushed
809 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
812 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
814 if (!is_shadow_present_pte(old_spte))
818 * For the spte updated out of mmu-lock is safe, since
819 * we always atomically update it, see the comments in
820 * spte_has_volatile_bits().
822 if (spte_can_locklessly_be_made_writable(old_spte) &&
823 !is_writable_pte(new_spte))
827 * Flush TLB when accessed/dirty states are changed in the page tables,
828 * to guarantee consistency between TLB and page tables.
831 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
833 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
836 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
838 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
845 * Rules for using mmu_spte_clear_track_bits:
846 * It sets the sptep from present to nonpresent, and track the
847 * state bits, it is used to clear the last level sptep.
848 * Returns non-zero if the PTE was previously valid.
850 static int mmu_spte_clear_track_bits(u64 *sptep)
853 u64 old_spte = *sptep;
855 if (!spte_has_volatile_bits(old_spte))
856 __update_clear_spte_fast(sptep, 0ull);
858 old_spte = __update_clear_spte_slow(sptep, 0ull);
860 if (!is_shadow_present_pte(old_spte))
863 pfn = spte_to_pfn(old_spte);
866 * KVM does not hold the refcount of the page used by
867 * kvm mmu, before reclaiming the page, we should
868 * unmap it from mmu first.
870 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
872 if (is_accessed_spte(old_spte))
873 kvm_set_pfn_accessed(pfn);
875 if (is_dirty_spte(old_spte))
876 kvm_set_pfn_dirty(pfn);
882 * Rules for using mmu_spte_clear_no_track:
883 * Directly clear spte without caring the state bits of sptep,
884 * it is used to set the upper level spte.
886 static void mmu_spte_clear_no_track(u64 *sptep)
888 __update_clear_spte_fast(sptep, 0ull);
891 static u64 mmu_spte_get_lockless(u64 *sptep)
893 return __get_spte_lockless(sptep);
896 static u64 mark_spte_for_access_track(u64 spte)
898 if (spte_ad_enabled(spte))
899 return spte & ~shadow_accessed_mask;
901 if (is_access_track_spte(spte))
905 * Making an Access Tracking PTE will result in removal of write access
906 * from the PTE. So, verify that we will be able to restore the write
907 * access in the fast page fault path later on.
909 WARN_ONCE((spte & PT_WRITABLE_MASK) &&
910 !spte_can_locklessly_be_made_writable(spte),
911 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
913 WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask <<
914 shadow_acc_track_saved_bits_shift),
915 "kvm: Access Tracking saved bit locations are not zero\n");
917 spte |= (spte & shadow_acc_track_saved_bits_mask) <<
918 shadow_acc_track_saved_bits_shift;
919 spte &= ~shadow_acc_track_mask;
924 /* Restore an acc-track PTE back to a regular PTE */
925 static u64 restore_acc_track_spte(u64 spte)
928 u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift)
929 & shadow_acc_track_saved_bits_mask;
931 WARN_ON_ONCE(spte_ad_enabled(spte));
932 WARN_ON_ONCE(!is_access_track_spte(spte));
934 new_spte &= ~shadow_acc_track_mask;
935 new_spte &= ~(shadow_acc_track_saved_bits_mask <<
936 shadow_acc_track_saved_bits_shift);
937 new_spte |= saved_bits;
942 /* Returns the Accessed status of the PTE and resets it at the same time. */
943 static bool mmu_spte_age(u64 *sptep)
945 u64 spte = mmu_spte_get_lockless(sptep);
947 if (!is_accessed_spte(spte))
950 if (spte_ad_enabled(spte)) {
951 clear_bit((ffs(shadow_accessed_mask) - 1),
952 (unsigned long *)sptep);
955 * Capture the dirty status of the page, so that it doesn't get
956 * lost when the SPTE is marked for access tracking.
958 if (is_writable_pte(spte))
959 kvm_set_pfn_dirty(spte_to_pfn(spte));
961 spte = mark_spte_for_access_track(spte);
962 mmu_spte_update_no_track(sptep, spte);
968 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
971 * Prevent page table teardown by making any free-er wait during
972 * kvm_flush_remote_tlbs() IPI to all active vcpus.
977 * Make sure a following spte read is not reordered ahead of the write
980 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
983 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
986 * Make sure the write to vcpu->mode is not reordered in front of
987 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
988 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
990 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
994 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
995 struct kmem_cache *base_cache, int min)
999 if (cache->nobjs >= min)
1001 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
1002 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL_ACCOUNT);
1004 return cache->nobjs >= min ? 0 : -ENOMEM;
1005 cache->objects[cache->nobjs++] = obj;
1010 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
1012 return cache->nobjs;
1015 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
1016 struct kmem_cache *cache)
1019 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
1022 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
1027 if (cache->nobjs >= min)
1029 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
1030 page = (void *)__get_free_page(GFP_KERNEL_ACCOUNT);
1032 return cache->nobjs >= min ? 0 : -ENOMEM;
1033 cache->objects[cache->nobjs++] = page;
1038 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
1041 free_page((unsigned long)mc->objects[--mc->nobjs]);
1044 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
1048 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
1049 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
1052 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
1055 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
1056 mmu_page_header_cache, 4);
1061 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
1063 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
1064 pte_list_desc_cache);
1065 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
1066 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
1067 mmu_page_header_cache);
1070 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
1075 p = mc->objects[--mc->nobjs];
1079 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
1081 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
1084 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
1086 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
1089 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
1091 if (!sp->role.direct)
1092 return sp->gfns[index];
1094 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
1097 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
1099 if (!sp->role.direct) {
1100 sp->gfns[index] = gfn;
1104 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
1105 pr_err_ratelimited("gfn mismatch under direct page %llx "
1106 "(expected %llx, got %llx)\n",
1108 kvm_mmu_page_get_gfn(sp, index), gfn);
1112 * Return the pointer to the large page information for a given gfn,
1113 * handling slots that are not large page aligned.
1115 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
1116 struct kvm_memory_slot *slot,
1121 idx = gfn_to_index(gfn, slot->base_gfn, level);
1122 return &slot->arch.lpage_info[level - 2][idx];
1125 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
1126 gfn_t gfn, int count)
1128 struct kvm_lpage_info *linfo;
1131 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1132 linfo = lpage_info_slot(gfn, slot, i);
1133 linfo->disallow_lpage += count;
1134 WARN_ON(linfo->disallow_lpage < 0);
1138 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1140 update_gfn_disallow_lpage_count(slot, gfn, 1);
1143 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1145 update_gfn_disallow_lpage_count(slot, gfn, -1);
1148 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1150 struct kvm_memslots *slots;
1151 struct kvm_memory_slot *slot;
1154 kvm->arch.indirect_shadow_pages++;
1156 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1157 slot = __gfn_to_memslot(slots, gfn);
1159 /* the non-leaf shadow pages are keeping readonly. */
1160 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1161 return kvm_slot_page_track_add_page(kvm, slot, gfn,
1162 KVM_PAGE_TRACK_WRITE);
1164 kvm_mmu_gfn_disallow_lpage(slot, gfn);
1167 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1169 struct kvm_memslots *slots;
1170 struct kvm_memory_slot *slot;
1173 kvm->arch.indirect_shadow_pages--;
1175 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1176 slot = __gfn_to_memslot(slots, gfn);
1177 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1178 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
1179 KVM_PAGE_TRACK_WRITE);
1181 kvm_mmu_gfn_allow_lpage(slot, gfn);
1184 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
1185 struct kvm_memory_slot *slot)
1187 struct kvm_lpage_info *linfo;
1190 linfo = lpage_info_slot(gfn, slot, level);
1191 return !!linfo->disallow_lpage;
1197 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
1200 struct kvm_memory_slot *slot;
1202 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1203 return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
1206 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
1208 unsigned long page_size;
1211 page_size = kvm_host_page_size(kvm, gfn);
1213 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1214 if (page_size >= KVM_HPAGE_SIZE(i))
1223 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
1226 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
1228 if (no_dirty_log && slot->dirty_bitmap)
1234 static struct kvm_memory_slot *
1235 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
1238 struct kvm_memory_slot *slot;
1240 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1241 if (!memslot_valid_for_gpte(slot, no_dirty_log))
1247 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
1248 bool *force_pt_level)
1250 int host_level, level, max_level;
1251 struct kvm_memory_slot *slot;
1253 if (unlikely(*force_pt_level))
1254 return PT_PAGE_TABLE_LEVEL;
1256 slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
1257 *force_pt_level = !memslot_valid_for_gpte(slot, true);
1258 if (unlikely(*force_pt_level))
1259 return PT_PAGE_TABLE_LEVEL;
1261 host_level = host_mapping_level(vcpu->kvm, large_gfn);
1263 if (host_level == PT_PAGE_TABLE_LEVEL)
1266 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
1268 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
1269 if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot))
1276 * About rmap_head encoding:
1278 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1279 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1280 * pte_list_desc containing more mappings.
1284 * Returns the number of pointers in the rmap chain, not counting the new one.
1286 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
1287 struct kvm_rmap_head *rmap_head)
1289 struct pte_list_desc *desc;
1292 if (!rmap_head->val) {
1293 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
1294 rmap_head->val = (unsigned long)spte;
1295 } else if (!(rmap_head->val & 1)) {
1296 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
1297 desc = mmu_alloc_pte_list_desc(vcpu);
1298 desc->sptes[0] = (u64 *)rmap_head->val;
1299 desc->sptes[1] = spte;
1300 rmap_head->val = (unsigned long)desc | 1;
1303 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
1304 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1305 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
1307 count += PTE_LIST_EXT;
1309 if (desc->sptes[PTE_LIST_EXT-1]) {
1310 desc->more = mmu_alloc_pte_list_desc(vcpu);
1313 for (i = 0; desc->sptes[i]; ++i)
1315 desc->sptes[i] = spte;
1321 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
1322 struct pte_list_desc *desc, int i,
1323 struct pte_list_desc *prev_desc)
1327 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
1329 desc->sptes[i] = desc->sptes[j];
1330 desc->sptes[j] = NULL;
1333 if (!prev_desc && !desc->more)
1334 rmap_head->val = (unsigned long)desc->sptes[0];
1337 prev_desc->more = desc->more;
1339 rmap_head->val = (unsigned long)desc->more | 1;
1340 mmu_free_pte_list_desc(desc);
1343 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1345 struct pte_list_desc *desc;
1346 struct pte_list_desc *prev_desc;
1349 if (!rmap_head->val) {
1350 pr_err("%s: %p 0->BUG\n", __func__, spte);
1352 } else if (!(rmap_head->val & 1)) {
1353 rmap_printk("%s: %p 1->0\n", __func__, spte);
1354 if ((u64 *)rmap_head->val != spte) {
1355 pr_err("%s: %p 1->BUG\n", __func__, spte);
1360 rmap_printk("%s: %p many->many\n", __func__, spte);
1361 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1364 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1365 if (desc->sptes[i] == spte) {
1366 pte_list_desc_remove_entry(rmap_head,
1367 desc, i, prev_desc);
1374 pr_err("%s: %p many->many\n", __func__, spte);
1379 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
1381 mmu_spte_clear_track_bits(sptep);
1382 __pte_list_remove(sptep, rmap_head);
1385 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1386 struct kvm_memory_slot *slot)
1390 idx = gfn_to_index(gfn, slot->base_gfn, level);
1391 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1394 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1395 struct kvm_mmu_page *sp)
1397 struct kvm_memslots *slots;
1398 struct kvm_memory_slot *slot;
1400 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1401 slot = __gfn_to_memslot(slots, gfn);
1402 return __gfn_to_rmap(gfn, sp->role.level, slot);
1405 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1407 struct kvm_mmu_memory_cache *cache;
1409 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1410 return mmu_memory_cache_free_objects(cache);
1413 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1415 struct kvm_mmu_page *sp;
1416 struct kvm_rmap_head *rmap_head;
1418 sp = page_header(__pa(spte));
1419 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1420 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1421 return pte_list_add(vcpu, spte, rmap_head);
1424 static void rmap_remove(struct kvm *kvm, u64 *spte)
1426 struct kvm_mmu_page *sp;
1428 struct kvm_rmap_head *rmap_head;
1430 sp = page_header(__pa(spte));
1431 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1432 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1433 __pte_list_remove(spte, rmap_head);
1437 * Used by the following functions to iterate through the sptes linked by a
1438 * rmap. All fields are private and not assumed to be used outside.
1440 struct rmap_iterator {
1441 /* private fields */
1442 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1443 int pos; /* index of the sptep */
1447 * Iteration must be started by this function. This should also be used after
1448 * removing/dropping sptes from the rmap link because in such cases the
1449 * information in the itererator may not be valid.
1451 * Returns sptep if found, NULL otherwise.
1453 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1454 struct rmap_iterator *iter)
1458 if (!rmap_head->val)
1461 if (!(rmap_head->val & 1)) {
1463 sptep = (u64 *)rmap_head->val;
1467 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1469 sptep = iter->desc->sptes[iter->pos];
1471 BUG_ON(!is_shadow_present_pte(*sptep));
1476 * Must be used with a valid iterator: e.g. after rmap_get_first().
1478 * Returns sptep if found, NULL otherwise.
1480 static u64 *rmap_get_next(struct rmap_iterator *iter)
1485 if (iter->pos < PTE_LIST_EXT - 1) {
1487 sptep = iter->desc->sptes[iter->pos];
1492 iter->desc = iter->desc->more;
1496 /* desc->sptes[0] cannot be NULL */
1497 sptep = iter->desc->sptes[iter->pos];
1504 BUG_ON(!is_shadow_present_pte(*sptep));
1508 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1509 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1510 _spte_; _spte_ = rmap_get_next(_iter_))
1512 static void drop_spte(struct kvm *kvm, u64 *sptep)
1514 if (mmu_spte_clear_track_bits(sptep))
1515 rmap_remove(kvm, sptep);
1519 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1521 if (is_large_pte(*sptep)) {
1522 WARN_ON(page_header(__pa(sptep))->role.level ==
1523 PT_PAGE_TABLE_LEVEL);
1524 drop_spte(kvm, sptep);
1532 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1534 if (__drop_large_spte(vcpu->kvm, sptep)) {
1535 struct kvm_mmu_page *sp = page_header(__pa(sptep));
1537 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1538 KVM_PAGES_PER_HPAGE(sp->role.level));
1543 * Write-protect on the specified @sptep, @pt_protect indicates whether
1544 * spte write-protection is caused by protecting shadow page table.
1546 * Note: write protection is difference between dirty logging and spte
1548 * - for dirty logging, the spte can be set to writable at anytime if
1549 * its dirty bitmap is properly set.
1550 * - for spte protection, the spte can be writable only after unsync-ing
1553 * Return true if tlb need be flushed.
1555 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1559 if (!is_writable_pte(spte) &&
1560 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1563 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1566 spte &= ~SPTE_MMU_WRITEABLE;
1567 spte = spte & ~PT_WRITABLE_MASK;
1569 return mmu_spte_update(sptep, spte);
1572 static bool __rmap_write_protect(struct kvm *kvm,
1573 struct kvm_rmap_head *rmap_head,
1577 struct rmap_iterator iter;
1580 for_each_rmap_spte(rmap_head, &iter, sptep)
1581 flush |= spte_write_protect(sptep, pt_protect);
1586 static bool spte_clear_dirty(u64 *sptep)
1590 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1592 spte &= ~shadow_dirty_mask;
1594 return mmu_spte_update(sptep, spte);
1597 static bool wrprot_ad_disabled_spte(u64 *sptep)
1599 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1600 (unsigned long *)sptep);
1602 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1604 return was_writable;
1608 * Gets the GFN ready for another round of dirty logging by clearing the
1609 * - D bit on ad-enabled SPTEs, and
1610 * - W bit on ad-disabled SPTEs.
1611 * Returns true iff any D or W bits were cleared.
1613 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1616 struct rmap_iterator iter;
1619 for_each_rmap_spte(rmap_head, &iter, sptep)
1620 if (spte_ad_enabled(*sptep))
1621 flush |= spte_clear_dirty(sptep);
1623 flush |= wrprot_ad_disabled_spte(sptep);
1628 static bool spte_set_dirty(u64 *sptep)
1632 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1634 spte |= shadow_dirty_mask;
1636 return mmu_spte_update(sptep, spte);
1639 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1642 struct rmap_iterator iter;
1645 for_each_rmap_spte(rmap_head, &iter, sptep)
1646 if (spte_ad_enabled(*sptep))
1647 flush |= spte_set_dirty(sptep);
1653 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1654 * @kvm: kvm instance
1655 * @slot: slot to protect
1656 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1657 * @mask: indicates which pages we should protect
1659 * Used when we do not need to care about huge page mappings: e.g. during dirty
1660 * logging we do not have any such mappings.
1662 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1663 struct kvm_memory_slot *slot,
1664 gfn_t gfn_offset, unsigned long mask)
1666 struct kvm_rmap_head *rmap_head;
1669 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1670 PT_PAGE_TABLE_LEVEL, slot);
1671 __rmap_write_protect(kvm, rmap_head, false);
1673 /* clear the first set bit */
1679 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1680 * protect the page if the D-bit isn't supported.
1681 * @kvm: kvm instance
1682 * @slot: slot to clear D-bit
1683 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1684 * @mask: indicates which pages we should clear D-bit
1686 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1688 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1689 struct kvm_memory_slot *slot,
1690 gfn_t gfn_offset, unsigned long mask)
1692 struct kvm_rmap_head *rmap_head;
1695 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1696 PT_PAGE_TABLE_LEVEL, slot);
1697 __rmap_clear_dirty(kvm, rmap_head);
1699 /* clear the first set bit */
1703 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1706 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1709 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1710 * enable dirty logging for them.
1712 * Used when we do not need to care about huge page mappings: e.g. during dirty
1713 * logging we do not have any such mappings.
1715 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1716 struct kvm_memory_slot *slot,
1717 gfn_t gfn_offset, unsigned long mask)
1719 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1720 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1723 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1727 * kvm_arch_write_log_dirty - emulate dirty page logging
1728 * @vcpu: Guest mode vcpu
1730 * Emulate arch specific page modification logging for the
1733 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu)
1735 if (kvm_x86_ops->write_log_dirty)
1736 return kvm_x86_ops->write_log_dirty(vcpu);
1741 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1742 struct kvm_memory_slot *slot, u64 gfn)
1744 struct kvm_rmap_head *rmap_head;
1746 bool write_protected = false;
1748 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1749 rmap_head = __gfn_to_rmap(gfn, i, slot);
1750 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1753 return write_protected;
1756 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1758 struct kvm_memory_slot *slot;
1760 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1761 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1764 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1767 struct rmap_iterator iter;
1770 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1771 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1773 pte_list_remove(rmap_head, sptep);
1780 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1781 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1784 return kvm_zap_rmapp(kvm, rmap_head);
1787 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1788 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1792 struct rmap_iterator iter;
1795 pte_t *ptep = (pte_t *)data;
1798 WARN_ON(pte_huge(*ptep));
1799 new_pfn = pte_pfn(*ptep);
1802 for_each_rmap_spte(rmap_head, &iter, sptep) {
1803 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1804 sptep, *sptep, gfn, level);
1808 if (pte_write(*ptep)) {
1809 pte_list_remove(rmap_head, sptep);
1812 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1813 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1815 new_spte &= ~PT_WRITABLE_MASK;
1816 new_spte &= ~SPTE_HOST_WRITEABLE;
1818 new_spte = mark_spte_for_access_track(new_spte);
1820 mmu_spte_clear_track_bits(sptep);
1821 mmu_spte_set(sptep, new_spte);
1825 if (need_flush && kvm_available_flush_tlb_with_range()) {
1826 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1833 struct slot_rmap_walk_iterator {
1835 struct kvm_memory_slot *slot;
1841 /* output fields. */
1843 struct kvm_rmap_head *rmap;
1846 /* private field. */
1847 struct kvm_rmap_head *end_rmap;
1851 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1853 iterator->level = level;
1854 iterator->gfn = iterator->start_gfn;
1855 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1856 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1861 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1862 struct kvm_memory_slot *slot, int start_level,
1863 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1865 iterator->slot = slot;
1866 iterator->start_level = start_level;
1867 iterator->end_level = end_level;
1868 iterator->start_gfn = start_gfn;
1869 iterator->end_gfn = end_gfn;
1871 rmap_walk_init_level(iterator, iterator->start_level);
1874 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1876 return !!iterator->rmap;
1879 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1881 if (++iterator->rmap <= iterator->end_rmap) {
1882 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1886 if (++iterator->level > iterator->end_level) {
1887 iterator->rmap = NULL;
1891 rmap_walk_init_level(iterator, iterator->level);
1894 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1895 _start_gfn, _end_gfn, _iter_) \
1896 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1897 _end_level_, _start_gfn, _end_gfn); \
1898 slot_rmap_walk_okay(_iter_); \
1899 slot_rmap_walk_next(_iter_))
1901 static int kvm_handle_hva_range(struct kvm *kvm,
1902 unsigned long start,
1905 int (*handler)(struct kvm *kvm,
1906 struct kvm_rmap_head *rmap_head,
1907 struct kvm_memory_slot *slot,
1910 unsigned long data))
1912 struct kvm_memslots *slots;
1913 struct kvm_memory_slot *memslot;
1914 struct slot_rmap_walk_iterator iterator;
1918 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1919 slots = __kvm_memslots(kvm, i);
1920 kvm_for_each_memslot(memslot, slots) {
1921 unsigned long hva_start, hva_end;
1922 gfn_t gfn_start, gfn_end;
1924 hva_start = max(start, memslot->userspace_addr);
1925 hva_end = min(end, memslot->userspace_addr +
1926 (memslot->npages << PAGE_SHIFT));
1927 if (hva_start >= hva_end)
1930 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1931 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1933 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1934 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1936 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1937 PT_MAX_HUGEPAGE_LEVEL,
1938 gfn_start, gfn_end - 1,
1940 ret |= handler(kvm, iterator.rmap, memslot,
1941 iterator.gfn, iterator.level, data);
1948 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1950 int (*handler)(struct kvm *kvm,
1951 struct kvm_rmap_head *rmap_head,
1952 struct kvm_memory_slot *slot,
1953 gfn_t gfn, int level,
1954 unsigned long data))
1956 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1959 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1961 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1964 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1966 return kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1969 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1970 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1974 struct rmap_iterator uninitialized_var(iter);
1977 for_each_rmap_spte(rmap_head, &iter, sptep)
1978 young |= mmu_spte_age(sptep);
1980 trace_kvm_age_page(gfn, level, slot, young);
1984 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1985 struct kvm_memory_slot *slot, gfn_t gfn,
1986 int level, unsigned long data)
1989 struct rmap_iterator iter;
1991 for_each_rmap_spte(rmap_head, &iter, sptep)
1992 if (is_accessed_spte(*sptep))
1997 #define RMAP_RECYCLE_THRESHOLD 1000
1999 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
2001 struct kvm_rmap_head *rmap_head;
2002 struct kvm_mmu_page *sp;
2004 sp = page_header(__pa(spte));
2006 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
2008 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
2009 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
2010 KVM_PAGES_PER_HPAGE(sp->role.level));
2013 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
2015 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
2018 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
2020 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
2024 static int is_empty_shadow_page(u64 *spt)
2029 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
2030 if (is_shadow_present_pte(*pos)) {
2031 printk(KERN_ERR "%s: %p %llx\n", __func__,
2040 * This value is the sum of all of the kvm instances's
2041 * kvm->arch.n_used_mmu_pages values. We need a global,
2042 * aggregate version in order to make the slab shrinker
2045 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
2047 kvm->arch.n_used_mmu_pages += nr;
2048 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
2051 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
2053 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
2054 hlist_del(&sp->hash_link);
2055 list_del(&sp->link);
2056 free_page((unsigned long)sp->spt);
2057 if (!sp->role.direct)
2058 free_page((unsigned long)sp->gfns);
2059 kmem_cache_free(mmu_page_header_cache, sp);
2062 static unsigned kvm_page_table_hashfn(gfn_t gfn)
2064 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
2067 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
2068 struct kvm_mmu_page *sp, u64 *parent_pte)
2073 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
2076 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
2079 __pte_list_remove(parent_pte, &sp->parent_ptes);
2082 static void drop_parent_pte(struct kvm_mmu_page *sp,
2085 mmu_page_remove_parent_pte(sp, parent_pte);
2086 mmu_spte_clear_no_track(parent_pte);
2089 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
2091 struct kvm_mmu_page *sp;
2093 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
2094 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
2096 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
2097 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
2098 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
2099 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
2103 static void mark_unsync(u64 *spte);
2104 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
2107 struct rmap_iterator iter;
2109 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
2114 static void mark_unsync(u64 *spte)
2116 struct kvm_mmu_page *sp;
2119 sp = page_header(__pa(spte));
2120 index = spte - sp->spt;
2121 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
2123 if (sp->unsync_children++)
2125 kvm_mmu_mark_parents_unsync(sp);
2128 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
2129 struct kvm_mmu_page *sp)
2134 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root)
2138 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
2139 struct kvm_mmu_page *sp, u64 *spte,
2145 #define KVM_PAGE_ARRAY_NR 16
2147 struct kvm_mmu_pages {
2148 struct mmu_page_and_offset {
2149 struct kvm_mmu_page *sp;
2151 } page[KVM_PAGE_ARRAY_NR];
2155 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
2161 for (i=0; i < pvec->nr; i++)
2162 if (pvec->page[i].sp == sp)
2165 pvec->page[pvec->nr].sp = sp;
2166 pvec->page[pvec->nr].idx = idx;
2168 return (pvec->nr == KVM_PAGE_ARRAY_NR);
2171 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
2173 --sp->unsync_children;
2174 WARN_ON((int)sp->unsync_children < 0);
2175 __clear_bit(idx, sp->unsync_child_bitmap);
2178 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
2179 struct kvm_mmu_pages *pvec)
2181 int i, ret, nr_unsync_leaf = 0;
2183 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
2184 struct kvm_mmu_page *child;
2185 u64 ent = sp->spt[i];
2187 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
2188 clear_unsync_child_bit(sp, i);
2192 child = page_header(ent & PT64_BASE_ADDR_MASK);
2194 if (child->unsync_children) {
2195 if (mmu_pages_add(pvec, child, i))
2198 ret = __mmu_unsync_walk(child, pvec);
2200 clear_unsync_child_bit(sp, i);
2202 } else if (ret > 0) {
2203 nr_unsync_leaf += ret;
2206 } else if (child->unsync) {
2208 if (mmu_pages_add(pvec, child, i))
2211 clear_unsync_child_bit(sp, i);
2214 return nr_unsync_leaf;
2217 #define INVALID_INDEX (-1)
2219 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
2220 struct kvm_mmu_pages *pvec)
2223 if (!sp->unsync_children)
2226 mmu_pages_add(pvec, sp, INVALID_INDEX);
2227 return __mmu_unsync_walk(sp, pvec);
2230 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
2232 WARN_ON(!sp->unsync);
2233 trace_kvm_mmu_sync_page(sp);
2235 --kvm->stat.mmu_unsync;
2238 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2239 struct list_head *invalid_list);
2240 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2241 struct list_head *invalid_list);
2244 #define for_each_valid_sp(_kvm, _sp, _gfn) \
2245 hlist_for_each_entry(_sp, \
2246 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2247 if ((_sp)->role.invalid) { \
2250 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
2251 for_each_valid_sp(_kvm, _sp, _gfn) \
2252 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2254 static inline bool is_ept_sp(struct kvm_mmu_page *sp)
2256 return sp->role.cr0_wp && sp->role.smap_andnot_wp;
2259 /* @sp->gfn should be write-protected at the call site */
2260 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2261 struct list_head *invalid_list)
2263 if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) ||
2264 vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
2265 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
2272 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
2273 struct list_head *invalid_list,
2276 if (!remote_flush && list_empty(invalid_list))
2279 if (!list_empty(invalid_list))
2280 kvm_mmu_commit_zap_page(kvm, invalid_list);
2282 kvm_flush_remote_tlbs(kvm);
2286 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
2287 struct list_head *invalid_list,
2288 bool remote_flush, bool local_flush)
2290 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
2294 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2297 #ifdef CONFIG_KVM_MMU_AUDIT
2298 #include "mmu_audit.c"
2300 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
2301 static void mmu_audit_disable(void) { }
2304 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2305 struct list_head *invalid_list)
2307 kvm_unlink_unsync_page(vcpu->kvm, sp);
2308 return __kvm_sync_page(vcpu, sp, invalid_list);
2311 /* @gfn should be write-protected at the call site */
2312 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
2313 struct list_head *invalid_list)
2315 struct kvm_mmu_page *s;
2318 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2322 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2323 ret |= kvm_sync_page(vcpu, s, invalid_list);
2329 struct mmu_page_path {
2330 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
2331 unsigned int idx[PT64_ROOT_MAX_LEVEL];
2334 #define for_each_sp(pvec, sp, parents, i) \
2335 for (i = mmu_pages_first(&pvec, &parents); \
2336 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2337 i = mmu_pages_next(&pvec, &parents, i))
2339 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2340 struct mmu_page_path *parents,
2345 for (n = i+1; n < pvec->nr; n++) {
2346 struct kvm_mmu_page *sp = pvec->page[n].sp;
2347 unsigned idx = pvec->page[n].idx;
2348 int level = sp->role.level;
2350 parents->idx[level-1] = idx;
2351 if (level == PT_PAGE_TABLE_LEVEL)
2354 parents->parent[level-2] = sp;
2360 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2361 struct mmu_page_path *parents)
2363 struct kvm_mmu_page *sp;
2369 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2371 sp = pvec->page[0].sp;
2372 level = sp->role.level;
2373 WARN_ON(level == PT_PAGE_TABLE_LEVEL);
2375 parents->parent[level-2] = sp;
2377 /* Also set up a sentinel. Further entries in pvec are all
2378 * children of sp, so this element is never overwritten.
2380 parents->parent[level-1] = NULL;
2381 return mmu_pages_next(pvec, parents, 0);
2384 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2386 struct kvm_mmu_page *sp;
2387 unsigned int level = 0;
2390 unsigned int idx = parents->idx[level];
2391 sp = parents->parent[level];
2395 WARN_ON(idx == INVALID_INDEX);
2396 clear_unsync_child_bit(sp, idx);
2398 } while (!sp->unsync_children);
2401 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2402 struct kvm_mmu_page *parent)
2405 struct kvm_mmu_page *sp;
2406 struct mmu_page_path parents;
2407 struct kvm_mmu_pages pages;
2408 LIST_HEAD(invalid_list);
2411 while (mmu_unsync_walk(parent, &pages)) {
2412 bool protected = false;
2414 for_each_sp(pages, sp, parents, i)
2415 protected |= rmap_write_protect(vcpu, sp->gfn);
2418 kvm_flush_remote_tlbs(vcpu->kvm);
2422 for_each_sp(pages, sp, parents, i) {
2423 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2424 mmu_pages_clear_parents(&parents);
2426 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2427 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2428 cond_resched_lock(&vcpu->kvm->mmu_lock);
2433 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2436 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2438 atomic_set(&sp->write_flooding_count, 0);
2441 static void clear_sp_write_flooding_count(u64 *spte)
2443 struct kvm_mmu_page *sp = page_header(__pa(spte));
2445 __clear_sp_write_flooding_count(sp);
2448 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2455 union kvm_mmu_page_role role;
2457 struct kvm_mmu_page *sp;
2458 bool need_sync = false;
2461 LIST_HEAD(invalid_list);
2463 role = vcpu->arch.mmu->mmu_role.base;
2465 role.direct = direct;
2467 role.gpte_is_8_bytes = true;
2468 role.access = access;
2469 if (!vcpu->arch.mmu->direct_map
2470 && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2471 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2472 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2473 role.quadrant = quadrant;
2475 for_each_valid_sp(vcpu->kvm, sp, gfn) {
2476 if (sp->gfn != gfn) {
2481 if (!need_sync && sp->unsync)
2484 if (sp->role.word != role.word)
2488 /* The page is good, but __kvm_sync_page might still end
2489 * up zapping it. If so, break in order to rebuild it.
2491 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2494 WARN_ON(!list_empty(&invalid_list));
2495 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2498 if (sp->unsync_children)
2499 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2501 __clear_sp_write_flooding_count(sp);
2502 trace_kvm_mmu_get_page(sp, false);
2506 ++vcpu->kvm->stat.mmu_cache_miss;
2508 sp = kvm_mmu_alloc_page(vcpu, direct);
2512 hlist_add_head(&sp->hash_link,
2513 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2516 * we should do write protection before syncing pages
2517 * otherwise the content of the synced shadow page may
2518 * be inconsistent with guest page table.
2520 account_shadowed(vcpu->kvm, sp);
2521 if (level == PT_PAGE_TABLE_LEVEL &&
2522 rmap_write_protect(vcpu, gfn))
2523 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2525 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2526 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2528 clear_page(sp->spt);
2529 trace_kvm_mmu_get_page(sp, true);
2531 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2533 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2534 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2538 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2539 struct kvm_vcpu *vcpu, hpa_t root,
2542 iterator->addr = addr;
2543 iterator->shadow_addr = root;
2544 iterator->level = vcpu->arch.mmu->shadow_root_level;
2546 if (iterator->level == PT64_ROOT_4LEVEL &&
2547 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2548 !vcpu->arch.mmu->direct_map)
2551 if (iterator->level == PT32E_ROOT_LEVEL) {
2553 * prev_root is currently only used for 64-bit hosts. So only
2554 * the active root_hpa is valid here.
2556 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2558 iterator->shadow_addr
2559 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2560 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2562 if (!iterator->shadow_addr)
2563 iterator->level = 0;
2567 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2568 struct kvm_vcpu *vcpu, u64 addr)
2570 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2574 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2576 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2579 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2580 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2584 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2587 if (is_last_spte(spte, iterator->level)) {
2588 iterator->level = 0;
2592 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2596 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2598 __shadow_walk_next(iterator, *iterator->sptep);
2601 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2602 struct kvm_mmu_page *sp)
2606 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2608 spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK |
2609 shadow_user_mask | shadow_x_mask | shadow_me_mask;
2611 if (sp_ad_disabled(sp))
2612 spte |= shadow_acc_track_value;
2614 spte |= shadow_accessed_mask;
2616 mmu_spte_set(sptep, spte);
2618 mmu_page_add_parent_pte(vcpu, sp, sptep);
2620 if (sp->unsync_children || sp->unsync)
2624 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2625 unsigned direct_access)
2627 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2628 struct kvm_mmu_page *child;
2631 * For the direct sp, if the guest pte's dirty bit
2632 * changed form clean to dirty, it will corrupt the
2633 * sp's access: allow writable in the read-only sp,
2634 * so we should update the spte at this point to get
2635 * a new sp with the correct access.
2637 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2638 if (child->role.access == direct_access)
2641 drop_parent_pte(child, sptep);
2642 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2646 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2650 struct kvm_mmu_page *child;
2653 if (is_shadow_present_pte(pte)) {
2654 if (is_last_spte(pte, sp->role.level)) {
2655 drop_spte(kvm, spte);
2656 if (is_large_pte(pte))
2659 child = page_header(pte & PT64_BASE_ADDR_MASK);
2660 drop_parent_pte(child, spte);
2665 if (is_mmio_spte(pte))
2666 mmu_spte_clear_no_track(spte);
2671 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2672 struct kvm_mmu_page *sp)
2676 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2677 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2680 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2683 struct rmap_iterator iter;
2685 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2686 drop_parent_pte(sp, sptep);
2689 static int mmu_zap_unsync_children(struct kvm *kvm,
2690 struct kvm_mmu_page *parent,
2691 struct list_head *invalid_list)
2694 struct mmu_page_path parents;
2695 struct kvm_mmu_pages pages;
2697 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2700 while (mmu_unsync_walk(parent, &pages)) {
2701 struct kvm_mmu_page *sp;
2703 for_each_sp(pages, sp, parents, i) {
2704 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2705 mmu_pages_clear_parents(&parents);
2713 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2714 struct kvm_mmu_page *sp,
2715 struct list_head *invalid_list,
2720 trace_kvm_mmu_prepare_zap_page(sp);
2721 ++kvm->stat.mmu_shadow_zapped;
2722 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2723 kvm_mmu_page_unlink_children(kvm, sp);
2724 kvm_mmu_unlink_parents(kvm, sp);
2726 /* Zapping children means active_mmu_pages has become unstable. */
2727 list_unstable = *nr_zapped;
2729 if (!sp->role.invalid && !sp->role.direct)
2730 unaccount_shadowed(kvm, sp);
2733 kvm_unlink_unsync_page(kvm, sp);
2734 if (!sp->root_count) {
2737 list_move(&sp->link, invalid_list);
2738 kvm_mod_used_mmu_pages(kvm, -1);
2740 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2742 if (!sp->role.invalid)
2743 kvm_reload_remote_mmus(kvm);
2746 sp->role.invalid = 1;
2747 return list_unstable;
2750 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2751 struct list_head *invalid_list)
2755 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2759 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2760 struct list_head *invalid_list)
2762 struct kvm_mmu_page *sp, *nsp;
2764 if (list_empty(invalid_list))
2768 * We need to make sure everyone sees our modifications to
2769 * the page tables and see changes to vcpu->mode here. The barrier
2770 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2771 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2773 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2774 * guest mode and/or lockless shadow page table walks.
2776 kvm_flush_remote_tlbs(kvm);
2778 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2779 WARN_ON(!sp->role.invalid || sp->root_count);
2780 kvm_mmu_free_page(sp);
2784 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2785 struct list_head *invalid_list)
2787 struct kvm_mmu_page *sp;
2789 if (list_empty(&kvm->arch.active_mmu_pages))
2792 sp = list_last_entry(&kvm->arch.active_mmu_pages,
2793 struct kvm_mmu_page, link);
2794 return kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2798 * Changing the number of mmu pages allocated to the vm
2799 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2801 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2803 LIST_HEAD(invalid_list);
2805 spin_lock(&kvm->mmu_lock);
2807 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2808 /* Need to free some mmu pages to achieve the goal. */
2809 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2810 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2813 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2814 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2817 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2819 spin_unlock(&kvm->mmu_lock);
2822 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2824 struct kvm_mmu_page *sp;
2825 LIST_HEAD(invalid_list);
2828 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2830 spin_lock(&kvm->mmu_lock);
2831 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2832 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2835 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2837 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2838 spin_unlock(&kvm->mmu_lock);
2842 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2844 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2846 trace_kvm_mmu_unsync_page(sp);
2847 ++vcpu->kvm->stat.mmu_unsync;
2850 kvm_mmu_mark_parents_unsync(sp);
2853 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2856 struct kvm_mmu_page *sp;
2858 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2861 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2868 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
2869 kvm_unsync_page(vcpu, sp);
2873 * We need to ensure that the marking of unsync pages is visible
2874 * before the SPTE is updated to allow writes because
2875 * kvm_mmu_sync_roots() checks the unsync flags without holding
2876 * the MMU lock and so can race with this. If the SPTE was updated
2877 * before the page had been marked as unsync-ed, something like the
2878 * following could happen:
2881 * ---------------------------------------------------------------------
2882 * 1.2 Host updates SPTE
2884 * 2.1 Guest writes a GPTE for GVA X.
2885 * (GPTE being in the guest page table shadowed
2886 * by the SP from CPU 1.)
2887 * This reads SPTE during the page table walk.
2888 * Since SPTE.W is read as 1, there is no
2891 * 2.2 Guest issues TLB flush.
2892 * That causes a VM Exit.
2894 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
2895 * Since it is false, so it just returns.
2897 * 2.4 Guest accesses GVA X.
2898 * Since the mapping in the SP was not updated,
2899 * so the old mapping for GVA X incorrectly
2903 * (sp->unsync = true)
2905 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2906 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2907 * pairs with this write barrier.
2914 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
2917 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) &&
2919 * Some reserved pages, such as those from NVDIMM
2920 * DAX devices, are not for MMIO, and can be mapped
2921 * with cached memory type for better performance.
2922 * However, the above check misconceives those pages
2923 * as MMIO, and results in KVM mapping them with UC
2924 * memory type, which would hurt the performance.
2925 * Therefore, we check the host memory type in addition
2926 * and only treat UC/UC-/WC pages as MMIO.
2928 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn));
2930 return !e820__mapped_raw_any(pfn_to_hpa(pfn),
2931 pfn_to_hpa(pfn + 1) - 1,
2935 /* Bits which may be returned by set_spte() */
2936 #define SET_SPTE_WRITE_PROTECTED_PT BIT(0)
2937 #define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1)
2939 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2940 unsigned pte_access, int level,
2941 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2942 bool can_unsync, bool host_writable)
2946 struct kvm_mmu_page *sp;
2948 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2951 sp = page_header(__pa(sptep));
2952 if (sp_ad_disabled(sp))
2953 spte |= shadow_acc_track_value;
2956 * For the EPT case, shadow_present_mask is 0 if hardware
2957 * supports exec-only page table entries. In that case,
2958 * ACC_USER_MASK and shadow_user_mask are used to represent
2959 * read access. See FNAME(gpte_access) in paging_tmpl.h.
2961 spte |= shadow_present_mask;
2963 spte |= spte_shadow_accessed_mask(spte);
2965 if (pte_access & ACC_EXEC_MASK)
2966 spte |= shadow_x_mask;
2968 spte |= shadow_nx_mask;
2970 if (pte_access & ACC_USER_MASK)
2971 spte |= shadow_user_mask;
2973 if (level > PT_PAGE_TABLE_LEVEL)
2974 spte |= PT_PAGE_SIZE_MASK;
2976 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2977 kvm_is_mmio_pfn(pfn));
2980 spte |= SPTE_HOST_WRITEABLE;
2982 pte_access &= ~ACC_WRITE_MASK;
2984 if (!kvm_is_mmio_pfn(pfn))
2985 spte |= shadow_me_mask;
2987 spte |= (u64)pfn << PAGE_SHIFT;
2989 if (pte_access & ACC_WRITE_MASK) {
2992 * Other vcpu creates new sp in the window between
2993 * mapping_level() and acquiring mmu-lock. We can
2994 * allow guest to retry the access, the mapping can
2995 * be fixed if guest refault.
2997 if (level > PT_PAGE_TABLE_LEVEL &&
2998 mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
3001 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
3004 * Optimization: for pte sync, if spte was writable the hash
3005 * lookup is unnecessary (and expensive). Write protection
3006 * is responsibility of mmu_get_page / kvm_sync_page.
3007 * Same reasoning can be applied to dirty page accounting.
3009 if (!can_unsync && is_writable_pte(*sptep))
3012 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
3013 pgprintk("%s: found shadow page for %llx, marking ro\n",
3015 ret |= SET_SPTE_WRITE_PROTECTED_PT;
3016 pte_access &= ~ACC_WRITE_MASK;
3017 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
3021 if (pte_access & ACC_WRITE_MASK) {
3022 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3023 spte |= spte_shadow_dirty_mask(spte);
3027 spte = mark_spte_for_access_track(spte);
3030 if (mmu_spte_update(sptep, spte))
3031 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
3036 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
3037 int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
3038 bool speculative, bool host_writable)
3040 int was_rmapped = 0;
3043 int ret = RET_PF_RETRY;
3046 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
3047 *sptep, write_fault, gfn);
3049 if (is_shadow_present_pte(*sptep)) {
3051 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
3052 * the parent of the now unreachable PTE.
3054 if (level > PT_PAGE_TABLE_LEVEL &&
3055 !is_large_pte(*sptep)) {
3056 struct kvm_mmu_page *child;
3059 child = page_header(pte & PT64_BASE_ADDR_MASK);
3060 drop_parent_pte(child, sptep);
3062 } else if (pfn != spte_to_pfn(*sptep)) {
3063 pgprintk("hfn old %llx new %llx\n",
3064 spte_to_pfn(*sptep), pfn);
3065 drop_spte(vcpu->kvm, sptep);
3071 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
3072 speculative, true, host_writable);
3073 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
3075 ret = RET_PF_EMULATE;
3076 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3079 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
3080 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
3081 KVM_PAGES_PER_HPAGE(level));
3083 if (unlikely(is_mmio_spte(*sptep)))
3084 ret = RET_PF_EMULATE;
3086 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
3087 trace_kvm_mmu_set_spte(level, gfn, sptep);
3088 if (!was_rmapped && is_large_pte(*sptep))
3089 ++vcpu->kvm->stat.lpages;
3091 if (is_shadow_present_pte(*sptep)) {
3093 rmap_count = rmap_add(vcpu, sptep, gfn);
3094 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
3095 rmap_recycle(vcpu, sptep, gfn);
3102 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
3105 struct kvm_memory_slot *slot;
3107 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
3109 return KVM_PFN_ERR_FAULT;
3111 return gfn_to_pfn_memslot_atomic(slot, gfn);
3114 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
3115 struct kvm_mmu_page *sp,
3116 u64 *start, u64 *end)
3118 struct page *pages[PTE_PREFETCH_NUM];
3119 struct kvm_memory_slot *slot;
3120 unsigned access = sp->role.access;
3124 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
3125 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
3129 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
3133 for (i = 0; i < ret; i++, gfn++, start++) {
3134 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
3135 page_to_pfn(pages[i]), true, true);
3142 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
3143 struct kvm_mmu_page *sp, u64 *sptep)
3145 u64 *spte, *start = NULL;
3148 WARN_ON(!sp->role.direct);
3150 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
3153 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
3154 if (is_shadow_present_pte(*spte) || spte == sptep) {
3157 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
3165 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
3167 struct kvm_mmu_page *sp;
3169 sp = page_header(__pa(sptep));
3172 * Without accessed bits, there's no way to distinguish between
3173 * actually accessed translations and prefetched, so disable pte
3174 * prefetch if accessed bits aren't available.
3176 if (sp_ad_disabled(sp))
3179 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3182 __direct_pte_prefetch(vcpu, sp, sptep);
3185 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, int write,
3186 int map_writable, int level, kvm_pfn_t pfn,
3189 struct kvm_shadow_walk_iterator it;
3190 struct kvm_mmu_page *sp;
3192 gfn_t gfn = gpa >> PAGE_SHIFT;
3193 gfn_t base_gfn = gfn;
3195 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3196 return RET_PF_RETRY;
3198 trace_kvm_mmu_spte_requested(gpa, level, pfn);
3199 for_each_shadow_entry(vcpu, gpa, it) {
3200 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
3201 if (it.level == level)
3204 drop_large_spte(vcpu, it.sptep);
3205 if (!is_shadow_present_pte(*it.sptep)) {
3206 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
3207 it.level - 1, true, ACC_ALL);
3209 link_shadow_page(vcpu, it.sptep, sp);
3213 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
3214 write, level, base_gfn, pfn, prefault,
3216 direct_pte_prefetch(vcpu, it.sptep);
3217 ++vcpu->stat.pf_fixed;
3221 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
3223 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
3226 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
3229 * Do not cache the mmio info caused by writing the readonly gfn
3230 * into the spte otherwise read access on readonly gfn also can
3231 * caused mmio page fault and treat it as mmio access.
3233 if (pfn == KVM_PFN_ERR_RO_FAULT)
3234 return RET_PF_EMULATE;
3236 if (pfn == KVM_PFN_ERR_HWPOISON) {
3237 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
3238 return RET_PF_RETRY;
3244 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
3245 gfn_t gfn, kvm_pfn_t *pfnp,
3248 kvm_pfn_t pfn = *pfnp;
3249 int level = *levelp;
3252 * Check if it's a transparent hugepage. If this would be an
3253 * hugetlbfs page, level wouldn't be set to
3254 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
3257 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
3258 level == PT_PAGE_TABLE_LEVEL &&
3259 PageTransCompoundMap(pfn_to_page(pfn)) &&
3260 !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
3263 * mmu_notifier_retry was successful and we hold the
3264 * mmu_lock here, so the pmd can't become splitting
3265 * from under us, and in turn
3266 * __split_huge_page_refcount() can't run from under
3267 * us and we can safely transfer the refcount from
3268 * PG_tail to PG_head as we switch the pfn to tail to
3271 *levelp = level = PT_DIRECTORY_LEVEL;
3272 mask = KVM_PAGES_PER_HPAGE(level) - 1;
3273 VM_BUG_ON((gfn & mask) != (pfn & mask));
3275 kvm_release_pfn_clean(pfn);
3283 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
3284 kvm_pfn_t pfn, unsigned access, int *ret_val)
3286 /* The pfn is invalid, report the error! */
3287 if (unlikely(is_error_pfn(pfn))) {
3288 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
3292 if (unlikely(is_noslot_pfn(pfn)))
3293 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
3298 static bool page_fault_can_be_fast(u32 error_code)
3301 * Do not fix the mmio spte with invalid generation number which
3302 * need to be updated by slow page fault path.
3304 if (unlikely(error_code & PFERR_RSVD_MASK))
3307 /* See if the page fault is due to an NX violation */
3308 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3309 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3313 * #PF can be fast if:
3314 * 1. The shadow page table entry is not present, which could mean that
3315 * the fault is potentially caused by access tracking (if enabled).
3316 * 2. The shadow page table entry is present and the fault
3317 * is caused by write-protect, that means we just need change the W
3318 * bit of the spte which can be done out of mmu-lock.
3320 * However, if access tracking is disabled we know that a non-present
3321 * page must be a genuine page fault where we have to create a new SPTE.
3322 * So, if access tracking is disabled, we return true only for write
3323 * accesses to a present page.
3326 return shadow_acc_track_mask != 0 ||
3327 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3328 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3332 * Returns true if the SPTE was fixed successfully. Otherwise,
3333 * someone else modified the SPTE from its original value.
3336 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3337 u64 *sptep, u64 old_spte, u64 new_spte)
3341 WARN_ON(!sp->role.direct);
3344 * Theoretically we could also set dirty bit (and flush TLB) here in
3345 * order to eliminate unnecessary PML logging. See comments in
3346 * set_spte. But fast_page_fault is very unlikely to happen with PML
3347 * enabled, so we do not do this. This might result in the same GPA
3348 * to be logged in PML buffer again when the write really happens, and
3349 * eventually to be called by mark_page_dirty twice. But it's also no
3350 * harm. This also avoids the TLB flush needed after setting dirty bit
3351 * so non-PML cases won't be impacted.
3353 * Compare with set_spte where instead shadow_dirty_mask is set.
3355 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3358 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3360 * The gfn of direct spte is stable since it is
3361 * calculated by sp->gfn.
3363 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3364 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3370 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3372 if (fault_err_code & PFERR_FETCH_MASK)
3373 return is_executable_pte(spte);
3375 if (fault_err_code & PFERR_WRITE_MASK)
3376 return is_writable_pte(spte);
3378 /* Fault was on Read access */
3379 return spte & PT_PRESENT_MASK;
3384 * - true: let the vcpu to access on the same address again.
3385 * - false: let the real page fault path to fix it.
3387 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
3390 struct kvm_shadow_walk_iterator iterator;
3391 struct kvm_mmu_page *sp;
3392 bool fault_handled = false;
3394 uint retry_count = 0;
3396 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3399 if (!page_fault_can_be_fast(error_code))
3402 walk_shadow_page_lockless_begin(vcpu);
3407 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
3408 if (!is_shadow_present_pte(spte) ||
3409 iterator.level < level)
3412 sp = page_header(__pa(iterator.sptep));
3413 if (!is_last_spte(spte, sp->role.level))
3417 * Check whether the memory access that caused the fault would
3418 * still cause it if it were to be performed right now. If not,
3419 * then this is a spurious fault caused by TLB lazily flushed,
3420 * or some other CPU has already fixed the PTE after the
3421 * current CPU took the fault.
3423 * Need not check the access of upper level table entries since
3424 * they are always ACC_ALL.
3426 if (is_access_allowed(error_code, spte)) {
3427 fault_handled = true;
3433 if (is_access_track_spte(spte))
3434 new_spte = restore_acc_track_spte(new_spte);
3437 * Currently, to simplify the code, write-protection can
3438 * be removed in the fast path only if the SPTE was
3439 * write-protected for dirty-logging or access tracking.
3441 if ((error_code & PFERR_WRITE_MASK) &&
3442 spte_can_locklessly_be_made_writable(spte))
3444 new_spte |= PT_WRITABLE_MASK;
3447 * Do not fix write-permission on the large spte. Since
3448 * we only dirty the first page into the dirty-bitmap in
3449 * fast_pf_fix_direct_spte(), other pages are missed
3450 * if its slot has dirty logging enabled.
3452 * Instead, we let the slow page fault path create a
3453 * normal spte to fix the access.
3455 * See the comments in kvm_arch_commit_memory_region().
3457 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3461 /* Verify that the fault can be handled in the fast path */
3462 if (new_spte == spte ||
3463 !is_access_allowed(error_code, new_spte))
3467 * Currently, fast page fault only works for direct mapping
3468 * since the gfn is not stable for indirect shadow page. See
3469 * Documentation/virtual/kvm/locking.txt to get more detail.
3471 fault_handled = fast_pf_fix_direct_spte(vcpu, sp,
3472 iterator.sptep, spte,
3477 if (++retry_count > 4) {
3478 printk_once(KERN_WARNING
3479 "kvm: Fast #PF retrying more than 4 times.\n");
3485 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
3486 spte, fault_handled);
3487 walk_shadow_page_lockless_end(vcpu);
3489 return fault_handled;
3492 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3493 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable);
3494 static int make_mmu_pages_available(struct kvm_vcpu *vcpu);
3496 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
3497 gfn_t gfn, bool prefault)
3501 bool force_pt_level = false;
3503 unsigned long mmu_seq;
3504 bool map_writable, write = error_code & PFERR_WRITE_MASK;
3506 level = mapping_level(vcpu, gfn, &force_pt_level);
3507 if (likely(!force_pt_level)) {
3509 * This path builds a PAE pagetable - so we can map
3510 * 2mb pages at maximum. Therefore check if the level
3511 * is larger than that.
3513 if (level > PT_DIRECTORY_LEVEL)
3514 level = PT_DIRECTORY_LEVEL;
3516 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3519 if (fast_page_fault(vcpu, v, level, error_code))
3520 return RET_PF_RETRY;
3522 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3525 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3526 return RET_PF_RETRY;
3528 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3532 spin_lock(&vcpu->kvm->mmu_lock);
3533 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3535 if (make_mmu_pages_available(vcpu) < 0)
3537 if (likely(!force_pt_level))
3538 transparent_hugepage_adjust(vcpu, gfn, &pfn, &level);
3539 r = __direct_map(vcpu, v, write, map_writable, level, pfn, prefault);
3541 spin_unlock(&vcpu->kvm->mmu_lock);
3542 kvm_release_pfn_clean(pfn);
3546 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3547 struct list_head *invalid_list)
3549 struct kvm_mmu_page *sp;
3551 if (!VALID_PAGE(*root_hpa))
3554 sp = page_header(*root_hpa & PT64_BASE_ADDR_MASK);
3556 if (!sp->root_count && sp->role.invalid)
3557 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3559 *root_hpa = INVALID_PAGE;
3562 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3563 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3564 ulong roots_to_free)
3567 LIST_HEAD(invalid_list);
3568 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3570 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3572 /* Before acquiring the MMU lock, see if we need to do any real work. */
3573 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3574 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3575 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3576 VALID_PAGE(mmu->prev_roots[i].hpa))
3579 if (i == KVM_MMU_NUM_PREV_ROOTS)
3583 spin_lock(&vcpu->kvm->mmu_lock);
3585 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3586 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3587 mmu_free_root_page(vcpu->kvm, &mmu->prev_roots[i].hpa,
3590 if (free_active_root) {
3591 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3592 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3593 mmu_free_root_page(vcpu->kvm, &mmu->root_hpa,
3596 for (i = 0; i < 4; ++i)
3597 if (mmu->pae_root[i] != 0)
3598 mmu_free_root_page(vcpu->kvm,
3601 mmu->root_hpa = INVALID_PAGE;
3606 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3607 spin_unlock(&vcpu->kvm->mmu_lock);
3609 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3611 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3615 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3616 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3623 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3625 struct kvm_mmu_page *sp;
3628 if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) {
3629 spin_lock(&vcpu->kvm->mmu_lock);
3630 if(make_mmu_pages_available(vcpu) < 0) {
3631 spin_unlock(&vcpu->kvm->mmu_lock);
3634 sp = kvm_mmu_get_page(vcpu, 0, 0,
3635 vcpu->arch.mmu->shadow_root_level, 1, ACC_ALL);
3637 spin_unlock(&vcpu->kvm->mmu_lock);
3638 vcpu->arch.mmu->root_hpa = __pa(sp->spt);
3639 } else if (vcpu->arch.mmu->shadow_root_level == PT32E_ROOT_LEVEL) {
3640 for (i = 0; i < 4; ++i) {
3641 hpa_t root = vcpu->arch.mmu->pae_root[i];
3643 MMU_WARN_ON(VALID_PAGE(root));
3644 spin_lock(&vcpu->kvm->mmu_lock);
3645 if (make_mmu_pages_available(vcpu) < 0) {
3646 spin_unlock(&vcpu->kvm->mmu_lock);
3649 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3650 i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3651 root = __pa(sp->spt);
3653 spin_unlock(&vcpu->kvm->mmu_lock);
3654 vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK;
3656 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3659 vcpu->arch.mmu->root_cr3 = vcpu->arch.mmu->get_cr3(vcpu);
3664 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3666 struct kvm_mmu_page *sp;
3668 gfn_t root_gfn, root_cr3;
3671 root_cr3 = vcpu->arch.mmu->get_cr3(vcpu);
3672 root_gfn = root_cr3 >> PAGE_SHIFT;
3674 if (mmu_check_root(vcpu, root_gfn))
3678 * Do we shadow a long mode page table? If so we need to
3679 * write-protect the guests page table root.
3681 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3682 hpa_t root = vcpu->arch.mmu->root_hpa;
3684 MMU_WARN_ON(VALID_PAGE(root));
3686 spin_lock(&vcpu->kvm->mmu_lock);
3687 if (make_mmu_pages_available(vcpu) < 0) {
3688 spin_unlock(&vcpu->kvm->mmu_lock);
3691 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
3692 vcpu->arch.mmu->shadow_root_level, 0, ACC_ALL);
3693 root = __pa(sp->spt);
3695 spin_unlock(&vcpu->kvm->mmu_lock);
3696 vcpu->arch.mmu->root_hpa = root;
3701 * We shadow a 32 bit page table. This may be a legacy 2-level
3702 * or a PAE 3-level page table. In either case we need to be aware that
3703 * the shadow page table may be a PAE or a long mode page table.
3705 pm_mask = PT_PRESENT_MASK;
3706 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3707 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3709 for (i = 0; i < 4; ++i) {
3710 hpa_t root = vcpu->arch.mmu->pae_root[i];
3712 MMU_WARN_ON(VALID_PAGE(root));
3713 if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) {
3714 pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i);
3715 if (!(pdptr & PT_PRESENT_MASK)) {
3716 vcpu->arch.mmu->pae_root[i] = 0;
3719 root_gfn = pdptr >> PAGE_SHIFT;
3720 if (mmu_check_root(vcpu, root_gfn))
3723 spin_lock(&vcpu->kvm->mmu_lock);
3724 if (make_mmu_pages_available(vcpu) < 0) {
3725 spin_unlock(&vcpu->kvm->mmu_lock);
3728 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3730 root = __pa(sp->spt);
3732 spin_unlock(&vcpu->kvm->mmu_lock);
3734 vcpu->arch.mmu->pae_root[i] = root | pm_mask;
3736 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3739 * If we shadow a 32 bit page table with a long mode page
3740 * table we enter this path.
3742 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3743 if (vcpu->arch.mmu->lm_root == NULL) {
3745 * The additional page necessary for this is only
3746 * allocated on demand.
3751 lm_root = (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3752 if (lm_root == NULL)
3755 lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask;
3757 vcpu->arch.mmu->lm_root = lm_root;
3760 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root);
3764 vcpu->arch.mmu->root_cr3 = root_cr3;
3769 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3771 if (vcpu->arch.mmu->direct_map)
3772 return mmu_alloc_direct_roots(vcpu);
3774 return mmu_alloc_shadow_roots(vcpu);
3777 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3780 struct kvm_mmu_page *sp;
3782 if (vcpu->arch.mmu->direct_map)
3785 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3788 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3790 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3791 hpa_t root = vcpu->arch.mmu->root_hpa;
3792 sp = page_header(root);
3795 * Even if another CPU was marking the SP as unsync-ed
3796 * simultaneously, any guest page table changes are not
3797 * guaranteed to be visible anyway until this VCPU issues a TLB
3798 * flush strictly after those changes are made. We only need to
3799 * ensure that the other CPU sets these flags before any actual
3800 * changes to the page tables are made. The comments in
3801 * mmu_need_write_protect() describe what could go wrong if this
3802 * requirement isn't satisfied.
3804 if (!smp_load_acquire(&sp->unsync) &&
3805 !smp_load_acquire(&sp->unsync_children))
3808 spin_lock(&vcpu->kvm->mmu_lock);
3809 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3811 mmu_sync_children(vcpu, sp);
3813 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3814 spin_unlock(&vcpu->kvm->mmu_lock);
3818 spin_lock(&vcpu->kvm->mmu_lock);
3819 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3821 for (i = 0; i < 4; ++i) {
3822 hpa_t root = vcpu->arch.mmu->pae_root[i];
3824 if (root && VALID_PAGE(root)) {
3825 root &= PT64_BASE_ADDR_MASK;
3826 sp = page_header(root);
3827 mmu_sync_children(vcpu, sp);
3831 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3832 spin_unlock(&vcpu->kvm->mmu_lock);
3834 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3836 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3837 u32 access, struct x86_exception *exception)
3840 exception->error_code = 0;
3844 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3846 struct x86_exception *exception)
3849 exception->error_code = 0;
3850 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3854 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3856 int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3858 return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3859 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3862 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3864 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3867 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3869 return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3872 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3875 * A nested guest cannot use the MMIO cache if it is using nested
3876 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3878 if (mmu_is_nested(vcpu))
3882 return vcpu_match_mmio_gpa(vcpu, addr);
3884 return vcpu_match_mmio_gva(vcpu, addr);
3887 /* return true if reserved bit is detected on spte. */
3889 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3891 struct kvm_shadow_walk_iterator iterator;
3892 u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull;
3894 bool reserved = false;
3896 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3899 walk_shadow_page_lockless_begin(vcpu);
3901 for (shadow_walk_init(&iterator, vcpu, addr),
3902 leaf = root = iterator.level;
3903 shadow_walk_okay(&iterator);
3904 __shadow_walk_next(&iterator, spte)) {
3905 spte = mmu_spte_get_lockless(iterator.sptep);
3907 sptes[leaf - 1] = spte;
3910 if (!is_shadow_present_pte(spte))
3913 reserved |= is_shadow_zero_bits_set(vcpu->arch.mmu, spte,
3917 walk_shadow_page_lockless_end(vcpu);
3920 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3922 while (root > leaf) {
3923 pr_err("------ spte 0x%llx level %d.\n",
3924 sptes[root - 1], root);
3933 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3938 if (mmio_info_in_cache(vcpu, addr, direct))
3939 return RET_PF_EMULATE;
3941 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3942 if (WARN_ON(reserved))
3945 if (is_mmio_spte(spte)) {
3946 gfn_t gfn = get_mmio_spte_gfn(spte);
3947 unsigned access = get_mmio_spte_access(spte);
3949 if (!check_mmio_spte(vcpu, spte))
3950 return RET_PF_INVALID;
3955 trace_handle_mmio_page_fault(addr, gfn, access);
3956 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3957 return RET_PF_EMULATE;
3961 * If the page table is zapped by other cpus, let CPU fault again on
3964 return RET_PF_RETRY;
3967 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3968 u32 error_code, gfn_t gfn)
3970 if (unlikely(error_code & PFERR_RSVD_MASK))
3973 if (!(error_code & PFERR_PRESENT_MASK) ||
3974 !(error_code & PFERR_WRITE_MASK))
3978 * guest is writing the page which is write tracked which can
3979 * not be fixed by page fault handler.
3981 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3987 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3989 struct kvm_shadow_walk_iterator iterator;
3992 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3995 walk_shadow_page_lockless_begin(vcpu);
3996 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3997 clear_sp_write_flooding_count(iterator.sptep);
3998 if (!is_shadow_present_pte(spte))
4001 walk_shadow_page_lockless_end(vcpu);
4004 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
4005 u32 error_code, bool prefault)
4007 gfn_t gfn = gva >> PAGE_SHIFT;
4010 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
4012 if (page_fault_handle_page_track(vcpu, error_code, gfn))
4013 return RET_PF_EMULATE;
4015 r = mmu_topup_memory_caches(vcpu);
4019 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa));
4022 return nonpaging_map(vcpu, gva & PAGE_MASK,
4023 error_code, gfn, prefault);
4026 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
4028 struct kvm_arch_async_pf arch;
4030 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
4032 arch.direct_map = vcpu->arch.mmu->direct_map;
4033 arch.cr3 = vcpu->arch.mmu->get_cr3(vcpu);
4035 return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
4038 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
4039 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable)
4041 struct kvm_memory_slot *slot;
4045 * Don't expose private memslots to L2.
4047 if (is_guest_mode(vcpu) && !kvm_is_visible_gfn(vcpu->kvm, gfn)) {
4048 *pfn = KVM_PFN_NOSLOT;
4052 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
4054 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
4056 return false; /* *pfn has correct page already */
4058 if (!prefault && kvm_can_do_async_pf(vcpu)) {
4059 trace_kvm_try_async_get_page(gva, gfn);
4060 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
4061 trace_kvm_async_pf_doublefault(gva, gfn);
4062 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
4064 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
4068 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
4072 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
4073 u64 fault_address, char *insn, int insn_len)
4077 vcpu->arch.l1tf_flush_l1d = true;
4078 switch (vcpu->arch.apf.host_apf_reason) {
4080 trace_kvm_page_fault(fault_address, error_code);
4082 if (kvm_event_needs_reinjection(vcpu))
4083 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
4084 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
4087 case KVM_PV_REASON_PAGE_NOT_PRESENT:
4088 vcpu->arch.apf.host_apf_reason = 0;
4089 local_irq_disable();
4090 kvm_async_pf_task_wait(fault_address, 0);
4093 case KVM_PV_REASON_PAGE_READY:
4094 vcpu->arch.apf.host_apf_reason = 0;
4095 local_irq_disable();
4096 kvm_async_pf_task_wake(fault_address);
4102 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
4105 check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
4107 int page_num = KVM_PAGES_PER_HPAGE(level);
4109 gfn &= ~(page_num - 1);
4111 return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
4114 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
4120 bool force_pt_level;
4121 gfn_t gfn = gpa >> PAGE_SHIFT;
4122 unsigned long mmu_seq;
4123 int write = error_code & PFERR_WRITE_MASK;
4126 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa));
4128 if (page_fault_handle_page_track(vcpu, error_code, gfn))
4129 return RET_PF_EMULATE;
4131 r = mmu_topup_memory_caches(vcpu);
4135 force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn,
4136 PT_DIRECTORY_LEVEL);
4137 level = mapping_level(vcpu, gfn, &force_pt_level);
4138 if (likely(!force_pt_level)) {
4139 if (level > PT_DIRECTORY_LEVEL &&
4140 !check_hugepage_cache_consistency(vcpu, gfn, level))
4141 level = PT_DIRECTORY_LEVEL;
4142 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
4145 if (fast_page_fault(vcpu, gpa, level, error_code))
4146 return RET_PF_RETRY;
4148 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4151 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
4152 return RET_PF_RETRY;
4154 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
4158 spin_lock(&vcpu->kvm->mmu_lock);
4159 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
4161 if (make_mmu_pages_available(vcpu) < 0)
4163 if (likely(!force_pt_level))
4164 transparent_hugepage_adjust(vcpu, gfn, &pfn, &level);
4165 r = __direct_map(vcpu, gpa, write, map_writable, level, pfn, prefault);
4167 spin_unlock(&vcpu->kvm->mmu_lock);
4168 kvm_release_pfn_clean(pfn);
4172 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
4173 struct kvm_mmu *context)
4175 context->page_fault = nonpaging_page_fault;
4176 context->gva_to_gpa = nonpaging_gva_to_gpa;
4177 context->sync_page = nonpaging_sync_page;
4178 context->invlpg = nonpaging_invlpg;
4179 context->update_pte = nonpaging_update_pte;
4180 context->root_level = 0;
4181 context->shadow_root_level = PT32E_ROOT_LEVEL;
4182 context->direct_map = true;
4183 context->nx = false;
4187 * Find out if a previously cached root matching the new CR3/role is available.
4188 * The current root is also inserted into the cache.
4189 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
4191 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
4192 * false is returned. This root should now be freed by the caller.
4194 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4195 union kvm_mmu_page_role new_role)
4198 struct kvm_mmu_root_info root;
4199 struct kvm_mmu *mmu = vcpu->arch.mmu;
4201 root.cr3 = mmu->root_cr3;
4202 root.hpa = mmu->root_hpa;
4204 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
4205 swap(root, mmu->prev_roots[i]);
4207 if (new_cr3 == root.cr3 && VALID_PAGE(root.hpa) &&
4208 page_header(root.hpa) != NULL &&
4209 new_role.word == page_header(root.hpa)->role.word)
4213 mmu->root_hpa = root.hpa;
4214 mmu->root_cr3 = root.cr3;
4216 return i < KVM_MMU_NUM_PREV_ROOTS;
4219 static bool fast_cr3_switch(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4220 union kvm_mmu_page_role new_role,
4221 bool skip_tlb_flush)
4223 struct kvm_mmu *mmu = vcpu->arch.mmu;
4226 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4227 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4228 * later if necessary.
4230 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
4231 mmu->root_level >= PT64_ROOT_4LEVEL) {
4232 if (mmu_check_root(vcpu, new_cr3 >> PAGE_SHIFT))
4235 if (cached_root_available(vcpu, new_cr3, new_role)) {
4236 kvm_make_request(KVM_REQ_LOAD_CR3, vcpu);
4237 if (!skip_tlb_flush) {
4238 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
4239 kvm_x86_ops->tlb_flush(vcpu, true);
4243 * The last MMIO access's GVA and GPA are cached in the
4244 * VCPU. When switching to a new CR3, that GVA->GPA
4245 * mapping may no longer be valid. So clear any cached
4246 * MMIO info even when we don't need to sync the shadow
4249 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4251 __clear_sp_write_flooding_count(
4252 page_header(mmu->root_hpa));
4261 static void __kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4262 union kvm_mmu_page_role new_role,
4263 bool skip_tlb_flush)
4265 if (!fast_cr3_switch(vcpu, new_cr3, new_role, skip_tlb_flush))
4266 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu,
4267 KVM_MMU_ROOT_CURRENT);
4270 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush)
4272 __kvm_mmu_new_cr3(vcpu, new_cr3, kvm_mmu_calc_root_page_role(vcpu),
4275 EXPORT_SYMBOL_GPL(kvm_mmu_new_cr3);
4277 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4279 return kvm_read_cr3(vcpu);
4282 static void inject_page_fault(struct kvm_vcpu *vcpu,
4283 struct x86_exception *fault)
4285 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
4288 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4289 unsigned access, int *nr_present)
4291 if (unlikely(is_mmio_spte(*sptep))) {
4292 if (gfn != get_mmio_spte_gfn(*sptep)) {
4293 mmu_spte_clear_no_track(sptep);
4298 mark_mmio_spte(vcpu, sptep, gfn, access);
4305 static inline bool is_last_gpte(struct kvm_mmu *mmu,
4306 unsigned level, unsigned gpte)
4309 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
4310 * If it is clear, there are no large pages at this level, so clear
4311 * PT_PAGE_SIZE_MASK in gpte if that is the case.
4313 gpte &= level - mmu->last_nonleaf_level;
4316 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
4317 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
4318 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
4320 gpte |= level - PT_PAGE_TABLE_LEVEL - 1;
4322 return gpte & PT_PAGE_SIZE_MASK;
4325 #define PTTYPE_EPT 18 /* arbitrary */
4326 #define PTTYPE PTTYPE_EPT
4327 #include "paging_tmpl.h"
4331 #include "paging_tmpl.h"
4335 #include "paging_tmpl.h"
4339 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4340 struct rsvd_bits_validate *rsvd_check,
4341 int maxphyaddr, int level, bool nx, bool gbpages,
4344 u64 exb_bit_rsvd = 0;
4345 u64 gbpages_bit_rsvd = 0;
4346 u64 nonleaf_bit8_rsvd = 0;
4348 rsvd_check->bad_mt_xwr = 0;
4351 exb_bit_rsvd = rsvd_bits(63, 63);
4353 gbpages_bit_rsvd = rsvd_bits(7, 7);
4356 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4357 * leaf entries) on AMD CPUs only.
4360 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4363 case PT32_ROOT_LEVEL:
4364 /* no rsvd bits for 2 level 4K page table entries */
4365 rsvd_check->rsvd_bits_mask[0][1] = 0;
4366 rsvd_check->rsvd_bits_mask[0][0] = 0;
4367 rsvd_check->rsvd_bits_mask[1][0] =
4368 rsvd_check->rsvd_bits_mask[0][0];
4371 rsvd_check->rsvd_bits_mask[1][1] = 0;
4375 if (is_cpuid_PSE36())
4376 /* 36bits PSE 4MB page */
4377 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4379 /* 32 bits PSE 4MB page */
4380 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4382 case PT32E_ROOT_LEVEL:
4383 rsvd_check->rsvd_bits_mask[0][2] =
4384 rsvd_bits(maxphyaddr, 63) |
4385 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
4386 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4387 rsvd_bits(maxphyaddr, 62); /* PDE */
4388 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4389 rsvd_bits(maxphyaddr, 62); /* PTE */
4390 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4391 rsvd_bits(maxphyaddr, 62) |
4392 rsvd_bits(13, 20); /* large page */
4393 rsvd_check->rsvd_bits_mask[1][0] =
4394 rsvd_check->rsvd_bits_mask[0][0];
4396 case PT64_ROOT_5LEVEL:
4397 rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd |
4398 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4399 rsvd_bits(maxphyaddr, 51);
4400 rsvd_check->rsvd_bits_mask[1][4] =
4401 rsvd_check->rsvd_bits_mask[0][4];
4403 case PT64_ROOT_4LEVEL:
4404 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
4405 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4406 rsvd_bits(maxphyaddr, 51);
4407 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
4408 nonleaf_bit8_rsvd | gbpages_bit_rsvd |
4409 rsvd_bits(maxphyaddr, 51);
4410 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4411 rsvd_bits(maxphyaddr, 51);
4412 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4413 rsvd_bits(maxphyaddr, 51);
4414 rsvd_check->rsvd_bits_mask[1][3] =
4415 rsvd_check->rsvd_bits_mask[0][3];
4416 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
4417 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
4419 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4420 rsvd_bits(maxphyaddr, 51) |
4421 rsvd_bits(13, 20); /* large page */
4422 rsvd_check->rsvd_bits_mask[1][0] =
4423 rsvd_check->rsvd_bits_mask[0][0];
4428 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4429 struct kvm_mmu *context)
4431 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4432 cpuid_maxphyaddr(vcpu), context->root_level,
4434 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4435 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
4439 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4440 int maxphyaddr, bool execonly)
4444 rsvd_check->rsvd_bits_mask[0][4] =
4445 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4446 rsvd_check->rsvd_bits_mask[0][3] =
4447 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4448 rsvd_check->rsvd_bits_mask[0][2] =
4449 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4450 rsvd_check->rsvd_bits_mask[0][1] =
4451 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4452 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
4455 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4456 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4457 rsvd_check->rsvd_bits_mask[1][2] =
4458 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
4459 rsvd_check->rsvd_bits_mask[1][1] =
4460 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
4461 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4463 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4464 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4465 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4466 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4467 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4469 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4470 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4472 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4475 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4476 struct kvm_mmu *context, bool execonly)
4478 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4479 cpuid_maxphyaddr(vcpu), execonly);
4483 * the page table on host is the shadow page table for the page
4484 * table in guest or amd nested guest, its mmu features completely
4485 * follow the features in guest.
4488 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4490 bool uses_nx = context->nx ||
4491 context->mmu_role.base.smep_andnot_wp;
4492 struct rsvd_bits_validate *shadow_zero_check;
4496 * Passing "true" to the last argument is okay; it adds a check
4497 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4499 shadow_zero_check = &context->shadow_zero_check;
4500 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4502 context->shadow_root_level, uses_nx,
4503 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4504 is_pse(vcpu), true);
4506 if (!shadow_me_mask)
4509 for (i = context->shadow_root_level; --i >= 0;) {
4510 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4511 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4515 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4517 static inline bool boot_cpu_is_amd(void)
4519 WARN_ON_ONCE(!tdp_enabled);
4520 return shadow_x_mask == 0;
4524 * the direct page table on host, use as much mmu features as
4525 * possible, however, kvm currently does not do execution-protection.
4528 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4529 struct kvm_mmu *context)
4531 struct rsvd_bits_validate *shadow_zero_check;
4534 shadow_zero_check = &context->shadow_zero_check;
4536 if (boot_cpu_is_amd())
4537 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4539 context->shadow_root_level, false,
4540 boot_cpu_has(X86_FEATURE_GBPAGES),
4543 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4547 if (!shadow_me_mask)
4550 for (i = context->shadow_root_level; --i >= 0;) {
4551 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4552 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4557 * as the comments in reset_shadow_zero_bits_mask() except it
4558 * is the shadow page table for intel nested guest.
4561 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4562 struct kvm_mmu *context, bool execonly)
4564 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4565 shadow_phys_bits, execonly);
4568 #define BYTE_MASK(access) \
4569 ((1 & (access) ? 2 : 0) | \
4570 (2 & (access) ? 4 : 0) | \
4571 (3 & (access) ? 8 : 0) | \
4572 (4 & (access) ? 16 : 0) | \
4573 (5 & (access) ? 32 : 0) | \
4574 (6 & (access) ? 64 : 0) | \
4575 (7 & (access) ? 128 : 0))
4578 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4579 struct kvm_mmu *mmu, bool ept)
4583 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4584 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4585 const u8 u = BYTE_MASK(ACC_USER_MASK);
4587 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4588 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4589 bool cr0_wp = is_write_protection(vcpu);
4591 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4592 unsigned pfec = byte << 1;
4595 * Each "*f" variable has a 1 bit for each UWX value
4596 * that causes a fault with the given PFEC.
4599 /* Faults from writes to non-writable pages */
4600 u8 wf = (pfec & PFERR_WRITE_MASK) ? ~w : 0;
4601 /* Faults from user mode accesses to supervisor pages */
4602 u8 uf = (pfec & PFERR_USER_MASK) ? ~u : 0;
4603 /* Faults from fetches of non-executable pages*/
4604 u8 ff = (pfec & PFERR_FETCH_MASK) ? ~x : 0;
4605 /* Faults from kernel mode fetches of user pages */
4607 /* Faults from kernel mode accesses of user pages */
4611 /* Faults from kernel mode accesses to user pages */
4612 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4614 /* Not really needed: !nx will cause pte.nx to fault */
4618 /* Allow supervisor writes if !cr0.wp */
4620 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4622 /* Disallow supervisor fetches of user code if cr4.smep */
4624 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4627 * SMAP:kernel-mode data accesses from user-mode
4628 * mappings should fault. A fault is considered
4629 * as a SMAP violation if all of the following
4630 * conditions are true:
4631 * - X86_CR4_SMAP is set in CR4
4632 * - A user page is accessed
4633 * - The access is not a fetch
4634 * - Page fault in kernel mode
4635 * - if CPL = 3 or X86_EFLAGS_AC is clear
4637 * Here, we cover the first three conditions.
4638 * The fourth is computed dynamically in permission_fault();
4639 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4640 * *not* subject to SMAP restrictions.
4643 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4646 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4651 * PKU is an additional mechanism by which the paging controls access to
4652 * user-mode addresses based on the value in the PKRU register. Protection
4653 * key violations are reported through a bit in the page fault error code.
4654 * Unlike other bits of the error code, the PK bit is not known at the
4655 * call site of e.g. gva_to_gpa; it must be computed directly in
4656 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4657 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4659 * In particular the following conditions come from the error code, the
4660 * page tables and the machine state:
4661 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4662 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4663 * - PK is always zero if U=0 in the page tables
4664 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4666 * The PKRU bitmask caches the result of these four conditions. The error
4667 * code (minus the P bit) and the page table's U bit form an index into the
4668 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4669 * with the two bits of the PKRU register corresponding to the protection key.
4670 * For the first three conditions above the bits will be 00, thus masking
4671 * away both AD and WD. For all reads or if the last condition holds, WD
4672 * only will be masked away.
4674 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4685 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4686 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4691 wp = is_write_protection(vcpu);
4693 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4694 unsigned pfec, pkey_bits;
4695 bool check_pkey, check_write, ff, uf, wf, pte_user;
4698 ff = pfec & PFERR_FETCH_MASK;
4699 uf = pfec & PFERR_USER_MASK;
4700 wf = pfec & PFERR_WRITE_MASK;
4702 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4703 pte_user = pfec & PFERR_RSVD_MASK;
4706 * Only need to check the access which is not an
4707 * instruction fetch and is to a user page.
4709 check_pkey = (!ff && pte_user);
4711 * write access is controlled by PKRU if it is a
4712 * user access or CR0.WP = 1.
4714 check_write = check_pkey && wf && (uf || wp);
4716 /* PKRU.AD stops both read and write access. */
4717 pkey_bits = !!check_pkey;
4718 /* PKRU.WD stops write access. */
4719 pkey_bits |= (!!check_write) << 1;
4721 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4725 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4727 unsigned root_level = mmu->root_level;
4729 mmu->last_nonleaf_level = root_level;
4730 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4731 mmu->last_nonleaf_level++;
4734 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4735 struct kvm_mmu *context,
4738 context->nx = is_nx(vcpu);
4739 context->root_level = level;
4741 reset_rsvds_bits_mask(vcpu, context);
4742 update_permission_bitmask(vcpu, context, false);
4743 update_pkru_bitmask(vcpu, context, false);
4744 update_last_nonleaf_level(vcpu, context);
4746 MMU_WARN_ON(!is_pae(vcpu));
4747 context->page_fault = paging64_page_fault;
4748 context->gva_to_gpa = paging64_gva_to_gpa;
4749 context->sync_page = paging64_sync_page;
4750 context->invlpg = paging64_invlpg;
4751 context->update_pte = paging64_update_pte;
4752 context->shadow_root_level = level;
4753 context->direct_map = false;
4756 static void paging64_init_context(struct kvm_vcpu *vcpu,
4757 struct kvm_mmu *context)
4759 int root_level = is_la57_mode(vcpu) ?
4760 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4762 paging64_init_context_common(vcpu, context, root_level);
4765 static void paging32_init_context(struct kvm_vcpu *vcpu,
4766 struct kvm_mmu *context)
4768 context->nx = false;
4769 context->root_level = PT32_ROOT_LEVEL;
4771 reset_rsvds_bits_mask(vcpu, context);
4772 update_permission_bitmask(vcpu, context, false);
4773 update_pkru_bitmask(vcpu, context, false);
4774 update_last_nonleaf_level(vcpu, context);
4776 context->page_fault = paging32_page_fault;
4777 context->gva_to_gpa = paging32_gva_to_gpa;
4778 context->sync_page = paging32_sync_page;
4779 context->invlpg = paging32_invlpg;
4780 context->update_pte = paging32_update_pte;
4781 context->shadow_root_level = PT32E_ROOT_LEVEL;
4782 context->direct_map = false;
4785 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4786 struct kvm_mmu *context)
4788 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4791 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
4793 union kvm_mmu_extended_role ext = {0};
4795 ext.cr0_pg = !!is_paging(vcpu);
4796 ext.cr4_pae = !!is_pae(vcpu);
4797 ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4798 ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4799 ext.cr4_pse = !!is_pse(vcpu);
4800 ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
4801 ext.cr4_la57 = !!kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
4802 ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
4809 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4812 union kvm_mmu_role role = {0};
4814 role.base.access = ACC_ALL;
4815 role.base.nxe = !!is_nx(vcpu);
4816 role.base.cr0_wp = is_write_protection(vcpu);
4817 role.base.smm = is_smm(vcpu);
4818 role.base.guest_mode = is_guest_mode(vcpu);
4823 role.ext = kvm_calc_mmu_role_ext(vcpu);
4828 static union kvm_mmu_role
4829 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4831 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4833 role.base.ad_disabled = (shadow_accessed_mask == 0);
4834 role.base.level = kvm_x86_ops->get_tdp_level(vcpu);
4835 role.base.direct = true;
4836 role.base.gpte_is_8_bytes = true;
4841 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4843 struct kvm_mmu *context = vcpu->arch.mmu;
4844 union kvm_mmu_role new_role =
4845 kvm_calc_tdp_mmu_root_page_role(vcpu, false);
4847 new_role.base.word &= mmu_base_role_mask.word;
4848 if (new_role.as_u64 == context->mmu_role.as_u64)
4851 context->mmu_role.as_u64 = new_role.as_u64;
4852 context->page_fault = tdp_page_fault;
4853 context->sync_page = nonpaging_sync_page;
4854 context->invlpg = nonpaging_invlpg;
4855 context->update_pte = nonpaging_update_pte;
4856 context->shadow_root_level = kvm_x86_ops->get_tdp_level(vcpu);
4857 context->direct_map = true;
4858 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
4859 context->get_cr3 = get_cr3;
4860 context->get_pdptr = kvm_pdptr_read;
4861 context->inject_page_fault = kvm_inject_page_fault;
4863 if (!is_paging(vcpu)) {
4864 context->nx = false;
4865 context->gva_to_gpa = nonpaging_gva_to_gpa;
4866 context->root_level = 0;
4867 } else if (is_long_mode(vcpu)) {
4868 context->nx = is_nx(vcpu);
4869 context->root_level = is_la57_mode(vcpu) ?
4870 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4871 reset_rsvds_bits_mask(vcpu, context);
4872 context->gva_to_gpa = paging64_gva_to_gpa;
4873 } else if (is_pae(vcpu)) {
4874 context->nx = is_nx(vcpu);
4875 context->root_level = PT32E_ROOT_LEVEL;
4876 reset_rsvds_bits_mask(vcpu, context);
4877 context->gva_to_gpa = paging64_gva_to_gpa;
4879 context->nx = false;
4880 context->root_level = PT32_ROOT_LEVEL;
4881 reset_rsvds_bits_mask(vcpu, context);
4882 context->gva_to_gpa = paging32_gva_to_gpa;
4885 update_permission_bitmask(vcpu, context, false);
4886 update_pkru_bitmask(vcpu, context, false);
4887 update_last_nonleaf_level(vcpu, context);
4888 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4891 static union kvm_mmu_role
4892 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4894 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4896 role.base.smep_andnot_wp = role.ext.cr4_smep &&
4897 !is_write_protection(vcpu);
4898 role.base.smap_andnot_wp = role.ext.cr4_smap &&
4899 !is_write_protection(vcpu);
4900 role.base.direct = !is_paging(vcpu);
4901 role.base.gpte_is_8_bytes = !!is_pae(vcpu);
4903 if (!is_long_mode(vcpu))
4904 role.base.level = PT32E_ROOT_LEVEL;
4905 else if (is_la57_mode(vcpu))
4906 role.base.level = PT64_ROOT_5LEVEL;
4908 role.base.level = PT64_ROOT_4LEVEL;
4913 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
4915 struct kvm_mmu *context = vcpu->arch.mmu;
4916 union kvm_mmu_role new_role =
4917 kvm_calc_shadow_mmu_root_page_role(vcpu, false);
4919 new_role.base.word &= mmu_base_role_mask.word;
4920 if (new_role.as_u64 == context->mmu_role.as_u64)
4923 if (!is_paging(vcpu))
4924 nonpaging_init_context(vcpu, context);
4925 else if (is_long_mode(vcpu))
4926 paging64_init_context(vcpu, context);
4927 else if (is_pae(vcpu))
4928 paging32E_init_context(vcpu, context);
4930 paging32_init_context(vcpu, context);
4932 context->mmu_role.as_u64 = new_role.as_u64;
4933 reset_shadow_zero_bits_mask(vcpu, context);
4935 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4937 static union kvm_mmu_role
4938 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4941 union kvm_mmu_role role = {0};
4943 /* SMM flag is inherited from root_mmu */
4944 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4946 role.base.level = PT64_ROOT_4LEVEL;
4947 role.base.gpte_is_8_bytes = true;
4948 role.base.direct = false;
4949 role.base.ad_disabled = !accessed_dirty;
4950 role.base.guest_mode = true;
4951 role.base.access = ACC_ALL;
4954 * WP=1 and NOT_WP=1 is an impossible combination, use WP and the
4955 * SMAP variation to denote shadow EPT entries.
4957 role.base.cr0_wp = true;
4958 role.base.smap_andnot_wp = true;
4960 role.ext = kvm_calc_mmu_role_ext(vcpu);
4961 role.ext.execonly = execonly;
4966 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4967 bool accessed_dirty, gpa_t new_eptp)
4969 struct kvm_mmu *context = vcpu->arch.mmu;
4970 union kvm_mmu_role new_role =
4971 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4974 __kvm_mmu_new_cr3(vcpu, new_eptp, new_role.base, false);
4976 new_role.base.word &= mmu_base_role_mask.word;
4977 if (new_role.as_u64 == context->mmu_role.as_u64)
4980 context->shadow_root_level = PT64_ROOT_4LEVEL;
4983 context->ept_ad = accessed_dirty;
4984 context->page_fault = ept_page_fault;
4985 context->gva_to_gpa = ept_gva_to_gpa;
4986 context->sync_page = ept_sync_page;
4987 context->invlpg = ept_invlpg;
4988 context->update_pte = ept_update_pte;
4989 context->root_level = PT64_ROOT_4LEVEL;
4990 context->direct_map = false;
4991 context->mmu_role.as_u64 = new_role.as_u64;
4993 update_permission_bitmask(vcpu, context, true);
4994 update_pkru_bitmask(vcpu, context, true);
4995 update_last_nonleaf_level(vcpu, context);
4996 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4997 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4999 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
5001 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
5003 struct kvm_mmu *context = vcpu->arch.mmu;
5005 kvm_init_shadow_mmu(vcpu);
5006 context->set_cr3 = kvm_x86_ops->set_cr3;
5007 context->get_cr3 = get_cr3;
5008 context->get_pdptr = kvm_pdptr_read;
5009 context->inject_page_fault = kvm_inject_page_fault;
5012 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
5014 union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false);
5015 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
5017 new_role.base.word &= mmu_base_role_mask.word;
5018 if (new_role.as_u64 == g_context->mmu_role.as_u64)
5021 g_context->mmu_role.as_u64 = new_role.as_u64;
5022 g_context->get_cr3 = get_cr3;
5023 g_context->get_pdptr = kvm_pdptr_read;
5024 g_context->inject_page_fault = kvm_inject_page_fault;
5027 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
5028 * L1's nested page tables (e.g. EPT12). The nested translation
5029 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
5030 * L2's page tables as the first level of translation and L1's
5031 * nested page tables as the second level of translation. Basically
5032 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
5034 if (!is_paging(vcpu)) {
5035 g_context->nx = false;
5036 g_context->root_level = 0;
5037 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
5038 } else if (is_long_mode(vcpu)) {
5039 g_context->nx = is_nx(vcpu);
5040 g_context->root_level = is_la57_mode(vcpu) ?
5041 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
5042 reset_rsvds_bits_mask(vcpu, g_context);
5043 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
5044 } else if (is_pae(vcpu)) {
5045 g_context->nx = is_nx(vcpu);
5046 g_context->root_level = PT32E_ROOT_LEVEL;
5047 reset_rsvds_bits_mask(vcpu, g_context);
5048 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
5050 g_context->nx = false;
5051 g_context->root_level = PT32_ROOT_LEVEL;
5052 reset_rsvds_bits_mask(vcpu, g_context);
5053 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
5056 update_permission_bitmask(vcpu, g_context, false);
5057 update_pkru_bitmask(vcpu, g_context, false);
5058 update_last_nonleaf_level(vcpu, g_context);
5061 void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots)
5066 vcpu->arch.mmu->root_hpa = INVALID_PAGE;
5068 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5069 vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5072 if (mmu_is_nested(vcpu))
5073 init_kvm_nested_mmu(vcpu);
5074 else if (tdp_enabled)
5075 init_kvm_tdp_mmu(vcpu);
5077 init_kvm_softmmu(vcpu);
5079 EXPORT_SYMBOL_GPL(kvm_init_mmu);
5081 static union kvm_mmu_page_role
5082 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
5084 union kvm_mmu_role role;
5087 role = kvm_calc_tdp_mmu_root_page_role(vcpu, true);
5089 role = kvm_calc_shadow_mmu_root_page_role(vcpu, true);
5094 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
5096 kvm_mmu_unload(vcpu);
5097 kvm_init_mmu(vcpu, true);
5099 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
5101 int kvm_mmu_load(struct kvm_vcpu *vcpu)
5105 r = mmu_topup_memory_caches(vcpu);
5108 r = mmu_alloc_roots(vcpu);
5109 kvm_mmu_sync_roots(vcpu);
5112 kvm_mmu_load_cr3(vcpu);
5113 kvm_x86_ops->tlb_flush(vcpu, true);
5117 EXPORT_SYMBOL_GPL(kvm_mmu_load);
5119 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
5121 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
5122 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
5123 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
5124 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
5126 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
5128 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
5129 struct kvm_mmu_page *sp, u64 *spte,
5132 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
5133 ++vcpu->kvm->stat.mmu_pde_zapped;
5137 ++vcpu->kvm->stat.mmu_pte_updated;
5138 vcpu->arch.mmu->update_pte(vcpu, sp, spte, new);
5141 static bool need_remote_flush(u64 old, u64 new)
5143 if (!is_shadow_present_pte(old))
5145 if (!is_shadow_present_pte(new))
5147 if ((old ^ new) & PT64_BASE_ADDR_MASK)
5149 old ^= shadow_nx_mask;
5150 new ^= shadow_nx_mask;
5151 return (old & ~new & PT64_PERM_MASK) != 0;
5154 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
5161 * Assume that the pte write on a page table of the same type
5162 * as the current vcpu paging mode since we update the sptes only
5163 * when they have the same mode.
5165 if (is_pae(vcpu) && *bytes == 4) {
5166 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
5171 if (*bytes == 4 || *bytes == 8) {
5172 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
5181 * If we're seeing too many writes to a page, it may no longer be a page table,
5182 * or we may be forking, in which case it is better to unmap the page.
5184 static bool detect_write_flooding(struct kvm_mmu_page *sp)
5187 * Skip write-flooding detected for the sp whose level is 1, because
5188 * it can become unsync, then the guest page is not write-protected.
5190 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
5193 atomic_inc(&sp->write_flooding_count);
5194 return atomic_read(&sp->write_flooding_count) >= 3;
5198 * Misaligned accesses are too much trouble to fix up; also, they usually
5199 * indicate a page is not used as a page table.
5201 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5204 unsigned offset, pte_size, misaligned;
5206 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5207 gpa, bytes, sp->role.word);
5209 offset = offset_in_page(gpa);
5210 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
5213 * Sometimes, the OS only writes the last one bytes to update status
5214 * bits, for example, in linux, andb instruction is used in clear_bit().
5216 if (!(offset & (pte_size - 1)) && bytes == 1)
5219 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5220 misaligned |= bytes < 4;
5225 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5227 unsigned page_offset, quadrant;
5231 page_offset = offset_in_page(gpa);
5232 level = sp->role.level;
5234 if (!sp->role.gpte_is_8_bytes) {
5235 page_offset <<= 1; /* 32->64 */
5237 * A 32-bit pde maps 4MB while the shadow pdes map
5238 * only 2MB. So we need to double the offset again
5239 * and zap two pdes instead of one.
5241 if (level == PT32_ROOT_LEVEL) {
5242 page_offset &= ~7; /* kill rounding error */
5246 quadrant = page_offset >> PAGE_SHIFT;
5247 page_offset &= ~PAGE_MASK;
5248 if (quadrant != sp->role.quadrant)
5252 spte = &sp->spt[page_offset / sizeof(*spte)];
5256 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5257 const u8 *new, int bytes,
5258 struct kvm_page_track_notifier_node *node)
5260 gfn_t gfn = gpa >> PAGE_SHIFT;
5261 struct kvm_mmu_page *sp;
5262 LIST_HEAD(invalid_list);
5263 u64 entry, gentry, *spte;
5265 bool remote_flush, local_flush;
5268 * If we don't have indirect shadow pages, it means no page is
5269 * write-protected, so we can exit simply.
5271 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5274 remote_flush = local_flush = false;
5276 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5279 * No need to care whether allocation memory is successful
5280 * or not since pte prefetch is skiped if it does not have
5281 * enough objects in the cache.
5283 mmu_topup_memory_caches(vcpu);
5285 spin_lock(&vcpu->kvm->mmu_lock);
5287 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5289 ++vcpu->kvm->stat.mmu_pte_write;
5290 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5292 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5293 if (detect_write_misaligned(sp, gpa, bytes) ||
5294 detect_write_flooding(sp)) {
5295 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5296 ++vcpu->kvm->stat.mmu_flooded;
5300 spte = get_written_sptes(sp, gpa, &npte);
5306 u32 base_role = vcpu->arch.mmu->mmu_role.base.word;
5309 mmu_page_zap_pte(vcpu->kvm, sp, spte);
5311 !((sp->role.word ^ base_role)
5312 & mmu_base_role_mask.word) && rmap_can_add(vcpu))
5313 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
5314 if (need_remote_flush(entry, *spte))
5315 remote_flush = true;
5319 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5320 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5321 spin_unlock(&vcpu->kvm->mmu_lock);
5324 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
5329 if (vcpu->arch.mmu->direct_map)
5332 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
5334 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
5338 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
5340 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
5342 LIST_HEAD(invalid_list);
5344 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
5347 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
5348 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
5351 ++vcpu->kvm->stat.mmu_recycled;
5353 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
5355 if (!kvm_mmu_available_pages(vcpu->kvm))
5360 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code,
5361 void *insn, int insn_len)
5363 int r, emulation_type = 0;
5364 enum emulation_result er;
5365 bool direct = vcpu->arch.mmu->direct_map;
5367 /* With shadow page tables, fault_address contains a GVA or nGPA. */
5368 if (vcpu->arch.mmu->direct_map) {
5369 vcpu->arch.gpa_available = true;
5370 vcpu->arch.gpa_val = cr2;
5374 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5375 r = handle_mmio_page_fault(vcpu, cr2, direct);
5376 if (r == RET_PF_EMULATE)
5380 if (r == RET_PF_INVALID) {
5381 r = vcpu->arch.mmu->page_fault(vcpu, cr2,
5382 lower_32_bits(error_code),
5384 WARN_ON(r == RET_PF_INVALID);
5387 if (r == RET_PF_RETRY)
5393 * Before emulating the instruction, check if the error code
5394 * was due to a RO violation while translating the guest page.
5395 * This can occur when using nested virtualization with nested
5396 * paging in both guests. If true, we simply unprotect the page
5397 * and resume the guest.
5399 if (vcpu->arch.mmu->direct_map &&
5400 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5401 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2));
5406 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5407 * optimistically try to just unprotect the page and let the processor
5408 * re-execute the instruction that caused the page fault. Do not allow
5409 * retrying MMIO emulation, as it's not only pointless but could also
5410 * cause us to enter an infinite loop because the processor will keep
5411 * faulting on the non-existent MMIO address. Retrying an instruction
5412 * from a nested guest is also pointless and dangerous as we are only
5413 * explicitly shadowing L1's page tables, i.e. unprotecting something
5414 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5416 if (!mmio_info_in_cache(vcpu, cr2, direct) && !is_guest_mode(vcpu))
5417 emulation_type = EMULTYPE_ALLOW_RETRY;
5420 * On AMD platforms, under certain conditions insn_len may be zero on #NPF.
5421 * This can happen if a guest gets a page-fault on data access but the HW
5422 * table walker is not able to read the instruction page (e.g instruction
5423 * page is not present in memory). In those cases we simply restart the
5424 * guest, with the exception of AMD Erratum 1096 which is unrecoverable.
5426 if (unlikely(insn && !insn_len)) {
5427 if (!kvm_x86_ops->need_emulation_on_page_fault(vcpu))
5431 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
5436 case EMULATE_USER_EXIT:
5437 ++vcpu->stat.mmio_exits;
5445 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5447 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5449 struct kvm_mmu *mmu = vcpu->arch.mmu;
5452 /* INVLPG on a * non-canonical address is a NOP according to the SDM. */
5453 if (is_noncanonical_address(gva, vcpu))
5456 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5459 * INVLPG is required to invalidate any global mappings for the VA,
5460 * irrespective of PCID. Since it would take us roughly similar amount
5461 * of work to determine whether any of the prev_root mappings of the VA
5462 * is marked global, or to just sync it blindly, so we might as well
5463 * just always sync it.
5465 * Mappings not reachable via the current cr3 or the prev_roots will be
5466 * synced when switching to that cr3, so nothing needs to be done here
5469 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5470 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5471 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5473 kvm_x86_ops->tlb_flush_gva(vcpu, gva);
5474 ++vcpu->stat.invlpg;
5476 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5478 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5480 struct kvm_mmu *mmu = vcpu->arch.mmu;
5481 bool tlb_flush = false;
5484 if (pcid == kvm_get_active_pcid(vcpu)) {
5485 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5489 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5490 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5491 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].cr3)) {
5492 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5498 kvm_x86_ops->tlb_flush_gva(vcpu, gva);
5500 ++vcpu->stat.invlpg;
5503 * Mappings not reachable via the current cr3 or the prev_roots will be
5504 * synced when switching to that cr3, so nothing needs to be done here
5508 EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva);
5510 void kvm_enable_tdp(void)
5514 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
5516 void kvm_disable_tdp(void)
5518 tdp_enabled = false;
5520 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
5523 /* The return value indicates if tlb flush on all vcpus is needed. */
5524 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
5526 /* The caller should hold mmu-lock before calling this function. */
5527 static __always_inline bool
5528 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5529 slot_level_handler fn, int start_level, int end_level,
5530 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
5532 struct slot_rmap_walk_iterator iterator;
5535 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5536 end_gfn, &iterator) {
5538 flush |= fn(kvm, iterator.rmap);
5540 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5541 if (flush && lock_flush_tlb) {
5542 kvm_flush_remote_tlbs_with_address(kvm,
5544 iterator.gfn - start_gfn + 1);
5547 cond_resched_lock(&kvm->mmu_lock);
5551 if (flush && lock_flush_tlb) {
5552 kvm_flush_remote_tlbs_with_address(kvm, start_gfn,
5553 end_gfn - start_gfn + 1);
5560 static __always_inline bool
5561 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5562 slot_level_handler fn, int start_level, int end_level,
5563 bool lock_flush_tlb)
5565 return slot_handle_level_range(kvm, memslot, fn, start_level,
5566 end_level, memslot->base_gfn,
5567 memslot->base_gfn + memslot->npages - 1,
5571 static __always_inline bool
5572 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5573 slot_level_handler fn, bool lock_flush_tlb)
5575 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5576 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5579 static __always_inline bool
5580 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5581 slot_level_handler fn, bool lock_flush_tlb)
5583 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
5584 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5587 static __always_inline bool
5588 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5589 slot_level_handler fn, bool lock_flush_tlb)
5591 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5592 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
5595 static void free_mmu_pages(struct kvm_vcpu *vcpu)
5597 free_page((unsigned long)vcpu->arch.mmu->pae_root);
5598 free_page((unsigned long)vcpu->arch.mmu->lm_root);
5601 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
5607 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5608 * while the PDP table is a per-vCPU construct that's allocated at MMU
5609 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5610 * x86_64. Therefore we need to allocate the PDP table in the first
5611 * 4GB of memory, which happens to fit the DMA32 zone. Except for
5612 * SVM's 32-bit NPT support, TDP paging doesn't use PAE paging and can
5613 * skip allocating the PDP table.
5615 if (tdp_enabled && kvm_x86_ops->get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5618 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5622 vcpu->arch.mmu->pae_root = page_address(page);
5623 for (i = 0; i < 4; ++i)
5624 vcpu->arch.mmu->pae_root[i] = INVALID_PAGE;
5629 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5633 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5634 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5636 vcpu->arch.root_mmu.root_hpa = INVALID_PAGE;
5637 vcpu->arch.root_mmu.root_cr3 = 0;
5638 vcpu->arch.root_mmu.translate_gpa = translate_gpa;
5639 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5640 vcpu->arch.root_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5642 vcpu->arch.guest_mmu.root_hpa = INVALID_PAGE;
5643 vcpu->arch.guest_mmu.root_cr3 = 0;
5644 vcpu->arch.guest_mmu.translate_gpa = translate_gpa;
5645 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5646 vcpu->arch.guest_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5648 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5649 return alloc_mmu_pages(vcpu);
5652 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5653 struct kvm_memory_slot *slot,
5654 struct kvm_page_track_notifier_node *node)
5656 struct kvm_mmu_page *sp;
5657 LIST_HEAD(invalid_list);
5662 spin_lock(&kvm->mmu_lock);
5664 if (list_empty(&kvm->arch.active_mmu_pages))
5667 flush = slot_handle_all_level(kvm, slot, kvm_zap_rmapp, false);
5669 for (i = 0; i < slot->npages; i++) {
5670 gfn = slot->base_gfn + i;
5672 for_each_valid_sp(kvm, sp, gfn) {
5676 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
5678 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5679 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
5681 cond_resched_lock(&kvm->mmu_lock);
5684 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
5687 spin_unlock(&kvm->mmu_lock);
5690 void kvm_mmu_init_vm(struct kvm *kvm)
5692 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5694 node->track_write = kvm_mmu_pte_write;
5695 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5696 kvm_page_track_register_notifier(kvm, node);
5699 void kvm_mmu_uninit_vm(struct kvm *kvm)
5701 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5703 kvm_page_track_unregister_notifier(kvm, node);
5706 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5708 struct kvm_memslots *slots;
5709 struct kvm_memory_slot *memslot;
5712 spin_lock(&kvm->mmu_lock);
5713 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5714 slots = __kvm_memslots(kvm, i);
5715 kvm_for_each_memslot(memslot, slots) {
5718 start = max(gfn_start, memslot->base_gfn);
5719 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5723 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5724 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
5725 start, end - 1, true);
5729 spin_unlock(&kvm->mmu_lock);
5732 static bool slot_rmap_write_protect(struct kvm *kvm,
5733 struct kvm_rmap_head *rmap_head)
5735 return __rmap_write_protect(kvm, rmap_head, false);
5738 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5739 struct kvm_memory_slot *memslot)
5743 spin_lock(&kvm->mmu_lock);
5744 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
5746 spin_unlock(&kvm->mmu_lock);
5749 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
5750 * which do tlb flush out of mmu-lock should be serialized by
5751 * kvm->slots_lock otherwise tlb flush would be missed.
5753 lockdep_assert_held(&kvm->slots_lock);
5756 * We can flush all the TLBs out of the mmu lock without TLB
5757 * corruption since we just change the spte from writable to
5758 * readonly so that we only need to care the case of changing
5759 * spte from present to present (changing the spte from present
5760 * to nonpresent will flush all the TLBs immediately), in other
5761 * words, the only case we care is mmu_spte_update() where we
5762 * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5763 * instead of PT_WRITABLE_MASK, that means it does not depend
5764 * on PT_WRITABLE_MASK anymore.
5767 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5771 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5772 struct kvm_rmap_head *rmap_head)
5775 struct rmap_iterator iter;
5776 int need_tlb_flush = 0;
5778 struct kvm_mmu_page *sp;
5781 for_each_rmap_spte(rmap_head, &iter, sptep) {
5782 sp = page_header(__pa(sptep));
5783 pfn = spte_to_pfn(*sptep);
5786 * We cannot do huge page mapping for indirect shadow pages,
5787 * which are found on the last rmap (level = 1) when not using
5788 * tdp; such shadow pages are synced with the page table in
5789 * the guest, and the guest page table is using 4K page size
5790 * mapping if the indirect sp has level = 1.
5792 if (sp->role.direct &&
5793 !kvm_is_reserved_pfn(pfn) &&
5794 PageTransCompoundMap(pfn_to_page(pfn))) {
5795 pte_list_remove(rmap_head, sptep);
5797 if (kvm_available_flush_tlb_with_range())
5798 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5799 KVM_PAGES_PER_HPAGE(sp->role.level));
5807 return need_tlb_flush;
5810 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5811 const struct kvm_memory_slot *memslot)
5813 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5814 spin_lock(&kvm->mmu_lock);
5815 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
5816 kvm_mmu_zap_collapsible_spte, true);
5817 spin_unlock(&kvm->mmu_lock);
5820 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5821 struct kvm_memory_slot *memslot)
5825 spin_lock(&kvm->mmu_lock);
5826 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
5827 spin_unlock(&kvm->mmu_lock);
5829 lockdep_assert_held(&kvm->slots_lock);
5832 * It's also safe to flush TLBs out of mmu lock here as currently this
5833 * function is only used for dirty logging, in which case flushing TLB
5834 * out of mmu lock also guarantees no dirty pages will be lost in
5838 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5841 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
5843 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
5844 struct kvm_memory_slot *memslot)
5848 spin_lock(&kvm->mmu_lock);
5849 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
5851 spin_unlock(&kvm->mmu_lock);
5853 /* see kvm_mmu_slot_remove_write_access */
5854 lockdep_assert_held(&kvm->slots_lock);
5857 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5860 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
5862 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
5863 struct kvm_memory_slot *memslot)
5867 spin_lock(&kvm->mmu_lock);
5868 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
5869 spin_unlock(&kvm->mmu_lock);
5871 lockdep_assert_held(&kvm->slots_lock);
5873 /* see kvm_mmu_slot_leaf_clear_dirty */
5875 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5878 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
5880 static void __kvm_mmu_zap_all(struct kvm *kvm, bool mmio_only)
5882 struct kvm_mmu_page *sp, *node;
5883 LIST_HEAD(invalid_list);
5886 spin_lock(&kvm->mmu_lock);
5888 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5889 if (mmio_only && !sp->mmio_cached)
5891 if (sp->role.invalid && sp->root_count)
5893 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign)) {
5894 WARN_ON_ONCE(mmio_only);
5897 if (cond_resched_lock(&kvm->mmu_lock))
5901 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5902 spin_unlock(&kvm->mmu_lock);
5905 void kvm_mmu_zap_all(struct kvm *kvm)
5907 return __kvm_mmu_zap_all(kvm, false);
5910 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5912 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5914 gen &= MMIO_SPTE_GEN_MASK;
5917 * Generation numbers are incremented in multiples of the number of
5918 * address spaces in order to provide unique generations across all
5919 * address spaces. Strip what is effectively the address space
5920 * modifier prior to checking for a wrap of the MMIO generation so
5921 * that a wrap in any address space is detected.
5923 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5926 * The very rare case: if the MMIO generation number has wrapped,
5927 * zap all shadow pages.
5929 if (unlikely(gen == 0)) {
5930 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5931 __kvm_mmu_zap_all(kvm, true);
5935 static unsigned long
5936 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5939 int nr_to_scan = sc->nr_to_scan;
5940 unsigned long freed = 0;
5942 mutex_lock(&kvm_lock);
5944 list_for_each_entry(kvm, &vm_list, vm_list) {
5946 LIST_HEAD(invalid_list);
5949 * Never scan more than sc->nr_to_scan VM instances.
5950 * Will not hit this condition practically since we do not try
5951 * to shrink more than one VM and it is very unlikely to see
5952 * !n_used_mmu_pages so many times.
5957 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5958 * here. We may skip a VM instance errorneosly, but we do not
5959 * want to shrink a VM that only started to populate its MMU
5962 if (!kvm->arch.n_used_mmu_pages)
5965 idx = srcu_read_lock(&kvm->srcu);
5966 spin_lock(&kvm->mmu_lock);
5968 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
5970 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5972 spin_unlock(&kvm->mmu_lock);
5973 srcu_read_unlock(&kvm->srcu, idx);
5976 * unfair on small ones
5977 * per-vm shrinkers cry out
5978 * sadness comes quickly
5980 list_move_tail(&kvm->vm_list, &vm_list);
5984 mutex_unlock(&kvm_lock);
5988 static unsigned long
5989 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5991 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5994 static struct shrinker mmu_shrinker = {
5995 .count_objects = mmu_shrink_count,
5996 .scan_objects = mmu_shrink_scan,
5997 .seeks = DEFAULT_SEEKS * 10,
6000 static void mmu_destroy_caches(void)
6002 kmem_cache_destroy(pte_list_desc_cache);
6003 kmem_cache_destroy(mmu_page_header_cache);
6006 static void kvm_set_mmio_spte_mask(void)
6011 * Set the reserved bits and the present bit of an paging-structure
6012 * entry to generate page fault with PFER.RSV = 1.
6016 * Mask the uppermost physical address bit, which would be reserved as
6017 * long as the supported physical address width is less than 52.
6021 /* Set the present bit. */
6025 * If reserved bit is not supported, clear the present bit to disable
6028 if (IS_ENABLED(CONFIG_X86_64) && shadow_phys_bits == 52)
6031 kvm_mmu_set_mmio_spte_mask(mask, mask);
6034 int kvm_mmu_module_init(void)
6039 * MMU roles use union aliasing which is, generally speaking, an
6040 * undefined behavior. However, we supposedly know how compilers behave
6041 * and the current status quo is unlikely to change. Guardians below are
6042 * supposed to let us know if the assumption becomes false.
6044 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
6045 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
6046 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
6048 kvm_mmu_reset_all_pte_masks();
6050 kvm_set_mmio_spte_mask();
6052 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
6053 sizeof(struct pte_list_desc),
6054 0, SLAB_ACCOUNT, NULL);
6055 if (!pte_list_desc_cache)
6058 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
6059 sizeof(struct kvm_mmu_page),
6060 0, SLAB_ACCOUNT, NULL);
6061 if (!mmu_page_header_cache)
6064 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
6067 ret = register_shrinker(&mmu_shrinker);
6074 mmu_destroy_caches();
6079 * Calculate mmu pages needed for kvm.
6081 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
6083 unsigned long nr_mmu_pages;
6084 unsigned long nr_pages = 0;
6085 struct kvm_memslots *slots;
6086 struct kvm_memory_slot *memslot;
6089 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
6090 slots = __kvm_memslots(kvm, i);
6092 kvm_for_each_memslot(memslot, slots)
6093 nr_pages += memslot->npages;
6096 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
6097 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
6099 return nr_mmu_pages;
6102 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
6104 kvm_mmu_unload(vcpu);
6105 free_mmu_pages(vcpu);
6106 mmu_free_memory_caches(vcpu);
6109 void kvm_mmu_module_exit(void)
6111 mmu_destroy_caches();
6112 percpu_counter_destroy(&kvm_total_used_mmu_pages);
6113 unregister_shrinker(&mmu_shrinker);
6114 mmu_audit_disable();