2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/moduleparam.h>
33 #include <linux/export.h>
34 #include <linux/swap.h>
35 #include <linux/hugetlb.h>
36 #include <linux/compiler.h>
37 #include <linux/srcu.h>
38 #include <linux/slab.h>
39 #include <linux/uaccess.h>
42 #include <asm/cmpxchg.h>
45 #include <asm/kvm_page_track.h>
48 * When setting this variable to true it enables Two-Dimensional-Paging
49 * where the hardware walks 2 page tables:
50 * 1. the guest-virtual to guest-physical
51 * 2. while doing 1. it walks guest-physical to host-physical
52 * If the hardware supports that we don't need to do shadow paging.
54 bool tdp_enabled = false;
58 AUDIT_POST_PAGE_FAULT,
69 module_param(dbg, bool, 0644);
71 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
72 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
73 #define MMU_WARN_ON(x) WARN_ON(x)
75 #define pgprintk(x...) do { } while (0)
76 #define rmap_printk(x...) do { } while (0)
77 #define MMU_WARN_ON(x) do { } while (0)
80 #define PTE_PREFETCH_NUM 8
82 #define PT_FIRST_AVAIL_BITS_SHIFT 10
83 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
85 #define PT64_LEVEL_BITS 9
87 #define PT64_LEVEL_SHIFT(level) \
88 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
90 #define PT64_INDEX(address, level)\
91 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
94 #define PT32_LEVEL_BITS 10
96 #define PT32_LEVEL_SHIFT(level) \
97 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
99 #define PT32_LVL_OFFSET_MASK(level) \
100 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
101 * PT32_LEVEL_BITS))) - 1))
103 #define PT32_INDEX(address, level)\
104 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
107 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
108 #define PT64_DIR_BASE_ADDR_MASK \
109 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
110 #define PT64_LVL_ADDR_MASK(level) \
111 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT64_LEVEL_BITS))) - 1))
113 #define PT64_LVL_OFFSET_MASK(level) \
114 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
115 * PT64_LEVEL_BITS))) - 1))
117 #define PT32_BASE_ADDR_MASK PAGE_MASK
118 #define PT32_DIR_BASE_ADDR_MASK \
119 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
120 #define PT32_LVL_ADDR_MASK(level) \
121 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
122 * PT32_LEVEL_BITS))) - 1))
124 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
125 | shadow_x_mask | shadow_nx_mask)
127 #define ACC_EXEC_MASK 1
128 #define ACC_WRITE_MASK PT_WRITABLE_MASK
129 #define ACC_USER_MASK PT_USER_MASK
130 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
132 #include <trace/events/kvm.h>
134 #define CREATE_TRACE_POINTS
135 #include "mmutrace.h"
137 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
138 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
140 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
142 /* make pte_list_desc fit well in cache line */
143 #define PTE_LIST_EXT 3
145 struct pte_list_desc {
146 u64 *sptes[PTE_LIST_EXT];
147 struct pte_list_desc *more;
150 struct kvm_shadow_walk_iterator {
158 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
159 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
160 shadow_walk_okay(&(_walker)); \
161 shadow_walk_next(&(_walker)))
163 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
164 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
165 shadow_walk_okay(&(_walker)) && \
166 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
167 __shadow_walk_next(&(_walker), spte))
169 static struct kmem_cache *pte_list_desc_cache;
170 static struct kmem_cache *mmu_page_header_cache;
171 static struct percpu_counter kvm_total_used_mmu_pages;
173 static u64 __read_mostly shadow_nx_mask;
174 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
175 static u64 __read_mostly shadow_user_mask;
176 static u64 __read_mostly shadow_accessed_mask;
177 static u64 __read_mostly shadow_dirty_mask;
178 static u64 __read_mostly shadow_mmio_mask;
179 static u64 __read_mostly shadow_present_mask;
181 static void mmu_spte_set(u64 *sptep, u64 spte);
182 static void mmu_free_roots(struct kvm_vcpu *vcpu);
184 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
186 shadow_mmio_mask = mmio_mask;
188 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
191 * the low bit of the generation number is always presumed to be zero.
192 * This disables mmio caching during memslot updates. The concept is
193 * similar to a seqcount but instead of retrying the access we just punt
194 * and ignore the cache.
196 * spte bits 3-11 are used as bits 1-9 of the generation number,
197 * the bits 52-61 are used as bits 10-19 of the generation number.
199 #define MMIO_SPTE_GEN_LOW_SHIFT 2
200 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
202 #define MMIO_GEN_SHIFT 20
203 #define MMIO_GEN_LOW_SHIFT 10
204 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
205 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
207 static u64 generation_mmio_spte_mask(unsigned int gen)
211 WARN_ON(gen & ~MMIO_GEN_MASK);
213 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
214 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
218 static unsigned int get_mmio_spte_generation(u64 spte)
222 spte &= ~shadow_mmio_mask;
224 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
225 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
229 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu)
231 return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK;
234 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
237 unsigned int gen = kvm_current_mmio_generation(vcpu);
238 u64 mask = generation_mmio_spte_mask(gen);
240 access &= ACC_WRITE_MASK | ACC_USER_MASK;
241 mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
243 trace_mark_mmio_spte(sptep, gfn, access, gen);
244 mmu_spte_set(sptep, mask);
247 static bool is_mmio_spte(u64 spte)
249 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
252 static gfn_t get_mmio_spte_gfn(u64 spte)
254 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
255 return (spte & ~mask) >> PAGE_SHIFT;
258 static unsigned get_mmio_spte_access(u64 spte)
260 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
261 return (spte & ~mask) & ~PAGE_MASK;
264 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
265 kvm_pfn_t pfn, unsigned access)
267 if (unlikely(is_noslot_pfn(pfn))) {
268 mark_mmio_spte(vcpu, sptep, gfn, access);
275 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
277 unsigned int kvm_gen, spte_gen;
279 kvm_gen = kvm_current_mmio_generation(vcpu);
280 spte_gen = get_mmio_spte_generation(spte);
282 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
283 return likely(kvm_gen == spte_gen);
286 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
287 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask)
289 shadow_user_mask = user_mask;
290 shadow_accessed_mask = accessed_mask;
291 shadow_dirty_mask = dirty_mask;
292 shadow_nx_mask = nx_mask;
293 shadow_x_mask = x_mask;
294 shadow_present_mask = p_mask;
296 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
298 static int is_cpuid_PSE36(void)
303 static int is_nx(struct kvm_vcpu *vcpu)
305 return vcpu->arch.efer & EFER_NX;
308 static int is_shadow_present_pte(u64 pte)
310 return (pte & 0xFFFFFFFFull) && !is_mmio_spte(pte);
313 static int is_large_pte(u64 pte)
315 return pte & PT_PAGE_SIZE_MASK;
318 static int is_last_spte(u64 pte, int level)
320 if (level == PT_PAGE_TABLE_LEVEL)
322 if (is_large_pte(pte))
327 static kvm_pfn_t spte_to_pfn(u64 pte)
329 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
332 static gfn_t pse36_gfn_delta(u32 gpte)
334 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
336 return (gpte & PT32_DIR_PSE36_MASK) << shift;
340 static void __set_spte(u64 *sptep, u64 spte)
342 WRITE_ONCE(*sptep, spte);
345 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
347 WRITE_ONCE(*sptep, spte);
350 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
352 return xchg(sptep, spte);
355 static u64 __get_spte_lockless(u64 *sptep)
357 return ACCESS_ONCE(*sptep);
368 static void count_spte_clear(u64 *sptep, u64 spte)
370 struct kvm_mmu_page *sp = page_header(__pa(sptep));
372 if (is_shadow_present_pte(spte))
375 /* Ensure the spte is completely set before we increase the count */
377 sp->clear_spte_count++;
380 static void __set_spte(u64 *sptep, u64 spte)
382 union split_spte *ssptep, sspte;
384 ssptep = (union split_spte *)sptep;
385 sspte = (union split_spte)spte;
387 ssptep->spte_high = sspte.spte_high;
390 * If we map the spte from nonpresent to present, We should store
391 * the high bits firstly, then set present bit, so cpu can not
392 * fetch this spte while we are setting the spte.
396 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
399 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
401 union split_spte *ssptep, sspte;
403 ssptep = (union split_spte *)sptep;
404 sspte = (union split_spte)spte;
406 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
409 * If we map the spte from present to nonpresent, we should clear
410 * present bit firstly to avoid vcpu fetch the old high bits.
414 ssptep->spte_high = sspte.spte_high;
415 count_spte_clear(sptep, spte);
418 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
420 union split_spte *ssptep, sspte, orig;
422 ssptep = (union split_spte *)sptep;
423 sspte = (union split_spte)spte;
425 /* xchg acts as a barrier before the setting of the high bits */
426 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
427 orig.spte_high = ssptep->spte_high;
428 ssptep->spte_high = sspte.spte_high;
429 count_spte_clear(sptep, spte);
435 * The idea using the light way get the spte on x86_32 guest is from
436 * gup_get_pte(arch/x86/mm/gup.c).
438 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
439 * coalesces them and we are running out of the MMU lock. Therefore
440 * we need to protect against in-progress updates of the spte.
442 * Reading the spte while an update is in progress may get the old value
443 * for the high part of the spte. The race is fine for a present->non-present
444 * change (because the high part of the spte is ignored for non-present spte),
445 * but for a present->present change we must reread the spte.
447 * All such changes are done in two steps (present->non-present and
448 * non-present->present), hence it is enough to count the number of
449 * present->non-present updates: if it changed while reading the spte,
450 * we might have hit the race. This is done using clear_spte_count.
452 static u64 __get_spte_lockless(u64 *sptep)
454 struct kvm_mmu_page *sp = page_header(__pa(sptep));
455 union split_spte spte, *orig = (union split_spte *)sptep;
459 count = sp->clear_spte_count;
462 spte.spte_low = orig->spte_low;
465 spte.spte_high = orig->spte_high;
468 if (unlikely(spte.spte_low != orig->spte_low ||
469 count != sp->clear_spte_count))
476 static bool spte_is_locklessly_modifiable(u64 spte)
478 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
479 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
482 static bool spte_has_volatile_bits(u64 spte)
485 * Always atomically update spte if it can be updated
486 * out of mmu-lock, it can ensure dirty bit is not lost,
487 * also, it can help us to get a stable is_writable_pte()
488 * to ensure tlb flush is not missed.
490 if (spte_is_locklessly_modifiable(spte))
493 if (!shadow_accessed_mask)
496 if (!is_shadow_present_pte(spte))
499 if ((spte & shadow_accessed_mask) &&
500 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
506 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
508 return (old_spte & bit_mask) && !(new_spte & bit_mask);
511 static bool spte_is_bit_changed(u64 old_spte, u64 new_spte, u64 bit_mask)
513 return (old_spte & bit_mask) != (new_spte & bit_mask);
516 /* Rules for using mmu_spte_set:
517 * Set the sptep from nonpresent to present.
518 * Note: the sptep being assigned *must* be either not present
519 * or in a state where the hardware will not attempt to update
522 static void mmu_spte_set(u64 *sptep, u64 new_spte)
524 WARN_ON(is_shadow_present_pte(*sptep));
525 __set_spte(sptep, new_spte);
528 /* Rules for using mmu_spte_update:
529 * Update the state bits, it means the mapped pfn is not changed.
531 * Whenever we overwrite a writable spte with a read-only one we
532 * should flush remote TLBs. Otherwise rmap_write_protect
533 * will find a read-only spte, even though the writable spte
534 * might be cached on a CPU's TLB, the return value indicates this
537 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
539 u64 old_spte = *sptep;
542 WARN_ON(!is_shadow_present_pte(new_spte));
544 if (!is_shadow_present_pte(old_spte)) {
545 mmu_spte_set(sptep, new_spte);
549 if (!spte_has_volatile_bits(old_spte))
550 __update_clear_spte_fast(sptep, new_spte);
552 old_spte = __update_clear_spte_slow(sptep, new_spte);
555 * For the spte updated out of mmu-lock is safe, since
556 * we always atomically update it, see the comments in
557 * spte_has_volatile_bits().
559 if (spte_is_locklessly_modifiable(old_spte) &&
560 !is_writable_pte(new_spte))
563 if (!shadow_accessed_mask) {
565 * We don't set page dirty when dropping non-writable spte.
566 * So do it now if the new spte is becoming non-writable.
569 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
574 * Flush TLB when accessed/dirty bits are changed in the page tables,
575 * to guarantee consistency between TLB and page tables.
577 if (spte_is_bit_changed(old_spte, new_spte,
578 shadow_accessed_mask | shadow_dirty_mask))
581 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
582 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
583 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
584 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
590 * Rules for using mmu_spte_clear_track_bits:
591 * It sets the sptep from present to nonpresent, and track the
592 * state bits, it is used to clear the last level sptep.
594 static int mmu_spte_clear_track_bits(u64 *sptep)
597 u64 old_spte = *sptep;
599 if (!spte_has_volatile_bits(old_spte))
600 __update_clear_spte_fast(sptep, 0ull);
602 old_spte = __update_clear_spte_slow(sptep, 0ull);
604 if (!is_shadow_present_pte(old_spte))
607 pfn = spte_to_pfn(old_spte);
610 * KVM does not hold the refcount of the page used by
611 * kvm mmu, before reclaiming the page, we should
612 * unmap it from mmu first.
614 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
616 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
617 kvm_set_pfn_accessed(pfn);
618 if (old_spte & (shadow_dirty_mask ? shadow_dirty_mask :
620 kvm_set_pfn_dirty(pfn);
625 * Rules for using mmu_spte_clear_no_track:
626 * Directly clear spte without caring the state bits of sptep,
627 * it is used to set the upper level spte.
629 static void mmu_spte_clear_no_track(u64 *sptep)
631 __update_clear_spte_fast(sptep, 0ull);
634 static u64 mmu_spte_get_lockless(u64 *sptep)
636 return __get_spte_lockless(sptep);
639 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
642 * Prevent page table teardown by making any free-er wait during
643 * kvm_flush_remote_tlbs() IPI to all active vcpus.
648 * Make sure a following spte read is not reordered ahead of the write
651 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
654 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
657 * Make sure the write to vcpu->mode is not reordered in front of
658 * reads to sptes. If it does, kvm_commit_zap_page() can see us
659 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
661 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
665 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
666 struct kmem_cache *base_cache, int min)
670 if (cache->nobjs >= min)
672 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
673 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
676 cache->objects[cache->nobjs++] = obj;
681 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
686 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
687 struct kmem_cache *cache)
690 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
693 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
698 if (cache->nobjs >= min)
700 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
701 page = (void *)__get_free_page(GFP_KERNEL);
704 cache->objects[cache->nobjs++] = page;
709 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
712 free_page((unsigned long)mc->objects[--mc->nobjs]);
715 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
719 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
720 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
723 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
726 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
727 mmu_page_header_cache, 4);
732 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
734 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
735 pte_list_desc_cache);
736 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
737 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
738 mmu_page_header_cache);
741 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
746 p = mc->objects[--mc->nobjs];
750 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
752 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
755 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
757 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
760 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
762 if (!sp->role.direct)
763 return sp->gfns[index];
765 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
768 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
771 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
773 sp->gfns[index] = gfn;
777 * Return the pointer to the large page information for a given gfn,
778 * handling slots that are not large page aligned.
780 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
781 struct kvm_memory_slot *slot,
786 idx = gfn_to_index(gfn, slot->base_gfn, level);
787 return &slot->arch.lpage_info[level - 2][idx];
790 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
791 gfn_t gfn, int count)
793 struct kvm_lpage_info *linfo;
796 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
797 linfo = lpage_info_slot(gfn, slot, i);
798 linfo->disallow_lpage += count;
799 WARN_ON(linfo->disallow_lpage < 0);
803 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
805 update_gfn_disallow_lpage_count(slot, gfn, 1);
808 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
810 update_gfn_disallow_lpage_count(slot, gfn, -1);
813 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
815 struct kvm_memslots *slots;
816 struct kvm_memory_slot *slot;
819 kvm->arch.indirect_shadow_pages++;
821 slots = kvm_memslots_for_spte_role(kvm, sp->role);
822 slot = __gfn_to_memslot(slots, gfn);
824 /* the non-leaf shadow pages are keeping readonly. */
825 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
826 return kvm_slot_page_track_add_page(kvm, slot, gfn,
827 KVM_PAGE_TRACK_WRITE);
829 kvm_mmu_gfn_disallow_lpage(slot, gfn);
832 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
834 struct kvm_memslots *slots;
835 struct kvm_memory_slot *slot;
838 kvm->arch.indirect_shadow_pages--;
840 slots = kvm_memslots_for_spte_role(kvm, sp->role);
841 slot = __gfn_to_memslot(slots, gfn);
842 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
843 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
844 KVM_PAGE_TRACK_WRITE);
846 kvm_mmu_gfn_allow_lpage(slot, gfn);
849 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
850 struct kvm_memory_slot *slot)
852 struct kvm_lpage_info *linfo;
855 linfo = lpage_info_slot(gfn, slot, level);
856 return !!linfo->disallow_lpage;
862 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
865 struct kvm_memory_slot *slot;
867 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
868 return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
871 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
873 unsigned long page_size;
876 page_size = kvm_host_page_size(kvm, gfn);
878 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
879 if (page_size >= KVM_HPAGE_SIZE(i))
888 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
891 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
893 if (no_dirty_log && slot->dirty_bitmap)
899 static struct kvm_memory_slot *
900 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
903 struct kvm_memory_slot *slot;
905 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
906 if (!memslot_valid_for_gpte(slot, no_dirty_log))
912 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
913 bool *force_pt_level)
915 int host_level, level, max_level;
916 struct kvm_memory_slot *slot;
918 if (unlikely(*force_pt_level))
919 return PT_PAGE_TABLE_LEVEL;
921 slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
922 *force_pt_level = !memslot_valid_for_gpte(slot, true);
923 if (unlikely(*force_pt_level))
924 return PT_PAGE_TABLE_LEVEL;
926 host_level = host_mapping_level(vcpu->kvm, large_gfn);
928 if (host_level == PT_PAGE_TABLE_LEVEL)
931 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
933 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
934 if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot))
941 * About rmap_head encoding:
943 * If the bit zero of rmap_head->val is clear, then it points to the only spte
944 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
945 * pte_list_desc containing more mappings.
949 * Returns the number of pointers in the rmap chain, not counting the new one.
951 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
952 struct kvm_rmap_head *rmap_head)
954 struct pte_list_desc *desc;
957 if (!rmap_head->val) {
958 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
959 rmap_head->val = (unsigned long)spte;
960 } else if (!(rmap_head->val & 1)) {
961 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
962 desc = mmu_alloc_pte_list_desc(vcpu);
963 desc->sptes[0] = (u64 *)rmap_head->val;
964 desc->sptes[1] = spte;
965 rmap_head->val = (unsigned long)desc | 1;
968 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
969 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
970 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
972 count += PTE_LIST_EXT;
974 if (desc->sptes[PTE_LIST_EXT-1]) {
975 desc->more = mmu_alloc_pte_list_desc(vcpu);
978 for (i = 0; desc->sptes[i]; ++i)
980 desc->sptes[i] = spte;
986 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
987 struct pte_list_desc *desc, int i,
988 struct pte_list_desc *prev_desc)
992 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
994 desc->sptes[i] = desc->sptes[j];
995 desc->sptes[j] = NULL;
998 if (!prev_desc && !desc->more)
999 rmap_head->val = (unsigned long)desc->sptes[0];
1002 prev_desc->more = desc->more;
1004 rmap_head->val = (unsigned long)desc->more | 1;
1005 mmu_free_pte_list_desc(desc);
1008 static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1010 struct pte_list_desc *desc;
1011 struct pte_list_desc *prev_desc;
1014 if (!rmap_head->val) {
1015 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
1017 } else if (!(rmap_head->val & 1)) {
1018 rmap_printk("pte_list_remove: %p 1->0\n", spte);
1019 if ((u64 *)rmap_head->val != spte) {
1020 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
1025 rmap_printk("pte_list_remove: %p many->many\n", spte);
1026 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1029 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1030 if (desc->sptes[i] == spte) {
1031 pte_list_desc_remove_entry(rmap_head,
1032 desc, i, prev_desc);
1039 pr_err("pte_list_remove: %p many->many\n", spte);
1044 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1045 struct kvm_memory_slot *slot)
1049 idx = gfn_to_index(gfn, slot->base_gfn, level);
1050 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1053 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1054 struct kvm_mmu_page *sp)
1056 struct kvm_memslots *slots;
1057 struct kvm_memory_slot *slot;
1059 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1060 slot = __gfn_to_memslot(slots, gfn);
1061 return __gfn_to_rmap(gfn, sp->role.level, slot);
1064 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1066 struct kvm_mmu_memory_cache *cache;
1068 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1069 return mmu_memory_cache_free_objects(cache);
1072 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1074 struct kvm_mmu_page *sp;
1075 struct kvm_rmap_head *rmap_head;
1077 sp = page_header(__pa(spte));
1078 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1079 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1080 return pte_list_add(vcpu, spte, rmap_head);
1083 static void rmap_remove(struct kvm *kvm, u64 *spte)
1085 struct kvm_mmu_page *sp;
1087 struct kvm_rmap_head *rmap_head;
1089 sp = page_header(__pa(spte));
1090 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1091 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1092 pte_list_remove(spte, rmap_head);
1096 * Used by the following functions to iterate through the sptes linked by a
1097 * rmap. All fields are private and not assumed to be used outside.
1099 struct rmap_iterator {
1100 /* private fields */
1101 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1102 int pos; /* index of the sptep */
1106 * Iteration must be started by this function. This should also be used after
1107 * removing/dropping sptes from the rmap link because in such cases the
1108 * information in the itererator may not be valid.
1110 * Returns sptep if found, NULL otherwise.
1112 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1113 struct rmap_iterator *iter)
1117 if (!rmap_head->val)
1120 if (!(rmap_head->val & 1)) {
1122 sptep = (u64 *)rmap_head->val;
1126 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1128 sptep = iter->desc->sptes[iter->pos];
1130 BUG_ON(!is_shadow_present_pte(*sptep));
1135 * Must be used with a valid iterator: e.g. after rmap_get_first().
1137 * Returns sptep if found, NULL otherwise.
1139 static u64 *rmap_get_next(struct rmap_iterator *iter)
1144 if (iter->pos < PTE_LIST_EXT - 1) {
1146 sptep = iter->desc->sptes[iter->pos];
1151 iter->desc = iter->desc->more;
1155 /* desc->sptes[0] cannot be NULL */
1156 sptep = iter->desc->sptes[iter->pos];
1163 BUG_ON(!is_shadow_present_pte(*sptep));
1167 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1168 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1169 _spte_; _spte_ = rmap_get_next(_iter_))
1171 static void drop_spte(struct kvm *kvm, u64 *sptep)
1173 if (mmu_spte_clear_track_bits(sptep))
1174 rmap_remove(kvm, sptep);
1178 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1180 if (is_large_pte(*sptep)) {
1181 WARN_ON(page_header(__pa(sptep))->role.level ==
1182 PT_PAGE_TABLE_LEVEL);
1183 drop_spte(kvm, sptep);
1191 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1193 if (__drop_large_spte(vcpu->kvm, sptep))
1194 kvm_flush_remote_tlbs(vcpu->kvm);
1198 * Write-protect on the specified @sptep, @pt_protect indicates whether
1199 * spte write-protection is caused by protecting shadow page table.
1201 * Note: write protection is difference between dirty logging and spte
1203 * - for dirty logging, the spte can be set to writable at anytime if
1204 * its dirty bitmap is properly set.
1205 * - for spte protection, the spte can be writable only after unsync-ing
1208 * Return true if tlb need be flushed.
1210 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1214 if (!is_writable_pte(spte) &&
1215 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1218 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1221 spte &= ~SPTE_MMU_WRITEABLE;
1222 spte = spte & ~PT_WRITABLE_MASK;
1224 return mmu_spte_update(sptep, spte);
1227 static bool __rmap_write_protect(struct kvm *kvm,
1228 struct kvm_rmap_head *rmap_head,
1232 struct rmap_iterator iter;
1235 for_each_rmap_spte(rmap_head, &iter, sptep)
1236 flush |= spte_write_protect(sptep, pt_protect);
1241 static bool spte_clear_dirty(u64 *sptep)
1245 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1247 spte &= ~shadow_dirty_mask;
1249 return mmu_spte_update(sptep, spte);
1252 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1255 struct rmap_iterator iter;
1258 for_each_rmap_spte(rmap_head, &iter, sptep)
1259 flush |= spte_clear_dirty(sptep);
1264 static bool spte_set_dirty(u64 *sptep)
1268 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1270 spte |= shadow_dirty_mask;
1272 return mmu_spte_update(sptep, spte);
1275 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1278 struct rmap_iterator iter;
1281 for_each_rmap_spte(rmap_head, &iter, sptep)
1282 flush |= spte_set_dirty(sptep);
1288 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1289 * @kvm: kvm instance
1290 * @slot: slot to protect
1291 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1292 * @mask: indicates which pages we should protect
1294 * Used when we do not need to care about huge page mappings: e.g. during dirty
1295 * logging we do not have any such mappings.
1297 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1298 struct kvm_memory_slot *slot,
1299 gfn_t gfn_offset, unsigned long mask)
1301 struct kvm_rmap_head *rmap_head;
1304 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1305 PT_PAGE_TABLE_LEVEL, slot);
1306 __rmap_write_protect(kvm, rmap_head, false);
1308 /* clear the first set bit */
1314 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages
1315 * @kvm: kvm instance
1316 * @slot: slot to clear D-bit
1317 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1318 * @mask: indicates which pages we should clear D-bit
1320 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1322 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1323 struct kvm_memory_slot *slot,
1324 gfn_t gfn_offset, unsigned long mask)
1326 struct kvm_rmap_head *rmap_head;
1329 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1330 PT_PAGE_TABLE_LEVEL, slot);
1331 __rmap_clear_dirty(kvm, rmap_head);
1333 /* clear the first set bit */
1337 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1340 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1343 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1344 * enable dirty logging for them.
1346 * Used when we do not need to care about huge page mappings: e.g. during dirty
1347 * logging we do not have any such mappings.
1349 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1350 struct kvm_memory_slot *slot,
1351 gfn_t gfn_offset, unsigned long mask)
1353 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1354 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1357 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1360 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1361 struct kvm_memory_slot *slot, u64 gfn)
1363 struct kvm_rmap_head *rmap_head;
1365 bool write_protected = false;
1367 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1368 rmap_head = __gfn_to_rmap(gfn, i, slot);
1369 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1372 return write_protected;
1375 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1377 struct kvm_memory_slot *slot;
1379 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1380 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1383 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1386 struct rmap_iterator iter;
1389 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1390 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1392 drop_spte(kvm, sptep);
1399 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1400 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1403 return kvm_zap_rmapp(kvm, rmap_head);
1406 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1407 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1411 struct rmap_iterator iter;
1414 pte_t *ptep = (pte_t *)data;
1417 WARN_ON(pte_huge(*ptep));
1418 new_pfn = pte_pfn(*ptep);
1421 for_each_rmap_spte(rmap_head, &iter, sptep) {
1422 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1423 sptep, *sptep, gfn, level);
1427 if (pte_write(*ptep)) {
1428 drop_spte(kvm, sptep);
1431 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1432 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1434 new_spte &= ~PT_WRITABLE_MASK;
1435 new_spte &= ~SPTE_HOST_WRITEABLE;
1436 new_spte &= ~shadow_accessed_mask;
1438 mmu_spte_clear_track_bits(sptep);
1439 mmu_spte_set(sptep, new_spte);
1444 kvm_flush_remote_tlbs(kvm);
1449 struct slot_rmap_walk_iterator {
1451 struct kvm_memory_slot *slot;
1457 /* output fields. */
1459 struct kvm_rmap_head *rmap;
1462 /* private field. */
1463 struct kvm_rmap_head *end_rmap;
1467 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1469 iterator->level = level;
1470 iterator->gfn = iterator->start_gfn;
1471 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1472 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1477 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1478 struct kvm_memory_slot *slot, int start_level,
1479 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1481 iterator->slot = slot;
1482 iterator->start_level = start_level;
1483 iterator->end_level = end_level;
1484 iterator->start_gfn = start_gfn;
1485 iterator->end_gfn = end_gfn;
1487 rmap_walk_init_level(iterator, iterator->start_level);
1490 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1492 return !!iterator->rmap;
1495 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1497 if (++iterator->rmap <= iterator->end_rmap) {
1498 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1502 if (++iterator->level > iterator->end_level) {
1503 iterator->rmap = NULL;
1507 rmap_walk_init_level(iterator, iterator->level);
1510 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1511 _start_gfn, _end_gfn, _iter_) \
1512 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1513 _end_level_, _start_gfn, _end_gfn); \
1514 slot_rmap_walk_okay(_iter_); \
1515 slot_rmap_walk_next(_iter_))
1517 static int kvm_handle_hva_range(struct kvm *kvm,
1518 unsigned long start,
1521 int (*handler)(struct kvm *kvm,
1522 struct kvm_rmap_head *rmap_head,
1523 struct kvm_memory_slot *slot,
1526 unsigned long data))
1528 struct kvm_memslots *slots;
1529 struct kvm_memory_slot *memslot;
1530 struct slot_rmap_walk_iterator iterator;
1534 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1535 slots = __kvm_memslots(kvm, i);
1536 kvm_for_each_memslot(memslot, slots) {
1537 unsigned long hva_start, hva_end;
1538 gfn_t gfn_start, gfn_end;
1540 hva_start = max(start, memslot->userspace_addr);
1541 hva_end = min(end, memslot->userspace_addr +
1542 (memslot->npages << PAGE_SHIFT));
1543 if (hva_start >= hva_end)
1546 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1547 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1549 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1550 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1552 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1553 PT_MAX_HUGEPAGE_LEVEL,
1554 gfn_start, gfn_end - 1,
1556 ret |= handler(kvm, iterator.rmap, memslot,
1557 iterator.gfn, iterator.level, data);
1564 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1566 int (*handler)(struct kvm *kvm,
1567 struct kvm_rmap_head *rmap_head,
1568 struct kvm_memory_slot *slot,
1569 gfn_t gfn, int level,
1570 unsigned long data))
1572 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1575 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1577 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1580 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1582 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1585 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1587 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1590 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1591 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1595 struct rmap_iterator uninitialized_var(iter);
1598 BUG_ON(!shadow_accessed_mask);
1600 for_each_rmap_spte(rmap_head, &iter, sptep) {
1601 if (*sptep & shadow_accessed_mask) {
1603 clear_bit((ffs(shadow_accessed_mask) - 1),
1604 (unsigned long *)sptep);
1608 trace_kvm_age_page(gfn, level, slot, young);
1612 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1613 struct kvm_memory_slot *slot, gfn_t gfn,
1614 int level, unsigned long data)
1617 struct rmap_iterator iter;
1621 * If there's no access bit in the secondary pte set by the
1622 * hardware it's up to gup-fast/gup to set the access bit in
1623 * the primary pte or in the page structure.
1625 if (!shadow_accessed_mask)
1628 for_each_rmap_spte(rmap_head, &iter, sptep) {
1629 if (*sptep & shadow_accessed_mask) {
1638 #define RMAP_RECYCLE_THRESHOLD 1000
1640 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1642 struct kvm_rmap_head *rmap_head;
1643 struct kvm_mmu_page *sp;
1645 sp = page_header(__pa(spte));
1647 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1649 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1650 kvm_flush_remote_tlbs(vcpu->kvm);
1653 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1656 * In case of absence of EPT Access and Dirty Bits supports,
1657 * emulate the accessed bit for EPT, by checking if this page has
1658 * an EPT mapping, and clearing it if it does. On the next access,
1659 * a new EPT mapping will be established.
1660 * This has some overhead, but not as much as the cost of swapping
1661 * out actively used pages or breaking up actively used hugepages.
1663 if (!shadow_accessed_mask) {
1665 * We are holding the kvm->mmu_lock, and we are blowing up
1666 * shadow PTEs. MMU notifier consumers need to be kept at bay.
1667 * This is correct as long as we don't decouple the mmu_lock
1668 * protected regions (like invalidate_range_start|end does).
1670 kvm->mmu_notifier_seq++;
1671 return kvm_handle_hva_range(kvm, start, end, 0,
1675 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1678 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1680 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1684 static int is_empty_shadow_page(u64 *spt)
1689 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1690 if (is_shadow_present_pte(*pos)) {
1691 printk(KERN_ERR "%s: %p %llx\n", __func__,
1700 * This value is the sum of all of the kvm instances's
1701 * kvm->arch.n_used_mmu_pages values. We need a global,
1702 * aggregate version in order to make the slab shrinker
1705 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1707 kvm->arch.n_used_mmu_pages += nr;
1708 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1711 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1713 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1714 hlist_del(&sp->hash_link);
1715 list_del(&sp->link);
1716 free_page((unsigned long)sp->spt);
1717 if (!sp->role.direct)
1718 free_page((unsigned long)sp->gfns);
1719 kmem_cache_free(mmu_page_header_cache, sp);
1722 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1724 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1727 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1728 struct kvm_mmu_page *sp, u64 *parent_pte)
1733 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1736 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1739 pte_list_remove(parent_pte, &sp->parent_ptes);
1742 static void drop_parent_pte(struct kvm_mmu_page *sp,
1745 mmu_page_remove_parent_pte(sp, parent_pte);
1746 mmu_spte_clear_no_track(parent_pte);
1749 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1751 struct kvm_mmu_page *sp;
1753 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1754 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1756 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1757 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1760 * The active_mmu_pages list is the FIFO list, do not move the
1761 * page until it is zapped. kvm_zap_obsolete_pages depends on
1762 * this feature. See the comments in kvm_zap_obsolete_pages().
1764 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1765 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1769 static void mark_unsync(u64 *spte);
1770 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1773 struct rmap_iterator iter;
1775 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1780 static void mark_unsync(u64 *spte)
1782 struct kvm_mmu_page *sp;
1785 sp = page_header(__pa(spte));
1786 index = spte - sp->spt;
1787 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1789 if (sp->unsync_children++)
1791 kvm_mmu_mark_parents_unsync(sp);
1794 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1795 struct kvm_mmu_page *sp)
1800 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1804 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1805 struct kvm_mmu_page *sp, u64 *spte,
1811 #define KVM_PAGE_ARRAY_NR 16
1813 struct kvm_mmu_pages {
1814 struct mmu_page_and_offset {
1815 struct kvm_mmu_page *sp;
1817 } page[KVM_PAGE_ARRAY_NR];
1821 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1827 for (i=0; i < pvec->nr; i++)
1828 if (pvec->page[i].sp == sp)
1831 pvec->page[pvec->nr].sp = sp;
1832 pvec->page[pvec->nr].idx = idx;
1834 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1837 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1839 --sp->unsync_children;
1840 WARN_ON((int)sp->unsync_children < 0);
1841 __clear_bit(idx, sp->unsync_child_bitmap);
1844 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1845 struct kvm_mmu_pages *pvec)
1847 int i, ret, nr_unsync_leaf = 0;
1849 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1850 struct kvm_mmu_page *child;
1851 u64 ent = sp->spt[i];
1853 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1854 clear_unsync_child_bit(sp, i);
1858 child = page_header(ent & PT64_BASE_ADDR_MASK);
1860 if (child->unsync_children) {
1861 if (mmu_pages_add(pvec, child, i))
1864 ret = __mmu_unsync_walk(child, pvec);
1866 clear_unsync_child_bit(sp, i);
1868 } else if (ret > 0) {
1869 nr_unsync_leaf += ret;
1872 } else if (child->unsync) {
1874 if (mmu_pages_add(pvec, child, i))
1877 clear_unsync_child_bit(sp, i);
1880 return nr_unsync_leaf;
1883 #define INVALID_INDEX (-1)
1885 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1886 struct kvm_mmu_pages *pvec)
1889 if (!sp->unsync_children)
1892 mmu_pages_add(pvec, sp, INVALID_INDEX);
1893 return __mmu_unsync_walk(sp, pvec);
1896 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1898 WARN_ON(!sp->unsync);
1899 trace_kvm_mmu_sync_page(sp);
1901 --kvm->stat.mmu_unsync;
1904 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1905 struct list_head *invalid_list);
1906 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1907 struct list_head *invalid_list);
1910 * NOTE: we should pay more attention on the zapped-obsolete page
1911 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1912 * since it has been deleted from active_mmu_pages but still can be found
1915 * for_each_gfn_valid_sp() has skipped that kind of pages.
1917 #define for_each_gfn_valid_sp(_kvm, _sp, _gfn) \
1918 hlist_for_each_entry(_sp, \
1919 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1920 if ((_sp)->gfn != (_gfn) || is_obsolete_sp((_kvm), (_sp)) \
1921 || (_sp)->role.invalid) {} else
1923 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1924 for_each_gfn_valid_sp(_kvm, _sp, _gfn) \
1925 if ((_sp)->role.direct) {} else
1927 /* @sp->gfn should be write-protected at the call site */
1928 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1929 struct list_head *invalid_list)
1931 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1932 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1936 if (vcpu->arch.mmu.sync_page(vcpu, sp) == 0) {
1937 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1944 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1945 struct list_head *invalid_list,
1946 bool remote_flush, bool local_flush)
1948 if (!list_empty(invalid_list)) {
1949 kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list);
1954 kvm_flush_remote_tlbs(vcpu->kvm);
1955 else if (local_flush)
1956 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1959 #ifdef CONFIG_KVM_MMU_AUDIT
1960 #include "mmu_audit.c"
1962 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1963 static void mmu_audit_disable(void) { }
1966 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1968 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1971 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1972 struct list_head *invalid_list)
1974 kvm_unlink_unsync_page(vcpu->kvm, sp);
1975 return __kvm_sync_page(vcpu, sp, invalid_list);
1978 /* @gfn should be write-protected at the call site */
1979 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
1980 struct list_head *invalid_list)
1982 struct kvm_mmu_page *s;
1985 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1989 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1990 ret |= kvm_sync_page(vcpu, s, invalid_list);
1996 struct mmu_page_path {
1997 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL];
1998 unsigned int idx[PT64_ROOT_LEVEL];
2001 #define for_each_sp(pvec, sp, parents, i) \
2002 for (i = mmu_pages_first(&pvec, &parents); \
2003 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2004 i = mmu_pages_next(&pvec, &parents, i))
2006 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2007 struct mmu_page_path *parents,
2012 for (n = i+1; n < pvec->nr; n++) {
2013 struct kvm_mmu_page *sp = pvec->page[n].sp;
2014 unsigned idx = pvec->page[n].idx;
2015 int level = sp->role.level;
2017 parents->idx[level-1] = idx;
2018 if (level == PT_PAGE_TABLE_LEVEL)
2021 parents->parent[level-2] = sp;
2027 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2028 struct mmu_page_path *parents)
2030 struct kvm_mmu_page *sp;
2036 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2038 sp = pvec->page[0].sp;
2039 level = sp->role.level;
2040 WARN_ON(level == PT_PAGE_TABLE_LEVEL);
2042 parents->parent[level-2] = sp;
2044 /* Also set up a sentinel. Further entries in pvec are all
2045 * children of sp, so this element is never overwritten.
2047 parents->parent[level-1] = NULL;
2048 return mmu_pages_next(pvec, parents, 0);
2051 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2053 struct kvm_mmu_page *sp;
2054 unsigned int level = 0;
2057 unsigned int idx = parents->idx[level];
2058 sp = parents->parent[level];
2062 WARN_ON(idx == INVALID_INDEX);
2063 clear_unsync_child_bit(sp, idx);
2065 } while (!sp->unsync_children);
2068 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2069 struct kvm_mmu_page *parent)
2072 struct kvm_mmu_page *sp;
2073 struct mmu_page_path parents;
2074 struct kvm_mmu_pages pages;
2075 LIST_HEAD(invalid_list);
2078 while (mmu_unsync_walk(parent, &pages)) {
2079 bool protected = false;
2081 for_each_sp(pages, sp, parents, i)
2082 protected |= rmap_write_protect(vcpu, sp->gfn);
2085 kvm_flush_remote_tlbs(vcpu->kvm);
2089 for_each_sp(pages, sp, parents, i) {
2090 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2091 mmu_pages_clear_parents(&parents);
2093 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2094 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2095 cond_resched_lock(&vcpu->kvm->mmu_lock);
2100 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2103 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2105 atomic_set(&sp->write_flooding_count, 0);
2108 static void clear_sp_write_flooding_count(u64 *spte)
2110 struct kvm_mmu_page *sp = page_header(__pa(spte));
2112 __clear_sp_write_flooding_count(sp);
2115 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2122 union kvm_mmu_page_role role;
2124 struct kvm_mmu_page *sp;
2125 bool need_sync = false;
2127 LIST_HEAD(invalid_list);
2129 role = vcpu->arch.mmu.base_role;
2131 role.direct = direct;
2134 role.access = access;
2135 if (!vcpu->arch.mmu.direct_map
2136 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
2137 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2138 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2139 role.quadrant = quadrant;
2141 for_each_gfn_valid_sp(vcpu->kvm, sp, gfn) {
2142 if (!need_sync && sp->unsync)
2145 if (sp->role.word != role.word)
2149 /* The page is good, but __kvm_sync_page might still end
2150 * up zapping it. If so, break in order to rebuild it.
2152 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2155 WARN_ON(!list_empty(&invalid_list));
2156 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2159 if (sp->unsync_children)
2160 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2162 __clear_sp_write_flooding_count(sp);
2163 trace_kvm_mmu_get_page(sp, false);
2167 ++vcpu->kvm->stat.mmu_cache_miss;
2169 sp = kvm_mmu_alloc_page(vcpu, direct);
2173 hlist_add_head(&sp->hash_link,
2174 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2177 * we should do write protection before syncing pages
2178 * otherwise the content of the synced shadow page may
2179 * be inconsistent with guest page table.
2181 account_shadowed(vcpu->kvm, sp);
2182 if (level == PT_PAGE_TABLE_LEVEL &&
2183 rmap_write_protect(vcpu, gfn))
2184 kvm_flush_remote_tlbs(vcpu->kvm);
2186 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2187 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2189 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2190 clear_page(sp->spt);
2191 trace_kvm_mmu_get_page(sp, true);
2193 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2197 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2198 struct kvm_vcpu *vcpu, u64 addr)
2200 iterator->addr = addr;
2201 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
2202 iterator->level = vcpu->arch.mmu.shadow_root_level;
2204 if (iterator->level == PT64_ROOT_LEVEL &&
2205 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
2206 !vcpu->arch.mmu.direct_map)
2209 if (iterator->level == PT32E_ROOT_LEVEL) {
2210 iterator->shadow_addr
2211 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2212 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2214 if (!iterator->shadow_addr)
2215 iterator->level = 0;
2219 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2221 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2224 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2225 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2229 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2232 if (is_last_spte(spte, iterator->level)) {
2233 iterator->level = 0;
2237 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2241 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2243 return __shadow_walk_next(iterator, *iterator->sptep);
2246 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2247 struct kvm_mmu_page *sp)
2251 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2253 spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK |
2254 shadow_user_mask | shadow_x_mask | shadow_accessed_mask;
2256 mmu_spte_set(sptep, spte);
2258 mmu_page_add_parent_pte(vcpu, sp, sptep);
2260 if (sp->unsync_children || sp->unsync)
2264 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2265 unsigned direct_access)
2267 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2268 struct kvm_mmu_page *child;
2271 * For the direct sp, if the guest pte's dirty bit
2272 * changed form clean to dirty, it will corrupt the
2273 * sp's access: allow writable in the read-only sp,
2274 * so we should update the spte at this point to get
2275 * a new sp with the correct access.
2277 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2278 if (child->role.access == direct_access)
2281 drop_parent_pte(child, sptep);
2282 kvm_flush_remote_tlbs(vcpu->kvm);
2286 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2290 struct kvm_mmu_page *child;
2293 if (is_shadow_present_pte(pte)) {
2294 if (is_last_spte(pte, sp->role.level)) {
2295 drop_spte(kvm, spte);
2296 if (is_large_pte(pte))
2299 child = page_header(pte & PT64_BASE_ADDR_MASK);
2300 drop_parent_pte(child, spte);
2305 if (is_mmio_spte(pte))
2306 mmu_spte_clear_no_track(spte);
2311 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2312 struct kvm_mmu_page *sp)
2316 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2317 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2320 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2323 struct rmap_iterator iter;
2325 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2326 drop_parent_pte(sp, sptep);
2329 static int mmu_zap_unsync_children(struct kvm *kvm,
2330 struct kvm_mmu_page *parent,
2331 struct list_head *invalid_list)
2334 struct mmu_page_path parents;
2335 struct kvm_mmu_pages pages;
2337 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2340 while (mmu_unsync_walk(parent, &pages)) {
2341 struct kvm_mmu_page *sp;
2343 for_each_sp(pages, sp, parents, i) {
2344 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2345 mmu_pages_clear_parents(&parents);
2353 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2354 struct list_head *invalid_list)
2358 trace_kvm_mmu_prepare_zap_page(sp);
2359 ++kvm->stat.mmu_shadow_zapped;
2360 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2361 kvm_mmu_page_unlink_children(kvm, sp);
2362 kvm_mmu_unlink_parents(kvm, sp);
2364 if (!sp->role.invalid && !sp->role.direct)
2365 unaccount_shadowed(kvm, sp);
2368 kvm_unlink_unsync_page(kvm, sp);
2369 if (!sp->root_count) {
2372 list_move(&sp->link, invalid_list);
2373 kvm_mod_used_mmu_pages(kvm, -1);
2375 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2378 * The obsolete pages can not be used on any vcpus.
2379 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2381 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2382 kvm_reload_remote_mmus(kvm);
2385 sp->role.invalid = 1;
2389 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2390 struct list_head *invalid_list)
2392 struct kvm_mmu_page *sp, *nsp;
2394 if (list_empty(invalid_list))
2398 * We need to make sure everyone sees our modifications to
2399 * the page tables and see changes to vcpu->mode here. The barrier
2400 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2401 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2403 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2404 * guest mode and/or lockless shadow page table walks.
2406 kvm_flush_remote_tlbs(kvm);
2408 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2409 WARN_ON(!sp->role.invalid || sp->root_count);
2410 kvm_mmu_free_page(sp);
2414 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2415 struct list_head *invalid_list)
2417 struct kvm_mmu_page *sp;
2419 if (list_empty(&kvm->arch.active_mmu_pages))
2422 sp = list_last_entry(&kvm->arch.active_mmu_pages,
2423 struct kvm_mmu_page, link);
2424 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2430 * Changing the number of mmu pages allocated to the vm
2431 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2433 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2435 LIST_HEAD(invalid_list);
2437 spin_lock(&kvm->mmu_lock);
2439 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2440 /* Need to free some mmu pages to achieve the goal. */
2441 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2442 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2445 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2446 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2449 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2451 spin_unlock(&kvm->mmu_lock);
2454 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2456 struct kvm_mmu_page *sp;
2457 LIST_HEAD(invalid_list);
2460 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2462 spin_lock(&kvm->mmu_lock);
2463 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2464 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2467 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2469 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2470 spin_unlock(&kvm->mmu_lock);
2474 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2476 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2478 trace_kvm_mmu_unsync_page(sp);
2479 ++vcpu->kvm->stat.mmu_unsync;
2482 kvm_mmu_mark_parents_unsync(sp);
2485 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2488 struct kvm_mmu_page *sp;
2490 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2493 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2500 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
2501 kvm_unsync_page(vcpu, sp);
2507 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
2510 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn));
2515 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2516 unsigned pte_access, int level,
2517 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2518 bool can_unsync, bool host_writable)
2523 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2527 * For the EPT case, shadow_present_mask is 0 if hardware
2528 * supports exec-only page table entries. In that case,
2529 * ACC_USER_MASK and shadow_user_mask are used to represent
2530 * read access. See FNAME(gpte_access) in paging_tmpl.h.
2532 spte |= shadow_present_mask;
2534 spte |= shadow_accessed_mask;
2536 if (pte_access & ACC_EXEC_MASK)
2537 spte |= shadow_x_mask;
2539 spte |= shadow_nx_mask;
2541 if (pte_access & ACC_USER_MASK)
2542 spte |= shadow_user_mask;
2544 if (level > PT_PAGE_TABLE_LEVEL)
2545 spte |= PT_PAGE_SIZE_MASK;
2547 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2548 kvm_is_mmio_pfn(pfn));
2551 spte |= SPTE_HOST_WRITEABLE;
2553 pte_access &= ~ACC_WRITE_MASK;
2555 spte |= (u64)pfn << PAGE_SHIFT;
2557 if (pte_access & ACC_WRITE_MASK) {
2560 * Other vcpu creates new sp in the window between
2561 * mapping_level() and acquiring mmu-lock. We can
2562 * allow guest to retry the access, the mapping can
2563 * be fixed if guest refault.
2565 if (level > PT_PAGE_TABLE_LEVEL &&
2566 mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
2569 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2572 * Optimization: for pte sync, if spte was writable the hash
2573 * lookup is unnecessary (and expensive). Write protection
2574 * is responsibility of mmu_get_page / kvm_sync_page.
2575 * Same reasoning can be applied to dirty page accounting.
2577 if (!can_unsync && is_writable_pte(*sptep))
2580 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2581 pgprintk("%s: found shadow page for %llx, marking ro\n",
2584 pte_access &= ~ACC_WRITE_MASK;
2585 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2589 if (pte_access & ACC_WRITE_MASK) {
2590 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2591 spte |= shadow_dirty_mask;
2595 if (mmu_spte_update(sptep, spte))
2596 kvm_flush_remote_tlbs(vcpu->kvm);
2601 static bool mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
2602 int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
2603 bool speculative, bool host_writable)
2605 int was_rmapped = 0;
2607 bool emulate = false;
2609 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2610 *sptep, write_fault, gfn);
2612 if (is_shadow_present_pte(*sptep)) {
2614 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2615 * the parent of the now unreachable PTE.
2617 if (level > PT_PAGE_TABLE_LEVEL &&
2618 !is_large_pte(*sptep)) {
2619 struct kvm_mmu_page *child;
2622 child = page_header(pte & PT64_BASE_ADDR_MASK);
2623 drop_parent_pte(child, sptep);
2624 kvm_flush_remote_tlbs(vcpu->kvm);
2625 } else if (pfn != spte_to_pfn(*sptep)) {
2626 pgprintk("hfn old %llx new %llx\n",
2627 spte_to_pfn(*sptep), pfn);
2628 drop_spte(vcpu->kvm, sptep);
2629 kvm_flush_remote_tlbs(vcpu->kvm);
2634 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2635 true, host_writable)) {
2638 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2641 if (unlikely(is_mmio_spte(*sptep)))
2644 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2645 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2646 is_large_pte(*sptep)? "2MB" : "4kB",
2647 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2649 if (!was_rmapped && is_large_pte(*sptep))
2650 ++vcpu->kvm->stat.lpages;
2652 if (is_shadow_present_pte(*sptep)) {
2654 rmap_count = rmap_add(vcpu, sptep, gfn);
2655 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2656 rmap_recycle(vcpu, sptep, gfn);
2660 kvm_release_pfn_clean(pfn);
2665 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2668 struct kvm_memory_slot *slot;
2670 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2672 return KVM_PFN_ERR_FAULT;
2674 return gfn_to_pfn_memslot_atomic(slot, gfn);
2677 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2678 struct kvm_mmu_page *sp,
2679 u64 *start, u64 *end)
2681 struct page *pages[PTE_PREFETCH_NUM];
2682 struct kvm_memory_slot *slot;
2683 unsigned access = sp->role.access;
2687 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2688 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2692 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2696 for (i = 0; i < ret; i++, gfn++, start++)
2697 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
2698 page_to_pfn(pages[i]), true, true);
2703 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2704 struct kvm_mmu_page *sp, u64 *sptep)
2706 u64 *spte, *start = NULL;
2709 WARN_ON(!sp->role.direct);
2711 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2714 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2715 if (is_shadow_present_pte(*spte) || spte == sptep) {
2718 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2726 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2728 struct kvm_mmu_page *sp;
2731 * Since it's no accessed bit on EPT, it's no way to
2732 * distinguish between actually accessed translations
2733 * and prefetched, so disable pte prefetch if EPT is
2736 if (!shadow_accessed_mask)
2739 sp = page_header(__pa(sptep));
2740 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2743 __direct_pte_prefetch(vcpu, sp, sptep);
2746 static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable,
2747 int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault)
2749 struct kvm_shadow_walk_iterator iterator;
2750 struct kvm_mmu_page *sp;
2754 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2757 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2758 if (iterator.level == level) {
2759 emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2760 write, level, gfn, pfn, prefault,
2762 direct_pte_prefetch(vcpu, iterator.sptep);
2763 ++vcpu->stat.pf_fixed;
2767 drop_large_spte(vcpu, iterator.sptep);
2768 if (!is_shadow_present_pte(*iterator.sptep)) {
2769 u64 base_addr = iterator.addr;
2771 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2772 pseudo_gfn = base_addr >> PAGE_SHIFT;
2773 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2774 iterator.level - 1, 1, ACC_ALL);
2776 link_shadow_page(vcpu, iterator.sptep, sp);
2782 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2786 info.si_signo = SIGBUS;
2788 info.si_code = BUS_MCEERR_AR;
2789 info.si_addr = (void __user *)address;
2790 info.si_addr_lsb = PAGE_SHIFT;
2792 send_sig_info(SIGBUS, &info, tsk);
2795 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2798 * Do not cache the mmio info caused by writing the readonly gfn
2799 * into the spte otherwise read access on readonly gfn also can
2800 * caused mmio page fault and treat it as mmio access.
2801 * Return 1 to tell kvm to emulate it.
2803 if (pfn == KVM_PFN_ERR_RO_FAULT)
2806 if (pfn == KVM_PFN_ERR_HWPOISON) {
2807 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2814 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2815 gfn_t *gfnp, kvm_pfn_t *pfnp,
2818 kvm_pfn_t pfn = *pfnp;
2820 int level = *levelp;
2823 * Check if it's a transparent hugepage. If this would be an
2824 * hugetlbfs page, level wouldn't be set to
2825 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2828 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
2829 level == PT_PAGE_TABLE_LEVEL &&
2830 PageTransCompoundMap(pfn_to_page(pfn)) &&
2831 !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
2834 * mmu_notifier_retry was successful and we hold the
2835 * mmu_lock here, so the pmd can't become splitting
2836 * from under us, and in turn
2837 * __split_huge_page_refcount() can't run from under
2838 * us and we can safely transfer the refcount from
2839 * PG_tail to PG_head as we switch the pfn to tail to
2842 *levelp = level = PT_DIRECTORY_LEVEL;
2843 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2844 VM_BUG_ON((gfn & mask) != (pfn & mask));
2848 kvm_release_pfn_clean(pfn);
2856 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2857 kvm_pfn_t pfn, unsigned access, int *ret_val)
2859 /* The pfn is invalid, report the error! */
2860 if (unlikely(is_error_pfn(pfn))) {
2861 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2865 if (unlikely(is_noslot_pfn(pfn)))
2866 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2871 static bool page_fault_can_be_fast(u32 error_code)
2874 * Do not fix the mmio spte with invalid generation number which
2875 * need to be updated by slow page fault path.
2877 if (unlikely(error_code & PFERR_RSVD_MASK))
2881 * #PF can be fast only if the shadow page table is present and it
2882 * is caused by write-protect, that means we just need change the
2883 * W bit of the spte which can be done out of mmu-lock.
2885 if (!(error_code & PFERR_PRESENT_MASK) ||
2886 !(error_code & PFERR_WRITE_MASK))
2893 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2894 u64 *sptep, u64 spte)
2898 WARN_ON(!sp->role.direct);
2901 * The gfn of direct spte is stable since it is calculated
2904 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2907 * Theoretically we could also set dirty bit (and flush TLB) here in
2908 * order to eliminate unnecessary PML logging. See comments in
2909 * set_spte. But fast_page_fault is very unlikely to happen with PML
2910 * enabled, so we do not do this. This might result in the same GPA
2911 * to be logged in PML buffer again when the write really happens, and
2912 * eventually to be called by mark_page_dirty twice. But it's also no
2913 * harm. This also avoids the TLB flush needed after setting dirty bit
2914 * so non-PML cases won't be impacted.
2916 * Compare with set_spte where instead shadow_dirty_mask is set.
2918 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2919 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2926 * - true: let the vcpu to access on the same address again.
2927 * - false: let the real page fault path to fix it.
2929 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2932 struct kvm_shadow_walk_iterator iterator;
2933 struct kvm_mmu_page *sp;
2937 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2940 if (!page_fault_can_be_fast(error_code))
2943 walk_shadow_page_lockless_begin(vcpu);
2944 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2945 if (!is_shadow_present_pte(spte) || iterator.level < level)
2949 * If the mapping has been changed, let the vcpu fault on the
2950 * same address again.
2952 if (!is_shadow_present_pte(spte)) {
2957 sp = page_header(__pa(iterator.sptep));
2958 if (!is_last_spte(spte, sp->role.level))
2962 * Check if it is a spurious fault caused by TLB lazily flushed.
2964 * Need not check the access of upper level table entries since
2965 * they are always ACC_ALL.
2967 if (is_writable_pte(spte)) {
2973 * Currently, to simplify the code, only the spte write-protected
2974 * by dirty-log can be fast fixed.
2976 if (!spte_is_locklessly_modifiable(spte))
2980 * Do not fix write-permission on the large spte since we only dirty
2981 * the first page into the dirty-bitmap in fast_pf_fix_direct_spte()
2982 * that means other pages are missed if its slot is dirty-logged.
2984 * Instead, we let the slow page fault path create a normal spte to
2987 * See the comments in kvm_arch_commit_memory_region().
2989 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2993 * Currently, fast page fault only works for direct mapping since
2994 * the gfn is not stable for indirect shadow page.
2995 * See Documentation/virtual/kvm/locking.txt to get more detail.
2997 ret = fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte);
2999 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
3001 walk_shadow_page_lockless_end(vcpu);
3006 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3007 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable);
3008 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
3010 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
3011 gfn_t gfn, bool prefault)
3015 bool force_pt_level = false;
3017 unsigned long mmu_seq;
3018 bool map_writable, write = error_code & PFERR_WRITE_MASK;
3020 level = mapping_level(vcpu, gfn, &force_pt_level);
3021 if (likely(!force_pt_level)) {
3023 * This path builds a PAE pagetable - so we can map
3024 * 2mb pages at maximum. Therefore check if the level
3025 * is larger than that.
3027 if (level > PT_DIRECTORY_LEVEL)
3028 level = PT_DIRECTORY_LEVEL;
3030 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3033 if (fast_page_fault(vcpu, v, level, error_code))
3036 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3039 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3042 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3045 spin_lock(&vcpu->kvm->mmu_lock);
3046 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3048 make_mmu_pages_available(vcpu);
3049 if (likely(!force_pt_level))
3050 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3051 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3052 spin_unlock(&vcpu->kvm->mmu_lock);
3057 spin_unlock(&vcpu->kvm->mmu_lock);
3058 kvm_release_pfn_clean(pfn);
3063 static void mmu_free_roots(struct kvm_vcpu *vcpu)
3066 struct kvm_mmu_page *sp;
3067 LIST_HEAD(invalid_list);
3069 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3072 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
3073 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
3074 vcpu->arch.mmu.direct_map)) {
3075 hpa_t root = vcpu->arch.mmu.root_hpa;
3077 spin_lock(&vcpu->kvm->mmu_lock);
3078 sp = page_header(root);
3080 if (!sp->root_count && sp->role.invalid) {
3081 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3082 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3084 spin_unlock(&vcpu->kvm->mmu_lock);
3085 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3089 spin_lock(&vcpu->kvm->mmu_lock);
3090 for (i = 0; i < 4; ++i) {
3091 hpa_t root = vcpu->arch.mmu.pae_root[i];
3094 root &= PT64_BASE_ADDR_MASK;
3095 sp = page_header(root);
3097 if (!sp->root_count && sp->role.invalid)
3098 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3101 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3103 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3104 spin_unlock(&vcpu->kvm->mmu_lock);
3105 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3108 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3112 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3113 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3120 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3122 struct kvm_mmu_page *sp;
3125 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3126 spin_lock(&vcpu->kvm->mmu_lock);
3127 make_mmu_pages_available(vcpu);
3128 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, 1, ACC_ALL);
3130 spin_unlock(&vcpu->kvm->mmu_lock);
3131 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3132 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3133 for (i = 0; i < 4; ++i) {
3134 hpa_t root = vcpu->arch.mmu.pae_root[i];
3136 MMU_WARN_ON(VALID_PAGE(root));
3137 spin_lock(&vcpu->kvm->mmu_lock);
3138 make_mmu_pages_available(vcpu);
3139 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3140 i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3141 root = __pa(sp->spt);
3143 spin_unlock(&vcpu->kvm->mmu_lock);
3144 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3146 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3153 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3155 struct kvm_mmu_page *sp;
3160 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3162 if (mmu_check_root(vcpu, root_gfn))
3166 * Do we shadow a long mode page table? If so we need to
3167 * write-protect the guests page table root.
3169 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3170 hpa_t root = vcpu->arch.mmu.root_hpa;
3172 MMU_WARN_ON(VALID_PAGE(root));
3174 spin_lock(&vcpu->kvm->mmu_lock);
3175 make_mmu_pages_available(vcpu);
3176 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3178 root = __pa(sp->spt);
3180 spin_unlock(&vcpu->kvm->mmu_lock);
3181 vcpu->arch.mmu.root_hpa = root;
3186 * We shadow a 32 bit page table. This may be a legacy 2-level
3187 * or a PAE 3-level page table. In either case we need to be aware that
3188 * the shadow page table may be a PAE or a long mode page table.
3190 pm_mask = PT_PRESENT_MASK;
3191 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3192 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3194 for (i = 0; i < 4; ++i) {
3195 hpa_t root = vcpu->arch.mmu.pae_root[i];
3197 MMU_WARN_ON(VALID_PAGE(root));
3198 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3199 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3200 if (!(pdptr & PT_PRESENT_MASK)) {
3201 vcpu->arch.mmu.pae_root[i] = 0;
3204 root_gfn = pdptr >> PAGE_SHIFT;
3205 if (mmu_check_root(vcpu, root_gfn))
3208 spin_lock(&vcpu->kvm->mmu_lock);
3209 make_mmu_pages_available(vcpu);
3210 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3212 root = __pa(sp->spt);
3214 spin_unlock(&vcpu->kvm->mmu_lock);
3216 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3218 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3221 * If we shadow a 32 bit page table with a long mode page
3222 * table we enter this path.
3224 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3225 if (vcpu->arch.mmu.lm_root == NULL) {
3227 * The additional page necessary for this is only
3228 * allocated on demand.
3233 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3234 if (lm_root == NULL)
3237 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3239 vcpu->arch.mmu.lm_root = lm_root;
3242 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3248 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3250 if (vcpu->arch.mmu.direct_map)
3251 return mmu_alloc_direct_roots(vcpu);
3253 return mmu_alloc_shadow_roots(vcpu);
3256 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3259 struct kvm_mmu_page *sp;
3261 if (vcpu->arch.mmu.direct_map)
3264 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3267 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3268 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3269 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3270 hpa_t root = vcpu->arch.mmu.root_hpa;
3271 sp = page_header(root);
3272 mmu_sync_children(vcpu, sp);
3273 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3276 for (i = 0; i < 4; ++i) {
3277 hpa_t root = vcpu->arch.mmu.pae_root[i];
3279 if (root && VALID_PAGE(root)) {
3280 root &= PT64_BASE_ADDR_MASK;
3281 sp = page_header(root);
3282 mmu_sync_children(vcpu, sp);
3285 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3288 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3290 spin_lock(&vcpu->kvm->mmu_lock);
3291 mmu_sync_roots(vcpu);
3292 spin_unlock(&vcpu->kvm->mmu_lock);
3294 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3296 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3297 u32 access, struct x86_exception *exception)
3300 exception->error_code = 0;
3304 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3306 struct x86_exception *exception)
3309 exception->error_code = 0;
3310 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3314 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3316 int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3318 return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3319 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3322 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3324 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3327 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3329 return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3332 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3335 return vcpu_match_mmio_gpa(vcpu, addr);
3337 return vcpu_match_mmio_gva(vcpu, addr);
3340 /* return true if reserved bit is detected on spte. */
3342 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3344 struct kvm_shadow_walk_iterator iterator;
3345 u64 sptes[PT64_ROOT_LEVEL], spte = 0ull;
3347 bool reserved = false;
3349 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3352 walk_shadow_page_lockless_begin(vcpu);
3354 for (shadow_walk_init(&iterator, vcpu, addr),
3355 leaf = root = iterator.level;
3356 shadow_walk_okay(&iterator);
3357 __shadow_walk_next(&iterator, spte)) {
3358 spte = mmu_spte_get_lockless(iterator.sptep);
3360 sptes[leaf - 1] = spte;
3363 if (!is_shadow_present_pte(spte))
3366 reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte,
3370 walk_shadow_page_lockless_end(vcpu);
3373 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3375 while (root > leaf) {
3376 pr_err("------ spte 0x%llx level %d.\n",
3377 sptes[root - 1], root);
3386 int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3391 if (mmio_info_in_cache(vcpu, addr, direct))
3392 return RET_MMIO_PF_EMULATE;
3394 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3395 if (WARN_ON(reserved))
3396 return RET_MMIO_PF_BUG;
3398 if (is_mmio_spte(spte)) {
3399 gfn_t gfn = get_mmio_spte_gfn(spte);
3400 unsigned access = get_mmio_spte_access(spte);
3402 if (!check_mmio_spte(vcpu, spte))
3403 return RET_MMIO_PF_INVALID;
3408 trace_handle_mmio_page_fault(addr, gfn, access);
3409 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3410 return RET_MMIO_PF_EMULATE;
3414 * If the page table is zapped by other cpus, let CPU fault again on
3417 return RET_MMIO_PF_RETRY;
3419 EXPORT_SYMBOL_GPL(handle_mmio_page_fault);
3421 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3422 u32 error_code, gfn_t gfn)
3424 if (unlikely(error_code & PFERR_RSVD_MASK))
3427 if (!(error_code & PFERR_PRESENT_MASK) ||
3428 !(error_code & PFERR_WRITE_MASK))
3432 * guest is writing the page which is write tracked which can
3433 * not be fixed by page fault handler.
3435 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3441 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3443 struct kvm_shadow_walk_iterator iterator;
3446 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3449 walk_shadow_page_lockless_begin(vcpu);
3450 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3451 clear_sp_write_flooding_count(iterator.sptep);
3452 if (!is_shadow_present_pte(spte))
3455 walk_shadow_page_lockless_end(vcpu);
3458 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3459 u32 error_code, bool prefault)
3461 gfn_t gfn = gva >> PAGE_SHIFT;
3464 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3466 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3469 r = mmu_topup_memory_caches(vcpu);
3473 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3476 return nonpaging_map(vcpu, gva & PAGE_MASK,
3477 error_code, gfn, prefault);
3480 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3482 struct kvm_arch_async_pf arch;
3484 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3486 arch.direct_map = vcpu->arch.mmu.direct_map;
3487 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3489 return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3492 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3494 if (unlikely(!lapic_in_kernel(vcpu) ||
3495 kvm_event_needs_reinjection(vcpu)))
3498 return kvm_x86_ops->interrupt_allowed(vcpu);
3501 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3502 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable)
3504 struct kvm_memory_slot *slot;
3507 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3509 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3511 return false; /* *pfn has correct page already */
3513 if (!prefault && can_do_async_pf(vcpu)) {
3514 trace_kvm_try_async_get_page(gva, gfn);
3515 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3516 trace_kvm_async_pf_doublefault(gva, gfn);
3517 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3519 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3523 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3528 check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
3530 int page_num = KVM_PAGES_PER_HPAGE(level);
3532 gfn &= ~(page_num - 1);
3534 return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
3537 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3543 bool force_pt_level;
3544 gfn_t gfn = gpa >> PAGE_SHIFT;
3545 unsigned long mmu_seq;
3546 int write = error_code & PFERR_WRITE_MASK;
3549 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3551 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3554 r = mmu_topup_memory_caches(vcpu);
3558 force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn,
3559 PT_DIRECTORY_LEVEL);
3560 level = mapping_level(vcpu, gfn, &force_pt_level);
3561 if (likely(!force_pt_level)) {
3562 if (level > PT_DIRECTORY_LEVEL &&
3563 !check_hugepage_cache_consistency(vcpu, gfn, level))
3564 level = PT_DIRECTORY_LEVEL;
3565 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3568 if (fast_page_fault(vcpu, gpa, level, error_code))
3571 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3574 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3577 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3580 spin_lock(&vcpu->kvm->mmu_lock);
3581 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3583 make_mmu_pages_available(vcpu);
3584 if (likely(!force_pt_level))
3585 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3586 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3587 spin_unlock(&vcpu->kvm->mmu_lock);
3592 spin_unlock(&vcpu->kvm->mmu_lock);
3593 kvm_release_pfn_clean(pfn);
3597 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3598 struct kvm_mmu *context)
3600 context->page_fault = nonpaging_page_fault;
3601 context->gva_to_gpa = nonpaging_gva_to_gpa;
3602 context->sync_page = nonpaging_sync_page;
3603 context->invlpg = nonpaging_invlpg;
3604 context->update_pte = nonpaging_update_pte;
3605 context->root_level = 0;
3606 context->shadow_root_level = PT32E_ROOT_LEVEL;
3607 context->root_hpa = INVALID_PAGE;
3608 context->direct_map = true;
3609 context->nx = false;
3612 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
3614 mmu_free_roots(vcpu);
3617 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3619 return kvm_read_cr3(vcpu);
3622 static void inject_page_fault(struct kvm_vcpu *vcpu,
3623 struct x86_exception *fault)
3625 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3628 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
3629 unsigned access, int *nr_present)
3631 if (unlikely(is_mmio_spte(*sptep))) {
3632 if (gfn != get_mmio_spte_gfn(*sptep)) {
3633 mmu_spte_clear_no_track(sptep);
3638 mark_mmio_spte(vcpu, sptep, gfn, access);
3645 static inline bool is_last_gpte(struct kvm_mmu *mmu,
3646 unsigned level, unsigned gpte)
3649 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
3650 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
3651 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
3653 gpte |= level - PT_PAGE_TABLE_LEVEL - 1;
3656 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3657 * If it is clear, there are no large pages at this level, so clear
3658 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3660 gpte &= level - mmu->last_nonleaf_level;
3662 return gpte & PT_PAGE_SIZE_MASK;
3665 #define PTTYPE_EPT 18 /* arbitrary */
3666 #define PTTYPE PTTYPE_EPT
3667 #include "paging_tmpl.h"
3671 #include "paging_tmpl.h"
3675 #include "paging_tmpl.h"
3679 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3680 struct rsvd_bits_validate *rsvd_check,
3681 int maxphyaddr, int level, bool nx, bool gbpages,
3684 u64 exb_bit_rsvd = 0;
3685 u64 gbpages_bit_rsvd = 0;
3686 u64 nonleaf_bit8_rsvd = 0;
3688 rsvd_check->bad_mt_xwr = 0;
3691 exb_bit_rsvd = rsvd_bits(63, 63);
3693 gbpages_bit_rsvd = rsvd_bits(7, 7);
3696 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3697 * leaf entries) on AMD CPUs only.
3700 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
3703 case PT32_ROOT_LEVEL:
3704 /* no rsvd bits for 2 level 4K page table entries */
3705 rsvd_check->rsvd_bits_mask[0][1] = 0;
3706 rsvd_check->rsvd_bits_mask[0][0] = 0;
3707 rsvd_check->rsvd_bits_mask[1][0] =
3708 rsvd_check->rsvd_bits_mask[0][0];
3711 rsvd_check->rsvd_bits_mask[1][1] = 0;
3715 if (is_cpuid_PSE36())
3716 /* 36bits PSE 4MB page */
3717 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3719 /* 32 bits PSE 4MB page */
3720 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3722 case PT32E_ROOT_LEVEL:
3723 rsvd_check->rsvd_bits_mask[0][2] =
3724 rsvd_bits(maxphyaddr, 63) |
3725 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3726 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3727 rsvd_bits(maxphyaddr, 62); /* PDE */
3728 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3729 rsvd_bits(maxphyaddr, 62); /* PTE */
3730 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3731 rsvd_bits(maxphyaddr, 62) |
3732 rsvd_bits(13, 20); /* large page */
3733 rsvd_check->rsvd_bits_mask[1][0] =
3734 rsvd_check->rsvd_bits_mask[0][0];
3736 case PT64_ROOT_LEVEL:
3737 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3738 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
3739 rsvd_bits(maxphyaddr, 51);
3740 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3741 nonleaf_bit8_rsvd | gbpages_bit_rsvd |
3742 rsvd_bits(maxphyaddr, 51);
3743 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3744 rsvd_bits(maxphyaddr, 51);
3745 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3746 rsvd_bits(maxphyaddr, 51);
3747 rsvd_check->rsvd_bits_mask[1][3] =
3748 rsvd_check->rsvd_bits_mask[0][3];
3749 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3750 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
3752 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3753 rsvd_bits(maxphyaddr, 51) |
3754 rsvd_bits(13, 20); /* large page */
3755 rsvd_check->rsvd_bits_mask[1][0] =
3756 rsvd_check->rsvd_bits_mask[0][0];
3761 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3762 struct kvm_mmu *context)
3764 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
3765 cpuid_maxphyaddr(vcpu), context->root_level,
3766 context->nx, guest_cpuid_has_gbpages(vcpu),
3767 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
3771 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
3772 int maxphyaddr, bool execonly)
3776 rsvd_check->rsvd_bits_mask[0][3] =
3777 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
3778 rsvd_check->rsvd_bits_mask[0][2] =
3779 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3780 rsvd_check->rsvd_bits_mask[0][1] =
3781 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3782 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
3785 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
3786 rsvd_check->rsvd_bits_mask[1][2] =
3787 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
3788 rsvd_check->rsvd_bits_mask[1][1] =
3789 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
3790 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
3792 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
3793 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
3794 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
3795 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
3796 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
3798 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
3799 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
3801 rsvd_check->bad_mt_xwr = bad_mt_xwr;
3804 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
3805 struct kvm_mmu *context, bool execonly)
3807 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
3808 cpuid_maxphyaddr(vcpu), execonly);
3812 * the page table on host is the shadow page table for the page
3813 * table in guest or amd nested guest, its mmu features completely
3814 * follow the features in guest.
3817 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3819 bool uses_nx = context->nx || context->base_role.smep_andnot_wp;
3822 * Passing "true" to the last argument is okay; it adds a check
3823 * on bit 8 of the SPTEs which KVM doesn't use anyway.
3825 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
3826 boot_cpu_data.x86_phys_bits,
3827 context->shadow_root_level, uses_nx,
3828 guest_cpuid_has_gbpages(vcpu), is_pse(vcpu),
3831 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
3833 static inline bool boot_cpu_is_amd(void)
3835 WARN_ON_ONCE(!tdp_enabled);
3836 return shadow_x_mask == 0;
3840 * the direct page table on host, use as much mmu features as
3841 * possible, however, kvm currently does not do execution-protection.
3844 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
3845 struct kvm_mmu *context)
3847 if (boot_cpu_is_amd())
3848 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
3849 boot_cpu_data.x86_phys_bits,
3850 context->shadow_root_level, false,
3851 boot_cpu_has(X86_FEATURE_GBPAGES),
3854 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
3855 boot_cpu_data.x86_phys_bits,
3861 * as the comments in reset_shadow_zero_bits_mask() except it
3862 * is the shadow page table for intel nested guest.
3865 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
3866 struct kvm_mmu *context, bool execonly)
3868 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
3869 boot_cpu_data.x86_phys_bits, execonly);
3872 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
3873 struct kvm_mmu *mmu, bool ept)
3875 unsigned bit, byte, pfec;
3877 bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0;
3879 cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3880 cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
3881 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3884 wf = pfec & PFERR_WRITE_MASK;
3885 uf = pfec & PFERR_USER_MASK;
3886 ff = pfec & PFERR_FETCH_MASK;
3888 * PFERR_RSVD_MASK bit is set in PFEC if the access is not
3889 * subject to SMAP restrictions, and cleared otherwise. The
3890 * bit is only meaningful if the SMAP bit is set in CR4.
3892 smapf = !(pfec & PFERR_RSVD_MASK);
3893 for (bit = 0; bit < 8; ++bit) {
3894 x = bit & ACC_EXEC_MASK;
3895 w = bit & ACC_WRITE_MASK;
3896 u = bit & ACC_USER_MASK;
3899 /* Not really needed: !nx will cause pte.nx to fault */
3901 /* Allow supervisor writes if !cr0.wp */
3902 w |= !is_write_protection(vcpu) && !uf;
3903 /* Disallow supervisor fetches of user code if cr4.smep */
3904 x &= !(cr4_smep && u && !uf);
3907 * SMAP:kernel-mode data accesses from user-mode
3908 * mappings should fault. A fault is considered
3909 * as a SMAP violation if all of the following
3910 * conditions are ture:
3911 * - X86_CR4_SMAP is set in CR4
3912 * - An user page is accessed
3913 * - Page fault in kernel mode
3914 * - if CPL = 3 or X86_EFLAGS_AC is clear
3916 * Here, we cover the first three conditions.
3917 * The fourth is computed dynamically in
3918 * permission_fault() and is in smapf.
3920 * Also, SMAP does not affect instruction
3921 * fetches, add the !ff check here to make it
3924 smap = cr4_smap && u && !uf && !ff;
3927 fault = (ff && !x) || (uf && !u) || (wf && !w) ||
3929 map |= fault << bit;
3931 mmu->permissions[byte] = map;
3936 * PKU is an additional mechanism by which the paging controls access to
3937 * user-mode addresses based on the value in the PKRU register. Protection
3938 * key violations are reported through a bit in the page fault error code.
3939 * Unlike other bits of the error code, the PK bit is not known at the
3940 * call site of e.g. gva_to_gpa; it must be computed directly in
3941 * permission_fault based on two bits of PKRU, on some machine state (CR4,
3942 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
3944 * In particular the following conditions come from the error code, the
3945 * page tables and the machine state:
3946 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
3947 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
3948 * - PK is always zero if U=0 in the page tables
3949 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
3951 * The PKRU bitmask caches the result of these four conditions. The error
3952 * code (minus the P bit) and the page table's U bit form an index into the
3953 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
3954 * with the two bits of the PKRU register corresponding to the protection key.
3955 * For the first three conditions above the bits will be 00, thus masking
3956 * away both AD and WD. For all reads or if the last condition holds, WD
3957 * only will be masked away.
3959 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3970 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
3971 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
3976 wp = is_write_protection(vcpu);
3978 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
3979 unsigned pfec, pkey_bits;
3980 bool check_pkey, check_write, ff, uf, wf, pte_user;
3983 ff = pfec & PFERR_FETCH_MASK;
3984 uf = pfec & PFERR_USER_MASK;
3985 wf = pfec & PFERR_WRITE_MASK;
3987 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
3988 pte_user = pfec & PFERR_RSVD_MASK;
3991 * Only need to check the access which is not an
3992 * instruction fetch and is to a user page.
3994 check_pkey = (!ff && pte_user);
3996 * write access is controlled by PKRU if it is a
3997 * user access or CR0.WP = 1.
3999 check_write = check_pkey && wf && (uf || wp);
4001 /* PKRU.AD stops both read and write access. */
4002 pkey_bits = !!check_pkey;
4003 /* PKRU.WD stops write access. */
4004 pkey_bits |= (!!check_write) << 1;
4006 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4010 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4012 unsigned root_level = mmu->root_level;
4014 mmu->last_nonleaf_level = root_level;
4015 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4016 mmu->last_nonleaf_level++;
4019 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4020 struct kvm_mmu *context,
4023 context->nx = is_nx(vcpu);
4024 context->root_level = level;
4026 reset_rsvds_bits_mask(vcpu, context);
4027 update_permission_bitmask(vcpu, context, false);
4028 update_pkru_bitmask(vcpu, context, false);
4029 update_last_nonleaf_level(vcpu, context);
4031 MMU_WARN_ON(!is_pae(vcpu));
4032 context->page_fault = paging64_page_fault;
4033 context->gva_to_gpa = paging64_gva_to_gpa;
4034 context->sync_page = paging64_sync_page;
4035 context->invlpg = paging64_invlpg;
4036 context->update_pte = paging64_update_pte;
4037 context->shadow_root_level = level;
4038 context->root_hpa = INVALID_PAGE;
4039 context->direct_map = false;
4042 static void paging64_init_context(struct kvm_vcpu *vcpu,
4043 struct kvm_mmu *context)
4045 paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
4048 static void paging32_init_context(struct kvm_vcpu *vcpu,
4049 struct kvm_mmu *context)
4051 context->nx = false;
4052 context->root_level = PT32_ROOT_LEVEL;
4054 reset_rsvds_bits_mask(vcpu, context);
4055 update_permission_bitmask(vcpu, context, false);
4056 update_pkru_bitmask(vcpu, context, false);
4057 update_last_nonleaf_level(vcpu, context);
4059 context->page_fault = paging32_page_fault;
4060 context->gva_to_gpa = paging32_gva_to_gpa;
4061 context->sync_page = paging32_sync_page;
4062 context->invlpg = paging32_invlpg;
4063 context->update_pte = paging32_update_pte;
4064 context->shadow_root_level = PT32E_ROOT_LEVEL;
4065 context->root_hpa = INVALID_PAGE;
4066 context->direct_map = false;
4069 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4070 struct kvm_mmu *context)
4072 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4075 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4077 struct kvm_mmu *context = &vcpu->arch.mmu;
4079 context->base_role.word = 0;
4080 context->base_role.smm = is_smm(vcpu);
4081 context->page_fault = tdp_page_fault;
4082 context->sync_page = nonpaging_sync_page;
4083 context->invlpg = nonpaging_invlpg;
4084 context->update_pte = nonpaging_update_pte;
4085 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4086 context->root_hpa = INVALID_PAGE;
4087 context->direct_map = true;
4088 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
4089 context->get_cr3 = get_cr3;
4090 context->get_pdptr = kvm_pdptr_read;
4091 context->inject_page_fault = kvm_inject_page_fault;
4093 if (!is_paging(vcpu)) {
4094 context->nx = false;
4095 context->gva_to_gpa = nonpaging_gva_to_gpa;
4096 context->root_level = 0;
4097 } else if (is_long_mode(vcpu)) {
4098 context->nx = is_nx(vcpu);
4099 context->root_level = PT64_ROOT_LEVEL;
4100 reset_rsvds_bits_mask(vcpu, context);
4101 context->gva_to_gpa = paging64_gva_to_gpa;
4102 } else if (is_pae(vcpu)) {
4103 context->nx = is_nx(vcpu);
4104 context->root_level = PT32E_ROOT_LEVEL;
4105 reset_rsvds_bits_mask(vcpu, context);
4106 context->gva_to_gpa = paging64_gva_to_gpa;
4108 context->nx = false;
4109 context->root_level = PT32_ROOT_LEVEL;
4110 reset_rsvds_bits_mask(vcpu, context);
4111 context->gva_to_gpa = paging32_gva_to_gpa;
4114 update_permission_bitmask(vcpu, context, false);
4115 update_pkru_bitmask(vcpu, context, false);
4116 update_last_nonleaf_level(vcpu, context);
4117 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4120 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
4122 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4123 bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4124 struct kvm_mmu *context = &vcpu->arch.mmu;
4126 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4128 if (!is_paging(vcpu))
4129 nonpaging_init_context(vcpu, context);
4130 else if (is_long_mode(vcpu))
4131 paging64_init_context(vcpu, context);
4132 else if (is_pae(vcpu))
4133 paging32E_init_context(vcpu, context);
4135 paging32_init_context(vcpu, context);
4137 context->base_role.nxe = is_nx(vcpu);
4138 context->base_role.cr4_pae = !!is_pae(vcpu);
4139 context->base_role.cr0_wp = is_write_protection(vcpu);
4140 context->base_role.smep_andnot_wp
4141 = smep && !is_write_protection(vcpu);
4142 context->base_role.smap_andnot_wp
4143 = smap && !is_write_protection(vcpu);
4144 context->base_role.smm = is_smm(vcpu);
4145 reset_shadow_zero_bits_mask(vcpu, context);
4147 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4149 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly)
4151 struct kvm_mmu *context = &vcpu->arch.mmu;
4153 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4155 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4158 context->page_fault = ept_page_fault;
4159 context->gva_to_gpa = ept_gva_to_gpa;
4160 context->sync_page = ept_sync_page;
4161 context->invlpg = ept_invlpg;
4162 context->update_pte = ept_update_pte;
4163 context->root_level = context->shadow_root_level;
4164 context->root_hpa = INVALID_PAGE;
4165 context->direct_map = false;
4167 update_permission_bitmask(vcpu, context, true);
4168 update_pkru_bitmask(vcpu, context, true);
4169 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4170 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4172 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4174 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4176 struct kvm_mmu *context = &vcpu->arch.mmu;
4178 kvm_init_shadow_mmu(vcpu);
4179 context->set_cr3 = kvm_x86_ops->set_cr3;
4180 context->get_cr3 = get_cr3;
4181 context->get_pdptr = kvm_pdptr_read;
4182 context->inject_page_fault = kvm_inject_page_fault;
4185 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4187 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4189 g_context->get_cr3 = get_cr3;
4190 g_context->get_pdptr = kvm_pdptr_read;
4191 g_context->inject_page_fault = kvm_inject_page_fault;
4194 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4195 * L1's nested page tables (e.g. EPT12). The nested translation
4196 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4197 * L2's page tables as the first level of translation and L1's
4198 * nested page tables as the second level of translation. Basically
4199 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4201 if (!is_paging(vcpu)) {
4202 g_context->nx = false;
4203 g_context->root_level = 0;
4204 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4205 } else if (is_long_mode(vcpu)) {
4206 g_context->nx = is_nx(vcpu);
4207 g_context->root_level = PT64_ROOT_LEVEL;
4208 reset_rsvds_bits_mask(vcpu, g_context);
4209 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4210 } else if (is_pae(vcpu)) {
4211 g_context->nx = is_nx(vcpu);
4212 g_context->root_level = PT32E_ROOT_LEVEL;
4213 reset_rsvds_bits_mask(vcpu, g_context);
4214 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4216 g_context->nx = false;
4217 g_context->root_level = PT32_ROOT_LEVEL;
4218 reset_rsvds_bits_mask(vcpu, g_context);
4219 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4222 update_permission_bitmask(vcpu, g_context, false);
4223 update_pkru_bitmask(vcpu, g_context, false);
4224 update_last_nonleaf_level(vcpu, g_context);
4227 static void init_kvm_mmu(struct kvm_vcpu *vcpu)
4229 if (mmu_is_nested(vcpu))
4230 init_kvm_nested_mmu(vcpu);
4231 else if (tdp_enabled)
4232 init_kvm_tdp_mmu(vcpu);
4234 init_kvm_softmmu(vcpu);
4237 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4239 kvm_mmu_unload(vcpu);
4242 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4244 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4248 r = mmu_topup_memory_caches(vcpu);
4251 r = mmu_alloc_roots(vcpu);
4252 kvm_mmu_sync_roots(vcpu);
4255 /* set_cr3() should ensure TLB has been flushed */
4256 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
4260 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4262 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4264 mmu_free_roots(vcpu);
4265 WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4267 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4269 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4270 struct kvm_mmu_page *sp, u64 *spte,
4273 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
4274 ++vcpu->kvm->stat.mmu_pde_zapped;
4278 ++vcpu->kvm->stat.mmu_pte_updated;
4279 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
4282 static bool need_remote_flush(u64 old, u64 new)
4284 if (!is_shadow_present_pte(old))
4286 if (!is_shadow_present_pte(new))
4288 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4290 old ^= shadow_nx_mask;
4291 new ^= shadow_nx_mask;
4292 return (old & ~new & PT64_PERM_MASK) != 0;
4295 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4296 const u8 *new, int *bytes)
4302 * Assume that the pte write on a page table of the same type
4303 * as the current vcpu paging mode since we update the sptes only
4304 * when they have the same mode.
4306 if (is_pae(vcpu) && *bytes == 4) {
4307 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4310 r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8);
4313 new = (const u8 *)&gentry;
4318 gentry = *(const u32 *)new;
4321 gentry = *(const u64 *)new;
4332 * If we're seeing too many writes to a page, it may no longer be a page table,
4333 * or we may be forking, in which case it is better to unmap the page.
4335 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4338 * Skip write-flooding detected for the sp whose level is 1, because
4339 * it can become unsync, then the guest page is not write-protected.
4341 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
4344 atomic_inc(&sp->write_flooding_count);
4345 return atomic_read(&sp->write_flooding_count) >= 3;
4349 * Misaligned accesses are too much trouble to fix up; also, they usually
4350 * indicate a page is not used as a page table.
4352 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4355 unsigned offset, pte_size, misaligned;
4357 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4358 gpa, bytes, sp->role.word);
4360 offset = offset_in_page(gpa);
4361 pte_size = sp->role.cr4_pae ? 8 : 4;
4364 * Sometimes, the OS only writes the last one bytes to update status
4365 * bits, for example, in linux, andb instruction is used in clear_bit().
4367 if (!(offset & (pte_size - 1)) && bytes == 1)
4370 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4371 misaligned |= bytes < 4;
4376 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4378 unsigned page_offset, quadrant;
4382 page_offset = offset_in_page(gpa);
4383 level = sp->role.level;
4385 if (!sp->role.cr4_pae) {
4386 page_offset <<= 1; /* 32->64 */
4388 * A 32-bit pde maps 4MB while the shadow pdes map
4389 * only 2MB. So we need to double the offset again
4390 * and zap two pdes instead of one.
4392 if (level == PT32_ROOT_LEVEL) {
4393 page_offset &= ~7; /* kill rounding error */
4397 quadrant = page_offset >> PAGE_SHIFT;
4398 page_offset &= ~PAGE_MASK;
4399 if (quadrant != sp->role.quadrant)
4403 spte = &sp->spt[page_offset / sizeof(*spte)];
4407 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4408 const u8 *new, int bytes)
4410 gfn_t gfn = gpa >> PAGE_SHIFT;
4411 struct kvm_mmu_page *sp;
4412 LIST_HEAD(invalid_list);
4413 u64 entry, gentry, *spte;
4415 bool remote_flush, local_flush;
4416 union kvm_mmu_page_role mask = { };
4421 mask.smep_andnot_wp = 1;
4422 mask.smap_andnot_wp = 1;
4426 * If we don't have indirect shadow pages, it means no page is
4427 * write-protected, so we can exit simply.
4429 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4432 remote_flush = local_flush = false;
4434 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4436 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4439 * No need to care whether allocation memory is successful
4440 * or not since pte prefetch is skiped if it does not have
4441 * enough objects in the cache.
4443 mmu_topup_memory_caches(vcpu);
4445 spin_lock(&vcpu->kvm->mmu_lock);
4446 ++vcpu->kvm->stat.mmu_pte_write;
4447 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4449 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4450 if (detect_write_misaligned(sp, gpa, bytes) ||
4451 detect_write_flooding(sp)) {
4452 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4453 ++vcpu->kvm->stat.mmu_flooded;
4457 spte = get_written_sptes(sp, gpa, &npte);
4464 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4466 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4467 & mask.word) && rmap_can_add(vcpu))
4468 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4469 if (need_remote_flush(entry, *spte))
4470 remote_flush = true;
4474 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
4475 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4476 spin_unlock(&vcpu->kvm->mmu_lock);
4479 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4484 if (vcpu->arch.mmu.direct_map)
4487 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4489 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4493 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4495 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4497 LIST_HEAD(invalid_list);
4499 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4502 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4503 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4506 ++vcpu->kvm->stat.mmu_recycled;
4508 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4511 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4512 void *insn, int insn_len)
4514 int r, emulation_type = EMULTYPE_RETRY;
4515 enum emulation_result er;
4516 bool direct = vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu);
4518 if (unlikely(error_code & PFERR_RSVD_MASK)) {
4519 r = handle_mmio_page_fault(vcpu, cr2, direct);
4520 if (r == RET_MMIO_PF_EMULATE) {
4524 if (r == RET_MMIO_PF_RETRY)
4530 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4536 if (mmio_info_in_cache(vcpu, cr2, direct))
4539 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4544 case EMULATE_USER_EXIT:
4545 ++vcpu->stat.mmio_exits;
4553 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4555 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4557 vcpu->arch.mmu.invlpg(vcpu, gva);
4558 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4559 ++vcpu->stat.invlpg;
4561 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4563 void kvm_enable_tdp(void)
4567 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4569 void kvm_disable_tdp(void)
4571 tdp_enabled = false;
4573 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4575 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4577 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4578 if (vcpu->arch.mmu.lm_root != NULL)
4579 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4582 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4588 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4589 * Therefore we need to allocate shadow page tables in the first
4590 * 4GB of memory, which happens to fit the DMA32 zone.
4592 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4596 vcpu->arch.mmu.pae_root = page_address(page);
4597 for (i = 0; i < 4; ++i)
4598 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4603 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4605 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4606 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4607 vcpu->arch.mmu.translate_gpa = translate_gpa;
4608 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4610 return alloc_mmu_pages(vcpu);
4613 void kvm_mmu_setup(struct kvm_vcpu *vcpu)
4615 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4620 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
4621 struct kvm_memory_slot *slot)
4623 kvm_mmu_invalidate_zap_all_pages(kvm);
4626 void kvm_mmu_init_vm(struct kvm *kvm)
4628 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
4630 node->track_write = kvm_mmu_pte_write;
4631 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
4632 kvm_page_track_register_notifier(kvm, node);
4635 void kvm_mmu_uninit_vm(struct kvm *kvm)
4637 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
4639 kvm_page_track_unregister_notifier(kvm, node);
4642 /* The return value indicates if tlb flush on all vcpus is needed. */
4643 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
4645 /* The caller should hold mmu-lock before calling this function. */
4647 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
4648 slot_level_handler fn, int start_level, int end_level,
4649 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
4651 struct slot_rmap_walk_iterator iterator;
4654 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
4655 end_gfn, &iterator) {
4657 flush |= fn(kvm, iterator.rmap);
4659 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4660 if (flush && lock_flush_tlb) {
4661 kvm_flush_remote_tlbs(kvm);
4664 cond_resched_lock(&kvm->mmu_lock);
4668 if (flush && lock_flush_tlb) {
4669 kvm_flush_remote_tlbs(kvm);
4677 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4678 slot_level_handler fn, int start_level, int end_level,
4679 bool lock_flush_tlb)
4681 return slot_handle_level_range(kvm, memslot, fn, start_level,
4682 end_level, memslot->base_gfn,
4683 memslot->base_gfn + memslot->npages - 1,
4688 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4689 slot_level_handler fn, bool lock_flush_tlb)
4691 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4692 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4696 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4697 slot_level_handler fn, bool lock_flush_tlb)
4699 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
4700 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4704 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
4705 slot_level_handler fn, bool lock_flush_tlb)
4707 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4708 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
4711 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
4713 struct kvm_memslots *slots;
4714 struct kvm_memory_slot *memslot;
4717 spin_lock(&kvm->mmu_lock);
4718 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
4719 slots = __kvm_memslots(kvm, i);
4720 kvm_for_each_memslot(memslot, slots) {
4723 start = max(gfn_start, memslot->base_gfn);
4724 end = min(gfn_end, memslot->base_gfn + memslot->npages);
4728 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
4729 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
4730 start, end - 1, true);
4734 spin_unlock(&kvm->mmu_lock);
4737 static bool slot_rmap_write_protect(struct kvm *kvm,
4738 struct kvm_rmap_head *rmap_head)
4740 return __rmap_write_protect(kvm, rmap_head, false);
4743 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
4744 struct kvm_memory_slot *memslot)
4748 spin_lock(&kvm->mmu_lock);
4749 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
4751 spin_unlock(&kvm->mmu_lock);
4754 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
4755 * which do tlb flush out of mmu-lock should be serialized by
4756 * kvm->slots_lock otherwise tlb flush would be missed.
4758 lockdep_assert_held(&kvm->slots_lock);
4761 * We can flush all the TLBs out of the mmu lock without TLB
4762 * corruption since we just change the spte from writable to
4763 * readonly so that we only need to care the case of changing
4764 * spte from present to present (changing the spte from present
4765 * to nonpresent will flush all the TLBs immediately), in other
4766 * words, the only case we care is mmu_spte_update() where we
4767 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
4768 * instead of PT_WRITABLE_MASK, that means it does not depend
4769 * on PT_WRITABLE_MASK anymore.
4772 kvm_flush_remote_tlbs(kvm);
4775 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
4776 struct kvm_rmap_head *rmap_head)
4779 struct rmap_iterator iter;
4780 int need_tlb_flush = 0;
4782 struct kvm_mmu_page *sp;
4785 for_each_rmap_spte(rmap_head, &iter, sptep) {
4786 sp = page_header(__pa(sptep));
4787 pfn = spte_to_pfn(*sptep);
4790 * We cannot do huge page mapping for indirect shadow pages,
4791 * which are found on the last rmap (level = 1) when not using
4792 * tdp; such shadow pages are synced with the page table in
4793 * the guest, and the guest page table is using 4K page size
4794 * mapping if the indirect sp has level = 1.
4796 if (sp->role.direct &&
4797 !kvm_is_reserved_pfn(pfn) &&
4798 PageTransCompoundMap(pfn_to_page(pfn))) {
4799 drop_spte(kvm, sptep);
4805 return need_tlb_flush;
4808 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
4809 const struct kvm_memory_slot *memslot)
4811 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
4812 spin_lock(&kvm->mmu_lock);
4813 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
4814 kvm_mmu_zap_collapsible_spte, true);
4815 spin_unlock(&kvm->mmu_lock);
4818 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
4819 struct kvm_memory_slot *memslot)
4823 spin_lock(&kvm->mmu_lock);
4824 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
4825 spin_unlock(&kvm->mmu_lock);
4827 lockdep_assert_held(&kvm->slots_lock);
4830 * It's also safe to flush TLBs out of mmu lock here as currently this
4831 * function is only used for dirty logging, in which case flushing TLB
4832 * out of mmu lock also guarantees no dirty pages will be lost in
4836 kvm_flush_remote_tlbs(kvm);
4838 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
4840 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
4841 struct kvm_memory_slot *memslot)
4845 spin_lock(&kvm->mmu_lock);
4846 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
4848 spin_unlock(&kvm->mmu_lock);
4850 /* see kvm_mmu_slot_remove_write_access */
4851 lockdep_assert_held(&kvm->slots_lock);
4854 kvm_flush_remote_tlbs(kvm);
4856 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
4858 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
4859 struct kvm_memory_slot *memslot)
4863 spin_lock(&kvm->mmu_lock);
4864 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
4865 spin_unlock(&kvm->mmu_lock);
4867 lockdep_assert_held(&kvm->slots_lock);
4869 /* see kvm_mmu_slot_leaf_clear_dirty */
4871 kvm_flush_remote_tlbs(kvm);
4873 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
4875 #define BATCH_ZAP_PAGES 10
4876 static void kvm_zap_obsolete_pages(struct kvm *kvm)
4878 struct kvm_mmu_page *sp, *node;
4882 list_for_each_entry_safe_reverse(sp, node,
4883 &kvm->arch.active_mmu_pages, link) {
4887 * No obsolete page exists before new created page since
4888 * active_mmu_pages is the FIFO list.
4890 if (!is_obsolete_sp(kvm, sp))
4894 * Since we are reversely walking the list and the invalid
4895 * list will be moved to the head, skip the invalid page
4896 * can help us to avoid the infinity list walking.
4898 if (sp->role.invalid)
4902 * Need not flush tlb since we only zap the sp with invalid
4903 * generation number.
4905 if (batch >= BATCH_ZAP_PAGES &&
4906 cond_resched_lock(&kvm->mmu_lock)) {
4911 ret = kvm_mmu_prepare_zap_page(kvm, sp,
4912 &kvm->arch.zapped_obsolete_pages);
4920 * Should flush tlb before free page tables since lockless-walking
4921 * may use the pages.
4923 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
4927 * Fast invalidate all shadow pages and use lock-break technique
4928 * to zap obsolete pages.
4930 * It's required when memslot is being deleted or VM is being
4931 * destroyed, in these cases, we should ensure that KVM MMU does
4932 * not use any resource of the being-deleted slot or all slots
4933 * after calling the function.
4935 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
4937 spin_lock(&kvm->mmu_lock);
4938 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
4939 kvm->arch.mmu_valid_gen++;
4942 * Notify all vcpus to reload its shadow page table
4943 * and flush TLB. Then all vcpus will switch to new
4944 * shadow page table with the new mmu_valid_gen.
4946 * Note: we should do this under the protection of
4947 * mmu-lock, otherwise, vcpu would purge shadow page
4948 * but miss tlb flush.
4950 kvm_reload_remote_mmus(kvm);
4952 kvm_zap_obsolete_pages(kvm);
4953 spin_unlock(&kvm->mmu_lock);
4956 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
4958 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
4961 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots)
4964 * The very rare case: if the generation-number is round,
4965 * zap all shadow pages.
4967 if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) {
4968 printk_ratelimited(KERN_DEBUG "kvm: zapping shadow pages for mmio generation wraparound\n");
4969 kvm_mmu_invalidate_zap_all_pages(kvm);
4973 static unsigned long
4974 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
4977 int nr_to_scan = sc->nr_to_scan;
4978 unsigned long freed = 0;
4980 spin_lock(&kvm_lock);
4982 list_for_each_entry(kvm, &vm_list, vm_list) {
4984 LIST_HEAD(invalid_list);
4987 * Never scan more than sc->nr_to_scan VM instances.
4988 * Will not hit this condition practically since we do not try
4989 * to shrink more than one VM and it is very unlikely to see
4990 * !n_used_mmu_pages so many times.
4995 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4996 * here. We may skip a VM instance errorneosly, but we do not
4997 * want to shrink a VM that only started to populate its MMU
5000 if (!kvm->arch.n_used_mmu_pages &&
5001 !kvm_has_zapped_obsolete_pages(kvm))
5004 idx = srcu_read_lock(&kvm->srcu);
5005 spin_lock(&kvm->mmu_lock);
5007 if (kvm_has_zapped_obsolete_pages(kvm)) {
5008 kvm_mmu_commit_zap_page(kvm,
5009 &kvm->arch.zapped_obsolete_pages);
5013 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
5015 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5018 spin_unlock(&kvm->mmu_lock);
5019 srcu_read_unlock(&kvm->srcu, idx);
5022 * unfair on small ones
5023 * per-vm shrinkers cry out
5024 * sadness comes quickly
5026 list_move_tail(&kvm->vm_list, &vm_list);
5030 spin_unlock(&kvm_lock);
5034 static unsigned long
5035 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5037 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5040 static struct shrinker mmu_shrinker = {
5041 .count_objects = mmu_shrink_count,
5042 .scan_objects = mmu_shrink_scan,
5043 .seeks = DEFAULT_SEEKS * 10,
5046 static void mmu_destroy_caches(void)
5048 if (pte_list_desc_cache)
5049 kmem_cache_destroy(pte_list_desc_cache);
5050 if (mmu_page_header_cache)
5051 kmem_cache_destroy(mmu_page_header_cache);
5054 int kvm_mmu_module_init(void)
5056 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5057 sizeof(struct pte_list_desc),
5059 if (!pte_list_desc_cache)
5062 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5063 sizeof(struct kvm_mmu_page),
5065 if (!mmu_page_header_cache)
5068 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5071 register_shrinker(&mmu_shrinker);
5076 mmu_destroy_caches();
5081 * Caculate mmu pages needed for kvm.
5083 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
5085 unsigned int nr_mmu_pages;
5086 unsigned int nr_pages = 0;
5087 struct kvm_memslots *slots;
5088 struct kvm_memory_slot *memslot;
5091 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5092 slots = __kvm_memslots(kvm, i);
5094 kvm_for_each_memslot(memslot, slots)
5095 nr_pages += memslot->npages;
5098 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5099 nr_mmu_pages = max(nr_mmu_pages,
5100 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
5102 return nr_mmu_pages;
5105 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5107 kvm_mmu_unload(vcpu);
5108 free_mmu_pages(vcpu);
5109 mmu_free_memory_caches(vcpu);
5112 void kvm_mmu_module_exit(void)
5114 mmu_destroy_caches();
5115 percpu_counter_destroy(&kvm_total_used_mmu_pages);
5116 unregister_shrinker(&mmu_shrinker);
5117 mmu_audit_disable();