3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/export.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
49 #define mod_64(x, y) ((x) % (y))
57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58 #define apic_debug(fmt, arg...)
60 /* 14 is the version for Xeon and Pentium 8.4.8*/
61 #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
62 #define LAPIC_MMIO_LENGTH (1 << 12)
63 /* followed define is not in apicdef.h */
64 #define APIC_SHORT_MASK 0xc0000
65 #define APIC_DEST_NOSHORT 0x0
66 #define APIC_DEST_MASK 0x800
67 #define MAX_APIC_VECTOR 256
68 #define APIC_VECTORS_PER_REG 32
70 #define APIC_BROADCAST 0xFF
71 #define X2APIC_BROADCAST 0xFFFFFFFFul
73 static inline int apic_test_vector(int vec, void *bitmap)
75 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
78 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
80 struct kvm_lapic *apic = vcpu->arch.apic;
82 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
83 apic_test_vector(vector, apic->regs + APIC_IRR);
86 static inline void apic_clear_vector(int vec, void *bitmap)
88 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
91 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
93 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
96 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
98 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
101 struct static_key_deferred apic_hw_disabled __read_mostly;
102 struct static_key_deferred apic_sw_disabled __read_mostly;
104 static inline int apic_enabled(struct kvm_lapic *apic)
106 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
110 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
113 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
114 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
116 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
118 return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
121 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
123 return apic->vcpu->vcpu_id;
126 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
127 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
129 case KVM_APIC_MODE_X2APIC: {
130 u32 offset = (dest_id >> 16) * 16;
131 u32 max_apic_id = map->max_apic_id;
133 if (offset <= max_apic_id) {
134 u8 cluster_size = min(max_apic_id - offset + 1, 16U);
136 *cluster = &map->phys_map[offset];
137 *mask = dest_id & (0xffff >> (16 - cluster_size));
144 case KVM_APIC_MODE_XAPIC_FLAT:
145 *cluster = map->xapic_flat_map;
146 *mask = dest_id & 0xff;
148 case KVM_APIC_MODE_XAPIC_CLUSTER:
149 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
150 *mask = dest_id & 0xf;
158 static void kvm_apic_map_free(struct rcu_head *rcu)
160 struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
165 static void recalculate_apic_map(struct kvm *kvm)
167 struct kvm_apic_map *new, *old = NULL;
168 struct kvm_vcpu *vcpu;
170 u32 max_id = 255; /* enough space for any xAPIC ID */
172 mutex_lock(&kvm->arch.apic_map_lock);
174 kvm_for_each_vcpu(i, vcpu, kvm)
175 if (kvm_apic_present(vcpu))
176 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
178 new = kvzalloc(sizeof(struct kvm_apic_map) +
179 sizeof(struct kvm_lapic *) * ((u64)max_id + 1), GFP_KERNEL);
184 new->max_apic_id = max_id;
186 kvm_for_each_vcpu(i, vcpu, kvm) {
187 struct kvm_lapic *apic = vcpu->arch.apic;
188 struct kvm_lapic **cluster;
194 if (!kvm_apic_present(vcpu))
197 xapic_id = kvm_xapic_id(apic);
198 x2apic_id = kvm_x2apic_id(apic);
200 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
201 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
202 x2apic_id <= new->max_apic_id)
203 new->phys_map[x2apic_id] = apic;
205 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
206 * prevent them from masking VCPUs with APIC ID <= 0xff.
208 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
209 new->phys_map[xapic_id] = apic;
211 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
213 if (apic_x2apic_mode(apic)) {
214 new->mode |= KVM_APIC_MODE_X2APIC;
216 ldr = GET_APIC_LOGICAL_ID(ldr);
217 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
218 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
220 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
223 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
227 cluster[ffs(mask) - 1] = apic;
230 old = rcu_dereference_protected(kvm->arch.apic_map,
231 lockdep_is_held(&kvm->arch.apic_map_lock));
232 rcu_assign_pointer(kvm->arch.apic_map, new);
233 mutex_unlock(&kvm->arch.apic_map_lock);
236 call_rcu(&old->rcu, kvm_apic_map_free);
238 kvm_make_scan_ioapic_request(kvm);
241 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
243 bool enabled = val & APIC_SPIV_APIC_ENABLED;
245 kvm_lapic_set_reg(apic, APIC_SPIV, val);
247 if (enabled != apic->sw_enabled) {
248 apic->sw_enabled = enabled;
250 static_key_slow_dec_deferred(&apic_sw_disabled);
251 recalculate_apic_map(apic->vcpu->kvm);
253 static_key_slow_inc(&apic_sw_disabled.key);
257 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
259 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
260 recalculate_apic_map(apic->vcpu->kvm);
263 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
265 kvm_lapic_set_reg(apic, APIC_LDR, id);
266 recalculate_apic_map(apic->vcpu->kvm);
269 static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
271 return ((id >> 4) << 16) | (1 << (id & 0xf));
274 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
276 u32 ldr = kvm_apic_calc_x2apic_ldr(id);
278 WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
280 kvm_lapic_set_reg(apic, APIC_ID, id);
281 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
282 recalculate_apic_map(apic->vcpu->kvm);
285 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
287 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
290 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
292 return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
295 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
297 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
300 static inline int apic_lvtt_period(struct kvm_lapic *apic)
302 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
305 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
307 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
310 static inline int apic_lvt_nmi_mode(u32 lvt_val)
312 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
315 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
317 struct kvm_lapic *apic = vcpu->arch.apic;
318 struct kvm_cpuid_entry2 *feat;
319 u32 v = APIC_VERSION;
321 if (!lapic_in_kernel(vcpu))
325 * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
326 * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
327 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
328 * version first and level-triggered interrupts never get EOIed in
331 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
332 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) &&
333 !ioapic_in_kernel(vcpu->kvm))
334 v |= APIC_LVR_DIRECTED_EOI;
335 kvm_lapic_set_reg(apic, APIC_LVR, v);
338 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
339 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
340 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
341 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
342 LINT_MASK, LINT_MASK, /* LVT0-1 */
343 LVT_MASK /* LVTERR */
346 static int find_highest_vector(void *bitmap)
351 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
352 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
353 reg = bitmap + REG_POS(vec);
355 return __fls(*reg) + vec;
361 static u8 count_vectors(void *bitmap)
367 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
368 reg = bitmap + REG_POS(vec);
369 count += hweight32(*reg);
375 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
378 u32 pir_val, irr_val, prev_irr_val;
381 max_updated_irr = -1;
384 for (i = vec = 0; i <= 7; i++, vec += 32) {
385 pir_val = READ_ONCE(pir[i]);
386 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
388 prev_irr_val = irr_val;
389 irr_val |= xchg(&pir[i], 0);
390 *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
391 if (prev_irr_val != irr_val) {
393 __fls(irr_val ^ prev_irr_val) + vec;
397 *max_irr = __fls(irr_val) + vec;
400 return ((max_updated_irr != -1) &&
401 (max_updated_irr == *max_irr));
403 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
405 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
407 struct kvm_lapic *apic = vcpu->arch.apic;
409 return __kvm_apic_update_irr(pir, apic->regs, max_irr);
411 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
413 static inline int apic_search_irr(struct kvm_lapic *apic)
415 return find_highest_vector(apic->regs + APIC_IRR);
418 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
423 * Note that irr_pending is just a hint. It will be always
424 * true with virtual interrupt delivery enabled.
426 if (!apic->irr_pending)
429 result = apic_search_irr(apic);
430 ASSERT(result == -1 || result >= 16);
435 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
437 struct kvm_vcpu *vcpu;
441 if (unlikely(vcpu->arch.apicv_active)) {
442 /* need to update RVI */
443 apic_clear_vector(vec, apic->regs + APIC_IRR);
444 kvm_x86_ops->hwapic_irr_update(vcpu,
445 apic_find_highest_irr(apic));
447 apic->irr_pending = false;
448 apic_clear_vector(vec, apic->regs + APIC_IRR);
449 if (apic_search_irr(apic) != -1)
450 apic->irr_pending = true;
454 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
456 struct kvm_vcpu *vcpu;
458 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
464 * With APIC virtualization enabled, all caching is disabled
465 * because the processor can modify ISR under the hood. Instead
468 if (unlikely(vcpu->arch.apicv_active))
469 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
472 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
474 * ISR (in service register) bit is set when injecting an interrupt.
475 * The highest vector is injected. Thus the latest bit set matches
476 * the highest bit in ISR.
478 apic->highest_isr_cache = vec;
482 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
487 * Note that isr_count is always 1, and highest_isr_cache
488 * is always -1, with APIC virtualization enabled.
490 if (!apic->isr_count)
492 if (likely(apic->highest_isr_cache != -1))
493 return apic->highest_isr_cache;
495 result = find_highest_vector(apic->regs + APIC_ISR);
496 ASSERT(result == -1 || result >= 16);
501 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
503 struct kvm_vcpu *vcpu;
504 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
510 * We do get here for APIC virtualization enabled if the guest
511 * uses the Hyper-V APIC enlightenment. In this case we may need
512 * to trigger a new interrupt delivery by writing the SVI field;
513 * on the other hand isr_count and highest_isr_cache are unused
514 * and must be left alone.
516 if (unlikely(vcpu->arch.apicv_active))
517 kvm_x86_ops->hwapic_isr_update(vcpu,
518 apic_find_highest_isr(apic));
521 BUG_ON(apic->isr_count < 0);
522 apic->highest_isr_cache = -1;
526 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
528 /* This may race with setting of irr in __apic_accept_irq() and
529 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
530 * will cause vmexit immediately and the value will be recalculated
531 * on the next vmentry.
533 return apic_find_highest_irr(vcpu->arch.apic);
535 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
537 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
538 int vector, int level, int trig_mode,
539 struct dest_map *dest_map);
541 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
542 struct dest_map *dest_map)
544 struct kvm_lapic *apic = vcpu->arch.apic;
546 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
547 irq->level, irq->trig_mode, dest_map);
550 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
553 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
557 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
560 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
564 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
566 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
569 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
572 if (pv_eoi_get_user(vcpu, &val) < 0)
573 apic_debug("Can't read EOI MSR value: 0x%llx\n",
574 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
578 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
580 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
581 apic_debug("Can't set EOI MSR value: 0x%llx\n",
582 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
585 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
588 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
590 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
591 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
592 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
595 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
598 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
601 if (apic->vcpu->arch.apicv_active)
602 highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
604 highest_irr = apic_find_highest_irr(apic);
605 if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
610 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
612 u32 tpr, isrv, ppr, old_ppr;
615 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
616 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
617 isr = apic_find_highest_isr(apic);
618 isrv = (isr != -1) ? isr : 0;
620 if ((tpr & 0xf0) >= (isrv & 0xf0))
625 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
626 apic, ppr, isr, isrv);
630 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
632 return ppr < old_ppr;
635 static void apic_update_ppr(struct kvm_lapic *apic)
639 if (__apic_update_ppr(apic, &ppr) &&
640 apic_has_interrupt_for_ppr(apic, ppr) != -1)
641 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
644 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
646 apic_update_ppr(vcpu->arch.apic);
648 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
650 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
652 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
653 apic_update_ppr(apic);
656 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
658 return mda == (apic_x2apic_mode(apic) ?
659 X2APIC_BROADCAST : APIC_BROADCAST);
662 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
664 if (kvm_apic_broadcast(apic, mda))
667 if (apic_x2apic_mode(apic))
668 return mda == kvm_x2apic_id(apic);
671 * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
672 * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and
673 * this allows unique addressing of VCPUs with APIC ID over 0xff.
674 * The 0xff condition is needed because writeable xAPIC ID.
676 if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
679 return mda == kvm_xapic_id(apic);
682 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
686 if (kvm_apic_broadcast(apic, mda))
689 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
691 if (apic_x2apic_mode(apic))
692 return ((logical_id >> 16) == (mda >> 16))
693 && (logical_id & mda & 0xffff) != 0;
695 logical_id = GET_APIC_LOGICAL_ID(logical_id);
697 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
699 return (logical_id & mda) != 0;
700 case APIC_DFR_CLUSTER:
701 return ((logical_id >> 4) == (mda >> 4))
702 && (logical_id & mda & 0xf) != 0;
704 apic_debug("Bad DFR vcpu %d: %08x\n",
705 apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
710 /* The KVM local APIC implementation has two quirks:
712 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
713 * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
714 * KVM doesn't do that aliasing.
716 * - in-kernel IOAPIC messages have to be delivered directly to
717 * x2APIC, because the kernel does not support interrupt remapping.
718 * In order to support broadcast without interrupt remapping, x2APIC
719 * rewrites the destination of non-IPI messages from APIC_BROADCAST
720 * to X2APIC_BROADCAST.
722 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
723 * important when userspace wants to use x2APIC-format MSIs, because
724 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
726 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
727 struct kvm_lapic *source, struct kvm_lapic *target)
729 bool ipi = source != NULL;
731 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
732 !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
733 return X2APIC_BROADCAST;
738 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
739 int short_hand, unsigned int dest, int dest_mode)
741 struct kvm_lapic *target = vcpu->arch.apic;
742 u32 mda = kvm_apic_mda(vcpu, dest, source, target);
744 apic_debug("target %p, source %p, dest 0x%x, "
745 "dest_mode 0x%x, short_hand 0x%x\n",
746 target, source, dest, dest_mode, short_hand);
749 switch (short_hand) {
750 case APIC_DEST_NOSHORT:
751 if (dest_mode == APIC_DEST_PHYSICAL)
752 return kvm_apic_match_physical_addr(target, mda);
754 return kvm_apic_match_logical_addr(target, mda);
756 return target == source;
757 case APIC_DEST_ALLINC:
759 case APIC_DEST_ALLBUT:
760 return target != source;
762 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
767 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
769 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
770 const unsigned long *bitmap, u32 bitmap_size)
775 mod = vector % dest_vcpus;
777 for (i = 0; i <= mod; i++) {
778 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
779 BUG_ON(idx == bitmap_size);
785 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
787 if (!kvm->arch.disabled_lapic_found) {
788 kvm->arch.disabled_lapic_found = true;
790 "Disabled LAPIC found during irq injection\n");
794 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
795 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
797 if (kvm->arch.x2apic_broadcast_quirk_disabled) {
798 if ((irq->dest_id == APIC_BROADCAST &&
799 map->mode != KVM_APIC_MODE_X2APIC))
801 if (irq->dest_id == X2APIC_BROADCAST)
804 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
805 if (irq->dest_id == (x2apic_ipi ?
806 X2APIC_BROADCAST : APIC_BROADCAST))
813 /* Return true if the interrupt can be handled by using *bitmap as index mask
814 * for valid destinations in *dst array.
815 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
816 * Note: we may have zero kvm_lapic destinations when we return true, which
817 * means that the interrupt should be dropped. In this case, *bitmap would be
818 * zero and *dst undefined.
820 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
821 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
822 struct kvm_apic_map *map, struct kvm_lapic ***dst,
823 unsigned long *bitmap)
827 if (irq->shorthand == APIC_DEST_SELF && src) {
831 } else if (irq->shorthand)
834 if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
837 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
838 if (irq->dest_id > map->max_apic_id) {
841 *dst = &map->phys_map[irq->dest_id];
848 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
852 if (!kvm_lowest_prio_delivery(irq))
855 if (!kvm_vector_hashing_enabled()) {
857 for_each_set_bit(i, bitmap, 16) {
862 else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
863 (*dst)[lowest]->vcpu) < 0)
870 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
873 if (!(*dst)[lowest]) {
874 kvm_apic_disabled_lapic_found(kvm);
880 *bitmap = (lowest >= 0) ? 1 << lowest : 0;
885 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
886 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
888 struct kvm_apic_map *map;
889 unsigned long bitmap;
890 struct kvm_lapic **dst = NULL;
896 if (irq->shorthand == APIC_DEST_SELF) {
897 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
902 map = rcu_dereference(kvm->arch.apic_map);
904 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
906 for_each_set_bit(i, &bitmap, 16) {
911 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
919 * This routine tries to handler interrupts in posted mode, here is how
920 * it deals with different cases:
921 * - For single-destination interrupts, handle it in posted mode
922 * - Else if vector hashing is enabled and it is a lowest-priority
923 * interrupt, handle it in posted mode and use the following mechanism
924 * to find the destinaiton vCPU.
925 * 1. For lowest-priority interrupts, store all the possible
926 * destination vCPUs in an array.
927 * 2. Use "guest vector % max number of destination vCPUs" to find
928 * the right destination vCPU in the array for the lowest-priority
930 * - Otherwise, use remapped mode to inject the interrupt.
932 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
933 struct kvm_vcpu **dest_vcpu)
935 struct kvm_apic_map *map;
936 unsigned long bitmap;
937 struct kvm_lapic **dst = NULL;
944 map = rcu_dereference(kvm->arch.apic_map);
946 if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
947 hweight16(bitmap) == 1) {
948 unsigned long i = find_first_bit(&bitmap, 16);
951 *dest_vcpu = dst[i]->vcpu;
961 * Add a pending IRQ into lapic.
962 * Return 1 if successfully added and 0 if discarded.
964 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
965 int vector, int level, int trig_mode,
966 struct dest_map *dest_map)
969 struct kvm_vcpu *vcpu = apic->vcpu;
971 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
973 switch (delivery_mode) {
975 vcpu->arch.apic_arb_prio++;
977 if (unlikely(trig_mode && !level))
980 /* FIXME add logic for vcpu on reset */
981 if (unlikely(!apic_enabled(apic)))
987 __set_bit(vcpu->vcpu_id, dest_map->map);
988 dest_map->vectors[vcpu->vcpu_id] = vector;
991 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
993 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
995 apic_clear_vector(vector, apic->regs + APIC_TMR);
998 if (vcpu->arch.apicv_active)
999 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
1001 kvm_lapic_set_irr(vector, apic);
1003 kvm_make_request(KVM_REQ_EVENT, vcpu);
1004 kvm_vcpu_kick(vcpu);
1010 vcpu->arch.pv.pv_unhalted = 1;
1011 kvm_make_request(KVM_REQ_EVENT, vcpu);
1012 kvm_vcpu_kick(vcpu);
1017 kvm_make_request(KVM_REQ_SMI, vcpu);
1018 kvm_vcpu_kick(vcpu);
1023 kvm_inject_nmi(vcpu);
1024 kvm_vcpu_kick(vcpu);
1028 if (!trig_mode || level) {
1030 /* assumes that there are only KVM_APIC_INIT/SIPI */
1031 apic->pending_events = (1UL << KVM_APIC_INIT);
1032 /* make sure pending_events is visible before sending
1035 kvm_make_request(KVM_REQ_EVENT, vcpu);
1036 kvm_vcpu_kick(vcpu);
1038 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
1043 case APIC_DM_STARTUP:
1044 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
1045 vcpu->vcpu_id, vector);
1047 apic->sipi_vector = vector;
1048 /* make sure sipi_vector is visible for the receiver */
1050 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1051 kvm_make_request(KVM_REQ_EVENT, vcpu);
1052 kvm_vcpu_kick(vcpu);
1055 case APIC_DM_EXTINT:
1057 * Should only be called by kvm_apic_local_deliver() with LVT0,
1058 * before NMI watchdog was enabled. Already handled by
1059 * kvm_apic_accept_pic_intr().
1064 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1071 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1073 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1076 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1078 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1081 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1085 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1086 if (!kvm_ioapic_handles_vector(apic, vector))
1089 /* Request a KVM exit to inform the userspace IOAPIC. */
1090 if (irqchip_split(apic->vcpu->kvm)) {
1091 apic->vcpu->arch.pending_ioapic_eoi = vector;
1092 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1096 if (apic_test_vector(vector, apic->regs + APIC_TMR))
1097 trigger_mode = IOAPIC_LEVEL_TRIG;
1099 trigger_mode = IOAPIC_EDGE_TRIG;
1101 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1104 static int apic_set_eoi(struct kvm_lapic *apic)
1106 int vector = apic_find_highest_isr(apic);
1108 trace_kvm_eoi(apic, vector);
1111 * Not every write EOI will has corresponding ISR,
1112 * one example is when Kernel check timer on setup_IO_APIC
1117 apic_clear_isr(vector, apic);
1118 apic_update_ppr(apic);
1120 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1121 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1123 kvm_ioapic_send_eoi(apic, vector);
1124 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1129 * this interface assumes a trap-like exit, which has already finished
1130 * desired side effect including vISR and vPPR update.
1132 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1134 struct kvm_lapic *apic = vcpu->arch.apic;
1136 trace_kvm_eoi(apic, vector);
1138 kvm_ioapic_send_eoi(apic, vector);
1139 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1141 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1143 static void apic_send_ipi(struct kvm_lapic *apic)
1145 u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1146 u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
1147 struct kvm_lapic_irq irq;
1149 irq.vector = icr_low & APIC_VECTOR_MASK;
1150 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1151 irq.dest_mode = icr_low & APIC_DEST_MASK;
1152 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1153 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1154 irq.shorthand = icr_low & APIC_SHORT_MASK;
1155 irq.msi_redir_hint = false;
1156 if (apic_x2apic_mode(apic))
1157 irq.dest_id = icr_high;
1159 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1161 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1163 apic_debug("icr_high 0x%x, icr_low 0x%x, "
1164 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1165 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1166 "msi_redir_hint 0x%x\n",
1167 icr_high, icr_low, irq.shorthand, irq.dest_id,
1168 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1169 irq.vector, irq.msi_redir_hint);
1171 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1174 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1176 ktime_t remaining, now;
1180 ASSERT(apic != NULL);
1182 /* if initial count is 0, current count should also be 0 */
1183 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1184 apic->lapic_timer.period == 0)
1188 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1189 if (ktime_to_ns(remaining) < 0)
1192 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1193 tmcct = div64_u64(ns,
1194 (APIC_BUS_CYCLE_NS * apic->divide_count));
1199 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1201 struct kvm_vcpu *vcpu = apic->vcpu;
1202 struct kvm_run *run = vcpu->run;
1204 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1205 run->tpr_access.rip = kvm_rip_read(vcpu);
1206 run->tpr_access.is_write = write;
1209 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1211 if (apic->vcpu->arch.tpr_access_reporting)
1212 __report_tpr_access(apic, write);
1215 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1219 if (offset >= LAPIC_MMIO_LENGTH)
1224 apic_debug("Access APIC ARBPRI register which is for P6\n");
1227 case APIC_TMCCT: /* Timer CCR */
1228 if (apic_lvtt_tscdeadline(apic))
1231 val = apic_get_tmcct(apic);
1234 apic_update_ppr(apic);
1235 val = kvm_lapic_get_reg(apic, offset);
1238 report_tpr_access(apic, false);
1241 val = kvm_lapic_get_reg(apic, offset);
1248 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1250 return container_of(dev, struct kvm_lapic, dev);
1253 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1256 unsigned char alignment = offset & 0xf;
1258 /* this bitmask has a bit cleared for each reserved register */
1259 static const u64 rmask = 0x43ff01ffffffe70cULL;
1261 if ((alignment + len) > 4) {
1262 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1267 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1268 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1273 result = __apic_read(apic, offset & ~0xf);
1275 trace_kvm_apic_read(offset, result);
1281 memcpy(data, (char *)&result + alignment, len);
1284 printk(KERN_ERR "Local APIC read with len = %x, "
1285 "should be 1,2, or 4 instead\n", len);
1290 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1292 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1294 return kvm_apic_hw_enabled(apic) &&
1295 addr >= apic->base_address &&
1296 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1299 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1300 gpa_t address, int len, void *data)
1302 struct kvm_lapic *apic = to_lapic(this);
1303 u32 offset = address - apic->base_address;
1305 if (!apic_mmio_in_range(apic, address))
1308 kvm_lapic_reg_read(apic, offset, len, data);
1313 static void update_divide_count(struct kvm_lapic *apic)
1315 u32 tmp1, tmp2, tdcr;
1317 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1319 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1320 apic->divide_count = 0x1 << (tmp2 & 0x7);
1322 apic_debug("timer divide count is 0x%x\n",
1323 apic->divide_count);
1326 static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1329 * Do not allow the guest to program periodic timers with small
1330 * interval, since the hrtimers are not throttled by the host
1333 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1334 s64 min_period = min_timer_period_us * 1000LL;
1336 if (apic->lapic_timer.period < min_period) {
1337 pr_info_ratelimited(
1338 "kvm: vcpu %i: requested %lld ns "
1339 "lapic timer period limited to %lld ns\n",
1340 apic->vcpu->vcpu_id,
1341 apic->lapic_timer.period, min_period);
1342 apic->lapic_timer.period = min_period;
1347 static void apic_update_lvtt(struct kvm_lapic *apic)
1349 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1350 apic->lapic_timer.timer_mode_mask;
1352 if (apic->lapic_timer.timer_mode != timer_mode) {
1353 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1354 APIC_LVT_TIMER_TSCDEADLINE)) {
1355 hrtimer_cancel(&apic->lapic_timer.timer);
1356 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1357 apic->lapic_timer.period = 0;
1358 apic->lapic_timer.tscdeadline = 0;
1360 apic->lapic_timer.timer_mode = timer_mode;
1361 limit_periodic_timer_frequency(apic);
1365 static void apic_timer_expired(struct kvm_lapic *apic)
1367 struct kvm_vcpu *vcpu = apic->vcpu;
1368 struct swait_queue_head *q = &vcpu->wq;
1369 struct kvm_timer *ktimer = &apic->lapic_timer;
1371 if (atomic_read(&apic->lapic_timer.pending))
1374 atomic_inc(&apic->lapic_timer.pending);
1375 kvm_set_pending_timer(vcpu);
1378 * For x86, the atomic_inc() is serialized, thus
1379 * using swait_active() is safe.
1381 if (swait_active(q))
1384 if (apic_lvtt_tscdeadline(apic))
1385 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1389 * On APICv, this test will cause a busy wait
1390 * during a higher-priority task.
1393 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1395 struct kvm_lapic *apic = vcpu->arch.apic;
1396 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1398 if (kvm_apic_hw_enabled(apic)) {
1399 int vec = reg & APIC_VECTOR_MASK;
1400 void *bitmap = apic->regs + APIC_ISR;
1402 if (vcpu->arch.apicv_active)
1403 bitmap = apic->regs + APIC_IRR;
1405 if (apic_test_vector(vec, bitmap))
1411 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1413 struct kvm_lapic *apic = vcpu->arch.apic;
1414 u64 guest_tsc, tsc_deadline;
1416 if (!lapic_in_kernel(vcpu))
1419 if (apic->lapic_timer.expired_tscdeadline == 0)
1422 if (!lapic_timer_int_injected(vcpu))
1425 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1426 apic->lapic_timer.expired_tscdeadline = 0;
1427 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1428 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1430 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1431 if (guest_tsc < tsc_deadline)
1432 __delay(min(tsc_deadline - guest_tsc,
1433 nsec_to_cycles(vcpu, lapic_timer_advance_ns)));
1436 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1438 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1441 struct kvm_vcpu *vcpu = apic->vcpu;
1442 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1443 unsigned long flags;
1446 if (unlikely(!tscdeadline || !this_tsc_khz))
1449 local_irq_save(flags);
1452 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1453 if (likely(tscdeadline > guest_tsc)) {
1454 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1455 do_div(ns, this_tsc_khz);
1456 expire = ktime_add_ns(now, ns);
1457 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1458 hrtimer_start(&apic->lapic_timer.timer,
1459 expire, HRTIMER_MODE_ABS_PINNED);
1461 apic_timer_expired(apic);
1463 local_irq_restore(flags);
1466 static void start_sw_period(struct kvm_lapic *apic)
1468 if (!apic->lapic_timer.period)
1471 if (apic_lvtt_oneshot(apic) &&
1472 ktime_after(ktime_get(),
1473 apic->lapic_timer.target_expiration)) {
1474 apic_timer_expired(apic);
1478 hrtimer_start(&apic->lapic_timer.timer,
1479 apic->lapic_timer.target_expiration,
1480 HRTIMER_MODE_ABS_PINNED);
1483 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1485 ktime_t now, remaining;
1486 u64 ns_remaining_old, ns_remaining_new;
1488 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1489 * APIC_BUS_CYCLE_NS * apic->divide_count;
1490 limit_periodic_timer_frequency(apic);
1493 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1494 if (ktime_to_ns(remaining) < 0)
1497 ns_remaining_old = ktime_to_ns(remaining);
1498 ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1499 apic->divide_count, old_divisor);
1501 apic->lapic_timer.tscdeadline +=
1502 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1503 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1504 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1507 static bool set_target_expiration(struct kvm_lapic *apic)
1513 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1514 * APIC_BUS_CYCLE_NS * apic->divide_count;
1516 if (!apic->lapic_timer.period) {
1517 apic->lapic_timer.tscdeadline = 0;
1521 limit_periodic_timer_frequency(apic);
1523 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1525 "timer initial count 0x%x, period %lldns, "
1526 "expire @ 0x%016" PRIx64 ".\n", __func__,
1527 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1528 kvm_lapic_get_reg(apic, APIC_TMICT),
1529 apic->lapic_timer.period,
1530 ktime_to_ns(ktime_add_ns(now,
1531 apic->lapic_timer.period)));
1533 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1534 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1535 apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1540 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1542 apic->lapic_timer.tscdeadline +=
1543 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1544 apic->lapic_timer.target_expiration =
1545 ktime_add_ns(apic->lapic_timer.target_expiration,
1546 apic->lapic_timer.period);
1549 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1551 if (!lapic_in_kernel(vcpu))
1554 return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1556 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1558 static void cancel_hv_timer(struct kvm_lapic *apic)
1560 WARN_ON(preemptible());
1561 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1562 kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1563 apic->lapic_timer.hv_timer_in_use = false;
1566 static bool start_hv_timer(struct kvm_lapic *apic)
1568 struct kvm_timer *ktimer = &apic->lapic_timer;
1571 WARN_ON(preemptible());
1572 if (!kvm_x86_ops->set_hv_timer)
1575 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1578 if (!ktimer->tscdeadline)
1581 r = kvm_x86_ops->set_hv_timer(apic->vcpu, ktimer->tscdeadline);
1585 ktimer->hv_timer_in_use = true;
1586 hrtimer_cancel(&ktimer->timer);
1589 * Also recheck ktimer->pending, in case the sw timer triggered in
1590 * the window. For periodic timer, leave the hv timer running for
1591 * simplicity, and the deadline will be recomputed on the next vmexit.
1593 if (!apic_lvtt_period(apic) && (r || atomic_read(&ktimer->pending))) {
1595 apic_timer_expired(apic);
1599 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, true);
1603 static void start_sw_timer(struct kvm_lapic *apic)
1605 struct kvm_timer *ktimer = &apic->lapic_timer;
1607 WARN_ON(preemptible());
1608 if (apic->lapic_timer.hv_timer_in_use)
1609 cancel_hv_timer(apic);
1610 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1613 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1614 start_sw_period(apic);
1615 else if (apic_lvtt_tscdeadline(apic))
1616 start_sw_tscdeadline(apic);
1617 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1620 static void restart_apic_timer(struct kvm_lapic *apic)
1623 if (!start_hv_timer(apic))
1624 start_sw_timer(apic);
1628 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1630 struct kvm_lapic *apic = vcpu->arch.apic;
1633 /* If the preempt notifier has already run, it also called apic_timer_expired */
1634 if (!apic->lapic_timer.hv_timer_in_use)
1636 WARN_ON(swait_active(&vcpu->wq));
1637 cancel_hv_timer(apic);
1638 apic_timer_expired(apic);
1640 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1641 advance_periodic_target_expiration(apic);
1642 restart_apic_timer(apic);
1647 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1649 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1651 restart_apic_timer(vcpu->arch.apic);
1653 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1655 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1657 struct kvm_lapic *apic = vcpu->arch.apic;
1660 /* Possibly the TSC deadline timer is not enabled yet */
1661 if (apic->lapic_timer.hv_timer_in_use)
1662 start_sw_timer(apic);
1665 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1667 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1669 struct kvm_lapic *apic = vcpu->arch.apic;
1671 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1672 restart_apic_timer(apic);
1675 static void start_apic_timer(struct kvm_lapic *apic)
1677 atomic_set(&apic->lapic_timer.pending, 0);
1679 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1680 && !set_target_expiration(apic))
1683 restart_apic_timer(apic);
1686 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1688 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1690 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1691 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1692 if (lvt0_in_nmi_mode) {
1693 apic_debug("Receive NMI setting on APIC_LVT0 "
1694 "for cpu %d\n", apic->vcpu->vcpu_id);
1695 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1697 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1701 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1705 trace_kvm_apic_write(reg, val);
1708 case APIC_ID: /* Local APIC ID */
1709 if (!apic_x2apic_mode(apic))
1710 kvm_apic_set_xapic_id(apic, val >> 24);
1716 report_tpr_access(apic, true);
1717 apic_set_tpr(apic, val & 0xff);
1725 if (!apic_x2apic_mode(apic))
1726 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1732 if (!apic_x2apic_mode(apic)) {
1733 kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1734 recalculate_apic_map(apic->vcpu->kvm);
1741 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1742 mask |= APIC_SPIV_DIRECTED_EOI;
1743 apic_set_spiv(apic, val & mask);
1744 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1748 for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1749 lvt_val = kvm_lapic_get_reg(apic,
1750 APIC_LVTT + 0x10 * i);
1751 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1752 lvt_val | APIC_LVT_MASKED);
1754 apic_update_lvtt(apic);
1755 atomic_set(&apic->lapic_timer.pending, 0);
1761 /* No delay here, so we always clear the pending bit */
1762 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1763 apic_send_ipi(apic);
1767 if (!apic_x2apic_mode(apic))
1769 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1773 apic_manage_nmi_watchdog(apic, val);
1778 /* TODO: Check vector */
1779 if (!kvm_apic_sw_enabled(apic))
1780 val |= APIC_LVT_MASKED;
1782 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1783 kvm_lapic_set_reg(apic, reg, val);
1788 if (!kvm_apic_sw_enabled(apic))
1789 val |= APIC_LVT_MASKED;
1790 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1791 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1792 apic_update_lvtt(apic);
1796 if (apic_lvtt_tscdeadline(apic))
1799 hrtimer_cancel(&apic->lapic_timer.timer);
1800 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1801 start_apic_timer(apic);
1805 uint32_t old_divisor = apic->divide_count;
1808 apic_debug("KVM_WRITE:TDCR %x\n", val);
1809 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1810 update_divide_count(apic);
1811 if (apic->divide_count != old_divisor &&
1812 apic->lapic_timer.period) {
1813 hrtimer_cancel(&apic->lapic_timer.timer);
1814 update_target_expiration(apic, old_divisor);
1815 restart_apic_timer(apic);
1820 if (apic_x2apic_mode(apic) && val != 0) {
1821 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1827 if (apic_x2apic_mode(apic)) {
1828 kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1837 apic_debug("Local APIC Write to read-only register %x\n", reg);
1840 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
1842 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1843 gpa_t address, int len, const void *data)
1845 struct kvm_lapic *apic = to_lapic(this);
1846 unsigned int offset = address - apic->base_address;
1849 if (!apic_mmio_in_range(apic, address))
1853 * APIC register must be aligned on 128-bits boundary.
1854 * 32/64/128 bits registers must be accessed thru 32 bits.
1857 if (len != 4 || (offset & 0xf)) {
1858 /* Don't shout loud, $infamous_os would cause only noise. */
1859 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1865 /* too common printing */
1866 if (offset != APIC_EOI)
1867 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1868 "0x%x\n", __func__, offset, len, val);
1870 kvm_lapic_reg_write(apic, offset & 0xff0, val);
1875 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1877 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1879 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1881 /* emulate APIC access in a trap manner */
1882 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1886 /* hw has done the conditional check and inst decode */
1889 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
1891 /* TODO: optimize to just emulate side effect w/o one more write */
1892 kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
1894 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1896 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1898 struct kvm_lapic *apic = vcpu->arch.apic;
1900 if (!vcpu->arch.apic)
1903 hrtimer_cancel(&apic->lapic_timer.timer);
1905 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1906 static_key_slow_dec_deferred(&apic_hw_disabled);
1908 if (!apic->sw_enabled)
1909 static_key_slow_dec_deferred(&apic_sw_disabled);
1912 free_page((unsigned long)apic->regs);
1918 *----------------------------------------------------------------------
1920 *----------------------------------------------------------------------
1922 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1924 struct kvm_lapic *apic = vcpu->arch.apic;
1926 if (!lapic_in_kernel(vcpu) ||
1927 !apic_lvtt_tscdeadline(apic))
1930 return apic->lapic_timer.tscdeadline;
1933 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1935 struct kvm_lapic *apic = vcpu->arch.apic;
1937 if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
1938 apic_lvtt_period(apic))
1941 hrtimer_cancel(&apic->lapic_timer.timer);
1942 apic->lapic_timer.tscdeadline = data;
1943 start_apic_timer(apic);
1946 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1948 struct kvm_lapic *apic = vcpu->arch.apic;
1950 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1951 | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
1954 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1958 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1960 return (tpr & 0xf0) >> 4;
1963 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1965 u64 old_value = vcpu->arch.apic_base;
1966 struct kvm_lapic *apic = vcpu->arch.apic;
1969 value |= MSR_IA32_APICBASE_BSP;
1971 vcpu->arch.apic_base = value;
1973 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
1974 kvm_update_cpuid(vcpu);
1979 /* update jump label if enable bit changes */
1980 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1981 if (value & MSR_IA32_APICBASE_ENABLE) {
1982 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
1983 static_key_slow_dec_deferred(&apic_hw_disabled);
1985 static_key_slow_inc(&apic_hw_disabled.key);
1986 recalculate_apic_map(vcpu->kvm);
1990 if ((old_value ^ value) & X2APIC_ENABLE) {
1991 if (value & X2APIC_ENABLE) {
1992 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
1993 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1995 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1998 apic->base_address = apic->vcpu->arch.apic_base &
1999 MSR_IA32_APICBASE_BASE;
2001 if ((value & MSR_IA32_APICBASE_ENABLE) &&
2002 apic->base_address != APIC_DEFAULT_PHYS_BASE)
2003 pr_warn_once("APIC base relocation is unsupported by KVM");
2005 /* with FSB delivery interrupt, we can restart APIC functionality */
2006 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
2007 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
2011 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
2013 struct kvm_lapic *apic = vcpu->arch.apic;
2019 apic_debug("%s\n", __func__);
2021 /* Stop the timer in case it's a reset to an active apic */
2022 hrtimer_cancel(&apic->lapic_timer.timer);
2025 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
2026 MSR_IA32_APICBASE_ENABLE);
2027 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2029 kvm_apic_set_version(apic->vcpu);
2031 for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2032 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
2033 apic_update_lvtt(apic);
2034 if (kvm_vcpu_is_reset_bsp(vcpu) &&
2035 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
2036 kvm_lapic_set_reg(apic, APIC_LVT0,
2037 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
2038 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2040 kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
2041 apic_set_spiv(apic, 0xff);
2042 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
2043 if (!apic_x2apic_mode(apic))
2044 kvm_apic_set_ldr(apic, 0);
2045 kvm_lapic_set_reg(apic, APIC_ESR, 0);
2046 kvm_lapic_set_reg(apic, APIC_ICR, 0);
2047 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2048 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2049 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
2050 for (i = 0; i < 8; i++) {
2051 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2052 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2053 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
2055 apic->irr_pending = vcpu->arch.apicv_active;
2056 apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
2057 apic->highest_isr_cache = -1;
2058 update_divide_count(apic);
2059 atomic_set(&apic->lapic_timer.pending, 0);
2060 if (kvm_vcpu_is_bsp(vcpu))
2061 kvm_lapic_set_base(vcpu,
2062 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
2063 vcpu->arch.pv_eoi.msr_val = 0;
2064 apic_update_ppr(apic);
2065 if (vcpu->arch.apicv_active) {
2066 kvm_x86_ops->apicv_post_state_restore(vcpu);
2067 kvm_x86_ops->hwapic_irr_update(vcpu, -1);
2068 kvm_x86_ops->hwapic_isr_update(vcpu, -1);
2071 vcpu->arch.apic_arb_prio = 0;
2072 vcpu->arch.apic_attention = 0;
2074 apic_debug("%s: vcpu=%p, id=0x%x, base_msr="
2075 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
2076 vcpu, kvm_lapic_get_reg(apic, APIC_ID),
2077 vcpu->arch.apic_base, apic->base_address);
2081 *----------------------------------------------------------------------
2083 *----------------------------------------------------------------------
2086 static bool lapic_is_periodic(struct kvm_lapic *apic)
2088 return apic_lvtt_period(apic);
2091 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2093 struct kvm_lapic *apic = vcpu->arch.apic;
2095 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
2096 return atomic_read(&apic->lapic_timer.pending);
2101 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
2103 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
2104 int vector, mode, trig_mode;
2106 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2107 vector = reg & APIC_VECTOR_MASK;
2108 mode = reg & APIC_MODE_MASK;
2109 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
2110 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2116 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2118 struct kvm_lapic *apic = vcpu->arch.apic;
2121 kvm_apic_local_deliver(apic, APIC_LVT0);
2124 static const struct kvm_io_device_ops apic_mmio_ops = {
2125 .read = apic_mmio_read,
2126 .write = apic_mmio_write,
2129 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2131 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2132 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2134 apic_timer_expired(apic);
2136 if (lapic_is_periodic(apic)) {
2137 advance_periodic_target_expiration(apic);
2138 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2139 return HRTIMER_RESTART;
2141 return HRTIMER_NORESTART;
2144 int kvm_create_lapic(struct kvm_vcpu *vcpu)
2146 struct kvm_lapic *apic;
2148 ASSERT(vcpu != NULL);
2149 apic_debug("apic_init %d\n", vcpu->vcpu_id);
2151 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
2155 vcpu->arch.apic = apic;
2157 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
2159 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2161 goto nomem_free_apic;
2165 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2166 HRTIMER_MODE_ABS_PINNED);
2167 apic->lapic_timer.timer.function = apic_timer_fn;
2170 * APIC is created enabled. This will prevent kvm_lapic_set_base from
2171 * thinking that APIC satet has changed.
2173 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2174 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2175 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2184 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2186 struct kvm_lapic *apic = vcpu->arch.apic;
2189 if (!apic_enabled(apic))
2192 __apic_update_ppr(apic, &ppr);
2193 return apic_has_interrupt_for_ppr(apic, ppr);
2196 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2198 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2201 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2203 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2204 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2209 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2211 struct kvm_lapic *apic = vcpu->arch.apic;
2213 if (atomic_read(&apic->lapic_timer.pending) > 0) {
2214 kvm_apic_local_deliver(apic, APIC_LVTT);
2215 if (apic_lvtt_tscdeadline(apic))
2216 apic->lapic_timer.tscdeadline = 0;
2217 if (apic_lvtt_oneshot(apic)) {
2218 apic->lapic_timer.tscdeadline = 0;
2219 apic->lapic_timer.target_expiration = 0;
2221 atomic_set(&apic->lapic_timer.pending, 0);
2225 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2227 int vector = kvm_apic_has_interrupt(vcpu);
2228 struct kvm_lapic *apic = vcpu->arch.apic;
2235 * We get here even with APIC virtualization enabled, if doing
2236 * nested virtualization and L1 runs with the "acknowledge interrupt
2237 * on exit" mode. Then we cannot inject the interrupt via RVI,
2238 * because the process would deliver it through the IDT.
2241 apic_clear_irr(vector, apic);
2242 if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2244 * For auto-EOI interrupts, there might be another pending
2245 * interrupt above PPR, so check whether to raise another
2248 apic_update_ppr(apic);
2251 * For normal interrupts, PPR has been raised and there cannot
2252 * be a higher-priority pending interrupt---except if there was
2253 * a concurrent interrupt injection, but that would have
2254 * triggered KVM_REQ_EVENT already.
2256 apic_set_isr(vector, apic);
2257 __apic_update_ppr(apic, &ppr);
2263 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2264 struct kvm_lapic_state *s, bool set)
2266 if (apic_x2apic_mode(vcpu->arch.apic)) {
2267 u32 *id = (u32 *)(s->regs + APIC_ID);
2268 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
2270 if (vcpu->kvm->arch.x2apic_format) {
2271 if (*id != vcpu->vcpu_id)
2280 /* In x2APIC mode, the LDR is fixed and based on the id */
2282 *ldr = kvm_apic_calc_x2apic_ldr(*id);
2288 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2290 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2291 return kvm_apic_state_fixup(vcpu, s, false);
2294 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2296 struct kvm_lapic *apic = vcpu->arch.apic;
2300 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2301 /* set SPIV separately to get count of SW disabled APICs right */
2302 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2304 r = kvm_apic_state_fixup(vcpu, s, true);
2307 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2309 recalculate_apic_map(vcpu->kvm);
2310 kvm_apic_set_version(vcpu);
2312 apic_update_ppr(apic);
2313 hrtimer_cancel(&apic->lapic_timer.timer);
2314 apic_update_lvtt(apic);
2315 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2316 update_divide_count(apic);
2317 start_apic_timer(apic);
2318 apic->irr_pending = true;
2319 apic->isr_count = vcpu->arch.apicv_active ?
2320 1 : count_vectors(apic->regs + APIC_ISR);
2321 apic->highest_isr_cache = -1;
2322 if (vcpu->arch.apicv_active) {
2323 kvm_x86_ops->apicv_post_state_restore(vcpu);
2324 kvm_x86_ops->hwapic_irr_update(vcpu,
2325 apic_find_highest_irr(apic));
2326 kvm_x86_ops->hwapic_isr_update(vcpu,
2327 apic_find_highest_isr(apic));
2329 kvm_make_request(KVM_REQ_EVENT, vcpu);
2330 if (ioapic_in_kernel(vcpu->kvm))
2331 kvm_rtc_eoi_tracking_restore_one(vcpu);
2333 vcpu->arch.apic_arb_prio = 0;
2338 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2340 struct hrtimer *timer;
2342 if (!lapic_in_kernel(vcpu))
2345 timer = &vcpu->arch.apic->lapic_timer.timer;
2346 if (hrtimer_cancel(timer))
2347 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
2351 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2353 * Detect whether guest triggered PV EOI since the
2354 * last entry. If yes, set EOI on guests's behalf.
2355 * Clear PV EOI in guest memory in any case.
2357 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2358 struct kvm_lapic *apic)
2363 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2364 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2366 * KVM_APIC_PV_EOI_PENDING is unset:
2367 * -> host disabled PV EOI.
2368 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2369 * -> host enabled PV EOI, guest did not execute EOI yet.
2370 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2371 * -> host enabled PV EOI, guest executed EOI.
2373 BUG_ON(!pv_eoi_enabled(vcpu));
2374 pending = pv_eoi_get_pending(vcpu);
2376 * Clear pending bit in any case: it will be set again on vmentry.
2377 * While this might not be ideal from performance point of view,
2378 * this makes sure pv eoi is only enabled when we know it's safe.
2380 pv_eoi_clr_pending(vcpu);
2383 vector = apic_set_eoi(apic);
2384 trace_kvm_pv_eoi(apic, vector);
2387 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2391 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2392 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2394 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2397 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2401 apic_set_tpr(vcpu->arch.apic, data & 0xff);
2405 * apic_sync_pv_eoi_to_guest - called before vmentry
2407 * Detect whether it's safe to enable PV EOI and
2410 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2411 struct kvm_lapic *apic)
2413 if (!pv_eoi_enabled(vcpu) ||
2414 /* IRR set or many bits in ISR: could be nested. */
2415 apic->irr_pending ||
2416 /* Cache not set: could be safe but we don't bother. */
2417 apic->highest_isr_cache == -1 ||
2418 /* Need EOI to update ioapic. */
2419 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2421 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2422 * so we need not do anything here.
2427 pv_eoi_set_pending(apic->vcpu);
2430 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2433 int max_irr, max_isr;
2434 struct kvm_lapic *apic = vcpu->arch.apic;
2436 apic_sync_pv_eoi_to_guest(vcpu, apic);
2438 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2441 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2442 max_irr = apic_find_highest_irr(apic);
2445 max_isr = apic_find_highest_isr(apic);
2448 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2450 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2454 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2457 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2458 &vcpu->arch.apic->vapic_cache,
2459 vapic_addr, sizeof(u32)))
2461 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2463 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2466 vcpu->arch.apic->vapic_addr = vapic_addr;
2470 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2472 struct kvm_lapic *apic = vcpu->arch.apic;
2473 u32 reg = (msr - APIC_BASE_MSR) << 4;
2475 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2478 if (reg == APIC_ICR2)
2481 /* if this is ICR write vector before command */
2482 if (reg == APIC_ICR)
2483 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2484 return kvm_lapic_reg_write(apic, reg, (u32)data);
2487 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2489 struct kvm_lapic *apic = vcpu->arch.apic;
2490 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2492 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2495 if (reg == APIC_DFR || reg == APIC_ICR2) {
2496 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2501 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2503 if (reg == APIC_ICR)
2504 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2506 *data = (((u64)high) << 32) | low;
2511 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2513 struct kvm_lapic *apic = vcpu->arch.apic;
2515 if (!lapic_in_kernel(vcpu))
2518 /* if this is ICR write vector before command */
2519 if (reg == APIC_ICR)
2520 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2521 return kvm_lapic_reg_write(apic, reg, (u32)data);
2524 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2526 struct kvm_lapic *apic = vcpu->arch.apic;
2529 if (!lapic_in_kernel(vcpu))
2532 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2534 if (reg == APIC_ICR)
2535 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2537 *data = (((u64)high) << 32) | low;
2542 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2544 u64 addr = data & ~KVM_MSR_ENABLED;
2545 if (!IS_ALIGNED(addr, 4))
2548 vcpu->arch.pv_eoi.msr_val = data;
2549 if (!pv_eoi_enabled(vcpu))
2551 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2555 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2557 struct kvm_lapic *apic = vcpu->arch.apic;
2561 if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2565 * INITs are latched while in SMM. Because an SMM CPU cannot
2566 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2567 * and delay processing of INIT until the next RSM.
2570 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2571 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2572 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2576 pe = xchg(&apic->pending_events, 0);
2577 if (test_bit(KVM_APIC_INIT, &pe)) {
2578 kvm_vcpu_reset(vcpu, true);
2579 if (kvm_vcpu_is_bsp(apic->vcpu))
2580 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2582 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2584 if (test_bit(KVM_APIC_SIPI, &pe) &&
2585 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2586 /* evaluate pending_events before reading the vector */
2588 sipi_vector = apic->sipi_vector;
2589 apic_debug("vcpu %d received sipi with vector # %x\n",
2590 vcpu->vcpu_id, sipi_vector);
2591 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2592 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2596 void kvm_lapic_init(void)
2598 /* do not patch jump label more than once per second */
2599 jump_label_rate_limit(&apic_hw_disabled, HZ);
2600 jump_label_rate_limit(&apic_sw_disabled, HZ);
2603 void kvm_lapic_exit(void)
2605 static_key_deferred_flush(&apic_hw_disabled);
2606 static_key_deferred_flush(&apic_sw_disabled);