arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/export.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <asm/delay.h>
  37 #include <linux/atomic.h>
  38 #include <linux/jump_label.h>
  39 #include "kvm_cache_regs.h"
  40 #include "irq.h"
  41 #include "trace.h"
  42 #include "x86.h"
  43 #include "cpuid.h"
  44 #include "hyperv.h"
  45
  46 #ifndef CONFIG_X86_64
  47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  48 #else
  49 #define mod_64(x, y) ((x) % (y))
  50 #endif
  51
  52 #define PRId64 "d"
  53 #define PRIx64 "llx"
  54 #define PRIu64 "u"
  55 #define PRIo64 "o"
  56
  57 #define APIC_BUS_CYCLE_NS 1
  58
  59 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  60 #define apic_debug(fmt, arg...)
  61
  62 /* 14 is the version for Xeon and Pentium 8.4.8*/
  63 #define APIC_VERSION                    (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
  64 #define LAPIC_MMIO_LENGTH               (1 << 12)
  65 /* followed define is not in apicdef.h */
  66 #define APIC_SHORT_MASK                 0xc0000
  67 #define APIC_DEST_NOSHORT               0x0
  68 #define APIC_DEST_MASK                  0x800
  69 #define MAX_APIC_VECTOR                 256
  70 #define APIC_VECTORS_PER_REG            32
  71
  72 #define APIC_BROADCAST                  0xFF
  73 #define X2APIC_BROADCAST                0xFFFFFFFFul
  74
  75 static inline int apic_test_vector(int vec, void *bitmap)
  76 {
  77         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  78 }
  79
  80 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  81 {
  82         struct kvm_lapic *apic = vcpu->arch.apic;
  83
  84         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  85                 apic_test_vector(vector, apic->regs + APIC_IRR);
  86 }
  87
  88 static inline void apic_clear_vector(int vec, void *bitmap)
  89 {
  90         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  91 }
  92
  93 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
  94 {
  95         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  96 }
  97
  98 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
  99 {
 100         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 101 }
 102
 103 struct static_key_deferred apic_hw_disabled __read_mostly;
 104 struct static_key_deferred apic_sw_disabled __read_mostly;
 105
 106 static inline int apic_enabled(struct kvm_lapic *apic)
 107 {
 108         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 109 }
 110
 111 #define LVT_MASK        \
 112         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 113
 114 #define LINT_MASK       \
 115         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 116          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 117
 118 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
 119 {
 120         return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
 121 }
 122
 123 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
 124 {
 125         return apic->vcpu->vcpu_id;
 126 }
 127
 128 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
 129                 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
 130         switch (map->mode) {
 131         case KVM_APIC_MODE_X2APIC: {
 132                 u32 offset = (dest_id >> 16) * 16;
 133                 u32 max_apic_id = map->max_apic_id;
 134
 135                 if (offset <= max_apic_id) {
 136                         u8 cluster_size = min(max_apic_id - offset + 1, 16U);
 137
 138                         *cluster = &map->phys_map[offset];
 139                         *mask = dest_id & (0xffff >> (16 - cluster_size));
 140                 } else {
 141                         *mask = 0;
 142                 }
 143
 144                 return true;
 145                 }
 146         case KVM_APIC_MODE_XAPIC_FLAT:
 147                 *cluster = map->xapic_flat_map;
 148                 *mask = dest_id & 0xff;
 149                 return true;
 150         case KVM_APIC_MODE_XAPIC_CLUSTER:
 151                 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
 152                 *mask = dest_id & 0xf;
 153                 return true;
 154         default:
 155                 /* Not optimized. */
 156                 return false;
 157         }
 158 }
 159
 160 static void kvm_apic_map_free(struct rcu_head *rcu)
 161 {
 162         struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
 163
 164         kvfree(map);
 165 }
 166
 167 static void recalculate_apic_map(struct kvm *kvm)
 168 {
 169         struct kvm_apic_map *new, *old = NULL;
 170         struct kvm_vcpu *vcpu;
 171         int i;
 172         u32 max_id = 255; /* enough space for any xAPIC ID */
 173
 174         mutex_lock(&kvm->arch.apic_map_lock);
 175
 176         kvm_for_each_vcpu(i, vcpu, kvm)
 177                 if (kvm_apic_present(vcpu))
 178                         max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
 179
 180         new = kvzalloc(sizeof(struct kvm_apic_map) +
 181                            sizeof(struct kvm_lapic *) * ((u64)max_id + 1), GFP_KERNEL);
 182
 183         if (!new)
 184                 goto out;
 185
 186         new->max_apic_id = max_id;
 187
 188         kvm_for_each_vcpu(i, vcpu, kvm) {
 189                 struct kvm_lapic *apic = vcpu->arch.apic;
 190                 struct kvm_lapic **cluster;
 191                 u16 mask;
 192                 u32 ldr;
 193                 u8 xapic_id;
 194                 u32 x2apic_id;
 195
 196                 if (!kvm_apic_present(vcpu))
 197                         continue;
 198
 199                 xapic_id = kvm_xapic_id(apic);
 200                 x2apic_id = kvm_x2apic_id(apic);
 201
 202                 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
 203                 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
 204                                 x2apic_id <= new->max_apic_id)
 205                         new->phys_map[x2apic_id] = apic;
 206                 /*
 207                  * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
 208                  * prevent them from masking VCPUs with APIC ID <= 0xff.
 209                  */
 210                 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
 211                         new->phys_map[xapic_id] = apic;
 212
 213                 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
 214
 215                 if (apic_x2apic_mode(apic)) {
 216                         new->mode |= KVM_APIC_MODE_X2APIC;
 217                 } else if (ldr) {
 218                         ldr = GET_APIC_LOGICAL_ID(ldr);
 219                         if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
 220                                 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
 221                         else
 222                                 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
 223                 }
 224
 225                 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
 226                         continue;
 227
 228                 if (mask)
 229                         cluster[ffs(mask) - 1] = apic;
 230         }
 231 out:
 232         old = rcu_dereference_protected(kvm->arch.apic_map,
 233                         lockdep_is_held(&kvm->arch.apic_map_lock));
 234         rcu_assign_pointer(kvm->arch.apic_map, new);
 235         mutex_unlock(&kvm->arch.apic_map_lock);
 236
 237         if (old)
 238                 call_rcu(&old->rcu, kvm_apic_map_free);
 239
 240         kvm_make_scan_ioapic_request(kvm);
 241 }
 242
 243 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 244 {
 245         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 246
 247         kvm_lapic_set_reg(apic, APIC_SPIV, val);
 248
 249         if (enabled != apic->sw_enabled) {
 250                 apic->sw_enabled = enabled;
 251                 if (enabled) {
 252                         static_key_slow_dec_deferred(&apic_sw_disabled);
 253                         recalculate_apic_map(apic->vcpu->kvm);
 254                 } else
 255                         static_key_slow_inc(&apic_sw_disabled.key);
 256         }
 257 }
 258
 259 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
 260 {
 261         kvm_lapic_set_reg(apic, APIC_ID, id << 24);
 262         recalculate_apic_map(apic->vcpu->kvm);
 263 }
 264
 265 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 266 {
 267         kvm_lapic_set_reg(apic, APIC_LDR, id);
 268         recalculate_apic_map(apic->vcpu->kvm);
 269 }
 270
 271 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
 272 {
 273         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
 274
 275         WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
 276
 277         kvm_lapic_set_reg(apic, APIC_ID, id);
 278         kvm_lapic_set_reg(apic, APIC_LDR, ldr);
 279         recalculate_apic_map(apic->vcpu->kvm);
 280 }
 281
 282 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 283 {
 284         return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 285 }
 286
 287 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 288 {
 289         return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 290 }
 291
 292 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 293 {
 294         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 295 }
 296
 297 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 298 {
 299         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 300 }
 301
 302 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 303 {
 304         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 305 }
 306
 307 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 308 {
 309         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 310 }
 311
 312 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 313 {
 314         struct kvm_lapic *apic = vcpu->arch.apic;
 315         struct kvm_cpuid_entry2 *feat;
 316         u32 v = APIC_VERSION;
 317
 318         if (!lapic_in_kernel(vcpu))
 319                 return;
 320
 321         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 322         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 323                 v |= APIC_LVR_DIRECTED_EOI;
 324         kvm_lapic_set_reg(apic, APIC_LVR, v);
 325 }
 326
 327 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
 328         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 329         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 330         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 331         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 332         LVT_MASK                /* LVTERR */
 333 };
 334
 335 static int find_highest_vector(void *bitmap)
 336 {
 337         int vec;
 338         u32 *reg;
 339
 340         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 341              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 342                 reg = bitmap + REG_POS(vec);
 343                 if (*reg)
 344                         return __fls(*reg) + vec;
 345         }
 346
 347         return -1;
 348 }
 349
 350 static u8 count_vectors(void *bitmap)
 351 {
 352         int vec;
 353         u32 *reg;
 354         u8 count = 0;
 355
 356         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 357                 reg = bitmap + REG_POS(vec);
 358                 count += hweight32(*reg);
 359         }
 360
 361         return count;
 362 }
 363
 364 int __kvm_apic_update_irr(u32 *pir, void *regs)
 365 {
 366         u32 i, vec;
 367         u32 pir_val, irr_val;
 368         int max_irr = -1;
 369
 370         for (i = vec = 0; i <= 7; i++, vec += 32) {
 371                 pir_val = READ_ONCE(pir[i]);
 372                 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
 373                 if (pir_val) {
 374                         irr_val |= xchg(&pir[i], 0);
 375                         *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
 376                 }
 377                 if (irr_val)
 378                         max_irr = __fls(irr_val) + vec;
 379         }
 380
 381         return max_irr;
 382 }
 383 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
 384
 385 int kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 386 {
 387         struct kvm_lapic *apic = vcpu->arch.apic;
 388
 389         return __kvm_apic_update_irr(pir, apic->regs);
 390 }
 391 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 392
 393 static inline int apic_search_irr(struct kvm_lapic *apic)
 394 {
 395         return find_highest_vector(apic->regs + APIC_IRR);
 396 }
 397
 398 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 399 {
 400         int result;
 401
 402         /*
 403          * Note that irr_pending is just a hint. It will be always
 404          * true with virtual interrupt delivery enabled.
 405          */
 406         if (!apic->irr_pending)
 407                 return -1;
 408
 409         result = apic_search_irr(apic);
 410         ASSERT(result == -1 || result >= 16);
 411
 412         return result;
 413 }
 414
 415 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 416 {
 417         struct kvm_vcpu *vcpu;
 418
 419         vcpu = apic->vcpu;
 420
 421         if (unlikely(vcpu->arch.apicv_active)) {
 422                 /* need to update RVI */
 423                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 424                 kvm_x86_ops->hwapic_irr_update(vcpu,
 425                                 apic_find_highest_irr(apic));
 426         } else {
 427                 apic->irr_pending = false;
 428                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 429                 if (apic_search_irr(apic) != -1)
 430                         apic->irr_pending = true;
 431         }
 432 }
 433
 434 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 435 {
 436         struct kvm_vcpu *vcpu;
 437
 438         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 439                 return;
 440
 441         vcpu = apic->vcpu;
 442
 443         /*
 444          * With APIC virtualization enabled, all caching is disabled
 445          * because the processor can modify ISR under the hood.  Instead
 446          * just set SVI.
 447          */
 448         if (unlikely(vcpu->arch.apicv_active))
 449                 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
 450         else {
 451                 ++apic->isr_count;
 452                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 453                 /*
 454                  * ISR (in service register) bit is set when injecting an interrupt.
 455                  * The highest vector is injected. Thus the latest bit set matches
 456                  * the highest bit in ISR.
 457                  */
 458                 apic->highest_isr_cache = vec;
 459         }
 460 }
 461
 462 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 463 {
 464         int result;
 465
 466         /*
 467          * Note that isr_count is always 1, and highest_isr_cache
 468          * is always -1, with APIC virtualization enabled.
 469          */
 470         if (!apic->isr_count)
 471                 return -1;
 472         if (likely(apic->highest_isr_cache != -1))
 473                 return apic->highest_isr_cache;
 474
 475         result = find_highest_vector(apic->regs + APIC_ISR);
 476         ASSERT(result == -1 || result >= 16);
 477
 478         return result;
 479 }
 480
 481 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 482 {
 483         struct kvm_vcpu *vcpu;
 484         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 485                 return;
 486
 487         vcpu = apic->vcpu;
 488
 489         /*
 490          * We do get here for APIC virtualization enabled if the guest
 491          * uses the Hyper-V APIC enlightenment.  In this case we may need
 492          * to trigger a new interrupt delivery by writing the SVI field;
 493          * on the other hand isr_count and highest_isr_cache are unused
 494          * and must be left alone.
 495          */
 496         if (unlikely(vcpu->arch.apicv_active))
 497                 kvm_x86_ops->hwapic_isr_update(vcpu,
 498                                                apic_find_highest_isr(apic));
 499         else {
 500                 --apic->isr_count;
 501                 BUG_ON(apic->isr_count < 0);
 502                 apic->highest_isr_cache = -1;
 503         }
 504 }
 505
 506 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 507 {
 508         /* This may race with setting of irr in __apic_accept_irq() and
 509          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 510          * will cause vmexit immediately and the value will be recalculated
 511          * on the next vmentry.
 512          */
 513         return apic_find_highest_irr(vcpu->arch.apic);
 514 }
 515 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
 516
 517 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 518                              int vector, int level, int trig_mode,
 519                              struct dest_map *dest_map);
 520
 521 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 522                      struct dest_map *dest_map)
 523 {
 524         struct kvm_lapic *apic = vcpu->arch.apic;
 525
 526         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 527                         irq->level, irq->trig_mode, dest_map);
 528 }
 529
 530 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 531 {
 532         return kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.pv_eoi.data, &val,
 533                                            sizeof(val));
 534 }
 535
 536 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 537 {
 538         return kvm_vcpu_read_guest_cached(vcpu, &vcpu->arch.pv_eoi.data, val,
 539                                           sizeof(*val));
 540 }
 541
 542 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 543 {
 544         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 545 }
 546
 547 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 548 {
 549         u8 val;
 550         if (pv_eoi_get_user(vcpu, &val) < 0)
 551                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 552                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 553         return val & 0x1;
 554 }
 555
 556 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 557 {
 558         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 559                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 560                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 561                 return;
 562         }
 563         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 564 }
 565
 566 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 567 {
 568         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 569                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 570                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 571                 return;
 572         }
 573         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 574 }
 575
 576 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
 577 {
 578         int highest_irr;
 579         if (kvm_x86_ops->sync_pir_to_irr && apic->vcpu->arch.apicv_active)
 580                 highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 581         else
 582                 highest_irr = apic_find_highest_irr(apic);
 583         if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
 584                 return -1;
 585         return highest_irr;
 586 }
 587
 588 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
 589 {
 590         u32 tpr, isrv, ppr, old_ppr;
 591         int isr;
 592
 593         old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
 594         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
 595         isr = apic_find_highest_isr(apic);
 596         isrv = (isr != -1) ? isr : 0;
 597
 598         if ((tpr & 0xf0) >= (isrv & 0xf0))
 599                 ppr = tpr & 0xff;
 600         else
 601                 ppr = isrv & 0xf0;
 602
 603         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 604                    apic, ppr, isr, isrv);
 605
 606         *new_ppr = ppr;
 607         if (old_ppr != ppr)
 608                 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
 609
 610         return ppr < old_ppr;
 611 }
 612
 613 static void apic_update_ppr(struct kvm_lapic *apic)
 614 {
 615         u32 ppr;
 616
 617         if (__apic_update_ppr(apic, &ppr) &&
 618             apic_has_interrupt_for_ppr(apic, ppr) != -1)
 619                 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 620 }
 621
 622 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
 623 {
 624         apic_update_ppr(vcpu->arch.apic);
 625 }
 626 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
 627
 628 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 629 {
 630         kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
 631         apic_update_ppr(apic);
 632 }
 633
 634 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
 635 {
 636         return mda == (apic_x2apic_mode(apic) ?
 637                         X2APIC_BROADCAST : APIC_BROADCAST);
 638 }
 639
 640 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
 641 {
 642         if (kvm_apic_broadcast(apic, mda))
 643                 return true;
 644
 645         if (apic_x2apic_mode(apic))
 646                 return mda == kvm_x2apic_id(apic);
 647
 648         /*
 649          * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
 650          * it were in x2APIC mode.  Hotplugged VCPUs start in xAPIC mode and
 651          * this allows unique addressing of VCPUs with APIC ID over 0xff.
 652          * The 0xff condition is needed because writeable xAPIC ID.
 653          */
 654         if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
 655                 return true;
 656
 657         return mda == kvm_xapic_id(apic);
 658 }
 659
 660 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 661 {
 662         u32 logical_id;
 663
 664         if (kvm_apic_broadcast(apic, mda))
 665                 return true;
 666
 667         logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
 668
 669         if (apic_x2apic_mode(apic))
 670                 return ((logical_id >> 16) == (mda >> 16))
 671                        && (logical_id & mda & 0xffff) != 0;
 672
 673         logical_id = GET_APIC_LOGICAL_ID(logical_id);
 674
 675         switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
 676         case APIC_DFR_FLAT:
 677                 return (logical_id & mda) != 0;
 678         case APIC_DFR_CLUSTER:
 679                 return ((logical_id >> 4) == (mda >> 4))
 680                        && (logical_id & mda & 0xf) != 0;
 681         default:
 682                 apic_debug("Bad DFR vcpu %d: %08x\n",
 683                            apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
 684                 return false;
 685         }
 686 }
 687
 688 /* The KVM local APIC implementation has two quirks:
 689  *
 690  *  - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
 691  *    in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
 692  *    KVM doesn't do that aliasing.
 693  *
 694  *  - in-kernel IOAPIC messages have to be delivered directly to
 695  *    x2APIC, because the kernel does not support interrupt remapping.
 696  *    In order to support broadcast without interrupt remapping, x2APIC
 697  *    rewrites the destination of non-IPI messages from APIC_BROADCAST
 698  *    to X2APIC_BROADCAST.
 699  *
 700  * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API.  This is
 701  * important when userspace wants to use x2APIC-format MSIs, because
 702  * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
 703  */
 704 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
 705                 struct kvm_lapic *source, struct kvm_lapic *target)
 706 {
 707         bool ipi = source != NULL;
 708
 709         if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
 710             !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
 711                 return X2APIC_BROADCAST;
 712
 713         return dest_id;
 714 }
 715
 716 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 717                            int short_hand, unsigned int dest, int dest_mode)
 718 {
 719         struct kvm_lapic *target = vcpu->arch.apic;
 720         u32 mda = kvm_apic_mda(vcpu, dest, source, target);
 721
 722         apic_debug("target %p, source %p, dest 0x%x, "
 723                    "dest_mode 0x%x, short_hand 0x%x\n",
 724                    target, source, dest, dest_mode, short_hand);
 725
 726         ASSERT(target);
 727         switch (short_hand) {
 728         case APIC_DEST_NOSHORT:
 729                 if (dest_mode == APIC_DEST_PHYSICAL)
 730                         return kvm_apic_match_physical_addr(target, mda);
 731                 else
 732                         return kvm_apic_match_logical_addr(target, mda);
 733         case APIC_DEST_SELF:
 734                 return target == source;
 735         case APIC_DEST_ALLINC:
 736                 return true;
 737         case APIC_DEST_ALLBUT:
 738                 return target != source;
 739         default:
 740                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 741                            short_hand);
 742                 return false;
 743         }
 744 }
 745 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
 746
 747 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
 748                        const unsigned long *bitmap, u32 bitmap_size)
 749 {
 750         u32 mod;
 751         int i, idx = -1;
 752
 753         mod = vector % dest_vcpus;
 754
 755         for (i = 0; i <= mod; i++) {
 756                 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
 757                 BUG_ON(idx == bitmap_size);
 758         }
 759
 760         return idx;
 761 }
 762
 763 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
 764 {
 765         if (!kvm->arch.disabled_lapic_found) {
 766                 kvm->arch.disabled_lapic_found = true;
 767                 printk(KERN_INFO
 768                        "Disabled LAPIC found during irq injection\n");
 769         }
 770 }
 771
 772 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
 773                 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
 774 {
 775         if (kvm->arch.x2apic_broadcast_quirk_disabled) {
 776                 if ((irq->dest_id == APIC_BROADCAST &&
 777                                 map->mode != KVM_APIC_MODE_X2APIC))
 778                         return true;
 779                 if (irq->dest_id == X2APIC_BROADCAST)
 780                         return true;
 781         } else {
 782                 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
 783                 if (irq->dest_id == (x2apic_ipi ?
 784                                      X2APIC_BROADCAST : APIC_BROADCAST))
 785                         return true;
 786         }
 787
 788         return false;
 789 }
 790
 791 /* Return true if the interrupt can be handled by using *bitmap as index mask
 792  * for valid destinations in *dst array.
 793  * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
 794  * Note: we may have zero kvm_lapic destinations when we return true, which
 795  * means that the interrupt should be dropped.  In this case, *bitmap would be
 796  * zero and *dst undefined.
 797  */
 798 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
 799                 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
 800                 struct kvm_apic_map *map, struct kvm_lapic ***dst,
 801                 unsigned long *bitmap)
 802 {
 803         int i, lowest;
 804
 805         if (irq->shorthand == APIC_DEST_SELF && src) {
 806                 *dst = src;
 807                 *bitmap = 1;
 808                 return true;
 809         } else if (irq->shorthand)
 810                 return false;
 811
 812         if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
 813                 return false;
 814
 815         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
 816                 if (irq->dest_id > map->max_apic_id) {
 817                         *bitmap = 0;
 818                 } else {
 819                         *dst = &map->phys_map[irq->dest_id];
 820                         *bitmap = 1;
 821                 }
 822                 return true;
 823         }
 824
 825         *bitmap = 0;
 826         if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
 827                                 (u16 *)bitmap))
 828                 return false;
 829
 830         if (!kvm_lowest_prio_delivery(irq))
 831                 return true;
 832
 833         if (!kvm_vector_hashing_enabled()) {
 834                 lowest = -1;
 835                 for_each_set_bit(i, bitmap, 16) {
 836                         if (!(*dst)[i])
 837                                 continue;
 838                         if (lowest < 0)
 839                                 lowest = i;
 840                         else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
 841                                                 (*dst)[lowest]->vcpu) < 0)
 842                                 lowest = i;
 843                 }
 844         } else {
 845                 if (!*bitmap)
 846                         return true;
 847
 848                 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
 849                                 bitmap, 16);
 850
 851                 if (!(*dst)[lowest]) {
 852                         kvm_apic_disabled_lapic_found(kvm);
 853                         *bitmap = 0;
 854                         return true;
 855                 }
 856         }
 857
 858         *bitmap = (lowest >= 0) ? 1 << lowest : 0;
 859
 860         return true;
 861 }
 862
 863 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 864                 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
 865 {
 866         struct kvm_apic_map *map;
 867         unsigned long bitmap;
 868         struct kvm_lapic **dst = NULL;
 869         int i;
 870         bool ret;
 871
 872         *r = -1;
 873
 874         if (irq->shorthand == APIC_DEST_SELF) {
 875                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 876                 return true;
 877         }
 878
 879         rcu_read_lock();
 880         map = rcu_dereference(kvm->arch.apic_map);
 881
 882         ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
 883         if (ret)
 884                 for_each_set_bit(i, &bitmap, 16) {
 885                         if (!dst[i])
 886                                 continue;
 887                         if (*r < 0)
 888                                 *r = 0;
 889                         *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 890                 }
 891
 892         rcu_read_unlock();
 893         return ret;
 894 }
 895
 896 /*
 897  * This routine tries to handler interrupts in posted mode, here is how
 898  * it deals with different cases:
 899  * - For single-destination interrupts, handle it in posted mode
 900  * - Else if vector hashing is enabled and it is a lowest-priority
 901  *   interrupt, handle it in posted mode and use the following mechanism
 902  *   to find the destinaiton vCPU.
 903  *      1. For lowest-priority interrupts, store all the possible
 904  *         destination vCPUs in an array.
 905  *      2. Use "guest vector % max number of destination vCPUs" to find
 906  *         the right destination vCPU in the array for the lowest-priority
 907  *         interrupt.
 908  * - Otherwise, use remapped mode to inject the interrupt.
 909  */
 910 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
 911                         struct kvm_vcpu **dest_vcpu)
 912 {
 913         struct kvm_apic_map *map;
 914         unsigned long bitmap;
 915         struct kvm_lapic **dst = NULL;
 916         bool ret = false;
 917
 918         if (irq->shorthand)
 919                 return false;
 920
 921         rcu_read_lock();
 922         map = rcu_dereference(kvm->arch.apic_map);
 923
 924         if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
 925                         hweight16(bitmap) == 1) {
 926                 unsigned long i = find_first_bit(&bitmap, 16);
 927
 928                 if (dst[i]) {
 929                         *dest_vcpu = dst[i]->vcpu;
 930                         ret = true;
 931                 }
 932         }
 933
 934         rcu_read_unlock();
 935         return ret;
 936 }
 937
 938 /*
 939  * Add a pending IRQ into lapic.
 940  * Return 1 if successfully added and 0 if discarded.
 941  */
 942 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 943                              int vector, int level, int trig_mode,
 944                              struct dest_map *dest_map)
 945 {
 946         int result = 0;
 947         struct kvm_vcpu *vcpu = apic->vcpu;
 948
 949         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 950                                   trig_mode, vector);
 951         switch (delivery_mode) {
 952         case APIC_DM_LOWEST:
 953                 vcpu->arch.apic_arb_prio++;
 954         case APIC_DM_FIXED:
 955                 if (unlikely(trig_mode && !level))
 956                         break;
 957
 958                 /* FIXME add logic for vcpu on reset */
 959                 if (unlikely(!apic_enabled(apic)))
 960                         break;
 961
 962                 result = 1;
 963
 964                 if (dest_map) {
 965                         __set_bit(vcpu->vcpu_id, dest_map->map);
 966                         dest_map->vectors[vcpu->vcpu_id] = vector;
 967                 }
 968
 969                 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
 970                         if (trig_mode)
 971                                 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
 972                         else
 973                                 apic_clear_vector(vector, apic->regs + APIC_TMR);
 974                 }
 975
 976                 if (vcpu->arch.apicv_active)
 977                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 978                 else {
 979                         kvm_lapic_set_irr(vector, apic);
 980
 981                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 982                         kvm_vcpu_kick(vcpu);
 983                 }
 984                 break;
 985
 986         case APIC_DM_REMRD:
 987                 result = 1;
 988                 vcpu->arch.pv.pv_unhalted = 1;
 989                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 990                 kvm_vcpu_kick(vcpu);
 991                 break;
 992
 993         case APIC_DM_SMI:
 994                 result = 1;
 995                 kvm_make_request(KVM_REQ_SMI, vcpu);
 996                 kvm_vcpu_kick(vcpu);
 997                 break;
 998
 999         case APIC_DM_NMI:
1000                 result = 1;
1001                 kvm_inject_nmi(vcpu);
1002                 kvm_vcpu_kick(vcpu);
1003                 break;
1004
1005         case APIC_DM_INIT:
1006                 if (!trig_mode || level) {
1007                         result = 1;
1008                         /* assumes that there are only KVM_APIC_INIT/SIPI */
1009                         apic->pending_events = (1UL << KVM_APIC_INIT);
1010                         /* make sure pending_events is visible before sending
1011                          * the request */
1012                         smp_wmb();
1013                         kvm_make_request(KVM_REQ_EVENT, vcpu);
1014                         kvm_vcpu_kick(vcpu);
1015                 } else {
1016                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
1017                                    vcpu->vcpu_id);
1018                 }
1019                 break;
1020
1021         case APIC_DM_STARTUP:
1022                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
1023                            vcpu->vcpu_id, vector);
1024                 result = 1;
1025                 apic->sipi_vector = vector;
1026                 /* make sure sipi_vector is visible for the receiver */
1027                 smp_wmb();
1028                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1029                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1030                 kvm_vcpu_kick(vcpu);
1031                 break;
1032
1033         case APIC_DM_EXTINT:
1034                 /*
1035                  * Should only be called by kvm_apic_local_deliver() with LVT0,
1036                  * before NMI watchdog was enabled. Already handled by
1037                  * kvm_apic_accept_pic_intr().
1038                  */
1039                 break;
1040
1041         default:
1042                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1043                        delivery_mode);
1044                 break;
1045         }
1046         return result;
1047 }
1048
1049 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1050 {
1051         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1052 }
1053
1054 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1055 {
1056         return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1057 }
1058
1059 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1060 {
1061         int trigger_mode;
1062
1063         /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1064         if (!kvm_ioapic_handles_vector(apic, vector))
1065                 return;
1066
1067         /* Request a KVM exit to inform the userspace IOAPIC. */
1068         if (irqchip_split(apic->vcpu->kvm)) {
1069                 apic->vcpu->arch.pending_ioapic_eoi = vector;
1070                 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1071                 return;
1072         }
1073
1074         if (apic_test_vector(vector, apic->regs + APIC_TMR))
1075                 trigger_mode = IOAPIC_LEVEL_TRIG;
1076         else
1077                 trigger_mode = IOAPIC_EDGE_TRIG;
1078
1079         kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1080 }
1081
1082 static int apic_set_eoi(struct kvm_lapic *apic)
1083 {
1084         int vector = apic_find_highest_isr(apic);
1085
1086         trace_kvm_eoi(apic, vector);
1087
1088         /*
1089          * Not every write EOI will has corresponding ISR,
1090          * one example is when Kernel check timer on setup_IO_APIC
1091          */
1092         if (vector == -1)
1093                 return vector;
1094
1095         apic_clear_isr(vector, apic);
1096         apic_update_ppr(apic);
1097
1098         if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1099                 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1100
1101         kvm_ioapic_send_eoi(apic, vector);
1102         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1103         return vector;
1104 }
1105
1106 /*
1107  * this interface assumes a trap-like exit, which has already finished
1108  * desired side effect including vISR and vPPR update.
1109  */
1110 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1111 {
1112         struct kvm_lapic *apic = vcpu->arch.apic;
1113
1114         trace_kvm_eoi(apic, vector);
1115
1116         kvm_ioapic_send_eoi(apic, vector);
1117         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1118 }
1119 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1120
1121 static void apic_send_ipi(struct kvm_lapic *apic)
1122 {
1123         u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1124         u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
1125         struct kvm_lapic_irq irq;
1126
1127         irq.vector = icr_low & APIC_VECTOR_MASK;
1128         irq.delivery_mode = icr_low & APIC_MODE_MASK;
1129         irq.dest_mode = icr_low & APIC_DEST_MASK;
1130         irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1131         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1132         irq.shorthand = icr_low & APIC_SHORT_MASK;
1133         irq.msi_redir_hint = false;
1134         if (apic_x2apic_mode(apic))
1135                 irq.dest_id = icr_high;
1136         else
1137                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1138
1139         trace_kvm_apic_ipi(icr_low, irq.dest_id);
1140
1141         apic_debug("icr_high 0x%x, icr_low 0x%x, "
1142                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1143                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1144                    "msi_redir_hint 0x%x\n",
1145                    icr_high, icr_low, irq.shorthand, irq.dest_id,
1146                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1147                    irq.vector, irq.msi_redir_hint);
1148
1149         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1150 }
1151
1152 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1153 {
1154         ktime_t remaining, now;
1155         s64 ns;
1156         u32 tmcct;
1157
1158         ASSERT(apic != NULL);
1159
1160         /* if initial count is 0, current count should also be 0 */
1161         if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1162                 apic->lapic_timer.period == 0)
1163                 return 0;
1164
1165         now = ktime_get();
1166         remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1167         if (ktime_to_ns(remaining) < 0)
1168                 remaining = 0;
1169
1170         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1171         tmcct = div64_u64(ns,
1172                          (APIC_BUS_CYCLE_NS * apic->divide_count));
1173
1174         return tmcct;
1175 }
1176
1177 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1178 {
1179         struct kvm_vcpu *vcpu = apic->vcpu;
1180         struct kvm_run *run = vcpu->run;
1181
1182         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1183         run->tpr_access.rip = kvm_rip_read(vcpu);
1184         run->tpr_access.is_write = write;
1185 }
1186
1187 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1188 {
1189         if (apic->vcpu->arch.tpr_access_reporting)
1190                 __report_tpr_access(apic, write);
1191 }
1192
1193 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1194 {
1195         u32 val = 0;
1196
1197         if (offset >= LAPIC_MMIO_LENGTH)
1198                 return 0;
1199
1200         switch (offset) {
1201         case APIC_ARBPRI:
1202                 apic_debug("Access APIC ARBPRI register which is for P6\n");
1203                 break;
1204
1205         case APIC_TMCCT:        /* Timer CCR */
1206                 if (apic_lvtt_tscdeadline(apic))
1207                         return 0;
1208
1209                 val = apic_get_tmcct(apic);
1210                 break;
1211         case APIC_PROCPRI:
1212                 apic_update_ppr(apic);
1213                 val = kvm_lapic_get_reg(apic, offset);
1214                 break;
1215         case APIC_TASKPRI:
1216                 report_tpr_access(apic, false);
1217                 /* fall thru */
1218         default:
1219                 val = kvm_lapic_get_reg(apic, offset);
1220                 break;
1221         }
1222
1223         return val;
1224 }
1225
1226 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1227 {
1228         return container_of(dev, struct kvm_lapic, dev);
1229 }
1230
1231 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1232                 void *data)
1233 {
1234         unsigned char alignment = offset & 0xf;
1235         u32 result;
1236         /* this bitmask has a bit cleared for each reserved register */
1237         static const u64 rmask = 0x43ff01ffffffe70cULL;
1238
1239         if ((alignment + len) > 4) {
1240                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1241                            offset, len);
1242                 return 1;
1243         }
1244
1245         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1246                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1247                            offset);
1248                 return 1;
1249         }
1250
1251         result = __apic_read(apic, offset & ~0xf);
1252
1253         trace_kvm_apic_read(offset, result);
1254
1255         switch (len) {
1256         case 1:
1257         case 2:
1258         case 4:
1259                 memcpy(data, (char *)&result + alignment, len);
1260                 break;
1261         default:
1262                 printk(KERN_ERR "Local APIC read with len = %x, "
1263                        "should be 1,2, or 4 instead\n", len);
1264                 break;
1265         }
1266         return 0;
1267 }
1268 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1269
1270 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1271 {
1272         return kvm_apic_hw_enabled(apic) &&
1273             addr >= apic->base_address &&
1274             addr < apic->base_address + LAPIC_MMIO_LENGTH;
1275 }
1276
1277 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1278                            gpa_t address, int len, void *data)
1279 {
1280         struct kvm_lapic *apic = to_lapic(this);
1281         u32 offset = address - apic->base_address;
1282
1283         if (!apic_mmio_in_range(apic, address))
1284                 return -EOPNOTSUPP;
1285
1286         kvm_lapic_reg_read(apic, offset, len, data);
1287
1288         return 0;
1289 }
1290
1291 static void update_divide_count(struct kvm_lapic *apic)
1292 {
1293         u32 tmp1, tmp2, tdcr;
1294
1295         tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1296         tmp1 = tdcr & 0xf;
1297         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1298         apic->divide_count = 0x1 << (tmp2 & 0x7);
1299
1300         apic_debug("timer divide count is 0x%x\n",
1301                                    apic->divide_count);
1302 }
1303
1304 static void apic_update_lvtt(struct kvm_lapic *apic)
1305 {
1306         u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1307                         apic->lapic_timer.timer_mode_mask;
1308
1309         if (apic->lapic_timer.timer_mode != timer_mode) {
1310                 apic->lapic_timer.timer_mode = timer_mode;
1311                 hrtimer_cancel(&apic->lapic_timer.timer);
1312         }
1313 }
1314
1315 static void apic_timer_expired(struct kvm_lapic *apic)
1316 {
1317         struct kvm_vcpu *vcpu = apic->vcpu;
1318         struct swait_queue_head *q = &vcpu->wq;
1319         struct kvm_timer *ktimer = &apic->lapic_timer;
1320
1321         if (atomic_read(&apic->lapic_timer.pending))
1322                 return;
1323
1324         atomic_inc(&apic->lapic_timer.pending);
1325         kvm_set_pending_timer(vcpu);
1326
1327         if (swait_active(q))
1328                 swake_up(q);
1329
1330         if (apic_lvtt_tscdeadline(apic))
1331                 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1332 }
1333
1334 /*
1335  * On APICv, this test will cause a busy wait
1336  * during a higher-priority task.
1337  */
1338
1339 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1340 {
1341         struct kvm_lapic *apic = vcpu->arch.apic;
1342         u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1343
1344         if (kvm_apic_hw_enabled(apic)) {
1345                 int vec = reg & APIC_VECTOR_MASK;
1346                 void *bitmap = apic->regs + APIC_ISR;
1347
1348                 if (vcpu->arch.apicv_active)
1349                         bitmap = apic->regs + APIC_IRR;
1350
1351                 if (apic_test_vector(vec, bitmap))
1352                         return true;
1353         }
1354         return false;
1355 }
1356
1357 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1358 {
1359         struct kvm_lapic *apic = vcpu->arch.apic;
1360         u64 guest_tsc, tsc_deadline;
1361
1362         if (!lapic_in_kernel(vcpu))
1363                 return;
1364
1365         if (apic->lapic_timer.expired_tscdeadline == 0)
1366                 return;
1367
1368         if (!lapic_timer_int_injected(vcpu))
1369                 return;
1370
1371         tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1372         apic->lapic_timer.expired_tscdeadline = 0;
1373         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1374         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1375
1376         /* __delay is delay_tsc whenever the hardware has TSC, thus always.  */
1377         if (guest_tsc < tsc_deadline)
1378                 __delay(min(tsc_deadline - guest_tsc,
1379                         nsec_to_cycles(vcpu, lapic_timer_advance_ns)));
1380 }
1381
1382 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1383 {
1384         u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1385         u64 ns = 0;
1386         ktime_t expire;
1387         struct kvm_vcpu *vcpu = apic->vcpu;
1388         unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1389         unsigned long flags;
1390         ktime_t now;
1391
1392         if (unlikely(!tscdeadline || !this_tsc_khz))
1393                 return;
1394
1395         local_irq_save(flags);
1396
1397         now = ktime_get();
1398         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1399         if (likely(tscdeadline > guest_tsc)) {
1400                 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1401                 do_div(ns, this_tsc_khz);
1402                 expire = ktime_add_ns(now, ns);
1403                 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1404                 hrtimer_start(&apic->lapic_timer.timer,
1405                                 expire, HRTIMER_MODE_ABS_PINNED);
1406         } else
1407                 apic_timer_expired(apic);
1408
1409         local_irq_restore(flags);
1410 }
1411
1412 static void start_sw_period(struct kvm_lapic *apic)
1413 {
1414         if (!apic->lapic_timer.period)
1415                 return;
1416
1417         if (apic_lvtt_oneshot(apic) &&
1418             ktime_after(ktime_get(),
1419                         apic->lapic_timer.target_expiration)) {
1420                 apic_timer_expired(apic);
1421                 return;
1422         }
1423
1424         hrtimer_start(&apic->lapic_timer.timer,
1425                 apic->lapic_timer.target_expiration,
1426                 HRTIMER_MODE_ABS_PINNED);
1427 }
1428
1429 static bool set_target_expiration(struct kvm_lapic *apic)
1430 {
1431         ktime_t now;
1432         u64 tscl = rdtsc();
1433
1434         now = ktime_get();
1435         apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1436                 * APIC_BUS_CYCLE_NS * apic->divide_count;
1437
1438         if (!apic->lapic_timer.period)
1439                 return false;
1440
1441         /*
1442          * Do not allow the guest to program periodic timers with small
1443          * interval, since the hrtimers are not throttled by the host
1444          * scheduler.
1445          */
1446         if (apic_lvtt_period(apic)) {
1447                 s64 min_period = min_timer_period_us * 1000LL;
1448
1449                 if (apic->lapic_timer.period < min_period) {
1450                         pr_info_ratelimited(
1451                             "kvm: vcpu %i: requested %lld ns "
1452                             "lapic timer period limited to %lld ns\n",
1453                             apic->vcpu->vcpu_id,
1454                             apic->lapic_timer.period, min_period);
1455                         apic->lapic_timer.period = min_period;
1456                 }
1457         }
1458
1459         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1460                    PRIx64 ", "
1461                    "timer initial count 0x%x, period %lldns, "
1462                    "expire @ 0x%016" PRIx64 ".\n", __func__,
1463                    APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1464                    kvm_lapic_get_reg(apic, APIC_TMICT),
1465                    apic->lapic_timer.period,
1466                    ktime_to_ns(ktime_add_ns(now,
1467                                 apic->lapic_timer.period)));
1468
1469         apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1470                 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1471         apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1472
1473         return true;
1474 }
1475
1476 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1477 {
1478         apic->lapic_timer.tscdeadline +=
1479                 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1480         apic->lapic_timer.target_expiration =
1481                 ktime_add_ns(apic->lapic_timer.target_expiration,
1482                                 apic->lapic_timer.period);
1483 }
1484
1485 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1486 {
1487         if (!lapic_in_kernel(vcpu))
1488                 return false;
1489
1490         return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1491 }
1492 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1493
1494 static void cancel_hv_timer(struct kvm_lapic *apic)
1495 {
1496         kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1497         apic->lapic_timer.hv_timer_in_use = false;
1498 }
1499
1500 static bool start_hv_timer(struct kvm_lapic *apic)
1501 {
1502         u64 tscdeadline = apic->lapic_timer.tscdeadline;
1503
1504         if ((atomic_read(&apic->lapic_timer.pending) &&
1505                 !apic_lvtt_period(apic)) ||
1506                 kvm_x86_ops->set_hv_timer(apic->vcpu, tscdeadline)) {
1507                 if (apic->lapic_timer.hv_timer_in_use)
1508                         cancel_hv_timer(apic);
1509         } else {
1510                 apic->lapic_timer.hv_timer_in_use = true;
1511                 hrtimer_cancel(&apic->lapic_timer.timer);
1512
1513                 /* In case the sw timer triggered in the window */
1514                 if (atomic_read(&apic->lapic_timer.pending) &&
1515                         !apic_lvtt_period(apic))
1516                         cancel_hv_timer(apic);
1517         }
1518         trace_kvm_hv_timer_state(apic->vcpu->vcpu_id,
1519                         apic->lapic_timer.hv_timer_in_use);
1520         return apic->lapic_timer.hv_timer_in_use;
1521 }
1522
1523 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1524 {
1525         struct kvm_lapic *apic = vcpu->arch.apic;
1526
1527         WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1528         WARN_ON(swait_active(&vcpu->wq));
1529         cancel_hv_timer(apic);
1530         apic_timer_expired(apic);
1531
1532         if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1533                 advance_periodic_target_expiration(apic);
1534                 if (!start_hv_timer(apic))
1535                         start_sw_period(apic);
1536         }
1537 }
1538 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1539
1540 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1541 {
1542         struct kvm_lapic *apic = vcpu->arch.apic;
1543
1544         WARN_ON(apic->lapic_timer.hv_timer_in_use);
1545
1546         start_hv_timer(apic);
1547 }
1548 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1549
1550 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1551 {
1552         struct kvm_lapic *apic = vcpu->arch.apic;
1553
1554         /* Possibly the TSC deadline timer is not enabled yet */
1555         if (!apic->lapic_timer.hv_timer_in_use)
1556                 return;
1557
1558         cancel_hv_timer(apic);
1559
1560         if (atomic_read(&apic->lapic_timer.pending))
1561                 return;
1562
1563         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1564                 start_sw_period(apic);
1565         else if (apic_lvtt_tscdeadline(apic))
1566                 start_sw_tscdeadline(apic);
1567 }
1568 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1569
1570 static void start_apic_timer(struct kvm_lapic *apic)
1571 {
1572         atomic_set(&apic->lapic_timer.pending, 0);
1573
1574         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1575                 if (set_target_expiration(apic) &&
1576                         !(kvm_x86_ops->set_hv_timer && start_hv_timer(apic)))
1577                         start_sw_period(apic);
1578         } else if (apic_lvtt_tscdeadline(apic)) {
1579                 if (!(kvm_x86_ops->set_hv_timer && start_hv_timer(apic)))
1580                         start_sw_tscdeadline(apic);
1581         }
1582 }
1583
1584 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1585 {
1586         bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1587
1588         if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1589                 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1590                 if (lvt0_in_nmi_mode) {
1591                         apic_debug("Receive NMI setting on APIC_LVT0 "
1592                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1593                         atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1594                 } else
1595                         atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1596         }
1597 }
1598
1599 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1600 {
1601         int ret = 0;
1602
1603         trace_kvm_apic_write(reg, val);
1604
1605         switch (reg) {
1606         case APIC_ID:           /* Local APIC ID */
1607                 if (!apic_x2apic_mode(apic))
1608                         kvm_apic_set_xapic_id(apic, val >> 24);
1609                 else
1610                         ret = 1;
1611                 break;
1612
1613         case APIC_TASKPRI:
1614                 report_tpr_access(apic, true);
1615                 apic_set_tpr(apic, val & 0xff);
1616                 break;
1617
1618         case APIC_EOI:
1619                 apic_set_eoi(apic);
1620                 break;
1621
1622         case APIC_LDR:
1623                 if (!apic_x2apic_mode(apic))
1624                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1625                 else
1626                         ret = 1;
1627                 break;
1628
1629         case APIC_DFR:
1630                 if (!apic_x2apic_mode(apic)) {
1631                         kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1632                         recalculate_apic_map(apic->vcpu->kvm);
1633                 } else
1634                         ret = 1;
1635                 break;
1636
1637         case APIC_SPIV: {
1638                 u32 mask = 0x3ff;
1639                 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1640                         mask |= APIC_SPIV_DIRECTED_EOI;
1641                 apic_set_spiv(apic, val & mask);
1642                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1643                         int i;
1644                         u32 lvt_val;
1645
1646                         for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1647                                 lvt_val = kvm_lapic_get_reg(apic,
1648                                                        APIC_LVTT + 0x10 * i);
1649                                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1650                                              lvt_val | APIC_LVT_MASKED);
1651                         }
1652                         apic_update_lvtt(apic);
1653                         atomic_set(&apic->lapic_timer.pending, 0);
1654
1655                 }
1656                 break;
1657         }
1658         case APIC_ICR:
1659                 /* No delay here, so we always clear the pending bit */
1660                 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1661                 apic_send_ipi(apic);
1662                 break;
1663
1664         case APIC_ICR2:
1665                 if (!apic_x2apic_mode(apic))
1666                         val &= 0xff000000;
1667                 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1668                 break;
1669
1670         case APIC_LVT0:
1671                 apic_manage_nmi_watchdog(apic, val);
1672         case APIC_LVTTHMR:
1673         case APIC_LVTPC:
1674         case APIC_LVT1:
1675         case APIC_LVTERR:
1676                 /* TODO: Check vector */
1677                 if (!kvm_apic_sw_enabled(apic))
1678                         val |= APIC_LVT_MASKED;
1679
1680                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1681                 kvm_lapic_set_reg(apic, reg, val);
1682
1683                 break;
1684
1685         case APIC_LVTT:
1686                 if (!kvm_apic_sw_enabled(apic))
1687                         val |= APIC_LVT_MASKED;
1688                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1689                 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1690                 apic_update_lvtt(apic);
1691                 break;
1692
1693         case APIC_TMICT:
1694                 if (apic_lvtt_tscdeadline(apic))
1695                         break;
1696
1697                 hrtimer_cancel(&apic->lapic_timer.timer);
1698                 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1699                 start_apic_timer(apic);
1700                 break;
1701
1702         case APIC_TDCR:
1703                 if (val & 4)
1704                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1705                 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1706                 update_divide_count(apic);
1707                 break;
1708
1709         case APIC_ESR:
1710                 if (apic_x2apic_mode(apic) && val != 0) {
1711                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1712                         ret = 1;
1713                 }
1714                 break;
1715
1716         case APIC_SELF_IPI:
1717                 if (apic_x2apic_mode(apic)) {
1718                         kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1719                 } else
1720                         ret = 1;
1721                 break;
1722         default:
1723                 ret = 1;
1724                 break;
1725         }
1726         if (ret)
1727                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1728         return ret;
1729 }
1730 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
1731
1732 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1733                             gpa_t address, int len, const void *data)
1734 {
1735         struct kvm_lapic *apic = to_lapic(this);
1736         unsigned int offset = address - apic->base_address;
1737         u32 val;
1738
1739         if (!apic_mmio_in_range(apic, address))
1740                 return -EOPNOTSUPP;
1741
1742         /*
1743          * APIC register must be aligned on 128-bits boundary.
1744          * 32/64/128 bits registers must be accessed thru 32 bits.
1745          * Refer SDM 8.4.1
1746          */
1747         if (len != 4 || (offset & 0xf)) {
1748                 /* Don't shout loud, $infamous_os would cause only noise. */
1749                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1750                 return 0;
1751         }
1752
1753         val = *(u32*)data;
1754
1755         /* too common printing */
1756         if (offset != APIC_EOI)
1757                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1758                            "0x%x\n", __func__, offset, len, val);
1759
1760         kvm_lapic_reg_write(apic, offset & 0xff0, val);
1761
1762         return 0;
1763 }
1764
1765 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1766 {
1767         kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1768 }
1769 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1770
1771 /* emulate APIC access in a trap manner */
1772 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1773 {
1774         u32 val = 0;
1775
1776         /* hw has done the conditional check and inst decode */
1777         offset &= 0xff0;
1778
1779         kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
1780
1781         /* TODO: optimize to just emulate side effect w/o one more write */
1782         kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
1783 }
1784 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1785
1786 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1787 {
1788         struct kvm_lapic *apic = vcpu->arch.apic;
1789
1790         if (!vcpu->arch.apic)
1791                 return;
1792
1793         hrtimer_cancel(&apic->lapic_timer.timer);
1794
1795         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1796                 static_key_slow_dec_deferred(&apic_hw_disabled);
1797
1798         if (!apic->sw_enabled)
1799                 static_key_slow_dec_deferred(&apic_sw_disabled);
1800
1801         if (apic->regs)
1802                 free_page((unsigned long)apic->regs);
1803
1804         kfree(apic);
1805 }
1806
1807 /*
1808  *----------------------------------------------------------------------
1809  * LAPIC interface
1810  *----------------------------------------------------------------------
1811  */
1812 u64 kvm_get_lapic_target_expiration_tsc(struct kvm_vcpu *vcpu)
1813 {
1814         struct kvm_lapic *apic = vcpu->arch.apic;
1815
1816         if (!lapic_in_kernel(vcpu))
1817                 return 0;
1818
1819         return apic->lapic_timer.tscdeadline;
1820 }
1821
1822 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1823 {
1824         struct kvm_lapic *apic = vcpu->arch.apic;
1825
1826         if (!lapic_in_kernel(vcpu) ||
1827                 !apic_lvtt_tscdeadline(apic))
1828                 return 0;
1829
1830         return apic->lapic_timer.tscdeadline;
1831 }
1832
1833 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1834 {
1835         struct kvm_lapic *apic = vcpu->arch.apic;
1836
1837         if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
1838                         apic_lvtt_period(apic))
1839                 return;
1840
1841         hrtimer_cancel(&apic->lapic_timer.timer);
1842         apic->lapic_timer.tscdeadline = data;
1843         start_apic_timer(apic);
1844 }
1845
1846 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1847 {
1848         struct kvm_lapic *apic = vcpu->arch.apic;
1849
1850         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1851                      | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
1852 }
1853
1854 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1855 {
1856         u64 tpr;
1857
1858         tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1859
1860         return (tpr & 0xf0) >> 4;
1861 }
1862
1863 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1864 {
1865         u64 old_value = vcpu->arch.apic_base;
1866         struct kvm_lapic *apic = vcpu->arch.apic;
1867
1868         if (!apic)
1869                 value |= MSR_IA32_APICBASE_BSP;
1870
1871         vcpu->arch.apic_base = value;
1872
1873         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
1874                 kvm_update_cpuid(vcpu);
1875
1876         if (!apic)
1877                 return;
1878
1879         /* update jump label if enable bit changes */
1880         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1881                 if (value & MSR_IA32_APICBASE_ENABLE) {
1882                         kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
1883                         static_key_slow_dec_deferred(&apic_hw_disabled);
1884                 } else {
1885                         static_key_slow_inc(&apic_hw_disabled.key);
1886                         recalculate_apic_map(vcpu->kvm);
1887                 }
1888         }
1889
1890         if ((old_value ^ value) & X2APIC_ENABLE) {
1891                 if (value & X2APIC_ENABLE) {
1892                         kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
1893                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1894                 } else
1895                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1896         }
1897
1898         apic->base_address = apic->vcpu->arch.apic_base &
1899                              MSR_IA32_APICBASE_BASE;
1900
1901         if ((value & MSR_IA32_APICBASE_ENABLE) &&
1902              apic->base_address != APIC_DEFAULT_PHYS_BASE)
1903                 pr_warn_once("APIC base relocation is unsupported by KVM");
1904
1905         /* with FSB delivery interrupt, we can restart APIC functionality */
1906         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1907                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1908
1909 }
1910
1911 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
1912 {
1913         struct kvm_lapic *apic;
1914         int i;
1915
1916         apic_debug("%s\n", __func__);
1917
1918         ASSERT(vcpu);
1919         apic = vcpu->arch.apic;
1920         ASSERT(apic != NULL);
1921
1922         /* Stop the timer in case it's a reset to an active apic */
1923         hrtimer_cancel(&apic->lapic_timer.timer);
1924
1925         if (!init_event) {
1926                 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
1927                                          MSR_IA32_APICBASE_ENABLE);
1928                 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
1929         }
1930         kvm_apic_set_version(apic->vcpu);
1931
1932         for (i = 0; i < KVM_APIC_LVT_NUM; i++)
1933                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1934         apic_update_lvtt(apic);
1935         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1936                 kvm_lapic_set_reg(apic, APIC_LVT0,
1937                              SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1938         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
1939
1940         kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
1941         apic_set_spiv(apic, 0xff);
1942         kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
1943         if (!apic_x2apic_mode(apic))
1944                 kvm_apic_set_ldr(apic, 0);
1945         kvm_lapic_set_reg(apic, APIC_ESR, 0);
1946         kvm_lapic_set_reg(apic, APIC_ICR, 0);
1947         kvm_lapic_set_reg(apic, APIC_ICR2, 0);
1948         kvm_lapic_set_reg(apic, APIC_TDCR, 0);
1949         kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1950         for (i = 0; i < 8; i++) {
1951                 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1952                 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1953                 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1954         }
1955         apic->irr_pending = vcpu->arch.apicv_active;
1956         apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
1957         apic->highest_isr_cache = -1;
1958         update_divide_count(apic);
1959         atomic_set(&apic->lapic_timer.pending, 0);
1960         if (kvm_vcpu_is_bsp(vcpu))
1961                 kvm_lapic_set_base(vcpu,
1962                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1963         vcpu->arch.pv_eoi.msr_val = 0;
1964         apic_update_ppr(apic);
1965
1966         vcpu->arch.apic_arb_prio = 0;
1967         vcpu->arch.apic_attention = 0;
1968
1969         apic_debug("%s: vcpu=%p, id=0x%x, base_msr="
1970                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1971                    vcpu, kvm_lapic_get_reg(apic, APIC_ID),
1972                    vcpu->arch.apic_base, apic->base_address);
1973 }
1974
1975 /*
1976  *----------------------------------------------------------------------
1977  * timer interface
1978  *----------------------------------------------------------------------
1979  */
1980
1981 static bool lapic_is_periodic(struct kvm_lapic *apic)
1982 {
1983         return apic_lvtt_period(apic);
1984 }
1985
1986 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1987 {
1988         struct kvm_lapic *apic = vcpu->arch.apic;
1989
1990         if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
1991                 return atomic_read(&apic->lapic_timer.pending);
1992
1993         return 0;
1994 }
1995
1996 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1997 {
1998         u32 reg = kvm_lapic_get_reg(apic, lvt_type);
1999         int vector, mode, trig_mode;
2000
2001         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2002                 vector = reg & APIC_VECTOR_MASK;
2003                 mode = reg & APIC_MODE_MASK;
2004                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
2005                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2006                                         NULL);
2007         }
2008         return 0;
2009 }
2010
2011 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2012 {
2013         struct kvm_lapic *apic = vcpu->arch.apic;
2014
2015         if (apic)
2016                 kvm_apic_local_deliver(apic, APIC_LVT0);
2017 }
2018
2019 static const struct kvm_io_device_ops apic_mmio_ops = {
2020         .read     = apic_mmio_read,
2021         .write    = apic_mmio_write,
2022 };
2023
2024 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2025 {
2026         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2027         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2028
2029         apic_timer_expired(apic);
2030
2031         if (lapic_is_periodic(apic)) {
2032                 advance_periodic_target_expiration(apic);
2033                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2034                 return HRTIMER_RESTART;
2035         } else
2036                 return HRTIMER_NORESTART;
2037 }
2038
2039 int kvm_create_lapic(struct kvm_vcpu *vcpu)
2040 {
2041         struct kvm_lapic *apic;
2042
2043         ASSERT(vcpu != NULL);
2044         apic_debug("apic_init %d\n", vcpu->vcpu_id);
2045
2046         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
2047         if (!apic)
2048                 goto nomem;
2049
2050         vcpu->arch.apic = apic;
2051
2052         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
2053         if (!apic->regs) {
2054                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2055                        vcpu->vcpu_id);
2056                 goto nomem_free_apic;
2057         }
2058         apic->vcpu = vcpu;
2059
2060         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2061                      HRTIMER_MODE_ABS_PINNED);
2062         apic->lapic_timer.timer.function = apic_timer_fn;
2063
2064         /*
2065          * APIC is created enabled. This will prevent kvm_lapic_set_base from
2066          * thinking that APIC satet has changed.
2067          */
2068         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2069         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2070         kvm_lapic_reset(vcpu, false);
2071         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2072
2073         return 0;
2074 nomem_free_apic:
2075         kfree(apic);
2076 nomem:
2077         return -ENOMEM;
2078 }
2079
2080 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2081 {
2082         struct kvm_lapic *apic = vcpu->arch.apic;
2083         u32 ppr;
2084
2085         if (!apic_enabled(apic))
2086                 return -1;
2087
2088         __apic_update_ppr(apic, &ppr);
2089         return apic_has_interrupt_for_ppr(apic, ppr);
2090 }
2091
2092 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2093 {
2094         u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2095         int r = 0;
2096
2097         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2098                 r = 1;
2099         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2100             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2101                 r = 1;
2102         return r;
2103 }
2104
2105 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2106 {
2107         struct kvm_lapic *apic = vcpu->arch.apic;
2108
2109         if (atomic_read(&apic->lapic_timer.pending) > 0) {
2110                 kvm_apic_local_deliver(apic, APIC_LVTT);
2111                 if (apic_lvtt_tscdeadline(apic))
2112                         apic->lapic_timer.tscdeadline = 0;
2113                 if (apic_lvtt_oneshot(apic)) {
2114                         apic->lapic_timer.tscdeadline = 0;
2115                         apic->lapic_timer.target_expiration = 0;
2116                 }
2117                 atomic_set(&apic->lapic_timer.pending, 0);
2118         }
2119 }
2120
2121 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2122 {
2123         int vector = kvm_apic_has_interrupt(vcpu);
2124         struct kvm_lapic *apic = vcpu->arch.apic;
2125         u32 ppr;
2126
2127         if (vector == -1)
2128                 return -1;
2129
2130         /*
2131          * We get here even with APIC virtualization enabled, if doing
2132          * nested virtualization and L1 runs with the "acknowledge interrupt
2133          * on exit" mode.  Then we cannot inject the interrupt via RVI,
2134          * because the process would deliver it through the IDT.
2135          */
2136
2137         apic_clear_irr(vector, apic);
2138         if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2139                 /*
2140                  * For auto-EOI interrupts, there might be another pending
2141                  * interrupt above PPR, so check whether to raise another
2142                  * KVM_REQ_EVENT.
2143                  */
2144                 apic_update_ppr(apic);
2145         } else {
2146                 /*
2147                  * For normal interrupts, PPR has been raised and there cannot
2148                  * be a higher-priority pending interrupt---except if there was
2149                  * a concurrent interrupt injection, but that would have
2150                  * triggered KVM_REQ_EVENT already.
2151                  */
2152                 apic_set_isr(vector, apic);
2153                 __apic_update_ppr(apic, &ppr);
2154         }
2155
2156         return vector;
2157 }
2158
2159 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2160                 struct kvm_lapic_state *s, bool set)
2161 {
2162         if (apic_x2apic_mode(vcpu->arch.apic)) {
2163                 u32 *id = (u32 *)(s->regs + APIC_ID);
2164
2165                 if (vcpu->kvm->arch.x2apic_format) {
2166                         if (*id != vcpu->vcpu_id)
2167                                 return -EINVAL;
2168                 } else {
2169                         if (set)
2170                                 *id >>= 24;
2171                         else
2172                                 *id <<= 24;
2173                 }
2174         }
2175
2176         return 0;
2177 }
2178
2179 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2180 {
2181         memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2182         return kvm_apic_state_fixup(vcpu, s, false);
2183 }
2184
2185 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2186 {
2187         struct kvm_lapic *apic = vcpu->arch.apic;
2188         int r;
2189
2190
2191         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2192         /* set SPIV separately to get count of SW disabled APICs right */
2193         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2194
2195         r = kvm_apic_state_fixup(vcpu, s, true);
2196         if (r)
2197                 return r;
2198         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2199
2200         recalculate_apic_map(vcpu->kvm);
2201         kvm_apic_set_version(vcpu);
2202
2203         apic_update_ppr(apic);
2204         hrtimer_cancel(&apic->lapic_timer.timer);
2205         apic_update_lvtt(apic);
2206         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2207         update_divide_count(apic);
2208         start_apic_timer(apic);
2209         apic->irr_pending = true;
2210         apic->isr_count = vcpu->arch.apicv_active ?
2211                                 1 : count_vectors(apic->regs + APIC_ISR);
2212         apic->highest_isr_cache = -1;
2213         if (vcpu->arch.apicv_active) {
2214                 kvm_x86_ops->apicv_post_state_restore(vcpu);
2215                 kvm_x86_ops->hwapic_irr_update(vcpu,
2216                                 apic_find_highest_irr(apic));
2217                 kvm_x86_ops->hwapic_isr_update(vcpu,
2218                                 apic_find_highest_isr(apic));
2219         }
2220         kvm_make_request(KVM_REQ_EVENT, vcpu);
2221         if (ioapic_in_kernel(vcpu->kvm))
2222                 kvm_rtc_eoi_tracking_restore_one(vcpu);
2223
2224         vcpu->arch.apic_arb_prio = 0;
2225
2226         return 0;
2227 }
2228
2229 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2230 {
2231         struct hrtimer *timer;
2232
2233         if (!lapic_in_kernel(vcpu))
2234                 return;
2235
2236         timer = &vcpu->arch.apic->lapic_timer.timer;
2237         if (hrtimer_cancel(timer))
2238                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
2239 }
2240
2241 /*
2242  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2243  *
2244  * Detect whether guest triggered PV EOI since the
2245  * last entry. If yes, set EOI on guests's behalf.
2246  * Clear PV EOI in guest memory in any case.
2247  */
2248 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2249                                         struct kvm_lapic *apic)
2250 {
2251         bool pending;
2252         int vector;
2253         /*
2254          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2255          * and KVM_PV_EOI_ENABLED in guest memory as follows:
2256          *
2257          * KVM_APIC_PV_EOI_PENDING is unset:
2258          *      -> host disabled PV EOI.
2259          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2260          *      -> host enabled PV EOI, guest did not execute EOI yet.
2261          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2262          *      -> host enabled PV EOI, guest executed EOI.
2263          */
2264         BUG_ON(!pv_eoi_enabled(vcpu));
2265         pending = pv_eoi_get_pending(vcpu);
2266         /*
2267          * Clear pending bit in any case: it will be set again on vmentry.
2268          * While this might not be ideal from performance point of view,
2269          * this makes sure pv eoi is only enabled when we know it's safe.
2270          */
2271         pv_eoi_clr_pending(vcpu);
2272         if (pending)
2273                 return;
2274         vector = apic_set_eoi(apic);
2275         trace_kvm_pv_eoi(apic, vector);
2276 }
2277
2278 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2279 {
2280         u32 data;
2281
2282         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2283                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2284
2285         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2286                 return;
2287
2288         if (kvm_vcpu_read_guest_cached(vcpu, &vcpu->arch.apic->vapic_cache, &data,
2289                                        sizeof(u32)))
2290                 return;
2291
2292         apic_set_tpr(vcpu->arch.apic, data & 0xff);
2293 }
2294
2295 /*
2296  * apic_sync_pv_eoi_to_guest - called before vmentry
2297  *
2298  * Detect whether it's safe to enable PV EOI and
2299  * if yes do so.
2300  */
2301 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2302                                         struct kvm_lapic *apic)
2303 {
2304         if (!pv_eoi_enabled(vcpu) ||
2305             /* IRR set or many bits in ISR: could be nested. */
2306             apic->irr_pending ||
2307             /* Cache not set: could be safe but we don't bother. */
2308             apic->highest_isr_cache == -1 ||
2309             /* Need EOI to update ioapic. */
2310             kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2311                 /*
2312                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2313                  * so we need not do anything here.
2314                  */
2315                 return;
2316         }
2317
2318         pv_eoi_set_pending(apic->vcpu);
2319 }
2320
2321 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2322 {
2323         u32 data, tpr;
2324         int max_irr, max_isr;
2325         struct kvm_lapic *apic = vcpu->arch.apic;
2326
2327         apic_sync_pv_eoi_to_guest(vcpu, apic);
2328
2329         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2330                 return;
2331
2332         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2333         max_irr = apic_find_highest_irr(apic);
2334         if (max_irr < 0)
2335                 max_irr = 0;
2336         max_isr = apic_find_highest_isr(apic);
2337         if (max_isr < 0)
2338                 max_isr = 0;
2339         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2340
2341         kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.apic->vapic_cache, &data,
2342                                     sizeof(u32));
2343 }
2344
2345 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2346 {
2347         if (vapic_addr) {
2348                 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu,
2349                                         &vcpu->arch.apic->vapic_cache,
2350                                         vapic_addr, sizeof(u32)))
2351                         return -EINVAL;
2352                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2353         } else {
2354                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2355         }
2356
2357         vcpu->arch.apic->vapic_addr = vapic_addr;
2358         return 0;
2359 }
2360
2361 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2362 {
2363         struct kvm_lapic *apic = vcpu->arch.apic;
2364         u32 reg = (msr - APIC_BASE_MSR) << 4;
2365
2366         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2367                 return 1;
2368
2369         if (reg == APIC_ICR2)
2370                 return 1;
2371
2372         /* if this is ICR write vector before command */
2373         if (reg == APIC_ICR)
2374                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2375         return kvm_lapic_reg_write(apic, reg, (u32)data);
2376 }
2377
2378 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2379 {
2380         struct kvm_lapic *apic = vcpu->arch.apic;
2381         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2382
2383         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2384                 return 1;
2385
2386         if (reg == APIC_DFR || reg == APIC_ICR2) {
2387                 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2388                            reg);
2389                 return 1;
2390         }
2391
2392         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2393                 return 1;
2394         if (reg == APIC_ICR)
2395                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2396
2397         *data = (((u64)high) << 32) | low;
2398
2399         return 0;
2400 }
2401
2402 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2403 {
2404         struct kvm_lapic *apic = vcpu->arch.apic;
2405
2406         if (!lapic_in_kernel(vcpu))
2407                 return 1;
2408
2409         /* if this is ICR write vector before command */
2410         if (reg == APIC_ICR)
2411                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2412         return kvm_lapic_reg_write(apic, reg, (u32)data);
2413 }
2414
2415 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2416 {
2417         struct kvm_lapic *apic = vcpu->arch.apic;
2418         u32 low, high = 0;
2419
2420         if (!lapic_in_kernel(vcpu))
2421                 return 1;
2422
2423         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2424                 return 1;
2425         if (reg == APIC_ICR)
2426                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2427
2428         *data = (((u64)high) << 32) | low;
2429
2430         return 0;
2431 }
2432
2433 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2434 {
2435         u64 addr = data & ~KVM_MSR_ENABLED;
2436         if (!IS_ALIGNED(addr, 4))
2437                 return 1;
2438
2439         vcpu->arch.pv_eoi.msr_val = data;
2440         if (!pv_eoi_enabled(vcpu))
2441                 return 0;
2442         return kvm_vcpu_gfn_to_hva_cache_init(vcpu, &vcpu->arch.pv_eoi.data,
2443                                          addr, sizeof(u8));
2444 }
2445
2446 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2447 {
2448         struct kvm_lapic *apic = vcpu->arch.apic;
2449         u8 sipi_vector;
2450         unsigned long pe;
2451
2452         if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2453                 return;
2454
2455         /*
2456          * INITs are latched while in SMM.  Because an SMM CPU cannot
2457          * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2458          * and delay processing of INIT until the next RSM.
2459          */
2460         if (is_smm(vcpu)) {
2461                 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2462                 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2463                         clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2464                 return;
2465         }
2466
2467         pe = xchg(&apic->pending_events, 0);
2468         if (test_bit(KVM_APIC_INIT, &pe)) {
2469                 kvm_lapic_reset(vcpu, true);
2470                 kvm_vcpu_reset(vcpu, true);
2471                 if (kvm_vcpu_is_bsp(apic->vcpu))
2472                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2473                 else
2474                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2475         }
2476         if (test_bit(KVM_APIC_SIPI, &pe) &&
2477             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2478                 /* evaluate pending_events before reading the vector */
2479                 smp_rmb();
2480                 sipi_vector = apic->sipi_vector;
2481                 apic_debug("vcpu %d received sipi with vector # %x\n",
2482                          vcpu->vcpu_id, sipi_vector);
2483                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2484                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2485         }
2486 }
2487
2488 void kvm_lapic_init(void)
2489 {
2490         /* do not patch jump label more than once per second */
2491         jump_label_rate_limit(&apic_hw_disabled, HZ);
2492         jump_label_rate_limit(&apic_sw_disabled, HZ);
2493 }
2494
2495 void kvm_lapic_exit(void)
2496 {
2497         static_key_deferred_flush(&apic_hw_disabled);
2498         static_key_deferred_flush(&apic_sw_disabled);
2499 }