3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <linux/atomic.h>
37 #include <linux/jump_label.h>
38 #include "kvm_cache_regs.h"
45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47 #define mod_64(x, y) ((x) % (y))
55 #define APIC_BUS_CYCLE_NS 1
57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58 #define apic_debug(fmt, arg...)
60 #define APIC_LVT_NUM 6
61 /* 14 is the version for Xeon and Pentium 8.4.8*/
62 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
63 #define LAPIC_MMIO_LENGTH (1 << 12)
64 /* followed define is not in apicdef.h */
65 #define APIC_SHORT_MASK 0xc0000
66 #define APIC_DEST_NOSHORT 0x0
67 #define APIC_DEST_MASK 0x800
68 #define MAX_APIC_VECTOR 256
69 #define APIC_VECTORS_PER_REG 32
71 #define APIC_BROADCAST 0xFF
72 #define X2APIC_BROADCAST 0xFFFFFFFFul
74 #define VEC_POS(v) ((v) & (32 - 1))
75 #define REG_POS(v) (((v) >> 5) << 4)
77 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
79 *((u32 *) (apic->regs + reg_off)) = val;
82 static inline int apic_test_vector(int vec, void *bitmap)
84 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
87 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
89 struct kvm_lapic *apic = vcpu->arch.apic;
91 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
92 apic_test_vector(vector, apic->regs + APIC_IRR);
95 static inline void apic_set_vector(int vec, void *bitmap)
97 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
100 static inline void apic_clear_vector(int vec, void *bitmap)
102 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
105 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
107 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
110 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
112 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
115 struct static_key_deferred apic_hw_disabled __read_mostly;
116 struct static_key_deferred apic_sw_disabled __read_mostly;
118 static inline int apic_enabled(struct kvm_lapic *apic)
120 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
124 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
127 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
128 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130 static inline int kvm_apic_id(struct kvm_lapic *apic)
132 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
135 #define KVM_X2APIC_CID_BITS 0
137 static void recalculate_apic_map(struct kvm *kvm)
139 struct kvm_apic_map *new, *old = NULL;
140 struct kvm_vcpu *vcpu;
143 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
145 mutex_lock(&kvm->arch.apic_map_lock);
151 /* flat mode is default */
154 new->lid_mask = 0xff;
155 new->broadcast = APIC_BROADCAST;
157 kvm_for_each_vcpu(i, vcpu, kvm) {
158 struct kvm_lapic *apic = vcpu->arch.apic;
162 if (!kvm_apic_present(vcpu))
166 * All APICs have to be configured in the same mode by an OS.
167 * We take advatage of this while building logical id loockup
168 * table. After reset APICs are in xapic/flat mode, so if we
169 * find apic with different setting we assume this is the mode
170 * OS wants all apics to be in; build lookup table accordingly.
172 if (apic_x2apic_mode(apic)) {
175 new->cid_mask = (1 << KVM_X2APIC_CID_BITS) - 1;
176 new->lid_mask = 0xffff;
177 new->broadcast = X2APIC_BROADCAST;
178 } else if (kvm_apic_sw_enabled(apic) &&
179 !new->cid_mask /* flat mode */ &&
180 kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_CLUSTER) {
186 new->phys_map[kvm_apic_id(apic)] = apic;
188 ldr = kvm_apic_get_reg(apic, APIC_LDR);
189 cid = apic_cluster_id(new, ldr);
190 lid = apic_logical_id(new, ldr);
193 new->logical_map[cid][ffs(lid) - 1] = apic;
196 old = rcu_dereference_protected(kvm->arch.apic_map,
197 lockdep_is_held(&kvm->arch.apic_map_lock));
198 rcu_assign_pointer(kvm->arch.apic_map, new);
199 mutex_unlock(&kvm->arch.apic_map_lock);
204 kvm_vcpu_request_scan_ioapic(kvm);
207 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
209 bool enabled = val & APIC_SPIV_APIC_ENABLED;
211 apic_set_reg(apic, APIC_SPIV, val);
213 if (enabled != apic->sw_enabled) {
214 apic->sw_enabled = enabled;
216 static_key_slow_dec_deferred(&apic_sw_disabled);
217 recalculate_apic_map(apic->vcpu->kvm);
219 static_key_slow_inc(&apic_sw_disabled.key);
223 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
225 apic_set_reg(apic, APIC_ID, id << 24);
226 recalculate_apic_map(apic->vcpu->kvm);
229 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
231 apic_set_reg(apic, APIC_LDR, id);
232 recalculate_apic_map(apic->vcpu->kvm);
235 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
237 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
240 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
242 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
245 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
247 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
250 static inline int apic_lvtt_period(struct kvm_lapic *apic)
252 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
255 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
257 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
260 static inline int apic_lvt_nmi_mode(u32 lvt_val)
262 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
265 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
267 struct kvm_lapic *apic = vcpu->arch.apic;
268 struct kvm_cpuid_entry2 *feat;
269 u32 v = APIC_VERSION;
271 if (!kvm_vcpu_has_lapic(vcpu))
274 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
275 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
276 v |= APIC_LVR_DIRECTED_EOI;
277 apic_set_reg(apic, APIC_LVR, v);
280 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
281 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
282 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
283 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
284 LINT_MASK, LINT_MASK, /* LVT0-1 */
285 LVT_MASK /* LVTERR */
288 static int find_highest_vector(void *bitmap)
293 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
294 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
295 reg = bitmap + REG_POS(vec);
297 return fls(*reg) - 1 + vec;
303 static u8 count_vectors(void *bitmap)
309 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
310 reg = bitmap + REG_POS(vec);
311 count += hweight32(*reg);
317 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
320 struct kvm_lapic *apic = vcpu->arch.apic;
322 for (i = 0; i <= 7; i++) {
323 pir_val = xchg(&pir[i], 0);
325 *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
328 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
330 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
332 apic->irr_pending = true;
333 apic_set_vector(vec, apic->regs + APIC_IRR);
336 static inline int apic_search_irr(struct kvm_lapic *apic)
338 return find_highest_vector(apic->regs + APIC_IRR);
341 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
346 * Note that irr_pending is just a hint. It will be always
347 * true with virtual interrupt delivery enabled.
349 if (!apic->irr_pending)
352 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
353 result = apic_search_irr(apic);
354 ASSERT(result == -1 || result >= 16);
359 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
361 struct kvm_vcpu *vcpu;
365 apic_clear_vector(vec, apic->regs + APIC_IRR);
366 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
367 /* try to update RVI */
368 kvm_make_request(KVM_REQ_EVENT, vcpu);
370 vec = apic_search_irr(apic);
371 apic->irr_pending = (vec != -1);
375 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
377 struct kvm_vcpu *vcpu;
379 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
385 * With APIC virtualization enabled, all caching is disabled
386 * because the processor can modify ISR under the hood. Instead
389 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
390 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
393 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
395 * ISR (in service register) bit is set when injecting an interrupt.
396 * The highest vector is injected. Thus the latest bit set matches
397 * the highest bit in ISR.
399 apic->highest_isr_cache = vec;
403 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
408 * Note that isr_count is always 1, and highest_isr_cache
409 * is always -1, with APIC virtualization enabled.
411 if (!apic->isr_count)
413 if (likely(apic->highest_isr_cache != -1))
414 return apic->highest_isr_cache;
416 result = find_highest_vector(apic->regs + APIC_ISR);
417 ASSERT(result == -1 || result >= 16);
422 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
424 struct kvm_vcpu *vcpu;
425 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
431 * We do get here for APIC virtualization enabled if the guest
432 * uses the Hyper-V APIC enlightenment. In this case we may need
433 * to trigger a new interrupt delivery by writing the SVI field;
434 * on the other hand isr_count and highest_isr_cache are unused
435 * and must be left alone.
437 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
438 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
439 apic_find_highest_isr(apic));
442 BUG_ON(apic->isr_count < 0);
443 apic->highest_isr_cache = -1;
447 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
451 /* This may race with setting of irr in __apic_accept_irq() and
452 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
453 * will cause vmexit immediately and the value will be recalculated
454 * on the next vmentry.
456 if (!kvm_vcpu_has_lapic(vcpu))
458 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
463 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
464 int vector, int level, int trig_mode,
465 unsigned long *dest_map);
467 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
468 unsigned long *dest_map)
470 struct kvm_lapic *apic = vcpu->arch.apic;
472 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
473 irq->level, irq->trig_mode, dest_map);
476 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
479 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
483 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
486 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
490 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
492 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
495 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
498 if (pv_eoi_get_user(vcpu, &val) < 0)
499 apic_debug("Can't read EOI MSR value: 0x%llx\n",
500 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
504 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
506 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
507 apic_debug("Can't set EOI MSR value: 0x%llx\n",
508 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
511 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
514 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
516 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
517 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
518 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
521 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
524 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
526 struct kvm_lapic *apic = vcpu->arch.apic;
529 for (i = 0; i < 8; i++)
530 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
533 static void apic_update_ppr(struct kvm_lapic *apic)
535 u32 tpr, isrv, ppr, old_ppr;
538 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
539 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
540 isr = apic_find_highest_isr(apic);
541 isrv = (isr != -1) ? isr : 0;
543 if ((tpr & 0xf0) >= (isrv & 0xf0))
548 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
549 apic, ppr, isr, isrv);
551 if (old_ppr != ppr) {
552 apic_set_reg(apic, APIC_PROCPRI, ppr);
554 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
558 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
560 apic_set_reg(apic, APIC_TASKPRI, tpr);
561 apic_update_ppr(apic);
564 static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
566 return dest == (apic_x2apic_mode(apic) ?
567 X2APIC_BROADCAST : APIC_BROADCAST);
570 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
572 return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
575 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
580 if (kvm_apic_broadcast(apic, mda))
583 if (apic_x2apic_mode(apic)) {
584 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
585 return logical_id & mda;
588 logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
590 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
592 if (logical_id & mda)
595 case APIC_DFR_CLUSTER:
596 if (((logical_id >> 4) == (mda >> 0x4))
597 && (logical_id & mda & 0xf))
601 apic_debug("Bad DFR vcpu %d: %08x\n",
602 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
609 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
610 int short_hand, unsigned int dest, int dest_mode)
613 struct kvm_lapic *target = vcpu->arch.apic;
615 apic_debug("target %p, source %p, dest 0x%x, "
616 "dest_mode 0x%x, short_hand 0x%x\n",
617 target, source, dest, dest_mode, short_hand);
620 switch (short_hand) {
621 case APIC_DEST_NOSHORT:
624 result = kvm_apic_match_physical_addr(target, dest);
627 result = kvm_apic_match_logical_addr(target, dest);
630 result = (target == source);
632 case APIC_DEST_ALLINC:
635 case APIC_DEST_ALLBUT:
636 result = (target != source);
639 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
647 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
648 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
650 struct kvm_apic_map *map;
651 unsigned long bitmap = 1;
652 struct kvm_lapic **dst;
658 if (irq->shorthand == APIC_DEST_SELF) {
659 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
667 map = rcu_dereference(kvm->arch.apic_map);
672 if (irq->dest_id == map->broadcast)
675 if (irq->dest_mode == 0) { /* physical mode */
676 if (irq->delivery_mode == APIC_DM_LOWEST)
678 dst = &map->phys_map[irq->dest_id & 0xff];
680 u32 mda = irq->dest_id << (32 - map->ldr_bits);
682 dst = map->logical_map[apic_cluster_id(map, mda)];
684 bitmap = apic_logical_id(map, mda);
686 if (irq->delivery_mode == APIC_DM_LOWEST) {
688 for_each_set_bit(i, &bitmap, 16) {
693 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
697 bitmap = (l >= 0) ? 1 << l : 0;
701 for_each_set_bit(i, &bitmap, 16) {
706 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
716 * Add a pending IRQ into lapic.
717 * Return 1 if successfully added and 0 if discarded.
719 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
720 int vector, int level, int trig_mode,
721 unsigned long *dest_map)
724 struct kvm_vcpu *vcpu = apic->vcpu;
726 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
728 switch (delivery_mode) {
730 vcpu->arch.apic_arb_prio++;
732 /* FIXME add logic for vcpu on reset */
733 if (unlikely(!apic_enabled(apic)))
739 __set_bit(vcpu->vcpu_id, dest_map);
741 if (kvm_x86_ops->deliver_posted_interrupt)
742 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
744 apic_set_irr(vector, apic);
746 kvm_make_request(KVM_REQ_EVENT, vcpu);
753 vcpu->arch.pv.pv_unhalted = 1;
754 kvm_make_request(KVM_REQ_EVENT, vcpu);
759 apic_debug("Ignoring guest SMI\n");
764 kvm_inject_nmi(vcpu);
769 if (!trig_mode || level) {
771 /* assumes that there are only KVM_APIC_INIT/SIPI */
772 apic->pending_events = (1UL << KVM_APIC_INIT);
773 /* make sure pending_events is visible before sending
776 kvm_make_request(KVM_REQ_EVENT, vcpu);
779 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
784 case APIC_DM_STARTUP:
785 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
786 vcpu->vcpu_id, vector);
788 apic->sipi_vector = vector;
789 /* make sure sipi_vector is visible for the receiver */
791 set_bit(KVM_APIC_SIPI, &apic->pending_events);
792 kvm_make_request(KVM_REQ_EVENT, vcpu);
798 * Should only be called by kvm_apic_local_deliver() with LVT0,
799 * before NMI watchdog was enabled. Already handled by
800 * kvm_apic_accept_pic_intr().
805 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
812 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
814 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
817 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
819 if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
820 kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
822 if (apic_test_vector(vector, apic->regs + APIC_TMR))
823 trigger_mode = IOAPIC_LEVEL_TRIG;
825 trigger_mode = IOAPIC_EDGE_TRIG;
826 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
830 static int apic_set_eoi(struct kvm_lapic *apic)
832 int vector = apic_find_highest_isr(apic);
834 trace_kvm_eoi(apic, vector);
837 * Not every write EOI will has corresponding ISR,
838 * one example is when Kernel check timer on setup_IO_APIC
843 apic_clear_isr(vector, apic);
844 apic_update_ppr(apic);
846 kvm_ioapic_send_eoi(apic, vector);
847 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
852 * this interface assumes a trap-like exit, which has already finished
853 * desired side effect including vISR and vPPR update.
855 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
857 struct kvm_lapic *apic = vcpu->arch.apic;
859 trace_kvm_eoi(apic, vector);
861 kvm_ioapic_send_eoi(apic, vector);
862 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
864 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
866 static void apic_send_ipi(struct kvm_lapic *apic)
868 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
869 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
870 struct kvm_lapic_irq irq;
872 irq.vector = icr_low & APIC_VECTOR_MASK;
873 irq.delivery_mode = icr_low & APIC_MODE_MASK;
874 irq.dest_mode = icr_low & APIC_DEST_MASK;
875 irq.level = icr_low & APIC_INT_ASSERT;
876 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
877 irq.shorthand = icr_low & APIC_SHORT_MASK;
878 if (apic_x2apic_mode(apic))
879 irq.dest_id = icr_high;
881 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
883 trace_kvm_apic_ipi(icr_low, irq.dest_id);
885 apic_debug("icr_high 0x%x, icr_low 0x%x, "
886 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
887 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
888 icr_high, icr_low, irq.shorthand, irq.dest_id,
889 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
892 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
895 static u32 apic_get_tmcct(struct kvm_lapic *apic)
901 ASSERT(apic != NULL);
903 /* if initial count is 0, current count should also be 0 */
904 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
905 apic->lapic_timer.period == 0)
908 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
909 if (ktime_to_ns(remaining) < 0)
910 remaining = ktime_set(0, 0);
912 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
913 tmcct = div64_u64(ns,
914 (APIC_BUS_CYCLE_NS * apic->divide_count));
919 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
921 struct kvm_vcpu *vcpu = apic->vcpu;
922 struct kvm_run *run = vcpu->run;
924 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
925 run->tpr_access.rip = kvm_rip_read(vcpu);
926 run->tpr_access.is_write = write;
929 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
931 if (apic->vcpu->arch.tpr_access_reporting)
932 __report_tpr_access(apic, write);
935 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
939 if (offset >= LAPIC_MMIO_LENGTH)
944 if (apic_x2apic_mode(apic))
945 val = kvm_apic_id(apic);
947 val = kvm_apic_id(apic) << 24;
950 apic_debug("Access APIC ARBPRI register which is for P6\n");
953 case APIC_TMCCT: /* Timer CCR */
954 if (apic_lvtt_tscdeadline(apic))
957 val = apic_get_tmcct(apic);
960 apic_update_ppr(apic);
961 val = kvm_apic_get_reg(apic, offset);
964 report_tpr_access(apic, false);
967 val = kvm_apic_get_reg(apic, offset);
974 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
976 return container_of(dev, struct kvm_lapic, dev);
979 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
982 unsigned char alignment = offset & 0xf;
984 /* this bitmask has a bit cleared for each reserved register */
985 static const u64 rmask = 0x43ff01ffffffe70cULL;
987 if ((alignment + len) > 4) {
988 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
993 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
994 apic_debug("KVM_APIC_READ: read reserved register %x\n",
999 result = __apic_read(apic, offset & ~0xf);
1001 trace_kvm_apic_read(offset, result);
1007 memcpy(data, (char *)&result + alignment, len);
1010 printk(KERN_ERR "Local APIC read with len = %x, "
1011 "should be 1,2, or 4 instead\n", len);
1017 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1019 return kvm_apic_hw_enabled(apic) &&
1020 addr >= apic->base_address &&
1021 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1024 static int apic_mmio_read(struct kvm_io_device *this,
1025 gpa_t address, int len, void *data)
1027 struct kvm_lapic *apic = to_lapic(this);
1028 u32 offset = address - apic->base_address;
1030 if (!apic_mmio_in_range(apic, address))
1033 apic_reg_read(apic, offset, len, data);
1038 static void update_divide_count(struct kvm_lapic *apic)
1040 u32 tmp1, tmp2, tdcr;
1042 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1044 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1045 apic->divide_count = 0x1 << (tmp2 & 0x7);
1047 apic_debug("timer divide count is 0x%x\n",
1048 apic->divide_count);
1051 static void apic_timer_expired(struct kvm_lapic *apic)
1053 struct kvm_vcpu *vcpu = apic->vcpu;
1054 wait_queue_head_t *q = &vcpu->wq;
1057 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1060 if (atomic_read(&apic->lapic_timer.pending))
1063 atomic_inc(&apic->lapic_timer.pending);
1064 /* FIXME: this code should not know anything about vcpus */
1065 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1067 if (waitqueue_active(q))
1068 wake_up_interruptible(q);
1071 static void start_apic_timer(struct kvm_lapic *apic)
1074 atomic_set(&apic->lapic_timer.pending, 0);
1076 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1077 /* lapic timer in oneshot or periodic mode */
1078 now = apic->lapic_timer.timer.base->get_time();
1079 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1080 * APIC_BUS_CYCLE_NS * apic->divide_count;
1082 if (!apic->lapic_timer.period)
1085 * Do not allow the guest to program periodic timers with small
1086 * interval, since the hrtimers are not throttled by the host
1089 if (apic_lvtt_period(apic)) {
1090 s64 min_period = min_timer_period_us * 1000LL;
1092 if (apic->lapic_timer.period < min_period) {
1093 pr_info_ratelimited(
1094 "kvm: vcpu %i: requested %lld ns "
1095 "lapic timer period limited to %lld ns\n",
1096 apic->vcpu->vcpu_id,
1097 apic->lapic_timer.period, min_period);
1098 apic->lapic_timer.period = min_period;
1102 hrtimer_start(&apic->lapic_timer.timer,
1103 ktime_add_ns(now, apic->lapic_timer.period),
1106 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1108 "timer initial count 0x%x, period %lldns, "
1109 "expire @ 0x%016" PRIx64 ".\n", __func__,
1110 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1111 kvm_apic_get_reg(apic, APIC_TMICT),
1112 apic->lapic_timer.period,
1113 ktime_to_ns(ktime_add_ns(now,
1114 apic->lapic_timer.period)));
1115 } else if (apic_lvtt_tscdeadline(apic)) {
1116 /* lapic timer in tsc deadline mode */
1117 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1119 struct kvm_vcpu *vcpu = apic->vcpu;
1120 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1121 unsigned long flags;
1123 if (unlikely(!tscdeadline || !this_tsc_khz))
1126 local_irq_save(flags);
1128 now = apic->lapic_timer.timer.base->get_time();
1129 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1130 if (likely(tscdeadline > guest_tsc)) {
1131 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1132 do_div(ns, this_tsc_khz);
1133 hrtimer_start(&apic->lapic_timer.timer,
1134 ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1136 apic_timer_expired(apic);
1138 local_irq_restore(flags);
1142 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1144 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1146 if (apic_lvt_nmi_mode(lvt0_val)) {
1147 if (!nmi_wd_enabled) {
1148 apic_debug("Receive NMI setting on APIC_LVT0 "
1149 "for cpu %d\n", apic->vcpu->vcpu_id);
1150 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1152 } else if (nmi_wd_enabled)
1153 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1156 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1160 trace_kvm_apic_write(reg, val);
1163 case APIC_ID: /* Local APIC ID */
1164 if (!apic_x2apic_mode(apic))
1165 kvm_apic_set_id(apic, val >> 24);
1171 report_tpr_access(apic, true);
1172 apic_set_tpr(apic, val & 0xff);
1180 if (!apic_x2apic_mode(apic))
1181 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1187 if (!apic_x2apic_mode(apic)) {
1188 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1189 recalculate_apic_map(apic->vcpu->kvm);
1196 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1197 mask |= APIC_SPIV_DIRECTED_EOI;
1198 apic_set_spiv(apic, val & mask);
1199 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1203 for (i = 0; i < APIC_LVT_NUM; i++) {
1204 lvt_val = kvm_apic_get_reg(apic,
1205 APIC_LVTT + 0x10 * i);
1206 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1207 lvt_val | APIC_LVT_MASKED);
1209 atomic_set(&apic->lapic_timer.pending, 0);
1215 /* No delay here, so we always clear the pending bit */
1216 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1217 apic_send_ipi(apic);
1221 if (!apic_x2apic_mode(apic))
1223 apic_set_reg(apic, APIC_ICR2, val);
1227 apic_manage_nmi_watchdog(apic, val);
1232 /* TODO: Check vector */
1233 if (!kvm_apic_sw_enabled(apic))
1234 val |= APIC_LVT_MASKED;
1236 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1237 apic_set_reg(apic, reg, val);
1242 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1244 if (apic->lapic_timer.timer_mode != timer_mode) {
1245 apic->lapic_timer.timer_mode = timer_mode;
1246 hrtimer_cancel(&apic->lapic_timer.timer);
1249 if (!kvm_apic_sw_enabled(apic))
1250 val |= APIC_LVT_MASKED;
1251 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1252 apic_set_reg(apic, APIC_LVTT, val);
1257 if (apic_lvtt_tscdeadline(apic))
1260 hrtimer_cancel(&apic->lapic_timer.timer);
1261 apic_set_reg(apic, APIC_TMICT, val);
1262 start_apic_timer(apic);
1267 apic_debug("KVM_WRITE:TDCR %x\n", val);
1268 apic_set_reg(apic, APIC_TDCR, val);
1269 update_divide_count(apic);
1273 if (apic_x2apic_mode(apic) && val != 0) {
1274 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1280 if (apic_x2apic_mode(apic)) {
1281 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1290 apic_debug("Local APIC Write to read-only register %x\n", reg);
1294 static int apic_mmio_write(struct kvm_io_device *this,
1295 gpa_t address, int len, const void *data)
1297 struct kvm_lapic *apic = to_lapic(this);
1298 unsigned int offset = address - apic->base_address;
1301 if (!apic_mmio_in_range(apic, address))
1305 * APIC register must be aligned on 128-bits boundary.
1306 * 32/64/128 bits registers must be accessed thru 32 bits.
1309 if (len != 4 || (offset & 0xf)) {
1310 /* Don't shout loud, $infamous_os would cause only noise. */
1311 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1317 /* too common printing */
1318 if (offset != APIC_EOI)
1319 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1320 "0x%x\n", __func__, offset, len, val);
1322 apic_reg_write(apic, offset & 0xff0, val);
1327 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1329 if (kvm_vcpu_has_lapic(vcpu))
1330 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1332 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1334 /* emulate APIC access in a trap manner */
1335 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1339 /* hw has done the conditional check and inst decode */
1342 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1344 /* TODO: optimize to just emulate side effect w/o one more write */
1345 apic_reg_write(vcpu->arch.apic, offset, val);
1347 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1349 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1351 struct kvm_lapic *apic = vcpu->arch.apic;
1353 if (!vcpu->arch.apic)
1356 hrtimer_cancel(&apic->lapic_timer.timer);
1358 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1359 static_key_slow_dec_deferred(&apic_hw_disabled);
1361 if (!apic->sw_enabled)
1362 static_key_slow_dec_deferred(&apic_sw_disabled);
1365 free_page((unsigned long)apic->regs);
1371 *----------------------------------------------------------------------
1373 *----------------------------------------------------------------------
1376 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1378 struct kvm_lapic *apic = vcpu->arch.apic;
1380 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1381 apic_lvtt_period(apic))
1384 return apic->lapic_timer.tscdeadline;
1387 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1389 struct kvm_lapic *apic = vcpu->arch.apic;
1391 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1392 apic_lvtt_period(apic))
1395 hrtimer_cancel(&apic->lapic_timer.timer);
1396 apic->lapic_timer.tscdeadline = data;
1397 start_apic_timer(apic);
1400 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1402 struct kvm_lapic *apic = vcpu->arch.apic;
1404 if (!kvm_vcpu_has_lapic(vcpu))
1407 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1408 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1411 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1415 if (!kvm_vcpu_has_lapic(vcpu))
1418 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1420 return (tpr & 0xf0) >> 4;
1423 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1425 u64 old_value = vcpu->arch.apic_base;
1426 struct kvm_lapic *apic = vcpu->arch.apic;
1429 value |= MSR_IA32_APICBASE_BSP;
1430 vcpu->arch.apic_base = value;
1434 if (!kvm_vcpu_is_bsp(apic->vcpu))
1435 value &= ~MSR_IA32_APICBASE_BSP;
1436 vcpu->arch.apic_base = value;
1438 /* update jump label if enable bit changes */
1439 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1440 if (value & MSR_IA32_APICBASE_ENABLE)
1441 static_key_slow_dec_deferred(&apic_hw_disabled);
1443 static_key_slow_inc(&apic_hw_disabled.key);
1444 recalculate_apic_map(vcpu->kvm);
1447 if ((old_value ^ value) & X2APIC_ENABLE) {
1448 if (value & X2APIC_ENABLE) {
1449 u32 id = kvm_apic_id(apic);
1450 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1451 kvm_apic_set_ldr(apic, ldr);
1452 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1454 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1457 apic->base_address = apic->vcpu->arch.apic_base &
1458 MSR_IA32_APICBASE_BASE;
1460 /* with FSB delivery interrupt, we can restart APIC functionality */
1461 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1462 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1466 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1468 struct kvm_lapic *apic;
1471 apic_debug("%s\n", __func__);
1474 apic = vcpu->arch.apic;
1475 ASSERT(apic != NULL);
1477 /* Stop the timer in case it's a reset to an active apic */
1478 hrtimer_cancel(&apic->lapic_timer.timer);
1480 kvm_apic_set_id(apic, vcpu->vcpu_id);
1481 kvm_apic_set_version(apic->vcpu);
1483 for (i = 0; i < APIC_LVT_NUM; i++)
1484 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1485 apic->lapic_timer.timer_mode = 0;
1486 apic_set_reg(apic, APIC_LVT0,
1487 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1489 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1490 apic_set_spiv(apic, 0xff);
1491 apic_set_reg(apic, APIC_TASKPRI, 0);
1492 kvm_apic_set_ldr(apic, 0);
1493 apic_set_reg(apic, APIC_ESR, 0);
1494 apic_set_reg(apic, APIC_ICR, 0);
1495 apic_set_reg(apic, APIC_ICR2, 0);
1496 apic_set_reg(apic, APIC_TDCR, 0);
1497 apic_set_reg(apic, APIC_TMICT, 0);
1498 for (i = 0; i < 8; i++) {
1499 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1500 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1501 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1503 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1504 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1505 apic->highest_isr_cache = -1;
1506 update_divide_count(apic);
1507 atomic_set(&apic->lapic_timer.pending, 0);
1508 if (kvm_vcpu_is_bsp(vcpu))
1509 kvm_lapic_set_base(vcpu,
1510 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1511 vcpu->arch.pv_eoi.msr_val = 0;
1512 apic_update_ppr(apic);
1514 vcpu->arch.apic_arb_prio = 0;
1515 vcpu->arch.apic_attention = 0;
1517 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1518 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1519 vcpu, kvm_apic_id(apic),
1520 vcpu->arch.apic_base, apic->base_address);
1524 *----------------------------------------------------------------------
1526 *----------------------------------------------------------------------
1529 static bool lapic_is_periodic(struct kvm_lapic *apic)
1531 return apic_lvtt_period(apic);
1534 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1536 struct kvm_lapic *apic = vcpu->arch.apic;
1538 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1539 apic_lvt_enabled(apic, APIC_LVTT))
1540 return atomic_read(&apic->lapic_timer.pending);
1545 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1547 u32 reg = kvm_apic_get_reg(apic, lvt_type);
1548 int vector, mode, trig_mode;
1550 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1551 vector = reg & APIC_VECTOR_MASK;
1552 mode = reg & APIC_MODE_MASK;
1553 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1554 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1560 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1562 struct kvm_lapic *apic = vcpu->arch.apic;
1565 kvm_apic_local_deliver(apic, APIC_LVT0);
1568 static const struct kvm_io_device_ops apic_mmio_ops = {
1569 .read = apic_mmio_read,
1570 .write = apic_mmio_write,
1573 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1575 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1576 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1578 apic_timer_expired(apic);
1580 if (lapic_is_periodic(apic)) {
1581 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1582 return HRTIMER_RESTART;
1584 return HRTIMER_NORESTART;
1587 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1589 struct kvm_lapic *apic;
1591 ASSERT(vcpu != NULL);
1592 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1594 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1598 vcpu->arch.apic = apic;
1600 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1602 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1604 goto nomem_free_apic;
1608 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1610 apic->lapic_timer.timer.function = apic_timer_fn;
1613 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1614 * thinking that APIC satet has changed.
1616 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1617 kvm_lapic_set_base(vcpu,
1618 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1620 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1621 kvm_lapic_reset(vcpu);
1622 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1631 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1633 struct kvm_lapic *apic = vcpu->arch.apic;
1636 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1639 apic_update_ppr(apic);
1640 highest_irr = apic_find_highest_irr(apic);
1641 if ((highest_irr == -1) ||
1642 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1647 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1649 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1652 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1654 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1655 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1660 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1662 struct kvm_lapic *apic = vcpu->arch.apic;
1664 if (!kvm_vcpu_has_lapic(vcpu))
1667 if (atomic_read(&apic->lapic_timer.pending) > 0) {
1668 kvm_apic_local_deliver(apic, APIC_LVTT);
1669 if (apic_lvtt_tscdeadline(apic))
1670 apic->lapic_timer.tscdeadline = 0;
1671 atomic_set(&apic->lapic_timer.pending, 0);
1675 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1677 int vector = kvm_apic_has_interrupt(vcpu);
1678 struct kvm_lapic *apic = vcpu->arch.apic;
1684 * We get here even with APIC virtualization enabled, if doing
1685 * nested virtualization and L1 runs with the "acknowledge interrupt
1686 * on exit" mode. Then we cannot inject the interrupt via RVI,
1687 * because the process would deliver it through the IDT.
1690 apic_set_isr(vector, apic);
1691 apic_update_ppr(apic);
1692 apic_clear_irr(vector, apic);
1696 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1697 struct kvm_lapic_state *s)
1699 struct kvm_lapic *apic = vcpu->arch.apic;
1701 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1702 /* set SPIV separately to get count of SW disabled APICs right */
1703 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1704 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1705 /* call kvm_apic_set_id() to put apic into apic_map */
1706 kvm_apic_set_id(apic, kvm_apic_id(apic));
1707 kvm_apic_set_version(vcpu);
1709 apic_update_ppr(apic);
1710 hrtimer_cancel(&apic->lapic_timer.timer);
1711 update_divide_count(apic);
1712 start_apic_timer(apic);
1713 apic->irr_pending = true;
1714 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1715 1 : count_vectors(apic->regs + APIC_ISR);
1716 apic->highest_isr_cache = -1;
1717 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
1718 kvm_make_request(KVM_REQ_EVENT, vcpu);
1719 kvm_rtc_eoi_tracking_restore_one(vcpu);
1722 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1724 struct hrtimer *timer;
1726 if (!kvm_vcpu_has_lapic(vcpu))
1729 timer = &vcpu->arch.apic->lapic_timer.timer;
1730 if (hrtimer_cancel(timer))
1731 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1735 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1737 * Detect whether guest triggered PV EOI since the
1738 * last entry. If yes, set EOI on guests's behalf.
1739 * Clear PV EOI in guest memory in any case.
1741 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1742 struct kvm_lapic *apic)
1747 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1748 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1750 * KVM_APIC_PV_EOI_PENDING is unset:
1751 * -> host disabled PV EOI.
1752 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1753 * -> host enabled PV EOI, guest did not execute EOI yet.
1754 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1755 * -> host enabled PV EOI, guest executed EOI.
1757 BUG_ON(!pv_eoi_enabled(vcpu));
1758 pending = pv_eoi_get_pending(vcpu);
1760 * Clear pending bit in any case: it will be set again on vmentry.
1761 * While this might not be ideal from performance point of view,
1762 * this makes sure pv eoi is only enabled when we know it's safe.
1764 pv_eoi_clr_pending(vcpu);
1767 vector = apic_set_eoi(apic);
1768 trace_kvm_pv_eoi(apic, vector);
1771 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1775 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1776 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1778 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1781 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1784 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1788 * apic_sync_pv_eoi_to_guest - called before vmentry
1790 * Detect whether it's safe to enable PV EOI and
1793 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1794 struct kvm_lapic *apic)
1796 if (!pv_eoi_enabled(vcpu) ||
1797 /* IRR set or many bits in ISR: could be nested. */
1798 apic->irr_pending ||
1799 /* Cache not set: could be safe but we don't bother. */
1800 apic->highest_isr_cache == -1 ||
1801 /* Need EOI to update ioapic. */
1802 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1804 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1805 * so we need not do anything here.
1810 pv_eoi_set_pending(apic->vcpu);
1813 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1816 int max_irr, max_isr;
1817 struct kvm_lapic *apic = vcpu->arch.apic;
1819 apic_sync_pv_eoi_to_guest(vcpu, apic);
1821 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1824 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1825 max_irr = apic_find_highest_irr(apic);
1828 max_isr = apic_find_highest_isr(apic);
1831 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1833 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1837 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1840 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1841 &vcpu->arch.apic->vapic_cache,
1842 vapic_addr, sizeof(u32)))
1844 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1846 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1849 vcpu->arch.apic->vapic_addr = vapic_addr;
1853 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1855 struct kvm_lapic *apic = vcpu->arch.apic;
1856 u32 reg = (msr - APIC_BASE_MSR) << 4;
1858 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1861 /* if this is ICR write vector before command */
1863 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1864 return apic_reg_write(apic, reg, (u32)data);
1867 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1869 struct kvm_lapic *apic = vcpu->arch.apic;
1870 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1872 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1875 if (apic_reg_read(apic, reg, 4, &low))
1878 apic_reg_read(apic, APIC_ICR2, 4, &high);
1880 *data = (((u64)high) << 32) | low;
1885 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1887 struct kvm_lapic *apic = vcpu->arch.apic;
1889 if (!kvm_vcpu_has_lapic(vcpu))
1892 /* if this is ICR write vector before command */
1893 if (reg == APIC_ICR)
1894 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1895 return apic_reg_write(apic, reg, (u32)data);
1898 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1900 struct kvm_lapic *apic = vcpu->arch.apic;
1903 if (!kvm_vcpu_has_lapic(vcpu))
1906 if (apic_reg_read(apic, reg, 4, &low))
1908 if (reg == APIC_ICR)
1909 apic_reg_read(apic, APIC_ICR2, 4, &high);
1911 *data = (((u64)high) << 32) | low;
1916 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1918 u64 addr = data & ~KVM_MSR_ENABLED;
1919 if (!IS_ALIGNED(addr, 4))
1922 vcpu->arch.pv_eoi.msr_val = data;
1923 if (!pv_eoi_enabled(vcpu))
1925 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1929 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
1931 struct kvm_lapic *apic = vcpu->arch.apic;
1932 unsigned int sipi_vector;
1935 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
1938 pe = xchg(&apic->pending_events, 0);
1940 if (test_bit(KVM_APIC_INIT, &pe)) {
1941 kvm_lapic_reset(vcpu);
1942 kvm_vcpu_reset(vcpu);
1943 if (kvm_vcpu_is_bsp(apic->vcpu))
1944 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1946 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
1948 if (test_bit(KVM_APIC_SIPI, &pe) &&
1949 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
1950 /* evaluate pending_events before reading the vector */
1952 sipi_vector = apic->sipi_vector;
1953 apic_debug("vcpu %d received sipi with vector # %x\n",
1954 vcpu->vcpu_id, sipi_vector);
1955 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
1956 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1960 void kvm_lapic_init(void)
1962 /* do not patch jump label more than once per second */
1963 jump_label_rate_limit(&apic_hw_disabled, HZ);
1964 jump_label_rate_limit(&apic_sw_disabled, HZ);