3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
20 #include <linux/kvm_host.h>
21 #include <linux/kvm.h>
23 #include <linux/highmem.h>
24 #include <linux/smp.h>
25 #include <linux/hrtimer.h>
27 #include <linux/module.h>
28 #include <linux/math64.h>
29 #include <asm/processor.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/atomic.h>
35 #include "kvm_cache_regs.h"
39 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
41 #define mod_64(x, y) ((x) % (y))
49 #define APIC_BUS_CYCLE_NS 1
51 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
52 #define apic_debug(fmt, arg...)
54 #define APIC_LVT_NUM 6
55 /* 14 is the version for Xeon and Pentium 8.4.8*/
56 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
57 #define LAPIC_MMIO_LENGTH (1 << 12)
58 /* followed define is not in apicdef.h */
59 #define APIC_SHORT_MASK 0xc0000
60 #define APIC_DEST_NOSHORT 0x0
61 #define APIC_DEST_MASK 0x800
62 #define MAX_APIC_VECTOR 256
64 #define VEC_POS(v) ((v) & (32 - 1))
65 #define REG_POS(v) (((v) >> 5) << 4)
67 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
69 return *((u32 *) (apic->regs + reg_off));
72 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
74 *((u32 *) (apic->regs + reg_off)) = val;
77 static inline int apic_test_and_set_vector(int vec, void *bitmap)
79 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
82 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
84 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
87 static inline void apic_set_vector(int vec, void *bitmap)
89 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
92 static inline void apic_clear_vector(int vec, void *bitmap)
94 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
97 static inline int apic_hw_enabled(struct kvm_lapic *apic)
99 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
102 static inline int apic_sw_enabled(struct kvm_lapic *apic)
104 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
107 static inline int apic_enabled(struct kvm_lapic *apic)
109 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
113 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
116 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
117 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
119 static inline int kvm_apic_id(struct kvm_lapic *apic)
121 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
124 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
126 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
129 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
131 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
134 static inline int apic_lvtt_period(struct kvm_lapic *apic)
136 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
139 static inline int apic_lvt_nmi_mode(u32 lvt_val)
141 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
144 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
145 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
146 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
147 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
148 LINT_MASK, LINT_MASK, /* LVT0-1 */
149 LVT_MASK /* LVTERR */
152 static int find_highest_vector(void *bitmap)
155 int word_offset = MAX_APIC_VECTOR >> 5;
157 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
160 if (likely(!word_offset && !word[0]))
163 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
166 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
168 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
171 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
173 apic_clear_vector(vec, apic->regs + APIC_IRR);
176 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
180 result = find_highest_vector(apic->regs + APIC_IRR);
181 ASSERT(result == -1 || result >= 16);
186 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
188 struct kvm_lapic *apic = vcpu->arch.apic;
193 highest_irr = apic_find_highest_irr(apic);
197 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
199 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig)
201 struct kvm_lapic *apic = vcpu->arch.apic;
203 if (!apic_test_and_set_irr(vec, apic)) {
204 /* a new pending irq is set in IRR */
206 apic_set_vector(vec, apic->regs + APIC_TMR);
208 apic_clear_vector(vec, apic->regs + APIC_TMR);
209 kvm_vcpu_kick(apic->vcpu);
215 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
219 result = find_highest_vector(apic->regs + APIC_ISR);
220 ASSERT(result == -1 || result >= 16);
225 static void apic_update_ppr(struct kvm_lapic *apic)
230 tpr = apic_get_reg(apic, APIC_TASKPRI);
231 isr = apic_find_highest_isr(apic);
232 isrv = (isr != -1) ? isr : 0;
234 if ((tpr & 0xf0) >= (isrv & 0xf0))
239 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
240 apic, ppr, isr, isrv);
242 apic_set_reg(apic, APIC_PROCPRI, ppr);
245 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
247 apic_set_reg(apic, APIC_TASKPRI, tpr);
248 apic_update_ppr(apic);
251 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
253 return kvm_apic_id(apic) == dest;
256 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
261 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
263 switch (apic_get_reg(apic, APIC_DFR)) {
265 if (logical_id & mda)
268 case APIC_DFR_CLUSTER:
269 if (((logical_id >> 4) == (mda >> 0x4))
270 && (logical_id & mda & 0xf))
274 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
275 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
282 static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
283 int short_hand, int dest, int dest_mode)
286 struct kvm_lapic *target = vcpu->arch.apic;
288 apic_debug("target %p, source %p, dest 0x%x, "
289 "dest_mode 0x%x, short_hand 0x%x",
290 target, source, dest, dest_mode, short_hand);
293 switch (short_hand) {
294 case APIC_DEST_NOSHORT:
295 if (dest_mode == 0) {
297 if ((dest == 0xFF) || (dest == kvm_apic_id(target)))
301 result = kvm_apic_match_logical_addr(target, dest);
304 if (target == source)
307 case APIC_DEST_ALLINC:
310 case APIC_DEST_ALLBUT:
311 if (target != source)
315 printk(KERN_WARNING "Bad dest shorthand value %x\n",
324 * Add a pending IRQ into lapic.
325 * Return 1 if successfully added and 0 if discarded.
327 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
328 int vector, int level, int trig_mode)
330 int orig_irr, result = 0;
331 struct kvm_vcpu *vcpu = apic->vcpu;
333 switch (delivery_mode) {
336 /* FIXME add logic for vcpu on reset */
337 if (unlikely(!apic_enabled(apic)))
340 orig_irr = apic_test_and_set_irr(vector, apic);
341 if (orig_irr && trig_mode) {
342 apic_debug("level trig mode repeatedly for vector %d",
348 apic_debug("level trig mode for vector %d", vector);
349 apic_set_vector(vector, apic->regs + APIC_TMR);
351 apic_clear_vector(vector, apic->regs + APIC_TMR);
355 result = (orig_irr == 0);
359 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
363 printk(KERN_DEBUG "Ignoring guest SMI\n");
367 kvm_inject_nmi(vcpu);
373 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
375 "INIT on a runnable vcpu %d\n",
377 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
380 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
385 case APIC_DM_STARTUP:
386 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
387 vcpu->vcpu_id, vector);
388 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
389 vcpu->arch.sipi_vector = vector;
390 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
397 * Should only be called by kvm_apic_local_deliver() with LVT0,
398 * before NMI watchdog was enabled. Already handled by
399 * kvm_apic_accept_pic_intr().
404 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
411 static struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
412 unsigned long *bitmap)
416 struct kvm_lapic *apic = NULL;
418 last = kvm->arch.round_robin_prev_vcpu;
422 if (++next == KVM_MAX_VCPUS)
424 if (kvm->vcpus[next] == NULL || !test_bit(next, bitmap))
426 apic = kvm->vcpus[next]->arch.apic;
427 if (apic && apic_enabled(apic))
430 } while (next != last);
431 kvm->arch.round_robin_prev_vcpu = next;
434 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
439 struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector,
440 unsigned long *bitmap)
442 struct kvm_lapic *apic;
444 apic = kvm_apic_round_robin(kvm, vector, bitmap);
450 static void apic_set_eoi(struct kvm_lapic *apic)
452 int vector = apic_find_highest_isr(apic);
455 * Not every write EOI will has corresponding ISR,
456 * one example is when Kernel check timer on setup_IO_APIC
461 apic_clear_vector(vector, apic->regs + APIC_ISR);
462 apic_update_ppr(apic);
464 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
465 trigger_mode = IOAPIC_LEVEL_TRIG;
467 trigger_mode = IOAPIC_EDGE_TRIG;
468 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
471 static void apic_send_ipi(struct kvm_lapic *apic)
473 u32 icr_low = apic_get_reg(apic, APIC_ICR);
474 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
476 unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
477 unsigned int short_hand = icr_low & APIC_SHORT_MASK;
478 unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
479 unsigned int level = icr_low & APIC_INT_ASSERT;
480 unsigned int dest_mode = icr_low & APIC_DEST_MASK;
481 unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
482 unsigned int vector = icr_low & APIC_VECTOR_MASK;
484 struct kvm_vcpu *target;
485 struct kvm_vcpu *vcpu;
486 DECLARE_BITMAP(lpr_map, KVM_MAX_VCPUS);
489 bitmap_zero(lpr_map, KVM_MAX_VCPUS);
490 apic_debug("icr_high 0x%x, icr_low 0x%x, "
491 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
492 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
493 icr_high, icr_low, short_hand, dest,
494 trig_mode, level, dest_mode, delivery_mode, vector);
496 for (i = 0; i < KVM_MAX_VCPUS; i++) {
497 vcpu = apic->vcpu->kvm->vcpus[i];
501 if (vcpu->arch.apic &&
502 apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) {
503 if (delivery_mode == APIC_DM_LOWEST)
504 __set_bit(vcpu->vcpu_id, lpr_map);
506 __apic_accept_irq(vcpu->arch.apic, delivery_mode,
507 vector, level, trig_mode);
511 if (delivery_mode == APIC_DM_LOWEST) {
512 target = kvm_get_lowest_prio_vcpu(vcpu->kvm, vector, lpr_map);
514 __apic_accept_irq(target->arch.apic, delivery_mode,
515 vector, level, trig_mode);
519 static u32 apic_get_tmcct(struct kvm_lapic *apic)
525 ASSERT(apic != NULL);
527 /* if initial count is 0, current count should also be 0 */
528 if (apic_get_reg(apic, APIC_TMICT) == 0)
531 remaining = hrtimer_expires_remaining(&apic->lapic_timer.timer);
532 if (ktime_to_ns(remaining) < 0)
533 remaining = ktime_set(0, 0);
535 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
536 tmcct = div64_u64(ns,
537 (APIC_BUS_CYCLE_NS * apic->divide_count));
542 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
544 struct kvm_vcpu *vcpu = apic->vcpu;
545 struct kvm_run *run = vcpu->run;
547 set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
548 run->tpr_access.rip = kvm_rip_read(vcpu);
549 run->tpr_access.is_write = write;
552 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
554 if (apic->vcpu->arch.tpr_access_reporting)
555 __report_tpr_access(apic, write);
558 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
562 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
564 if (offset >= LAPIC_MMIO_LENGTH)
569 printk(KERN_WARNING "Access APIC ARBPRI register "
570 "which is for P6\n");
573 case APIC_TMCCT: /* Timer CCR */
574 val = apic_get_tmcct(apic);
578 report_tpr_access(apic, false);
581 apic_update_ppr(apic);
582 val = apic_get_reg(apic, offset);
589 static void apic_mmio_read(struct kvm_io_device *this,
590 gpa_t address, int len, void *data)
592 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
593 unsigned int offset = address - apic->base_address;
594 unsigned char alignment = offset & 0xf;
597 if ((alignment + len) > 4) {
598 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
599 (unsigned long)address, len);
602 result = __apic_read(apic, offset & ~0xf);
608 memcpy(data, (char *)&result + alignment, len);
611 printk(KERN_ERR "Local APIC read with len = %x, "
612 "should be 1,2, or 4 instead\n", len);
617 static void update_divide_count(struct kvm_lapic *apic)
619 u32 tmp1, tmp2, tdcr;
621 tdcr = apic_get_reg(apic, APIC_TDCR);
623 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
624 apic->divide_count = 0x1 << (tmp2 & 0x7);
626 apic_debug("timer divide count is 0x%x\n",
627 apic->lapic_timer.divide_count);
630 static void start_apic_timer(struct kvm_lapic *apic)
632 ktime_t now = apic->lapic_timer.timer.base->get_time();
634 apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) *
635 APIC_BUS_CYCLE_NS * apic->divide_count;
636 atomic_set(&apic->lapic_timer.pending, 0);
638 if (!apic->lapic_timer.period)
641 hrtimer_start(&apic->lapic_timer.timer,
642 ktime_add_ns(now, apic->lapic_timer.period),
645 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
647 "timer initial count 0x%x, period %lldns, "
648 "expire @ 0x%016" PRIx64 ".\n", __func__,
649 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
650 apic_get_reg(apic, APIC_TMICT),
651 apic->lapic_timer.period,
652 ktime_to_ns(ktime_add_ns(now,
653 apic->lapic_timer.period)));
656 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
658 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
660 if (apic_lvt_nmi_mode(lvt0_val)) {
661 if (!nmi_wd_enabled) {
662 apic_debug("Receive NMI setting on APIC_LVT0 "
663 "for cpu %d\n", apic->vcpu->vcpu_id);
664 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
666 } else if (nmi_wd_enabled)
667 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
670 static void apic_mmio_write(struct kvm_io_device *this,
671 gpa_t address, int len, const void *data)
673 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
674 unsigned int offset = address - apic->base_address;
675 unsigned char alignment = offset & 0xf;
679 * APIC register must be aligned on 128-bits boundary.
680 * 32/64/128 bits registers must be accessed thru 32 bits.
683 if (len != 4 || alignment) {
684 /* Don't shout loud, $infamous_os would cause only noise. */
685 apic_debug("apic write: bad size=%d %lx\n",
692 /* too common printing */
693 if (offset != APIC_EOI)
694 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
695 "0x%x\n", __func__, offset, len, val);
699 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
702 case APIC_ID: /* Local APIC ID */
703 apic_set_reg(apic, APIC_ID, val);
707 report_tpr_access(apic, true);
708 apic_set_tpr(apic, val & 0xff);
716 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
720 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
724 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
725 if (!(val & APIC_SPIV_APIC_ENABLED)) {
729 for (i = 0; i < APIC_LVT_NUM; i++) {
730 lvt_val = apic_get_reg(apic,
731 APIC_LVTT + 0x10 * i);
732 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
733 lvt_val | APIC_LVT_MASKED);
735 atomic_set(&apic->lapic_timer.pending, 0);
741 /* No delay here, so we always clear the pending bit */
742 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
747 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
751 apic_manage_nmi_watchdog(apic, val);
757 /* TODO: Check vector */
758 if (!apic_sw_enabled(apic))
759 val |= APIC_LVT_MASKED;
761 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
762 apic_set_reg(apic, offset, val);
767 hrtimer_cancel(&apic->lapic_timer.timer);
768 apic_set_reg(apic, APIC_TMICT, val);
769 start_apic_timer(apic);
774 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
775 apic_set_reg(apic, APIC_TDCR, val);
776 update_divide_count(apic);
780 apic_debug("Local APIC Write to read-only register %x\n",
787 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
790 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
794 if (apic_hw_enabled(apic) &&
795 (addr >= apic->base_address) &&
796 (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
802 void kvm_free_lapic(struct kvm_vcpu *vcpu)
804 if (!vcpu->arch.apic)
807 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
809 if (vcpu->arch.apic->regs_page)
810 __free_page(vcpu->arch.apic->regs_page);
812 kfree(vcpu->arch.apic);
816 *----------------------------------------------------------------------
818 *----------------------------------------------------------------------
821 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
823 struct kvm_lapic *apic = vcpu->arch.apic;
827 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
828 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
830 EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr);
832 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
834 struct kvm_lapic *apic = vcpu->arch.apic;
839 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
841 return (tpr & 0xf0) >> 4;
843 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
845 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
847 struct kvm_lapic *apic = vcpu->arch.apic;
850 value |= MSR_IA32_APICBASE_BSP;
851 vcpu->arch.apic_base = value;
854 if (apic->vcpu->vcpu_id)
855 value &= ~MSR_IA32_APICBASE_BSP;
857 vcpu->arch.apic_base = value;
858 apic->base_address = apic->vcpu->arch.apic_base &
859 MSR_IA32_APICBASE_BASE;
861 /* with FSB delivery interrupt, we can restart APIC functionality */
862 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
863 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
867 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
869 return vcpu->arch.apic_base;
871 EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
873 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
875 struct kvm_lapic *apic;
878 apic_debug("%s\n", __func__);
881 apic = vcpu->arch.apic;
882 ASSERT(apic != NULL);
884 /* Stop the timer in case it's a reset to an active apic */
885 hrtimer_cancel(&apic->lapic_timer.timer);
887 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
888 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
890 for (i = 0; i < APIC_LVT_NUM; i++)
891 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
892 apic_set_reg(apic, APIC_LVT0,
893 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
895 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
896 apic_set_reg(apic, APIC_SPIV, 0xff);
897 apic_set_reg(apic, APIC_TASKPRI, 0);
898 apic_set_reg(apic, APIC_LDR, 0);
899 apic_set_reg(apic, APIC_ESR, 0);
900 apic_set_reg(apic, APIC_ICR, 0);
901 apic_set_reg(apic, APIC_ICR2, 0);
902 apic_set_reg(apic, APIC_TDCR, 0);
903 apic_set_reg(apic, APIC_TMICT, 0);
904 for (i = 0; i < 8; i++) {
905 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
906 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
907 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
909 update_divide_count(apic);
910 atomic_set(&apic->lapic_timer.pending, 0);
911 if (vcpu->vcpu_id == 0)
912 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
913 apic_update_ppr(apic);
915 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
916 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
917 vcpu, kvm_apic_id(apic),
918 vcpu->arch.apic_base, apic->base_address);
920 EXPORT_SYMBOL_GPL(kvm_lapic_reset);
922 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
924 struct kvm_lapic *apic = vcpu->arch.apic;
929 ret = apic_enabled(apic);
933 EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
936 *----------------------------------------------------------------------
938 *----------------------------------------------------------------------
941 static bool lapic_is_periodic(struct kvm_timer *ktimer)
943 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
945 return apic_lvtt_period(apic);
948 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
950 struct kvm_lapic *lapic = vcpu->arch.apic;
952 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
953 return atomic_read(&lapic->lapic_timer.pending);
958 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
960 u32 reg = apic_get_reg(apic, lvt_type);
961 int vector, mode, trig_mode;
963 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
964 vector = reg & APIC_VECTOR_MASK;
965 mode = reg & APIC_MODE_MASK;
966 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
967 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
972 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
974 struct kvm_lapic *apic = vcpu->arch.apic;
977 kvm_apic_local_deliver(apic, APIC_LVT0);
980 struct kvm_timer_ops lapic_timer_ops = {
981 .is_periodic = lapic_is_periodic,
984 int kvm_create_lapic(struct kvm_vcpu *vcpu)
986 struct kvm_lapic *apic;
988 ASSERT(vcpu != NULL);
989 apic_debug("apic_init %d\n", vcpu->vcpu_id);
991 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
995 vcpu->arch.apic = apic;
997 apic->regs_page = alloc_page(GFP_KERNEL);
998 if (apic->regs_page == NULL) {
999 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1001 goto nomem_free_apic;
1003 apic->regs = page_address(apic->regs_page);
1004 memset(apic->regs, 0, PAGE_SIZE);
1007 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1009 apic->lapic_timer.timer.function = kvm_timer_fn;
1010 apic->lapic_timer.t_ops = &lapic_timer_ops;
1011 apic->lapic_timer.kvm = vcpu->kvm;
1012 apic->lapic_timer.vcpu_id = vcpu->vcpu_id;
1014 apic->base_address = APIC_DEFAULT_PHYS_BASE;
1015 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1017 kvm_lapic_reset(vcpu);
1018 apic->dev.read = apic_mmio_read;
1019 apic->dev.write = apic_mmio_write;
1020 apic->dev.in_range = apic_mmio_range;
1021 apic->dev.private = apic;
1029 EXPORT_SYMBOL_GPL(kvm_create_lapic);
1031 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1033 struct kvm_lapic *apic = vcpu->arch.apic;
1036 if (!apic || !apic_enabled(apic))
1039 apic_update_ppr(apic);
1040 highest_irr = apic_find_highest_irr(apic);
1041 if ((highest_irr == -1) ||
1042 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1047 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1049 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1052 if (vcpu->vcpu_id == 0) {
1053 if (!apic_hw_enabled(vcpu->arch.apic))
1055 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1056 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1062 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1064 struct kvm_lapic *apic = vcpu->arch.apic;
1066 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1067 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1068 atomic_dec(&apic->lapic_timer.pending);
1072 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1074 int vector = kvm_apic_has_interrupt(vcpu);
1075 struct kvm_lapic *apic = vcpu->arch.apic;
1080 apic_set_vector(vector, apic->regs + APIC_ISR);
1081 apic_update_ppr(apic);
1082 apic_clear_irr(vector, apic);
1086 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1088 struct kvm_lapic *apic = vcpu->arch.apic;
1090 apic->base_address = vcpu->arch.apic_base &
1091 MSR_IA32_APICBASE_BASE;
1092 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1093 apic_update_ppr(apic);
1094 hrtimer_cancel(&apic->lapic_timer.timer);
1095 update_divide_count(apic);
1096 start_apic_timer(apic);
1099 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1101 struct kvm_lapic *apic = vcpu->arch.apic;
1102 struct hrtimer *timer;
1107 timer = &apic->lapic_timer.timer;
1108 if (hrtimer_cancel(timer))
1109 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1112 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1117 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1120 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1121 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1122 kunmap_atomic(vapic, KM_USER0);
1124 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1127 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1130 int max_irr, max_isr;
1131 struct kvm_lapic *apic;
1134 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1137 apic = vcpu->arch.apic;
1138 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1139 max_irr = apic_find_highest_irr(apic);
1142 max_isr = apic_find_highest_isr(apic);
1145 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1147 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1148 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1149 kunmap_atomic(vapic, KM_USER0);
1152 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1154 if (!irqchip_in_kernel(vcpu->kvm))
1157 vcpu->arch.apic->vapic_addr = vapic_addr;