2 * Copyright (C) 2001 MandrakeSoft S.A.
3 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 * http://www.linux-mandrake.com/
9 * http://www.mandrakesoft.com/
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or (at your option) any later version.
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this library; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * Yunhong Jiang <yunhong.jiang@intel.com>
26 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
27 * Based on Xen 3.1 code.
30 #include <linux/kvm_host.h>
31 #include <linux/kvm.h>
33 #include <linux/highmem.h>
34 #include <linux/smp.h>
35 #include <linux/hrtimer.h>
37 #include <linux/slab.h>
38 #include <linux/export.h>
39 #include <asm/processor.h>
41 #include <asm/current.h>
42 #include <trace/events/kvm.h>
49 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
51 #define ioapic_debug(fmt, arg...)
53 static int ioapic_service(struct kvm_ioapic *vioapic, int irq,
56 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
60 unsigned long result = 0;
62 switch (ioapic->ioregsel) {
63 case IOAPIC_REG_VERSION:
64 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
65 | (IOAPIC_VERSION_ID & 0xff));
68 case IOAPIC_REG_APIC_ID:
69 case IOAPIC_REG_ARB_ID:
70 result = ((ioapic->id & 0xf) << 24);
75 u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
78 if (redir_index < IOAPIC_NUM_PINS)
80 ioapic->redirtbl[redir_index].bits;
82 redir_content = ~0ULL;
84 result = (ioapic->ioregsel & 0x1) ?
85 (redir_content >> 32) & 0xffffffff :
86 redir_content & 0xffffffff;
94 static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic)
96 ioapic->rtc_status.pending_eoi = 0;
97 bitmap_zero(ioapic->rtc_status.dest_map, KVM_MAX_VCPUS);
100 static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic);
102 static void rtc_status_pending_eoi_check_valid(struct kvm_ioapic *ioapic)
104 if (WARN_ON(ioapic->rtc_status.pending_eoi < 0))
105 kvm_rtc_eoi_tracking_restore_all(ioapic);
108 static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
110 bool new_val, old_val;
111 struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
112 union kvm_ioapic_redirect_entry *e;
114 e = &ioapic->redirtbl[RTC_GSI];
115 if (!kvm_apic_match_dest(vcpu, NULL, 0, e->fields.dest_id,
116 e->fields.dest_mode))
119 new_val = kvm_apic_pending_eoi(vcpu, e->fields.vector);
120 old_val = test_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map);
122 if (new_val == old_val)
126 __set_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map);
127 ioapic->rtc_status.pending_eoi++;
129 __clear_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map);
130 ioapic->rtc_status.pending_eoi--;
131 rtc_status_pending_eoi_check_valid(ioapic);
135 void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
137 struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
139 spin_lock(&ioapic->lock);
140 __rtc_irq_eoi_tracking_restore_one(vcpu);
141 spin_unlock(&ioapic->lock);
144 static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic)
146 struct kvm_vcpu *vcpu;
149 if (RTC_GSI >= IOAPIC_NUM_PINS)
152 rtc_irq_eoi_tracking_reset(ioapic);
153 kvm_for_each_vcpu(i, vcpu, ioapic->kvm)
154 __rtc_irq_eoi_tracking_restore_one(vcpu);
157 static void rtc_irq_eoi(struct kvm_ioapic *ioapic, struct kvm_vcpu *vcpu)
159 if (test_and_clear_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map)) {
160 --ioapic->rtc_status.pending_eoi;
161 rtc_status_pending_eoi_check_valid(ioapic);
165 static bool rtc_irq_check_coalesced(struct kvm_ioapic *ioapic)
167 if (ioapic->rtc_status.pending_eoi > 0)
168 return true; /* coalesced */
173 static int ioapic_set_irq(struct kvm_ioapic *ioapic, unsigned int irq,
174 int irq_level, bool line_status)
176 union kvm_ioapic_redirect_entry entry;
181 entry = ioapic->redirtbl[irq];
182 edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
185 ioapic->irr &= ~mask;
191 * Return 0 for coalesced interrupts; for edge-triggered interrupts,
192 * this only happens if a previous edge has not been delivered due
193 * do masking. For level interrupts, the remote_irr field tells
194 * us if the interrupt is waiting for an EOI.
196 * RTC is special: it is edge-triggered, but userspace likes to know
197 * if it has been already ack-ed via EOI because coalesced RTC
198 * interrupts lead to time drift in Windows guests. So we track
199 * EOI manually for the RTC interrupt.
201 if (irq == RTC_GSI && line_status &&
202 rtc_irq_check_coalesced(ioapic)) {
207 old_irr = ioapic->irr;
209 if ((edge && old_irr == ioapic->irr) ||
210 (!edge && entry.fields.remote_irr)) {
215 ret = ioapic_service(ioapic, irq, line_status);
218 trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
222 static void kvm_ioapic_inject_all(struct kvm_ioapic *ioapic, unsigned long irr)
226 rtc_irq_eoi_tracking_reset(ioapic);
227 for_each_set_bit(idx, &irr, IOAPIC_NUM_PINS)
228 ioapic_set_irq(ioapic, idx, 1, true);
230 kvm_rtc_eoi_tracking_restore_all(ioapic);
234 static void update_handled_vectors(struct kvm_ioapic *ioapic)
236 DECLARE_BITMAP(handled_vectors, 256);
239 memset(handled_vectors, 0, sizeof(handled_vectors));
240 for (i = 0; i < IOAPIC_NUM_PINS; ++i)
241 __set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
242 memcpy(ioapic->handled_vectors, handled_vectors,
243 sizeof(handled_vectors));
247 void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap,
250 struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
251 union kvm_ioapic_redirect_entry *e;
254 spin_lock(&ioapic->lock);
255 for (index = 0; index < IOAPIC_NUM_PINS; index++) {
256 e = &ioapic->redirtbl[index];
257 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG ||
258 kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index) ||
260 if (kvm_apic_match_dest(vcpu, NULL, 0,
261 e->fields.dest_id, e->fields.dest_mode)) {
262 __set_bit(e->fields.vector,
263 (unsigned long *)eoi_exit_bitmap);
264 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG)
265 __set_bit(e->fields.vector,
266 (unsigned long *)tmr);
270 spin_unlock(&ioapic->lock);
273 void kvm_vcpu_request_scan_ioapic(struct kvm *kvm)
275 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
279 kvm_make_scan_ioapic_request(kvm);
282 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
285 bool mask_before, mask_after;
286 union kvm_ioapic_redirect_entry *e;
288 switch (ioapic->ioregsel) {
289 case IOAPIC_REG_VERSION:
290 /* Writes are ignored. */
293 case IOAPIC_REG_APIC_ID:
294 ioapic->id = (val >> 24) & 0xf;
297 case IOAPIC_REG_ARB_ID:
301 index = (ioapic->ioregsel - 0x10) >> 1;
303 ioapic_debug("change redir index %x val %x\n", index, val);
304 if (index >= IOAPIC_NUM_PINS)
306 e = &ioapic->redirtbl[index];
307 mask_before = e->fields.mask;
308 if (ioapic->ioregsel & 1) {
309 e->bits &= 0xffffffff;
310 e->bits |= (u64) val << 32;
312 e->bits &= ~0xffffffffULL;
313 e->bits |= (u32) val;
314 e->fields.remote_irr = 0;
316 update_handled_vectors(ioapic);
317 mask_after = e->fields.mask;
318 if (mask_before != mask_after)
319 kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
320 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
321 && ioapic->irr & (1 << index))
322 ioapic_service(ioapic, index, false);
323 kvm_vcpu_request_scan_ioapic(ioapic->kvm);
328 static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status)
330 union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
331 struct kvm_lapic_irq irqe;
334 if (entry->fields.mask)
337 ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
338 "vector=%x trig_mode=%x\n",
339 entry->fields.dest_id, entry->fields.dest_mode,
340 entry->fields.delivery_mode, entry->fields.vector,
341 entry->fields.trig_mode);
343 irqe.dest_id = entry->fields.dest_id;
344 irqe.vector = entry->fields.vector;
345 irqe.dest_mode = entry->fields.dest_mode;
346 irqe.trig_mode = entry->fields.trig_mode;
347 irqe.delivery_mode = entry->fields.delivery_mode << 8;
351 if (irqe.trig_mode == IOAPIC_EDGE_TRIG)
352 ioapic->irr &= ~(1 << irq);
354 if (irq == RTC_GSI && line_status) {
356 * pending_eoi cannot ever become negative (see
357 * rtc_status_pending_eoi_check_valid) and the caller
358 * ensures that it is only called if it is >= zero, namely
359 * if rtc_irq_check_coalesced returns false).
361 BUG_ON(ioapic->rtc_status.pending_eoi != 0);
362 ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe,
363 ioapic->rtc_status.dest_map);
364 ioapic->rtc_status.pending_eoi = (ret < 0 ? 0 : ret);
366 ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, NULL);
368 if (ret && irqe.trig_mode == IOAPIC_LEVEL_TRIG)
369 entry->fields.remote_irr = 1;
374 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
375 int level, bool line_status)
379 BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS);
381 spin_lock(&ioapic->lock);
382 irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
383 irq_source_id, level);
384 ret = ioapic_set_irq(ioapic, irq, irq_level, line_status);
386 spin_unlock(&ioapic->lock);
391 void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
395 spin_lock(&ioapic->lock);
396 for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
397 __clear_bit(irq_source_id, &ioapic->irq_states[i]);
398 spin_unlock(&ioapic->lock);
401 static void kvm_ioapic_eoi_inject_work(struct work_struct *work)
404 struct kvm_ioapic *ioapic = container_of(work, struct kvm_ioapic,
406 spin_lock(&ioapic->lock);
407 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
408 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
410 if (ent->fields.trig_mode != IOAPIC_LEVEL_TRIG)
413 if (ioapic->irr & (1 << i) && !ent->fields.remote_irr)
414 ioapic_service(ioapic, i, false);
416 spin_unlock(&ioapic->lock);
419 #define IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT 10000
421 static void __kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu,
422 struct kvm_ioapic *ioapic, int vector, int trigger_mode)
426 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
427 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
429 if (ent->fields.vector != vector)
433 rtc_irq_eoi(ioapic, vcpu);
435 * We are dropping lock while calling ack notifiers because ack
436 * notifier callbacks for assigned devices call into IOAPIC
437 * recursively. Since remote_irr is cleared only after call
438 * to notifiers if the same vector will be delivered while lock
439 * is dropped it will be put into irr and will be delivered
440 * after ack notifier returns.
442 spin_unlock(&ioapic->lock);
443 kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
444 spin_lock(&ioapic->lock);
446 if (trigger_mode != IOAPIC_LEVEL_TRIG)
449 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
450 ent->fields.remote_irr = 0;
451 if (!ent->fields.mask && (ioapic->irr & (1 << i))) {
452 ++ioapic->irq_eoi[i];
453 if (ioapic->irq_eoi[i] == IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT) {
455 * Real hardware does not deliver the interrupt
456 * immediately during eoi broadcast, and this
457 * lets a buggy guest make slow progress
458 * even if it does not correctly handle a
459 * level-triggered interrupt. Emulate this
460 * behavior if we detect an interrupt storm.
462 schedule_delayed_work(&ioapic->eoi_inject, HZ / 100);
463 ioapic->irq_eoi[i] = 0;
464 trace_kvm_ioapic_delayed_eoi_inj(ent->bits);
466 ioapic_service(ioapic, i, false);
469 ioapic->irq_eoi[i] = 0;
474 bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector)
476 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
478 return test_bit(vector, ioapic->handled_vectors);
481 void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector, int trigger_mode)
483 struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
485 spin_lock(&ioapic->lock);
486 __kvm_ioapic_update_eoi(vcpu, ioapic, vector, trigger_mode);
487 spin_unlock(&ioapic->lock);
490 static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
492 return container_of(dev, struct kvm_ioapic, dev);
495 static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
497 return ((addr >= ioapic->base_address &&
498 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
501 static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
504 struct kvm_ioapic *ioapic = to_ioapic(this);
506 if (!ioapic_in_range(ioapic, addr))
509 ioapic_debug("addr %lx\n", (unsigned long)addr);
510 ASSERT(!(addr & 0xf)); /* check alignment */
513 spin_lock(&ioapic->lock);
515 case IOAPIC_REG_SELECT:
516 result = ioapic->ioregsel;
519 case IOAPIC_REG_WINDOW:
520 result = ioapic_read_indirect(ioapic, addr, len);
527 spin_unlock(&ioapic->lock);
531 *(u64 *) val = result;
536 memcpy(val, (char *)&result, len);
539 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
544 static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
547 struct kvm_ioapic *ioapic = to_ioapic(this);
549 if (!ioapic_in_range(ioapic, addr))
552 ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
553 (void*)addr, len, val);
554 ASSERT(!(addr & 0xf)); /* check alignment */
568 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
573 spin_lock(&ioapic->lock);
575 case IOAPIC_REG_SELECT:
576 ioapic->ioregsel = data & 0xFF; /* 8-bit register */
579 case IOAPIC_REG_WINDOW:
580 ioapic_write_indirect(ioapic, data);
586 spin_unlock(&ioapic->lock);
590 static void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
594 cancel_delayed_work_sync(&ioapic->eoi_inject);
595 for (i = 0; i < IOAPIC_NUM_PINS; i++)
596 ioapic->redirtbl[i].fields.mask = 1;
597 ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
598 ioapic->ioregsel = 0;
601 memset(ioapic->irq_eoi, 0x00, IOAPIC_NUM_PINS);
602 rtc_irq_eoi_tracking_reset(ioapic);
603 update_handled_vectors(ioapic);
606 static const struct kvm_io_device_ops ioapic_mmio_ops = {
607 .read = ioapic_mmio_read,
608 .write = ioapic_mmio_write,
611 int kvm_ioapic_init(struct kvm *kvm)
613 struct kvm_ioapic *ioapic;
616 ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
619 spin_lock_init(&ioapic->lock);
620 INIT_DELAYED_WORK(&ioapic->eoi_inject, kvm_ioapic_eoi_inject_work);
621 kvm->arch.vioapic = ioapic;
622 kvm_ioapic_reset(ioapic);
623 kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
625 mutex_lock(&kvm->slots_lock);
626 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
627 IOAPIC_MEM_LENGTH, &ioapic->dev);
628 mutex_unlock(&kvm->slots_lock);
630 kvm->arch.vioapic = NULL;
637 void kvm_ioapic_destroy(struct kvm *kvm)
639 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
641 cancel_delayed_work_sync(&ioapic->eoi_inject);
643 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
644 kvm->arch.vioapic = NULL;
649 int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
651 struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
655 spin_lock(&ioapic->lock);
656 memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
657 spin_unlock(&ioapic->lock);
661 int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
663 struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
667 spin_lock(&ioapic->lock);
668 memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
670 update_handled_vectors(ioapic);
671 kvm_vcpu_request_scan_ioapic(kvm);
672 kvm_ioapic_inject_all(ioapic, state->irr);
673 spin_unlock(&ioapic->lock);