2 * 8253/8254 interval timer emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2006 Intel Corporation
6 * Copyright (c) 2007 Keir Fraser, XenSource Inc
7 * Copyright (c) 2008 Intel Corporation
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 * Sheng Yang <sheng.yang@intel.com>
29 * Based on QEMU and Xen.
32 #include <linux/kvm_host.h>
38 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
40 #define mod_64(x, y) ((x) % (y))
43 #define RW_STATE_LSB 1
44 #define RW_STATE_MSB 2
45 #define RW_STATE_WORD0 3
46 #define RW_STATE_WORD1 4
48 /* Compute with 96 bit intermediate result: (a*b)/c */
49 static u64 muldiv64(u64 a, u32 b, u32 c)
60 rl = (u64)u.l.low * (u64)b;
61 rh = (u64)u.l.high * (u64)b;
63 res.l.high = div64_u64(rh, c);
64 res.l.low = div64_u64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c);
68 static void pit_set_gate(struct kvm *kvm, int channel, u32 val)
70 struct kvm_kpit_channel_state *c =
71 &kvm->arch.vpit->pit_state.channels[channel];
73 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
79 /* XXX: just disable/enable counting */
85 /* Restart counting on rising edge. */
87 c->count_load_time = ktime_get();
94 static int pit_get_gate(struct kvm *kvm, int channel)
96 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
98 return kvm->arch.vpit->pit_state.channels[channel].gate;
101 static s64 __kpit_elapsed(struct kvm *kvm)
105 struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;
107 if (!ps->pit_timer.period)
111 * The Counter does not stop when it reaches zero. In
112 * Modes 0, 1, 4, and 5 the Counter ``wraps around'' to
113 * the highest count, either FFFF hex for binary counting
114 * or 9999 for BCD counting, and continues counting.
115 * Modes 2 and 3 are periodic; the Counter reloads
116 * itself with the initial count and continues counting
119 remaining = hrtimer_get_remaining(&ps->pit_timer.timer);
120 elapsed = ps->pit_timer.period - ktime_to_ns(remaining);
121 elapsed = mod_64(elapsed, ps->pit_timer.period);
126 static s64 kpit_elapsed(struct kvm *kvm, struct kvm_kpit_channel_state *c,
130 return __kpit_elapsed(kvm);
132 return ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
135 static int pit_get_count(struct kvm *kvm, int channel)
137 struct kvm_kpit_channel_state *c =
138 &kvm->arch.vpit->pit_state.channels[channel];
142 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
144 t = kpit_elapsed(kvm, c, channel);
145 d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
152 counter = (c->count - d) & 0xffff;
155 /* XXX: may be incorrect for odd counts */
156 counter = c->count - (mod_64((2 * d), c->count));
159 counter = c->count - mod_64(d, c->count);
165 static int pit_get_out(struct kvm *kvm, int channel)
167 struct kvm_kpit_channel_state *c =
168 &kvm->arch.vpit->pit_state.channels[channel];
172 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
174 t = kpit_elapsed(kvm, c, channel);
175 d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
180 out = (d >= c->count);
183 out = (d < c->count);
186 out = ((mod_64(d, c->count) == 0) && (d != 0));
189 out = (mod_64(d, c->count) < ((c->count + 1) >> 1));
193 out = (d == c->count);
200 static void pit_latch_count(struct kvm *kvm, int channel)
202 struct kvm_kpit_channel_state *c =
203 &kvm->arch.vpit->pit_state.channels[channel];
205 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
207 if (!c->count_latched) {
208 c->latched_count = pit_get_count(kvm, channel);
209 c->count_latched = c->rw_mode;
213 static void pit_latch_status(struct kvm *kvm, int channel)
215 struct kvm_kpit_channel_state *c =
216 &kvm->arch.vpit->pit_state.channels[channel];
218 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
220 if (!c->status_latched) {
221 /* TODO: Return NULL COUNT (bit 6). */
222 c->status = ((pit_get_out(kvm, channel) << 7) |
226 c->status_latched = 1;
230 int pit_has_pending_timer(struct kvm_vcpu *vcpu)
232 struct kvm_pit *pit = vcpu->kvm->arch.vpit;
234 if (pit && kvm_vcpu_is_bsp(vcpu) && pit->pit_state.irq_ack)
235 return atomic_read(&pit->pit_state.pit_timer.pending);
239 static void kvm_pit_ack_irq(struct kvm_irq_ack_notifier *kian)
241 struct kvm_kpit_state *ps = container_of(kian, struct kvm_kpit_state,
243 spin_lock(&ps->inject_lock);
244 if (atomic_dec_return(&ps->pit_timer.pending) < 0)
245 atomic_inc(&ps->pit_timer.pending);
247 spin_unlock(&ps->inject_lock);
250 void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu)
252 struct kvm_pit *pit = vcpu->kvm->arch.vpit;
253 struct hrtimer *timer;
255 if (!kvm_vcpu_is_bsp(vcpu) || !pit)
258 timer = &pit->pit_state.pit_timer.timer;
259 if (hrtimer_cancel(timer))
260 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
263 static void destroy_pit_timer(struct kvm_timer *pt)
265 pr_debug("pit: execute del timer!\n");
266 hrtimer_cancel(&pt->timer);
269 static bool kpit_is_periodic(struct kvm_timer *ktimer)
271 struct kvm_kpit_state *ps = container_of(ktimer, struct kvm_kpit_state,
273 return ps->is_periodic;
276 static struct kvm_timer_ops kpit_ops = {
277 .is_periodic = kpit_is_periodic,
280 static void create_pit_timer(struct kvm_kpit_state *ps, u32 val, int is_period)
282 struct kvm_timer *pt = &ps->pit_timer;
285 interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ);
287 pr_debug("pit: create pit timer, interval is %llu nsec\n", interval);
289 /* TODO The new value only affected after the retriggered */
290 hrtimer_cancel(&pt->timer);
291 pt->period = interval;
292 ps->is_periodic = is_period;
294 pt->timer.function = kvm_timer_fn;
295 pt->t_ops = &kpit_ops;
296 pt->kvm = ps->pit->kvm;
297 pt->vcpu = pt->kvm->bsp_vcpu;
299 atomic_set(&pt->pending, 0);
302 hrtimer_start(&pt->timer, ktime_add_ns(ktime_get(), interval),
306 static void pit_load_count(struct kvm *kvm, int channel, u32 val)
308 struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;
310 WARN_ON(!mutex_is_locked(&ps->lock));
312 pr_debug("pit: load_count val is %d, channel is %d\n", val, channel);
315 * The largest possible initial count is 0; this is equivalent
316 * to 216 for binary counting and 104 for BCD counting.
321 ps->channels[channel].count = val;
324 ps->channels[channel].count_load_time = ktime_get();
328 /* Two types of timer
329 * mode 1 is one shot, mode 2 is period, otherwise del timer */
330 switch (ps->channels[0].mode) {
333 /* FIXME: enhance mode 4 precision */
335 if (!(ps->flags & KVM_PIT_FLAGS_HPET_LEGACY)) {
336 create_pit_timer(ps, val, 0);
341 if (!(ps->flags & KVM_PIT_FLAGS_HPET_LEGACY)){
342 create_pit_timer(ps, val, 1);
346 destroy_pit_timer(&ps->pit_timer);
350 void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val, int hpet_legacy_start)
353 if (hpet_legacy_start) {
354 /* save existing mode for later reenablement */
355 saved_mode = kvm->arch.vpit->pit_state.channels[0].mode;
356 kvm->arch.vpit->pit_state.channels[0].mode = 0xff; /* disable timer */
357 pit_load_count(kvm, channel, val);
358 kvm->arch.vpit->pit_state.channels[0].mode = saved_mode;
360 pit_load_count(kvm, channel, val);
364 static inline struct kvm_pit *dev_to_pit(struct kvm_io_device *dev)
366 return container_of(dev, struct kvm_pit, dev);
369 static inline struct kvm_pit *speaker_to_pit(struct kvm_io_device *dev)
371 return container_of(dev, struct kvm_pit, speaker_dev);
374 static inline int pit_in_range(gpa_t addr)
376 return ((addr >= KVM_PIT_BASE_ADDRESS) &&
377 (addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH));
380 static int pit_ioport_write(struct kvm_io_device *this,
381 gpa_t addr, int len, const void *data)
383 struct kvm_pit *pit = dev_to_pit(this);
384 struct kvm_kpit_state *pit_state = &pit->pit_state;
385 struct kvm *kvm = pit->kvm;
387 struct kvm_kpit_channel_state *s;
388 u32 val = *(u32 *) data;
389 if (!pit_in_range(addr))
393 addr &= KVM_PIT_CHANNEL_MASK;
395 mutex_lock(&pit_state->lock);
398 pr_debug("pit: write addr is 0x%x, len is %d, val is 0x%x\n",
399 (unsigned int)addr, len, val);
404 /* Read-Back Command. */
405 for (channel = 0; channel < 3; channel++) {
406 s = &pit_state->channels[channel];
407 if (val & (2 << channel)) {
409 pit_latch_count(kvm, channel);
411 pit_latch_status(kvm, channel);
415 /* Select Counter <channel>. */
416 s = &pit_state->channels[channel];
417 access = (val >> 4) & KVM_PIT_CHANNEL_MASK;
419 pit_latch_count(kvm, channel);
422 s->read_state = access;
423 s->write_state = access;
424 s->mode = (val >> 1) & 7;
432 s = &pit_state->channels[addr];
433 switch (s->write_state) {
436 pit_load_count(kvm, addr, val);
439 pit_load_count(kvm, addr, val << 8);
442 s->write_latch = val;
443 s->write_state = RW_STATE_WORD1;
446 pit_load_count(kvm, addr, s->write_latch | (val << 8));
447 s->write_state = RW_STATE_WORD0;
452 mutex_unlock(&pit_state->lock);
456 static int pit_ioport_read(struct kvm_io_device *this,
457 gpa_t addr, int len, void *data)
459 struct kvm_pit *pit = dev_to_pit(this);
460 struct kvm_kpit_state *pit_state = &pit->pit_state;
461 struct kvm *kvm = pit->kvm;
463 struct kvm_kpit_channel_state *s;
464 if (!pit_in_range(addr))
467 addr &= KVM_PIT_CHANNEL_MASK;
468 s = &pit_state->channels[addr];
470 mutex_lock(&pit_state->lock);
472 if (s->status_latched) {
473 s->status_latched = 0;
475 } else if (s->count_latched) {
476 switch (s->count_latched) {
479 ret = s->latched_count & 0xff;
480 s->count_latched = 0;
483 ret = s->latched_count >> 8;
484 s->count_latched = 0;
487 ret = s->latched_count & 0xff;
488 s->count_latched = RW_STATE_MSB;
492 switch (s->read_state) {
495 count = pit_get_count(kvm, addr);
499 count = pit_get_count(kvm, addr);
500 ret = (count >> 8) & 0xff;
503 count = pit_get_count(kvm, addr);
505 s->read_state = RW_STATE_WORD1;
508 count = pit_get_count(kvm, addr);
509 ret = (count >> 8) & 0xff;
510 s->read_state = RW_STATE_WORD0;
515 if (len > sizeof(ret))
517 memcpy(data, (char *)&ret, len);
519 mutex_unlock(&pit_state->lock);
523 static int speaker_ioport_write(struct kvm_io_device *this,
524 gpa_t addr, int len, const void *data)
526 struct kvm_pit *pit = speaker_to_pit(this);
527 struct kvm_kpit_state *pit_state = &pit->pit_state;
528 struct kvm *kvm = pit->kvm;
529 u32 val = *(u32 *) data;
530 if (addr != KVM_SPEAKER_BASE_ADDRESS)
533 mutex_lock(&pit_state->lock);
534 pit_state->speaker_data_on = (val >> 1) & 1;
535 pit_set_gate(kvm, 2, val & 1);
536 mutex_unlock(&pit_state->lock);
540 static int speaker_ioport_read(struct kvm_io_device *this,
541 gpa_t addr, int len, void *data)
543 struct kvm_pit *pit = speaker_to_pit(this);
544 struct kvm_kpit_state *pit_state = &pit->pit_state;
545 struct kvm *kvm = pit->kvm;
546 unsigned int refresh_clock;
548 if (addr != KVM_SPEAKER_BASE_ADDRESS)
551 /* Refresh clock toggles at about 15us. We approximate as 2^14ns. */
552 refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1;
554 mutex_lock(&pit_state->lock);
555 ret = ((pit_state->speaker_data_on << 1) | pit_get_gate(kvm, 2) |
556 (pit_get_out(kvm, 2) << 5) | (refresh_clock << 4));
557 if (len > sizeof(ret))
559 memcpy(data, (char *)&ret, len);
560 mutex_unlock(&pit_state->lock);
564 void kvm_pit_reset(struct kvm_pit *pit)
567 struct kvm_kpit_channel_state *c;
569 mutex_lock(&pit->pit_state.lock);
570 pit->pit_state.flags = 0;
571 for (i = 0; i < 3; i++) {
572 c = &pit->pit_state.channels[i];
575 pit_load_count(pit->kvm, i, 0);
577 mutex_unlock(&pit->pit_state.lock);
579 atomic_set(&pit->pit_state.pit_timer.pending, 0);
580 pit->pit_state.irq_ack = 1;
583 static void pit_mask_notifer(struct kvm_irq_mask_notifier *kimn, bool mask)
585 struct kvm_pit *pit = container_of(kimn, struct kvm_pit, mask_notifier);
588 atomic_set(&pit->pit_state.pit_timer.pending, 0);
589 pit->pit_state.irq_ack = 1;
593 static const struct kvm_io_device_ops pit_dev_ops = {
594 .read = pit_ioport_read,
595 .write = pit_ioport_write,
598 static const struct kvm_io_device_ops speaker_dev_ops = {
599 .read = speaker_ioport_read,
600 .write = speaker_ioport_write,
603 /* Caller must have writers lock on slots_lock */
604 struct kvm_pit *kvm_create_pit(struct kvm *kvm, u32 flags)
607 struct kvm_kpit_state *pit_state;
610 pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL);
614 pit->irq_source_id = kvm_request_irq_source_id(kvm);
615 if (pit->irq_source_id < 0) {
620 mutex_init(&pit->pit_state.lock);
621 mutex_lock(&pit->pit_state.lock);
622 spin_lock_init(&pit->pit_state.inject_lock);
624 kvm->arch.vpit = pit;
627 pit_state = &pit->pit_state;
628 pit_state->pit = pit;
629 hrtimer_init(&pit_state->pit_timer.timer,
630 CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
631 pit_state->irq_ack_notifier.gsi = 0;
632 pit_state->irq_ack_notifier.irq_acked = kvm_pit_ack_irq;
633 kvm_register_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier);
634 pit_state->pit_timer.reinject = true;
635 mutex_unlock(&pit->pit_state.lock);
639 pit->mask_notifier.func = pit_mask_notifer;
640 kvm_register_irq_mask_notifier(kvm, 0, &pit->mask_notifier);
642 kvm_iodevice_init(&pit->dev, &pit_dev_ops);
643 ret = __kvm_io_bus_register_dev(&kvm->pio_bus, &pit->dev);
647 if (flags & KVM_PIT_SPEAKER_DUMMY) {
648 kvm_iodevice_init(&pit->speaker_dev, &speaker_dev_ops);
649 ret = __kvm_io_bus_register_dev(&kvm->pio_bus,
652 goto fail_unregister;
658 __kvm_io_bus_unregister_dev(&kvm->pio_bus, &pit->dev);
661 if (pit->irq_source_id >= 0)
662 kvm_free_irq_source_id(kvm, pit->irq_source_id);
668 void kvm_free_pit(struct kvm *kvm)
670 struct hrtimer *timer;
672 if (kvm->arch.vpit) {
673 kvm_unregister_irq_mask_notifier(kvm, 0,
674 &kvm->arch.vpit->mask_notifier);
675 kvm_unregister_irq_ack_notifier(kvm,
676 &kvm->arch.vpit->pit_state.irq_ack_notifier);
677 mutex_lock(&kvm->arch.vpit->pit_state.lock);
678 timer = &kvm->arch.vpit->pit_state.pit_timer.timer;
679 hrtimer_cancel(timer);
680 kvm_free_irq_source_id(kvm, kvm->arch.vpit->irq_source_id);
681 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
682 kfree(kvm->arch.vpit);
686 static void __inject_pit_timer_intr(struct kvm *kvm)
688 struct kvm_vcpu *vcpu;
691 kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1);
692 kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0);
695 * Provides NMI watchdog support via Virtual Wire mode.
696 * The route is: PIT -> PIC -> LVT0 in NMI mode.
698 * Note: Our Virtual Wire implementation is simplified, only
699 * propagating PIT interrupts to all VCPUs when they have set
700 * LVT0 to NMI delivery. Other PIC interrupts are just sent to
701 * VCPU0, and only if its LVT0 is in EXTINT mode.
703 if (kvm->arch.vapics_in_nmi_mode > 0)
704 kvm_for_each_vcpu(i, vcpu, kvm)
705 kvm_apic_nmi_wd_deliver(vcpu);
708 void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
710 struct kvm_pit *pit = vcpu->kvm->arch.vpit;
711 struct kvm *kvm = vcpu->kvm;
712 struct kvm_kpit_state *ps;
716 ps = &pit->pit_state;
718 /* Try to inject pending interrupts when
719 * last one has been acked.
721 spin_lock(&ps->inject_lock);
722 if (atomic_read(&ps->pit_timer.pending) && ps->irq_ack) {
726 spin_unlock(&ps->inject_lock);
728 __inject_pit_timer_intr(kvm);