1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
4 * cpuid support routines
6 * derived from arch/x86/kvm/x86.c
8 * Copyright 2011 Red Hat, Inc. and/or its affiliates.
9 * Copyright IBM Corporation, 2008
12 #include <linux/kvm_host.h>
13 #include <linux/export.h>
14 #include <linux/vmalloc.h>
15 #include <linux/uaccess.h>
16 #include <linux/sched/stat.h>
18 #include <asm/processor.h>
20 #include <asm/fpu/xstate.h>
22 #include <asm/cpuid.h>
30 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be
31 * aligned to sizeof(unsigned long) because it's not accessed via bitops.
33 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly;
34 EXPORT_SYMBOL_GPL(kvm_cpu_caps);
36 u32 xstate_required_size(u64 xstate_bv, bool compacted)
39 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
41 xstate_bv &= XFEATURE_MASK_EXTEND;
43 if (xstate_bv & 0x1) {
44 u32 eax, ebx, ecx, edx, offset;
45 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx);
46 /* ECX[1]: 64B alignment in compacted form */
48 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret;
51 ret = max(ret, offset + eax);
62 * This one is tied to SSB in the user API, and not
63 * visible in /proc/cpuinfo.
65 #define KVM_X86_FEATURE_AMD_PSFD (13*32+28) /* Predictive Store Forwarding Disable */
69 /* Scattered Flag - For features that are scattered by cpufeatures.h. */
72 BUILD_BUG_ON(X86_FEATURE_##name >= MAX_CPU_FEATURES); \
73 (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0); \
77 * Magic value used by KVM when querying userspace-provided CPUID entries and
78 * doesn't care about the CPIUD index because the index of the function in
79 * question is not significant. Note, this magic value must have at least one
80 * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find()
81 * to avoid false positives when processing guest CPUID input.
83 #define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull
85 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find(
86 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u64 index)
88 struct kvm_cpuid_entry2 *e;
91 for (i = 0; i < nent; i++) {
94 if (e->function != function)
98 * If the index isn't significant, use the first entry with a
99 * matching function. It's userspace's responsibilty to not
100 * provide "duplicate" entries in all cases.
102 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index)
107 * Similarly, use the first matching entry if KVM is doing a
108 * lookup (as opposed to emulating CPUID) for a function that's
109 * architecturally defined as not having a significant index.
111 if (index == KVM_CPUID_INDEX_NOT_SIGNIFICANT) {
113 * Direct lookups from KVM should not diverge from what
114 * KVM defines internally (the architectural behavior).
116 WARN_ON_ONCE(cpuid_function_is_indexed(function));
124 static int kvm_check_cpuid(struct kvm_vcpu *vcpu,
125 struct kvm_cpuid_entry2 *entries,
128 struct kvm_cpuid_entry2 *best;
132 * The existing code assumes virtual address is 48-bit or 57-bit in the
133 * canonical address checks; exit if it is ever changed.
135 best = cpuid_entry2_find(entries, nent, 0x80000008,
136 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
138 int vaddr_bits = (best->eax & 0xff00) >> 8;
140 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0)
145 * Exposing dynamic xfeatures to the guest requires additional
146 * enabling in the FPU, e.g. to expand the guest XSAVE state size.
148 best = cpuid_entry2_find(entries, nent, 0xd, 0);
152 xfeatures = best->eax | ((u64)best->edx << 32);
153 xfeatures &= XFEATURE_MASK_USER_DYNAMIC;
157 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures);
160 /* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */
161 static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2,
164 struct kvm_cpuid_entry2 *orig;
167 if (nent != vcpu->arch.cpuid_nent)
170 for (i = 0; i < nent; i++) {
171 orig = &vcpu->arch.cpuid_entries[i];
172 if (e2[i].function != orig->function ||
173 e2[i].index != orig->index ||
174 e2[i].flags != orig->flags ||
175 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx ||
176 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx)
183 static void kvm_update_kvm_cpuid_base(struct kvm_vcpu *vcpu)
186 struct kvm_cpuid_entry2 *entry;
188 vcpu->arch.kvm_cpuid_base = 0;
190 for_each_possible_hypervisor_cpuid_base(function) {
191 entry = kvm_find_cpuid_entry(vcpu, function);
196 signature[0] = entry->ebx;
197 signature[1] = entry->ecx;
198 signature[2] = entry->edx;
200 BUILD_BUG_ON(sizeof(signature) > sizeof(KVM_SIGNATURE));
201 if (!memcmp(signature, KVM_SIGNATURE, sizeof(signature))) {
202 vcpu->arch.kvm_cpuid_base = function;
209 static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu,
210 struct kvm_cpuid_entry2 *entries, int nent)
212 u32 base = vcpu->arch.kvm_cpuid_base;
217 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES,
218 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
221 static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu)
223 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries,
224 vcpu->arch.cpuid_nent);
227 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu)
229 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu);
232 * save the feature bitmap to avoid cpuid lookup for every PV
236 vcpu->arch.pv_cpuid.features = best->eax;
240 * Calculate guest's supported XCR0 taking into account guest CPUID data and
241 * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0).
243 static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent)
245 struct kvm_cpuid_entry2 *best;
247 best = cpuid_entry2_find(entries, nent, 0xd, 0);
251 return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0;
254 static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries,
257 struct kvm_cpuid_entry2 *best;
258 u64 guest_supported_xcr0 = cpuid_get_supported_xcr0(entries, nent);
260 best = cpuid_entry2_find(entries, nent, 1, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
262 /* Update OSXSAVE bit */
263 if (boot_cpu_has(X86_FEATURE_XSAVE))
264 cpuid_entry_change(best, X86_FEATURE_OSXSAVE,
265 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE));
267 cpuid_entry_change(best, X86_FEATURE_APIC,
268 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE);
271 best = cpuid_entry2_find(entries, nent, 7, 0);
272 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7)
273 cpuid_entry_change(best, X86_FEATURE_OSPKE,
274 kvm_read_cr4_bits(vcpu, X86_CR4_PKE));
276 best = cpuid_entry2_find(entries, nent, 0xD, 0);
278 best->ebx = xstate_required_size(vcpu->arch.xcr0, false);
280 best = cpuid_entry2_find(entries, nent, 0xD, 1);
281 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) ||
282 cpuid_entry_has(best, X86_FEATURE_XSAVEC)))
283 best->ebx = xstate_required_size(vcpu->arch.xcr0, true);
285 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent);
286 if (kvm_hlt_in_guest(vcpu->kvm) && best &&
287 (best->eax & (1 << KVM_FEATURE_PV_UNHALT)))
288 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT);
290 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) {
291 best = cpuid_entry2_find(entries, nent, 0x1, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
293 cpuid_entry_change(best, X86_FEATURE_MWAIT,
294 vcpu->arch.ia32_misc_enable_msr &
295 MSR_IA32_MISC_ENABLE_MWAIT);
299 * Bits 127:0 of the allowed SECS.ATTRIBUTES (CPUID.0x12.0x1) enumerate
300 * the supported XSAVE Feature Request Mask (XFRM), i.e. the enclave's
301 * requested XCR0 value. The enclave's XFRM must be a subset of XCRO
302 * at the time of EENTER, thus adjust the allowed XFRM by the guest's
303 * supported XCR0. Similar to XCR0 handling, FP and SSE are forced to
304 * '1' even on CPUs that don't support XSAVE.
306 best = cpuid_entry2_find(entries, nent, 0x12, 0x1);
308 best->ecx &= guest_supported_xcr0 & 0xffffffff;
309 best->edx &= guest_supported_xcr0 >> 32;
310 best->ecx |= XFEATURE_MASK_FPSSE;
314 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu)
316 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
318 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime);
320 static bool kvm_cpuid_has_hyperv(struct kvm_cpuid_entry2 *entries, int nent)
322 struct kvm_cpuid_entry2 *entry;
324 entry = cpuid_entry2_find(entries, nent, HYPERV_CPUID_INTERFACE,
325 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
326 return entry && entry->eax == HYPERV_CPUID_SIGNATURE_EAX;
329 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
331 struct kvm_lapic *apic = vcpu->arch.apic;
332 struct kvm_cpuid_entry2 *best;
334 best = kvm_find_cpuid_entry(vcpu, 1);
336 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER))
337 apic->lapic_timer.timer_mode_mask = 3 << 17;
339 apic->lapic_timer.timer_mode_mask = 1 << 17;
341 kvm_apic_set_version(vcpu);
344 vcpu->arch.guest_supported_xcr0 =
345 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
348 * FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if
349 * XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't
350 * supported by the host.
352 vcpu->arch.guest_fpu.fpstate->user_xfeatures = vcpu->arch.guest_supported_xcr0 |
355 kvm_update_pv_runtime(vcpu);
357 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
358 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
360 kvm_pmu_refresh(vcpu);
361 vcpu->arch.cr4_guest_rsvd_bits =
362 __cr4_reserved_bits(guest_cpuid_has, vcpu);
364 kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries,
365 vcpu->arch.cpuid_nent));
367 /* Invoke the vendor callback only after the above state is updated. */
368 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu);
371 * Except for the MMU, which needs to do its thing any vendor specific
372 * adjustments to the reserved GPA bits.
374 kvm_mmu_after_set_cpuid(vcpu);
377 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu)
379 struct kvm_cpuid_entry2 *best;
381 best = kvm_find_cpuid_entry(vcpu, 0x80000000);
382 if (!best || best->eax < 0x80000008)
384 best = kvm_find_cpuid_entry(vcpu, 0x80000008);
386 return best->eax & 0xff;
392 * This "raw" version returns the reserved GPA bits without any adjustments for
393 * encryption technologies that usurp bits. The raw mask should be used if and
394 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs.
396 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu)
398 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63);
401 static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2,
406 __kvm_update_cpuid_runtime(vcpu, e2, nent);
409 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
410 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
411 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
412 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with
413 * the core vCPU model on the fly. It would've been better to forbid any
414 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately
415 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do
416 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check
417 * whether the supplied CPUID data is equal to what's already set.
419 if (vcpu->arch.last_vmentry_cpu != -1) {
420 r = kvm_cpuid_check_equal(vcpu, e2, nent);
428 if (kvm_cpuid_has_hyperv(e2, nent)) {
429 r = kvm_hv_vcpu_init(vcpu);
434 r = kvm_check_cpuid(vcpu, e2, nent);
438 kvfree(vcpu->arch.cpuid_entries);
439 vcpu->arch.cpuid_entries = e2;
440 vcpu->arch.cpuid_nent = nent;
442 kvm_update_kvm_cpuid_base(vcpu);
443 kvm_vcpu_after_set_cpuid(vcpu);
448 /* when an old userspace process fills a new kernel module */
449 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
450 struct kvm_cpuid *cpuid,
451 struct kvm_cpuid_entry __user *entries)
454 struct kvm_cpuid_entry *e = NULL;
455 struct kvm_cpuid_entry2 *e2 = NULL;
457 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
461 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent));
465 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT);
471 for (i = 0; i < cpuid->nent; i++) {
472 e2[i].function = e[i].function;
473 e2[i].eax = e[i].eax;
474 e2[i].ebx = e[i].ebx;
475 e2[i].ecx = e[i].ecx;
476 e2[i].edx = e[i].edx;
479 e2[i].padding[0] = 0;
480 e2[i].padding[1] = 0;
481 e2[i].padding[2] = 0;
484 r = kvm_set_cpuid(vcpu, e2, cpuid->nent);
494 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
495 struct kvm_cpuid2 *cpuid,
496 struct kvm_cpuid_entry2 __user *entries)
498 struct kvm_cpuid_entry2 *e2 = NULL;
501 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
505 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent));
510 r = kvm_set_cpuid(vcpu, e2, cpuid->nent);
517 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
518 struct kvm_cpuid2 *cpuid,
519 struct kvm_cpuid_entry2 __user *entries)
524 if (cpuid->nent < vcpu->arch.cpuid_nent)
527 if (copy_to_user(entries, vcpu->arch.cpuid_entries,
528 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
533 cpuid->nent = vcpu->arch.cpuid_nent;
537 /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */
538 static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf)
540 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32);
541 struct kvm_cpuid_entry2 entry;
543 reverse_cpuid_check(leaf);
545 cpuid_count(cpuid.function, cpuid.index,
546 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx);
548 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg);
551 static __always_inline
552 void kvm_cpu_cap_init_kvm_defined(enum kvm_only_cpuid_leafs leaf, u32 mask)
554 /* Use kvm_cpu_cap_mask for leafs that aren't KVM-only. */
555 BUILD_BUG_ON(leaf < NCAPINTS);
557 kvm_cpu_caps[leaf] = mask;
559 __kvm_cpu_cap_mask(leaf);
562 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask)
564 /* Use kvm_cpu_cap_init_kvm_defined for KVM-only leafs. */
565 BUILD_BUG_ON(leaf >= NCAPINTS);
567 kvm_cpu_caps[leaf] &= mask;
569 __kvm_cpu_cap_mask(leaf);
572 void kvm_set_cpu_caps(void)
575 unsigned int f_gbpages = F(GBPAGES);
576 unsigned int f_lm = F(LM);
577 unsigned int f_xfd = F(XFD);
579 unsigned int f_gbpages = 0;
580 unsigned int f_lm = 0;
581 unsigned int f_xfd = 0;
583 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps));
585 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) >
586 sizeof(boot_cpu_data.x86_capability));
588 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability,
589 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)));
591 kvm_cpu_cap_mask(CPUID_1_ECX,
593 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not*
594 * advertised to guests via CPUID!
596 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
597 0 /* DS-CPL, VMX, SMX, EST */ |
598 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
599 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) |
600 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
601 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
602 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
605 /* KVM emulates x2apic in software irrespective of host support. */
606 kvm_cpu_cap_set(X86_FEATURE_X2APIC);
608 kvm_cpu_cap_mask(CPUID_1_EDX,
609 F(FPU) | F(VME) | F(DE) | F(PSE) |
610 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
611 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
612 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
613 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) |
614 0 /* Reserved, DS, ACPI */ | F(MMX) |
615 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
616 0 /* HTT, TM, Reserved, PBE */
619 kvm_cpu_cap_mask(CPUID_7_0_EBX,
620 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) |
621 F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) |
622 F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) |
623 F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) |
624 F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) |
625 F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) |
628 kvm_cpu_cap_mask(CPUID_7_ECX,
629 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) |
630 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
631 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
632 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ |
633 F(SGX_LC) | F(BUS_LOCK_DETECT)
635 /* Set LA57 based on hardware capability. */
636 if (cpuid_ecx(7) & F(LA57))
637 kvm_cpu_cap_set(X86_FEATURE_LA57);
640 * PKU not yet implemented for shadow paging and requires OSPKE
641 * to be set on the host. Clear it if that is not the case
643 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE))
644 kvm_cpu_cap_clear(X86_FEATURE_PKU);
646 kvm_cpu_cap_mask(CPUID_7_EDX,
647 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
648 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
649 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
650 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) |
651 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16)
654 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
655 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST);
656 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES);
658 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS))
659 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL);
660 if (boot_cpu_has(X86_FEATURE_STIBP))
661 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP);
662 if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
663 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
665 kvm_cpu_cap_mask(CPUID_7_1_EAX,
666 F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | F(AMX_FP16) |
670 kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX,
671 F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(PREFETCHITI)
674 kvm_cpu_cap_mask(CPUID_D_1_EAX,
675 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd
678 kvm_cpu_cap_init_kvm_defined(CPUID_12_EAX,
679 SF(SGX1) | SF(SGX2) | SF(SGX_EDECCSSA)
682 kvm_cpu_cap_mask(CPUID_8000_0001_ECX,
683 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
684 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
685 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) |
686 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) |
687 F(TOPOEXT) | 0 /* PERFCTR_CORE */
690 kvm_cpu_cap_mask(CPUID_8000_0001_EDX,
691 F(FPU) | F(VME) | F(DE) | F(PSE) |
692 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
693 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
694 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
695 F(PAT) | F(PSE36) | 0 /* Reserved */ |
696 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
697 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) |
698 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW)
701 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64))
702 kvm_cpu_cap_set(X86_FEATURE_GBPAGES);
704 kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
705 F(CLZERO) | F(XSAVEERPTR) |
706 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
707 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
708 __feature_bit(KVM_X86_FEATURE_AMD_PSFD)
712 * AMD has separate bits for each SPEC_CTRL bit.
713 * arch/x86/kernel/cpu/bugs.c is kind enough to
714 * record that in cpufeatures so use them.
716 if (boot_cpu_has(X86_FEATURE_IBPB))
717 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB);
718 if (boot_cpu_has(X86_FEATURE_IBRS))
719 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS);
720 if (boot_cpu_has(X86_FEATURE_STIBP))
721 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP);
722 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
723 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD);
724 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
725 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO);
727 * The preference is to use SPEC CTRL MSR instead of the
730 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
731 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
732 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
735 * Hide all SVM features by default, SVM will set the cap bits for
736 * features it emulates and/or exposes for L1.
738 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0);
740 kvm_cpu_cap_mask(CPUID_8000_001F_EAX,
741 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) |
744 kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
745 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
746 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
751 * Hide RDTSCP and RDPID if either feature is reported as supported but
752 * probing MSR_TSC_AUX failed. This is purely a sanity check and
753 * should never happen, but the guest will likely crash if RDTSCP or
754 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in
755 * the past. For example, the sanity check may fire if this instance of
756 * KVM is running as L1 on top of an older, broken KVM.
758 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) ||
759 kvm_cpu_cap_has(X86_FEATURE_RDPID)) &&
760 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) {
761 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
762 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
765 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps);
767 struct kvm_cpuid_array {
768 struct kvm_cpuid_entry2 *entries;
773 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array,
774 u32 function, u32 index)
776 struct kvm_cpuid_entry2 *entry;
778 if (array->nent >= array->maxnent)
781 entry = &array->entries[array->nent++];
783 memset(entry, 0, sizeof(*entry));
784 entry->function = function;
785 entry->index = index;
786 switch (function & 0xC0000000) {
788 /* Hypervisor leaves are always synthesized by __do_cpuid_func. */
793 * 0x80000021 is sometimes synthesized by __do_cpuid_func, which
794 * would result in out-of-bounds calls to do_host_cpuid.
797 static int max_cpuid_80000000;
798 if (!READ_ONCE(max_cpuid_80000000))
799 WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000));
800 if (function > READ_ONCE(max_cpuid_80000000))
809 cpuid_count(entry->function, entry->index,
810 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
812 if (cpuid_function_is_indexed(function))
813 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
818 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func)
820 struct kvm_cpuid_entry2 *entry;
822 if (array->nent >= array->maxnent)
825 entry = &array->entries[array->nent];
826 entry->function = func;
836 entry->ecx = F(MOVBE);
840 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
842 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
843 entry->ecx = F(RDPID);
853 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
855 struct kvm_cpuid_entry2 *entry;
858 /* all calls to cpuid_count() should be made on the same cpu */
863 entry = do_host_cpuid(array, function, 0);
869 /* Limited to the highest leaf implemented in KVM. */
870 entry->eax = min(entry->eax, 0x1fU);
873 cpuid_entry_override(entry, CPUID_1_EDX);
874 cpuid_entry_override(entry, CPUID_1_ECX);
878 * On ancient CPUs, function 2 entries are STATEFUL. That is,
879 * CPUID(function=2, index=0) may return different results each
880 * time, with the least-significant byte in EAX enumerating the
881 * number of times software should do CPUID(2, 0).
883 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less
884 * idiotic. Intel's SDM states that EAX & 0xff "will always
885 * return 01H. Software should ignore this value and not
886 * interpret it as an informational descriptor", while AMD's
887 * APM states that CPUID(2) is reserved.
889 * WARN if a frankenstein CPU that supports virtualization and
890 * a stateful CPUID.0x2 is encountered.
892 WARN_ON_ONCE((entry->eax & 0xff) > 1);
894 /* functions 4 and 0x8000001d have additional index. */
898 * Read entries until the cache type in the previous entry is
899 * zero, i.e. indicates an invalid entry.
901 for (i = 1; entry->eax & 0x1f; ++i) {
902 entry = do_host_cpuid(array, function, i);
907 case 6: /* Thermal management */
908 entry->eax = 0x4; /* allow ARAT */
913 /* function 7 has additional index. */
915 entry->eax = min(entry->eax, 1u);
916 cpuid_entry_override(entry, CPUID_7_0_EBX);
917 cpuid_entry_override(entry, CPUID_7_ECX);
918 cpuid_entry_override(entry, CPUID_7_EDX);
920 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */
921 if (entry->eax == 1) {
922 entry = do_host_cpuid(array, function, 1);
926 cpuid_entry_override(entry, CPUID_7_1_EAX);
927 cpuid_entry_override(entry, CPUID_7_1_EDX);
932 case 0xa: { /* Architectural Performance Monitoring */
933 union cpuid10_eax eax;
934 union cpuid10_edx edx;
936 if (!static_cpu_has(X86_FEATURE_ARCH_PERFMON)) {
937 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
941 eax.split.version_id = kvm_pmu_cap.version;
942 eax.split.num_counters = kvm_pmu_cap.num_counters_gp;
943 eax.split.bit_width = kvm_pmu_cap.bit_width_gp;
944 eax.split.mask_length = kvm_pmu_cap.events_mask_len;
945 edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed;
946 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed;
948 if (kvm_pmu_cap.version)
949 edx.split.anythread_deprecated = 1;
950 edx.split.reserved1 = 0;
951 edx.split.reserved2 = 0;
953 entry->eax = eax.full;
954 entry->ebx = kvm_pmu_cap.events_mask;
956 entry->edx = edx.full;
960 * Per Intel's SDM, the 0x1f is a superset of 0xb,
961 * thus they can be handled by common code.
966 * Populate entries until the level type (ECX[15:8]) of the
967 * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is
968 * the starting entry, filled by the primary do_host_cpuid().
970 for (i = 1; entry->ecx & 0xff00; ++i) {
971 entry = do_host_cpuid(array, function, i);
977 u64 permitted_xcr0 = kvm_caps.supported_xcr0 & xstate_get_guest_group_perm();
978 u64 permitted_xss = kvm_caps.supported_xss;
980 entry->eax &= permitted_xcr0;
981 entry->ebx = xstate_required_size(permitted_xcr0, false);
982 entry->ecx = entry->ebx;
983 entry->edx &= permitted_xcr0 >> 32;
987 entry = do_host_cpuid(array, function, 1);
991 cpuid_entry_override(entry, CPUID_D_1_EAX);
992 if (entry->eax & (F(XSAVES)|F(XSAVEC)))
993 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss,
996 WARN_ON_ONCE(permitted_xss != 0);
999 entry->ecx &= permitted_xss;
1000 entry->edx &= permitted_xss >> 32;
1002 for (i = 2; i < 64; ++i) {
1004 if (permitted_xcr0 & BIT_ULL(i))
1006 else if (permitted_xss & BIT_ULL(i))
1011 entry = do_host_cpuid(array, function, i);
1016 * The supported check above should have filtered out
1017 * invalid sub-leafs. Only valid sub-leafs should
1018 * reach this point, and they should have a non-zero
1019 * save state size. Furthermore, check whether the
1020 * processor agrees with permitted_xcr0/permitted_xss
1021 * on whether this is an XCR0- or IA32_XSS-managed area.
1023 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) {
1028 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
1029 entry->ecx &= ~BIT_ULL(2);
1036 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) {
1037 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1042 * Index 0: Sub-features, MISCSELECT (a.k.a extended features)
1043 * and max enclave sizes. The SGX sub-features and MISCSELECT
1044 * are restricted by kernel and KVM capabilities (like most
1045 * feature flags), while enclave size is unrestricted.
1047 cpuid_entry_override(entry, CPUID_12_EAX);
1048 entry->ebx &= SGX_MISC_EXINFO;
1050 entry = do_host_cpuid(array, function, 1);
1055 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la
1056 * feature flags. Advertise all supported flags, including
1057 * privileged attributes that require explicit opt-in from
1058 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is
1059 * expected to derive it from supported XCR0.
1061 entry->eax &= SGX_ATTR_PRIV_MASK | SGX_ATTR_UNPRIV_MASK;
1066 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) {
1067 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1071 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
1072 if (!do_host_cpuid(array, function, i))
1076 /* Intel AMX TILE */
1078 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {
1079 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1083 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
1084 if (!do_host_cpuid(array, function, i))
1088 case 0x1e: /* TMUL information */
1089 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {
1090 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1094 case KVM_CPUID_SIGNATURE: {
1095 const u32 *sigptr = (const u32 *)KVM_SIGNATURE;
1096 entry->eax = KVM_CPUID_FEATURES;
1097 entry->ebx = sigptr[0];
1098 entry->ecx = sigptr[1];
1099 entry->edx = sigptr[2];
1102 case KVM_CPUID_FEATURES:
1103 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
1104 (1 << KVM_FEATURE_NOP_IO_DELAY) |
1105 (1 << KVM_FEATURE_CLOCKSOURCE2) |
1106 (1 << KVM_FEATURE_ASYNC_PF) |
1107 (1 << KVM_FEATURE_PV_EOI) |
1108 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) |
1109 (1 << KVM_FEATURE_PV_UNHALT) |
1110 (1 << KVM_FEATURE_PV_TLB_FLUSH) |
1111 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) |
1112 (1 << KVM_FEATURE_PV_SEND_IPI) |
1113 (1 << KVM_FEATURE_POLL_CONTROL) |
1114 (1 << KVM_FEATURE_PV_SCHED_YIELD) |
1115 (1 << KVM_FEATURE_ASYNC_PF_INT);
1117 if (sched_info_on())
1118 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
1125 entry->eax = min(entry->eax, 0x80000021);
1127 * Serializing LFENCE is reported in a multitude of ways, and
1128 * NullSegClearsBase is not reported in CPUID on Zen2; help
1129 * userspace by providing the CPUID leaf ourselves.
1131 * However, only do it if the host has CPUID leaf 0x8000001d.
1132 * QEMU thinks that it can query the host blindly for that
1133 * CPUID leaf if KVM reports that it supports 0x8000001d or
1134 * above. The processor merrily returns values from the
1135 * highest Intel leaf which QEMU tries to use as the guest's
1136 * 0x8000001d. Even worse, this can result in an infinite
1137 * loop if said highest leaf has no subleaves indexed by ECX.
1139 if (entry->eax >= 0x8000001d &&
1140 (static_cpu_has(X86_FEATURE_LFENCE_RDTSC)
1141 || !static_cpu_has_bug(X86_BUG_NULL_SEG)))
1142 entry->eax = max(entry->eax, 0x80000021);
1145 entry->ebx &= ~GENMASK(27, 16);
1146 cpuid_entry_override(entry, CPUID_8000_0001_EDX);
1147 cpuid_entry_override(entry, CPUID_8000_0001_ECX);
1150 /* Drop reserved bits, pass host L2 cache and TLB info. */
1151 entry->edx &= ~GENMASK(17, 16);
1153 case 0x80000007: /* Advanced power management */
1154 /* invariant TSC is CPUID.80000007H:EDX[8] */
1155 entry->edx &= (1 << 8);
1156 /* mask against host */
1157 entry->edx &= boot_cpu_data.x86_power;
1158 entry->eax = entry->ebx = entry->ecx = 0;
1161 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
1162 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
1163 unsigned phys_as = entry->eax & 0xff;
1166 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as
1167 * the guest operates in the same PA space as the host, i.e.
1168 * reductions in MAXPHYADDR for memory encryption affect shadow
1171 * If TDP is enabled but an explicit guest MAXPHYADDR is not
1172 * provided, use the raw bare metal MAXPHYADDR as reductions to
1173 * the HPAs do not affect GPAs.
1176 g_phys_as = boot_cpu_data.x86_phys_bits;
1177 else if (!g_phys_as)
1178 g_phys_as = phys_as;
1180 entry->eax = g_phys_as | (virt_as << 8);
1181 entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8));
1183 cpuid_entry_override(entry, CPUID_8000_0008_EBX);
1187 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) {
1188 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1191 entry->eax = 1; /* SVM revision 1 */
1192 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
1193 ASID emulation to nested SVM */
1194 entry->ecx = 0; /* Reserved */
1195 cpuid_entry_override(entry, CPUID_8000_000A_EDX);
1198 entry->ecx = entry->edx = 0;
1201 entry->eax &= GENMASK(2, 0);
1202 entry->ebx = entry->ecx = entry->edx = 0;
1207 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) {
1208 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1210 cpuid_entry_override(entry, CPUID_8000_001F_EAX);
1211 /* Clear NumVMPL since KVM does not support VMPL. */
1212 entry->ebx &= ~GENMASK(31, 12);
1214 * Enumerate '0' for "PA bits reduction", the adjusted
1215 * MAXPHYADDR is enumerated directly (see 0x80000008).
1217 entry->ebx &= ~GENMASK(11, 6);
1221 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1224 entry->ebx = entry->ecx = entry->edx = 0;
1226 * Pass down these bits:
1227 * EAX 0 NNDBP, Processor ignores nested data breakpoints
1228 * EAX 2 LAS, LFENCE always serializing
1229 * EAX 6 NSCB, Null selector clear base
1231 * Other defined bits are for MSRs that KVM does not expose:
1232 * EAX 3 SPCL, SMM page configuration lock
1233 * EAX 13 PCMSR, Prefetch control MSR
1235 * KVM doesn't support SMM_CTL.
1236 * EAX 9 SMM_CTL MSR is not supported
1238 entry->eax &= BIT(0) | BIT(2) | BIT(6);
1239 entry->eax |= BIT(9);
1240 if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC))
1241 entry->eax |= BIT(2);
1242 if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
1243 entry->eax |= BIT(6);
1245 /*Add support for Centaur's CPUID instruction*/
1247 /*Just support up to 0xC0000004 now*/
1248 entry->eax = min(entry->eax, 0xC0000004);
1251 cpuid_entry_override(entry, CPUID_C000_0001_EDX);
1253 case 3: /* Processor serial number */
1254 case 5: /* MONITOR/MWAIT */
1259 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1271 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func,
1274 if (type == KVM_GET_EMULATED_CPUID)
1275 return __do_cpuid_func_emulated(array, func);
1277 return __do_cpuid_func(array, func);
1280 #define CENTAUR_CPUID_SIGNATURE 0xC0000000
1282 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func,
1288 if (func == CENTAUR_CPUID_SIGNATURE &&
1289 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR)
1292 r = do_cpuid_func(array, func, type);
1296 limit = array->entries[array->nent - 1].eax;
1297 for (func = func + 1; func <= limit; ++func) {
1298 r = do_cpuid_func(array, func, type);
1306 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries,
1307 __u32 num_entries, unsigned int ioctl_type)
1312 if (ioctl_type != KVM_GET_EMULATED_CPUID)
1316 * We want to make sure that ->padding is being passed clean from
1317 * userspace in case we want to use it for something in the future.
1319 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we
1320 * have to give ourselves satisfied only with the emulated side. /me
1323 for (i = 0; i < num_entries; i++) {
1324 if (copy_from_user(pad, entries[i].padding, sizeof(pad)))
1327 if (pad[0] || pad[1] || pad[2])
1333 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid,
1334 struct kvm_cpuid_entry2 __user *entries,
1337 static const u32 funcs[] = {
1338 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE,
1341 struct kvm_cpuid_array array = {
1346 if (cpuid->nent < 1)
1348 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1349 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
1351 if (sanity_check_entries(entries, cpuid->nent, type))
1354 array.entries = kvcalloc(cpuid->nent, sizeof(struct kvm_cpuid_entry2), GFP_KERNEL);
1358 array.maxnent = cpuid->nent;
1360 for (i = 0; i < ARRAY_SIZE(funcs); i++) {
1361 r = get_cpuid_func(&array, funcs[i], type);
1365 cpuid->nent = array.nent;
1367 if (copy_to_user(entries, array.entries,
1368 array.nent * sizeof(struct kvm_cpuid_entry2)))
1372 kvfree(array.entries);
1376 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry_index(struct kvm_vcpu *vcpu,
1377 u32 function, u32 index)
1379 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent,
1382 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry_index);
1384 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
1387 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent,
1388 function, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
1390 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
1393 * Intel CPUID semantics treats any query for an out-of-range leaf as if the
1394 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics
1395 * returns all zeroes for any undefined leaf, whether or not the leaf is in
1396 * range. Centaur/VIA follows Intel semantics.
1398 * A leaf is considered out-of-range if its function is higher than the maximum
1399 * supported leaf of its associated class or if its associated class does not
1402 * There are three primary classes to be considered, with their respective
1403 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary
1404 * class exists if a guest CPUID entry for its <base> leaf exists. For a given
1405 * class, CPUID.<base>.EAX contains the max supported leaf for the class.
1407 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff
1408 * - Hypervisor: 0x40000000 - 0x4fffffff
1409 * - Extended: 0x80000000 - 0xbfffffff
1410 * - Centaur: 0xc0000000 - 0xcfffffff
1412 * The Hypervisor class is further subdivided into sub-classes that each act as
1413 * their own independent class associated with a 0x100 byte range. E.g. if Qemu
1414 * is advertising support for both HyperV and KVM, the resulting Hypervisor
1415 * CPUID sub-classes are:
1417 * - HyperV: 0x40000000 - 0x400000ff
1418 * - KVM: 0x40000100 - 0x400001ff
1420 static struct kvm_cpuid_entry2 *
1421 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index)
1423 struct kvm_cpuid_entry2 *basic, *class;
1424 u32 function = *fn_ptr;
1426 basic = kvm_find_cpuid_entry(vcpu, 0);
1430 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) ||
1431 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx))
1434 if (function >= 0x40000000 && function <= 0x4fffffff)
1435 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00);
1436 else if (function >= 0xc0000000)
1437 class = kvm_find_cpuid_entry(vcpu, 0xc0000000);
1439 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000);
1441 if (class && function <= class->eax)
1445 * Leaf specific adjustments are also applied when redirecting to the
1446 * max basic entry, e.g. if the max basic leaf is 0xb but there is no
1447 * entry for CPUID.0xb.index (see below), then the output value for EDX
1448 * needs to be pulled from CPUID.0xb.1.
1450 *fn_ptr = basic->eax;
1453 * The class does not exist or the requested function is out of range;
1454 * the effective CPUID entry is the max basic leaf. Note, the index of
1455 * the original requested leaf is observed!
1457 return kvm_find_cpuid_entry_index(vcpu, basic->eax, index);
1460 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx,
1461 u32 *ecx, u32 *edx, bool exact_only)
1463 u32 orig_function = *eax, function = *eax, index = *ecx;
1464 struct kvm_cpuid_entry2 *entry;
1465 bool exact, used_max_basic = false;
1467 entry = kvm_find_cpuid_entry_index(vcpu, function, index);
1470 if (!entry && !exact_only) {
1471 entry = get_out_of_range_cpuid_entry(vcpu, &function, index);
1472 used_max_basic = !!entry;
1480 if (function == 7 && index == 0) {
1482 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) &&
1483 (data & TSX_CTRL_CPUID_CLEAR))
1484 *ebx &= ~(F(RTM) | F(HLE));
1487 *eax = *ebx = *ecx = *edx = 0;
1489 * When leaf 0BH or 1FH is defined, CL is pass-through
1490 * and EDX is always the x2APIC ID, even for undefined
1491 * subleaves. Index 1 will exist iff the leaf is
1492 * implemented, so we pass through CL iff leaf 1
1493 * exists. EDX can be copied from any existing index.
1495 if (function == 0xb || function == 0x1f) {
1496 entry = kvm_find_cpuid_entry_index(vcpu, function, 1);
1498 *ecx = index & 0xff;
1503 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact,
1507 EXPORT_SYMBOL_GPL(kvm_cpuid);
1509 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
1511 u32 eax, ebx, ecx, edx;
1513 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0))
1516 eax = kvm_rax_read(vcpu);
1517 ecx = kvm_rcx_read(vcpu);
1518 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false);
1519 kvm_rax_write(vcpu, eax);
1520 kvm_rbx_write(vcpu, ebx);
1521 kvm_rcx_write(vcpu, ecx);
1522 kvm_rdx_write(vcpu, edx);
1523 return kvm_skip_emulated_instruction(vcpu);
1525 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);