1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
4 * cpuid support routines
6 * derived from arch/x86/kvm/x86.c
8 * Copyright 2011 Red Hat, Inc. and/or its affiliates.
9 * Copyright IBM Corporation, 2008
12 #include <linux/kvm_host.h>
13 #include <linux/export.h>
14 #include <linux/vmalloc.h>
15 #include <linux/uaccess.h>
16 #include <linux/sched/stat.h>
18 #include <asm/processor.h>
20 #include <asm/fpu/xstate.h>
29 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be
30 * aligned to sizeof(unsigned long) because it's not accessed via bitops.
32 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly;
33 EXPORT_SYMBOL_GPL(kvm_cpu_caps);
35 u32 xstate_required_size(u64 xstate_bv, bool compacted)
38 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
40 xstate_bv &= XFEATURE_MASK_EXTEND;
42 if (xstate_bv & 0x1) {
43 u32 eax, ebx, ecx, edx, offset;
44 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx);
45 /* ECX[1]: 64B alignment in compacted form */
47 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret;
50 ret = max(ret, offset + eax);
61 * This one is tied to SSB in the user API, and not
62 * visible in /proc/cpuinfo.
64 #define KVM_X86_FEATURE_PSFD (13*32+28) /* Predictive Store Forwarding Disable */
67 #define SF(name) (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0)
70 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find(
71 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u32 index)
73 struct kvm_cpuid_entry2 *e;
76 for (i = 0; i < nent; i++) {
79 if (e->function == function &&
80 (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index))
87 static int kvm_check_cpuid(struct kvm_vcpu *vcpu,
88 struct kvm_cpuid_entry2 *entries,
91 struct kvm_cpuid_entry2 *best;
95 * The existing code assumes virtual address is 48-bit or 57-bit in the
96 * canonical address checks; exit if it is ever changed.
98 best = cpuid_entry2_find(entries, nent, 0x80000008, 0);
100 int vaddr_bits = (best->eax & 0xff00) >> 8;
102 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0)
107 * Exposing dynamic xfeatures to the guest requires additional
108 * enabling in the FPU, e.g. to expand the guest XSAVE state size.
110 best = cpuid_entry2_find(entries, nent, 0xd, 0);
114 xfeatures = best->eax | ((u64)best->edx << 32);
115 xfeatures &= XFEATURE_MASK_USER_DYNAMIC;
119 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures);
122 /* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */
123 static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2,
126 struct kvm_cpuid_entry2 *orig;
129 if (nent != vcpu->arch.cpuid_nent)
132 for (i = 0; i < nent; i++) {
133 orig = &vcpu->arch.cpuid_entries[i];
134 if (e2[i].function != orig->function ||
135 e2[i].index != orig->index ||
136 e2[i].flags != orig->flags ||
137 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx ||
138 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx)
145 static void kvm_update_kvm_cpuid_base(struct kvm_vcpu *vcpu)
148 struct kvm_cpuid_entry2 *entry;
150 vcpu->arch.kvm_cpuid_base = 0;
152 for_each_possible_hypervisor_cpuid_base(function) {
153 entry = kvm_find_cpuid_entry(vcpu, function, 0);
158 signature[0] = entry->ebx;
159 signature[1] = entry->ecx;
160 signature[2] = entry->edx;
162 BUILD_BUG_ON(sizeof(signature) > sizeof(KVM_SIGNATURE));
163 if (!memcmp(signature, KVM_SIGNATURE, sizeof(signature))) {
164 vcpu->arch.kvm_cpuid_base = function;
171 static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu,
172 struct kvm_cpuid_entry2 *entries, int nent)
174 u32 base = vcpu->arch.kvm_cpuid_base;
179 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES, 0);
182 static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu)
184 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries,
185 vcpu->arch.cpuid_nent);
188 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu)
190 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu);
193 * save the feature bitmap to avoid cpuid lookup for every PV
197 vcpu->arch.pv_cpuid.features = best->eax;
201 * Calculate guest's supported XCR0 taking into account guest CPUID data and
202 * supported_xcr0 (comprised of host configuration and KVM_SUPPORTED_XCR0).
204 static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent)
206 struct kvm_cpuid_entry2 *best;
208 best = cpuid_entry2_find(entries, nent, 0xd, 0);
212 return (best->eax | ((u64)best->edx << 32)) & supported_xcr0;
215 static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries,
218 struct kvm_cpuid_entry2 *best;
219 u64 guest_supported_xcr0 = cpuid_get_supported_xcr0(entries, nent);
221 best = cpuid_entry2_find(entries, nent, 1, 0);
223 /* Update OSXSAVE bit */
224 if (boot_cpu_has(X86_FEATURE_XSAVE))
225 cpuid_entry_change(best, X86_FEATURE_OSXSAVE,
226 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE));
228 cpuid_entry_change(best, X86_FEATURE_APIC,
229 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE);
232 best = cpuid_entry2_find(entries, nent, 7, 0);
233 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7)
234 cpuid_entry_change(best, X86_FEATURE_OSPKE,
235 kvm_read_cr4_bits(vcpu, X86_CR4_PKE));
237 best = cpuid_entry2_find(entries, nent, 0xD, 0);
239 best->ebx = xstate_required_size(vcpu->arch.xcr0, false);
241 best = cpuid_entry2_find(entries, nent, 0xD, 1);
242 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) ||
243 cpuid_entry_has(best, X86_FEATURE_XSAVEC)))
244 best->ebx = xstate_required_size(vcpu->arch.xcr0, true);
246 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent);
247 if (kvm_hlt_in_guest(vcpu->kvm) && best &&
248 (best->eax & (1 << KVM_FEATURE_PV_UNHALT)))
249 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT);
251 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) {
252 best = cpuid_entry2_find(entries, nent, 0x1, 0);
254 cpuid_entry_change(best, X86_FEATURE_MWAIT,
255 vcpu->arch.ia32_misc_enable_msr &
256 MSR_IA32_MISC_ENABLE_MWAIT);
260 * Bits 127:0 of the allowed SECS.ATTRIBUTES (CPUID.0x12.0x1) enumerate
261 * the supported XSAVE Feature Request Mask (XFRM), i.e. the enclave's
262 * requested XCR0 value. The enclave's XFRM must be a subset of XCRO
263 * at the time of EENTER, thus adjust the allowed XFRM by the guest's
264 * supported XCR0. Similar to XCR0 handling, FP and SSE are forced to
265 * '1' even on CPUs that don't support XSAVE.
267 best = cpuid_entry2_find(entries, nent, 0x12, 0x1);
269 best->ecx &= guest_supported_xcr0 & 0xffffffff;
270 best->edx &= guest_supported_xcr0 >> 32;
271 best->ecx |= XFEATURE_MASK_FPSSE;
275 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu)
277 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
279 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime);
281 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
283 struct kvm_lapic *apic = vcpu->arch.apic;
284 struct kvm_cpuid_entry2 *best;
285 u64 guest_supported_xcr0;
287 best = kvm_find_cpuid_entry(vcpu, 1, 0);
289 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER))
290 apic->lapic_timer.timer_mode_mask = 3 << 17;
292 apic->lapic_timer.timer_mode_mask = 1 << 17;
294 kvm_apic_set_version(vcpu);
297 guest_supported_xcr0 =
298 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
300 vcpu->arch.guest_fpu.fpstate->user_xfeatures = guest_supported_xcr0;
302 kvm_update_pv_runtime(vcpu);
304 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
305 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
307 kvm_pmu_refresh(vcpu);
308 vcpu->arch.cr4_guest_rsvd_bits =
309 __cr4_reserved_bits(guest_cpuid_has, vcpu);
311 kvm_hv_set_cpuid(vcpu);
313 /* Invoke the vendor callback only after the above state is updated. */
314 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu);
317 * Except for the MMU, which needs to do its thing any vendor specific
318 * adjustments to the reserved GPA bits.
320 kvm_mmu_after_set_cpuid(vcpu);
323 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu)
325 struct kvm_cpuid_entry2 *best;
327 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
328 if (!best || best->eax < 0x80000008)
330 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
332 return best->eax & 0xff;
338 * This "raw" version returns the reserved GPA bits without any adjustments for
339 * encryption technologies that usurp bits. The raw mask should be used if and
340 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs.
342 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu)
344 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63);
347 static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2,
352 __kvm_update_cpuid_runtime(vcpu, e2, nent);
355 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
356 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
357 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
358 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with
359 * the core vCPU model on the fly. It would've been better to forbid any
360 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately
361 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do
362 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check
363 * whether the supplied CPUID data is equal to what's already set.
365 if (vcpu->arch.last_vmentry_cpu != -1) {
366 r = kvm_cpuid_check_equal(vcpu, e2, nent);
374 r = kvm_check_cpuid(vcpu, e2, nent);
378 kvfree(vcpu->arch.cpuid_entries);
379 vcpu->arch.cpuid_entries = e2;
380 vcpu->arch.cpuid_nent = nent;
382 kvm_update_kvm_cpuid_base(vcpu);
383 kvm_vcpu_after_set_cpuid(vcpu);
388 /* when an old userspace process fills a new kernel module */
389 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
390 struct kvm_cpuid *cpuid,
391 struct kvm_cpuid_entry __user *entries)
394 struct kvm_cpuid_entry *e = NULL;
395 struct kvm_cpuid_entry2 *e2 = NULL;
397 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
401 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent));
405 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT);
411 for (i = 0; i < cpuid->nent; i++) {
412 e2[i].function = e[i].function;
413 e2[i].eax = e[i].eax;
414 e2[i].ebx = e[i].ebx;
415 e2[i].ecx = e[i].ecx;
416 e2[i].edx = e[i].edx;
419 e2[i].padding[0] = 0;
420 e2[i].padding[1] = 0;
421 e2[i].padding[2] = 0;
424 r = kvm_set_cpuid(vcpu, e2, cpuid->nent);
434 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
435 struct kvm_cpuid2 *cpuid,
436 struct kvm_cpuid_entry2 __user *entries)
438 struct kvm_cpuid_entry2 *e2 = NULL;
441 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
445 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent));
450 r = kvm_set_cpuid(vcpu, e2, cpuid->nent);
457 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
458 struct kvm_cpuid2 *cpuid,
459 struct kvm_cpuid_entry2 __user *entries)
464 if (cpuid->nent < vcpu->arch.cpuid_nent)
467 if (copy_to_user(entries, vcpu->arch.cpuid_entries,
468 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
473 cpuid->nent = vcpu->arch.cpuid_nent;
477 /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */
478 static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf)
480 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32);
481 struct kvm_cpuid_entry2 entry;
483 reverse_cpuid_check(leaf);
485 cpuid_count(cpuid.function, cpuid.index,
486 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx);
488 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg);
491 static __always_inline
492 void kvm_cpu_cap_init_scattered(enum kvm_only_cpuid_leafs leaf, u32 mask)
494 /* Use kvm_cpu_cap_mask for non-scattered leafs. */
495 BUILD_BUG_ON(leaf < NCAPINTS);
497 kvm_cpu_caps[leaf] = mask;
499 __kvm_cpu_cap_mask(leaf);
502 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask)
504 /* Use kvm_cpu_cap_init_scattered for scattered leafs. */
505 BUILD_BUG_ON(leaf >= NCAPINTS);
507 kvm_cpu_caps[leaf] &= mask;
509 __kvm_cpu_cap_mask(leaf);
512 void kvm_set_cpu_caps(void)
515 unsigned int f_gbpages = F(GBPAGES);
516 unsigned int f_lm = F(LM);
517 unsigned int f_xfd = F(XFD);
519 unsigned int f_gbpages = 0;
520 unsigned int f_lm = 0;
521 unsigned int f_xfd = 0;
523 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps));
525 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) >
526 sizeof(boot_cpu_data.x86_capability));
528 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability,
529 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)));
531 kvm_cpu_cap_mask(CPUID_1_ECX,
533 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not*
534 * advertised to guests via CPUID!
536 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
537 0 /* DS-CPL, VMX, SMX, EST */ |
538 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
539 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) |
540 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
541 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
542 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
545 /* KVM emulates x2apic in software irrespective of host support. */
546 kvm_cpu_cap_set(X86_FEATURE_X2APIC);
548 kvm_cpu_cap_mask(CPUID_1_EDX,
549 F(FPU) | F(VME) | F(DE) | F(PSE) |
550 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
551 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
552 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
553 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) |
554 0 /* Reserved, DS, ACPI */ | F(MMX) |
555 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
556 0 /* HTT, TM, Reserved, PBE */
559 kvm_cpu_cap_mask(CPUID_7_0_EBX,
560 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) |
561 F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) |
562 F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) |
563 F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) |
564 F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) |
565 F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) |
568 kvm_cpu_cap_mask(CPUID_7_ECX,
569 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) |
570 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
571 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
572 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ |
573 F(SGX_LC) | F(BUS_LOCK_DETECT)
575 /* Set LA57 based on hardware capability. */
576 if (cpuid_ecx(7) & F(LA57))
577 kvm_cpu_cap_set(X86_FEATURE_LA57);
580 * PKU not yet implemented for shadow paging and requires OSPKE
581 * to be set on the host. Clear it if that is not the case
583 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE))
584 kvm_cpu_cap_clear(X86_FEATURE_PKU);
586 kvm_cpu_cap_mask(CPUID_7_EDX,
587 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
588 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
589 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
590 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) |
591 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16)
594 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
595 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST);
596 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES);
598 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS))
599 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL);
600 if (boot_cpu_has(X86_FEATURE_STIBP))
601 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP);
602 if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
603 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
605 kvm_cpu_cap_mask(CPUID_7_1_EAX,
606 F(AVX_VNNI) | F(AVX512_BF16)
609 kvm_cpu_cap_mask(CPUID_D_1_EAX,
610 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd
613 kvm_cpu_cap_init_scattered(CPUID_12_EAX,
617 kvm_cpu_cap_mask(CPUID_8000_0001_ECX,
618 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
619 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
620 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) |
621 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) |
622 F(TOPOEXT) | 0 /* PERFCTR_CORE */
625 kvm_cpu_cap_mask(CPUID_8000_0001_EDX,
626 F(FPU) | F(VME) | F(DE) | F(PSE) |
627 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
628 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
629 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
630 F(PAT) | F(PSE36) | 0 /* Reserved */ |
631 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
632 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) |
633 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW)
636 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64))
637 kvm_cpu_cap_set(X86_FEATURE_GBPAGES);
639 kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
640 F(CLZERO) | F(XSAVEERPTR) |
641 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
642 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
643 __feature_bit(KVM_X86_FEATURE_PSFD)
647 * AMD has separate bits for each SPEC_CTRL bit.
648 * arch/x86/kernel/cpu/bugs.c is kind enough to
649 * record that in cpufeatures so use them.
651 if (boot_cpu_has(X86_FEATURE_IBPB))
652 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB);
653 if (boot_cpu_has(X86_FEATURE_IBRS))
654 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS);
655 if (boot_cpu_has(X86_FEATURE_STIBP))
656 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP);
657 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
658 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD);
659 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
660 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO);
662 * The preference is to use SPEC CTRL MSR instead of the
665 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
666 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
667 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
670 * Hide all SVM features by default, SVM will set the cap bits for
671 * features it emulates and/or exposes for L1.
673 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0);
675 kvm_cpu_cap_mask(CPUID_8000_001F_EAX,
676 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) |
679 kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
680 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
681 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
686 * Hide RDTSCP and RDPID if either feature is reported as supported but
687 * probing MSR_TSC_AUX failed. This is purely a sanity check and
688 * should never happen, but the guest will likely crash if RDTSCP or
689 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in
690 * the past. For example, the sanity check may fire if this instance of
691 * KVM is running as L1 on top of an older, broken KVM.
693 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) ||
694 kvm_cpu_cap_has(X86_FEATURE_RDPID)) &&
695 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) {
696 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
697 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
700 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps);
702 struct kvm_cpuid_array {
703 struct kvm_cpuid_entry2 *entries;
708 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array,
709 u32 function, u32 index)
711 struct kvm_cpuid_entry2 *entry;
713 if (array->nent >= array->maxnent)
716 entry = &array->entries[array->nent++];
718 memset(entry, 0, sizeof(*entry));
719 entry->function = function;
720 entry->index = index;
721 switch (function & 0xC0000000) {
723 /* Hypervisor leaves are always synthesized by __do_cpuid_func. */
728 * 0x80000021 is sometimes synthesized by __do_cpuid_func, which
729 * would result in out-of-bounds calls to do_host_cpuid.
732 static int max_cpuid_80000000;
733 if (!READ_ONCE(max_cpuid_80000000))
734 WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000));
735 if (function > READ_ONCE(max_cpuid_80000000))
744 cpuid_count(entry->function, entry->index,
745 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
762 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
769 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func)
771 struct kvm_cpuid_entry2 *entry;
773 if (array->nent >= array->maxnent)
776 entry = &array->entries[array->nent];
777 entry->function = func;
787 entry->ecx = F(MOVBE);
791 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
793 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
794 entry->ecx = F(RDPID);
804 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
806 struct kvm_cpuid_entry2 *entry;
809 /* all calls to cpuid_count() should be made on the same cpu */
814 entry = do_host_cpuid(array, function, 0);
820 /* Limited to the highest leaf implemented in KVM. */
821 entry->eax = min(entry->eax, 0x1fU);
824 cpuid_entry_override(entry, CPUID_1_EDX);
825 cpuid_entry_override(entry, CPUID_1_ECX);
829 * On ancient CPUs, function 2 entries are STATEFUL. That is,
830 * CPUID(function=2, index=0) may return different results each
831 * time, with the least-significant byte in EAX enumerating the
832 * number of times software should do CPUID(2, 0).
834 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less
835 * idiotic. Intel's SDM states that EAX & 0xff "will always
836 * return 01H. Software should ignore this value and not
837 * interpret it as an informational descriptor", while AMD's
838 * APM states that CPUID(2) is reserved.
840 * WARN if a frankenstein CPU that supports virtualization and
841 * a stateful CPUID.0x2 is encountered.
843 WARN_ON_ONCE((entry->eax & 0xff) > 1);
845 /* functions 4 and 0x8000001d have additional index. */
849 * Read entries until the cache type in the previous entry is
850 * zero, i.e. indicates an invalid entry.
852 for (i = 1; entry->eax & 0x1f; ++i) {
853 entry = do_host_cpuid(array, function, i);
858 case 6: /* Thermal management */
859 entry->eax = 0x4; /* allow ARAT */
864 /* function 7 has additional index. */
866 entry->eax = min(entry->eax, 1u);
867 cpuid_entry_override(entry, CPUID_7_0_EBX);
868 cpuid_entry_override(entry, CPUID_7_ECX);
869 cpuid_entry_override(entry, CPUID_7_EDX);
871 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */
872 if (entry->eax == 1) {
873 entry = do_host_cpuid(array, function, 1);
877 cpuid_entry_override(entry, CPUID_7_1_EAX);
885 case 0xa: { /* Architectural Performance Monitoring */
886 struct x86_pmu_capability cap;
887 union cpuid10_eax eax;
888 union cpuid10_edx edx;
890 perf_get_x86_pmu_capability(&cap);
893 * The guest architecture pmu is only supported if the architecture
894 * pmu exists on the host and the module parameters allow it.
896 if (!cap.version || !enable_pmu)
897 memset(&cap, 0, sizeof(cap));
899 eax.split.version_id = min(cap.version, 2);
900 eax.split.num_counters = cap.num_counters_gp;
901 eax.split.bit_width = cap.bit_width_gp;
902 eax.split.mask_length = cap.events_mask_len;
904 edx.split.num_counters_fixed =
905 min(cap.num_counters_fixed, KVM_PMC_MAX_FIXED);
906 edx.split.bit_width_fixed = cap.bit_width_fixed;
908 edx.split.anythread_deprecated = 1;
909 edx.split.reserved1 = 0;
910 edx.split.reserved2 = 0;
912 entry->eax = eax.full;
913 entry->ebx = cap.events_mask;
915 entry->edx = edx.full;
919 * Per Intel's SDM, the 0x1f is a superset of 0xb,
920 * thus they can be handled by common code.
925 * Populate entries until the level type (ECX[15:8]) of the
926 * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is
927 * the starting entry, filled by the primary do_host_cpuid().
929 for (i = 1; entry->ecx & 0xff00; ++i) {
930 entry = do_host_cpuid(array, function, i);
936 u64 permitted_xcr0 = supported_xcr0 & xstate_get_guest_group_perm();
937 u64 permitted_xss = supported_xss;
939 entry->eax &= permitted_xcr0;
940 entry->ebx = xstate_required_size(permitted_xcr0, false);
941 entry->ecx = entry->ebx;
942 entry->edx &= permitted_xcr0 >> 32;
946 entry = do_host_cpuid(array, function, 1);
950 cpuid_entry_override(entry, CPUID_D_1_EAX);
951 if (entry->eax & (F(XSAVES)|F(XSAVEC)))
952 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss,
955 WARN_ON_ONCE(permitted_xss != 0);
958 entry->ecx &= permitted_xss;
959 entry->edx &= permitted_xss >> 32;
961 for (i = 2; i < 64; ++i) {
963 if (permitted_xcr0 & BIT_ULL(i))
965 else if (permitted_xss & BIT_ULL(i))
970 entry = do_host_cpuid(array, function, i);
975 * The supported check above should have filtered out
976 * invalid sub-leafs. Only valid sub-leafs should
977 * reach this point, and they should have a non-zero
978 * save state size. Furthermore, check whether the
979 * processor agrees with permitted_xcr0/permitted_xss
980 * on whether this is an XCR0- or IA32_XSS-managed area.
982 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) {
987 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
988 entry->ecx &= ~BIT_ULL(2);
995 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) {
996 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1001 * Index 0: Sub-features, MISCSELECT (a.k.a extended features)
1002 * and max enclave sizes. The SGX sub-features and MISCSELECT
1003 * are restricted by kernel and KVM capabilities (like most
1004 * feature flags), while enclave size is unrestricted.
1006 cpuid_entry_override(entry, CPUID_12_EAX);
1007 entry->ebx &= SGX_MISC_EXINFO;
1009 entry = do_host_cpuid(array, function, 1);
1014 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la
1015 * feature flags. Advertise all supported flags, including
1016 * privileged attributes that require explicit opt-in from
1017 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is
1018 * expected to derive it from supported XCR0.
1020 entry->eax &= SGX_ATTR_DEBUG | SGX_ATTR_MODE64BIT |
1021 SGX_ATTR_PROVISIONKEY | SGX_ATTR_EINITTOKENKEY |
1027 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) {
1028 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1032 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
1033 if (!do_host_cpuid(array, function, i))
1037 /* Intel AMX TILE */
1039 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {
1040 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1044 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
1045 if (!do_host_cpuid(array, function, i))
1049 case 0x1e: /* TMUL information */
1050 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {
1051 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1055 case KVM_CPUID_SIGNATURE: {
1056 const u32 *sigptr = (const u32 *)KVM_SIGNATURE;
1057 entry->eax = KVM_CPUID_FEATURES;
1058 entry->ebx = sigptr[0];
1059 entry->ecx = sigptr[1];
1060 entry->edx = sigptr[2];
1063 case KVM_CPUID_FEATURES:
1064 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
1065 (1 << KVM_FEATURE_NOP_IO_DELAY) |
1066 (1 << KVM_FEATURE_CLOCKSOURCE2) |
1067 (1 << KVM_FEATURE_ASYNC_PF) |
1068 (1 << KVM_FEATURE_PV_EOI) |
1069 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) |
1070 (1 << KVM_FEATURE_PV_UNHALT) |
1071 (1 << KVM_FEATURE_PV_TLB_FLUSH) |
1072 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) |
1073 (1 << KVM_FEATURE_PV_SEND_IPI) |
1074 (1 << KVM_FEATURE_POLL_CONTROL) |
1075 (1 << KVM_FEATURE_PV_SCHED_YIELD) |
1076 (1 << KVM_FEATURE_ASYNC_PF_INT);
1078 if (sched_info_on())
1079 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
1086 entry->eax = min(entry->eax, 0x80000021);
1088 * Serializing LFENCE is reported in a multitude of ways,
1089 * and NullSegClearsBase is not reported in CPUID on Zen2;
1090 * help userspace by providing the CPUID leaf ourselves.
1092 if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC)
1093 || !static_cpu_has_bug(X86_BUG_NULL_SEG))
1094 entry->eax = max(entry->eax, 0x80000021);
1097 cpuid_entry_override(entry, CPUID_8000_0001_EDX);
1098 cpuid_entry_override(entry, CPUID_8000_0001_ECX);
1101 /* L2 cache and TLB: pass through host info. */
1103 case 0x80000007: /* Advanced power management */
1104 /* invariant TSC is CPUID.80000007H:EDX[8] */
1105 entry->edx &= (1 << 8);
1106 /* mask against host */
1107 entry->edx &= boot_cpu_data.x86_power;
1108 entry->eax = entry->ebx = entry->ecx = 0;
1111 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
1112 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
1113 unsigned phys_as = entry->eax & 0xff;
1116 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as
1117 * the guest operates in the same PA space as the host, i.e.
1118 * reductions in MAXPHYADDR for memory encryption affect shadow
1121 * If TDP is enabled but an explicit guest MAXPHYADDR is not
1122 * provided, use the raw bare metal MAXPHYADDR as reductions to
1123 * the HPAs do not affect GPAs.
1126 g_phys_as = boot_cpu_data.x86_phys_bits;
1127 else if (!g_phys_as)
1128 g_phys_as = phys_as;
1130 entry->eax = g_phys_as | (virt_as << 8);
1132 cpuid_entry_override(entry, CPUID_8000_0008_EBX);
1136 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) {
1137 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1140 entry->eax = 1; /* SVM revision 1 */
1141 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
1142 ASID emulation to nested SVM */
1143 entry->ecx = 0; /* Reserved */
1144 cpuid_entry_override(entry, CPUID_8000_000A_EDX);
1147 entry->ecx = entry->edx = 0;
1153 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) {
1154 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1156 cpuid_entry_override(entry, CPUID_8000_001F_EAX);
1159 * Enumerate '0' for "PA bits reduction", the adjusted
1160 * MAXPHYADDR is enumerated directly (see 0x80000008).
1162 entry->ebx &= ~GENMASK(11, 6);
1166 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1169 entry->ebx = entry->ecx = entry->edx = 0;
1171 * Pass down these bits:
1172 * EAX 0 NNDBP, Processor ignores nested data breakpoints
1173 * EAX 2 LAS, LFENCE always serializing
1174 * EAX 6 NSCB, Null selector clear base
1176 * Other defined bits are for MSRs that KVM does not expose:
1177 * EAX 3 SPCL, SMM page configuration lock
1178 * EAX 13 PCMSR, Prefetch control MSR
1180 entry->eax &= BIT(0) | BIT(2) | BIT(6);
1181 if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC))
1182 entry->eax |= BIT(2);
1183 if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
1184 entry->eax |= BIT(6);
1186 /*Add support for Centaur's CPUID instruction*/
1188 /*Just support up to 0xC0000004 now*/
1189 entry->eax = min(entry->eax, 0xC0000004);
1192 cpuid_entry_override(entry, CPUID_C000_0001_EDX);
1194 case 3: /* Processor serial number */
1195 case 5: /* MONITOR/MWAIT */
1200 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1212 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func,
1215 if (type == KVM_GET_EMULATED_CPUID)
1216 return __do_cpuid_func_emulated(array, func);
1218 return __do_cpuid_func(array, func);
1221 #define CENTAUR_CPUID_SIGNATURE 0xC0000000
1223 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func,
1229 if (func == CENTAUR_CPUID_SIGNATURE &&
1230 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR)
1233 r = do_cpuid_func(array, func, type);
1237 limit = array->entries[array->nent - 1].eax;
1238 for (func = func + 1; func <= limit; ++func) {
1239 r = do_cpuid_func(array, func, type);
1247 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries,
1248 __u32 num_entries, unsigned int ioctl_type)
1253 if (ioctl_type != KVM_GET_EMULATED_CPUID)
1257 * We want to make sure that ->padding is being passed clean from
1258 * userspace in case we want to use it for something in the future.
1260 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we
1261 * have to give ourselves satisfied only with the emulated side. /me
1264 for (i = 0; i < num_entries; i++) {
1265 if (copy_from_user(pad, entries[i].padding, sizeof(pad)))
1268 if (pad[0] || pad[1] || pad[2])
1274 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid,
1275 struct kvm_cpuid_entry2 __user *entries,
1278 static const u32 funcs[] = {
1279 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE,
1282 struct kvm_cpuid_array array = {
1287 if (cpuid->nent < 1)
1289 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1290 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
1292 if (sanity_check_entries(entries, cpuid->nent, type))
1295 array.entries = kvcalloc(sizeof(struct kvm_cpuid_entry2), cpuid->nent, GFP_KERNEL);
1299 array.maxnent = cpuid->nent;
1301 for (i = 0; i < ARRAY_SIZE(funcs); i++) {
1302 r = get_cpuid_func(&array, funcs[i], type);
1306 cpuid->nent = array.nent;
1308 if (copy_to_user(entries, array.entries,
1309 array.nent * sizeof(struct kvm_cpuid_entry2)))
1313 kvfree(array.entries);
1317 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
1318 u32 function, u32 index)
1320 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent,
1323 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
1326 * Intel CPUID semantics treats any query for an out-of-range leaf as if the
1327 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics
1328 * returns all zeroes for any undefined leaf, whether or not the leaf is in
1329 * range. Centaur/VIA follows Intel semantics.
1331 * A leaf is considered out-of-range if its function is higher than the maximum
1332 * supported leaf of its associated class or if its associated class does not
1335 * There are three primary classes to be considered, with their respective
1336 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary
1337 * class exists if a guest CPUID entry for its <base> leaf exists. For a given
1338 * class, CPUID.<base>.EAX contains the max supported leaf for the class.
1340 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff
1341 * - Hypervisor: 0x40000000 - 0x4fffffff
1342 * - Extended: 0x80000000 - 0xbfffffff
1343 * - Centaur: 0xc0000000 - 0xcfffffff
1345 * The Hypervisor class is further subdivided into sub-classes that each act as
1346 * their own independent class associated with a 0x100 byte range. E.g. if Qemu
1347 * is advertising support for both HyperV and KVM, the resulting Hypervisor
1348 * CPUID sub-classes are:
1350 * - HyperV: 0x40000000 - 0x400000ff
1351 * - KVM: 0x40000100 - 0x400001ff
1353 static struct kvm_cpuid_entry2 *
1354 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index)
1356 struct kvm_cpuid_entry2 *basic, *class;
1357 u32 function = *fn_ptr;
1359 basic = kvm_find_cpuid_entry(vcpu, 0, 0);
1363 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) ||
1364 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx))
1367 if (function >= 0x40000000 && function <= 0x4fffffff)
1368 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00, 0);
1369 else if (function >= 0xc0000000)
1370 class = kvm_find_cpuid_entry(vcpu, 0xc0000000, 0);
1372 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
1374 if (class && function <= class->eax)
1378 * Leaf specific adjustments are also applied when redirecting to the
1379 * max basic entry, e.g. if the max basic leaf is 0xb but there is no
1380 * entry for CPUID.0xb.index (see below), then the output value for EDX
1381 * needs to be pulled from CPUID.0xb.1.
1383 *fn_ptr = basic->eax;
1386 * The class does not exist or the requested function is out of range;
1387 * the effective CPUID entry is the max basic leaf. Note, the index of
1388 * the original requested leaf is observed!
1390 return kvm_find_cpuid_entry(vcpu, basic->eax, index);
1393 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx,
1394 u32 *ecx, u32 *edx, bool exact_only)
1396 u32 orig_function = *eax, function = *eax, index = *ecx;
1397 struct kvm_cpuid_entry2 *entry;
1398 bool exact, used_max_basic = false;
1400 entry = kvm_find_cpuid_entry(vcpu, function, index);
1403 if (!entry && !exact_only) {
1404 entry = get_out_of_range_cpuid_entry(vcpu, &function, index);
1405 used_max_basic = !!entry;
1413 if (function == 7 && index == 0) {
1415 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) &&
1416 (data & TSX_CTRL_CPUID_CLEAR))
1417 *ebx &= ~(F(RTM) | F(HLE));
1420 *eax = *ebx = *ecx = *edx = 0;
1422 * When leaf 0BH or 1FH is defined, CL is pass-through
1423 * and EDX is always the x2APIC ID, even for undefined
1424 * subleaves. Index 1 will exist iff the leaf is
1425 * implemented, so we pass through CL iff leaf 1
1426 * exists. EDX can be copied from any existing index.
1428 if (function == 0xb || function == 0x1f) {
1429 entry = kvm_find_cpuid_entry(vcpu, function, 1);
1431 *ecx = index & 0xff;
1436 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact,
1440 EXPORT_SYMBOL_GPL(kvm_cpuid);
1442 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
1444 u32 eax, ebx, ecx, edx;
1446 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0))
1449 eax = kvm_rax_read(vcpu);
1450 ecx = kvm_rcx_read(vcpu);
1451 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false);
1452 kvm_rax_write(vcpu, eax);
1453 kvm_rbx_write(vcpu, ebx);
1454 kvm_rcx_write(vcpu, ecx);
1455 kvm_rdx_write(vcpu, edx);
1456 return kvm_skip_emulated_instruction(vcpu);
1458 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);