1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
4 * cpuid support routines
6 * derived from arch/x86/kvm/x86.c
8 * Copyright 2011 Red Hat, Inc. and/or its affiliates.
9 * Copyright IBM Corporation, 2008
12 #include <linux/kvm_host.h>
13 #include <linux/export.h>
14 #include <linux/vmalloc.h>
15 #include <linux/uaccess.h>
16 #include <linux/sched/stat.h>
18 #include <asm/processor.h>
20 #include <asm/fpu/xstate.h>
22 #include <asm/cpuid.h>
30 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be
31 * aligned to sizeof(unsigned long) because it's not accessed via bitops.
33 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly;
34 EXPORT_SYMBOL_GPL(kvm_cpu_caps);
36 u32 xstate_required_size(u64 xstate_bv, bool compacted)
39 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
41 xstate_bv &= XFEATURE_MASK_EXTEND;
43 if (xstate_bv & 0x1) {
44 u32 eax, ebx, ecx, edx, offset;
45 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx);
46 /* ECX[1]: 64B alignment in compacted form */
48 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret;
51 ret = max(ret, offset + eax);
62 * This one is tied to SSB in the user API, and not
63 * visible in /proc/cpuinfo.
65 #define KVM_X86_FEATURE_PSFD (13*32+28) /* Predictive Store Forwarding Disable */
68 #define SF(name) (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0)
71 * Magic value used by KVM when querying userspace-provided CPUID entries and
72 * doesn't care about the CPIUD index because the index of the function in
73 * question is not significant. Note, this magic value must have at least one
74 * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find()
75 * to avoid false positives when processing guest CPUID input.
77 #define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull
79 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find(
80 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u64 index)
82 struct kvm_cpuid_entry2 *e;
85 for (i = 0; i < nent; i++) {
88 if (e->function != function)
92 * If the index isn't significant, use the first entry with a
93 * matching function. It's userspace's responsibilty to not
94 * provide "duplicate" entries in all cases.
96 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index)
101 * Similarly, use the first matching entry if KVM is doing a
102 * lookup (as opposed to emulating CPUID) for a function that's
103 * architecturally defined as not having a significant index.
105 if (index == KVM_CPUID_INDEX_NOT_SIGNIFICANT) {
107 * Direct lookups from KVM should not diverge from what
108 * KVM defines internally (the architectural behavior).
110 WARN_ON_ONCE(cpuid_function_is_indexed(function));
118 static int kvm_check_cpuid(struct kvm_vcpu *vcpu,
119 struct kvm_cpuid_entry2 *entries,
122 struct kvm_cpuid_entry2 *best;
126 * The existing code assumes virtual address is 48-bit or 57-bit in the
127 * canonical address checks; exit if it is ever changed.
129 best = cpuid_entry2_find(entries, nent, 0x80000008,
130 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
132 int vaddr_bits = (best->eax & 0xff00) >> 8;
134 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0)
139 * Exposing dynamic xfeatures to the guest requires additional
140 * enabling in the FPU, e.g. to expand the guest XSAVE state size.
142 best = cpuid_entry2_find(entries, nent, 0xd, 0);
146 xfeatures = best->eax | ((u64)best->edx << 32);
147 xfeatures &= XFEATURE_MASK_USER_DYNAMIC;
151 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures);
154 /* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */
155 static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2,
158 struct kvm_cpuid_entry2 *orig;
161 if (nent != vcpu->arch.cpuid_nent)
164 for (i = 0; i < nent; i++) {
165 orig = &vcpu->arch.cpuid_entries[i];
166 if (e2[i].function != orig->function ||
167 e2[i].index != orig->index ||
168 e2[i].flags != orig->flags ||
169 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx ||
170 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx)
177 static void kvm_update_kvm_cpuid_base(struct kvm_vcpu *vcpu)
180 struct kvm_cpuid_entry2 *entry;
182 vcpu->arch.kvm_cpuid_base = 0;
184 for_each_possible_hypervisor_cpuid_base(function) {
185 entry = kvm_find_cpuid_entry(vcpu, function);
190 signature[0] = entry->ebx;
191 signature[1] = entry->ecx;
192 signature[2] = entry->edx;
194 BUILD_BUG_ON(sizeof(signature) > sizeof(KVM_SIGNATURE));
195 if (!memcmp(signature, KVM_SIGNATURE, sizeof(signature))) {
196 vcpu->arch.kvm_cpuid_base = function;
203 static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu,
204 struct kvm_cpuid_entry2 *entries, int nent)
206 u32 base = vcpu->arch.kvm_cpuid_base;
211 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES,
212 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
215 static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu)
217 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries,
218 vcpu->arch.cpuid_nent);
221 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu)
223 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu);
226 * save the feature bitmap to avoid cpuid lookup for every PV
230 vcpu->arch.pv_cpuid.features = best->eax;
234 * Calculate guest's supported XCR0 taking into account guest CPUID data and
235 * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0).
237 static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent)
239 struct kvm_cpuid_entry2 *best;
241 best = cpuid_entry2_find(entries, nent, 0xd, 0);
245 return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0;
248 static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries,
251 struct kvm_cpuid_entry2 *best;
252 u64 guest_supported_xcr0 = cpuid_get_supported_xcr0(entries, nent);
254 best = cpuid_entry2_find(entries, nent, 1, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
256 /* Update OSXSAVE bit */
257 if (boot_cpu_has(X86_FEATURE_XSAVE))
258 cpuid_entry_change(best, X86_FEATURE_OSXSAVE,
259 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE));
261 cpuid_entry_change(best, X86_FEATURE_APIC,
262 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE);
265 best = cpuid_entry2_find(entries, nent, 7, 0);
266 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7)
267 cpuid_entry_change(best, X86_FEATURE_OSPKE,
268 kvm_read_cr4_bits(vcpu, X86_CR4_PKE));
270 best = cpuid_entry2_find(entries, nent, 0xD, 0);
272 best->ebx = xstate_required_size(vcpu->arch.xcr0, false);
274 best = cpuid_entry2_find(entries, nent, 0xD, 1);
275 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) ||
276 cpuid_entry_has(best, X86_FEATURE_XSAVEC)))
277 best->ebx = xstate_required_size(vcpu->arch.xcr0, true);
279 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent);
280 if (kvm_hlt_in_guest(vcpu->kvm) && best &&
281 (best->eax & (1 << KVM_FEATURE_PV_UNHALT)))
282 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT);
284 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) {
285 best = cpuid_entry2_find(entries, nent, 0x1, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
287 cpuid_entry_change(best, X86_FEATURE_MWAIT,
288 vcpu->arch.ia32_misc_enable_msr &
289 MSR_IA32_MISC_ENABLE_MWAIT);
293 * Bits 127:0 of the allowed SECS.ATTRIBUTES (CPUID.0x12.0x1) enumerate
294 * the supported XSAVE Feature Request Mask (XFRM), i.e. the enclave's
295 * requested XCR0 value. The enclave's XFRM must be a subset of XCRO
296 * at the time of EENTER, thus adjust the allowed XFRM by the guest's
297 * supported XCR0. Similar to XCR0 handling, FP and SSE are forced to
298 * '1' even on CPUs that don't support XSAVE.
300 best = cpuid_entry2_find(entries, nent, 0x12, 0x1);
302 best->ecx &= guest_supported_xcr0 & 0xffffffff;
303 best->edx &= guest_supported_xcr0 >> 32;
304 best->ecx |= XFEATURE_MASK_FPSSE;
308 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu)
310 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
312 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime);
314 static bool kvm_cpuid_has_hyperv(struct kvm_cpuid_entry2 *entries, int nent)
316 struct kvm_cpuid_entry2 *entry;
318 entry = cpuid_entry2_find(entries, nent, HYPERV_CPUID_INTERFACE,
319 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
320 return entry && entry->eax == HYPERV_CPUID_SIGNATURE_EAX;
323 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
325 struct kvm_lapic *apic = vcpu->arch.apic;
326 struct kvm_cpuid_entry2 *best;
328 best = kvm_find_cpuid_entry(vcpu, 1);
330 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER))
331 apic->lapic_timer.timer_mode_mask = 3 << 17;
333 apic->lapic_timer.timer_mode_mask = 1 << 17;
335 kvm_apic_set_version(vcpu);
338 vcpu->arch.guest_supported_xcr0 =
339 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
342 * FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if
343 * XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't
344 * supported by the host.
346 vcpu->arch.guest_fpu.fpstate->user_xfeatures = vcpu->arch.guest_supported_xcr0 |
349 kvm_update_pv_runtime(vcpu);
351 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
352 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
354 kvm_pmu_refresh(vcpu);
355 vcpu->arch.cr4_guest_rsvd_bits =
356 __cr4_reserved_bits(guest_cpuid_has, vcpu);
358 kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries,
359 vcpu->arch.cpuid_nent));
361 /* Invoke the vendor callback only after the above state is updated. */
362 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu);
365 * Except for the MMU, which needs to do its thing any vendor specific
366 * adjustments to the reserved GPA bits.
368 kvm_mmu_after_set_cpuid(vcpu);
371 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu)
373 struct kvm_cpuid_entry2 *best;
375 best = kvm_find_cpuid_entry(vcpu, 0x80000000);
376 if (!best || best->eax < 0x80000008)
378 best = kvm_find_cpuid_entry(vcpu, 0x80000008);
380 return best->eax & 0xff;
386 * This "raw" version returns the reserved GPA bits without any adjustments for
387 * encryption technologies that usurp bits. The raw mask should be used if and
388 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs.
390 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu)
392 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63);
395 static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2,
400 __kvm_update_cpuid_runtime(vcpu, e2, nent);
403 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
404 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
405 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
406 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with
407 * the core vCPU model on the fly. It would've been better to forbid any
408 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately
409 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do
410 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check
411 * whether the supplied CPUID data is equal to what's already set.
413 if (vcpu->arch.last_vmentry_cpu != -1) {
414 r = kvm_cpuid_check_equal(vcpu, e2, nent);
422 if (kvm_cpuid_has_hyperv(e2, nent)) {
423 r = kvm_hv_vcpu_init(vcpu);
428 r = kvm_check_cpuid(vcpu, e2, nent);
432 kvfree(vcpu->arch.cpuid_entries);
433 vcpu->arch.cpuid_entries = e2;
434 vcpu->arch.cpuid_nent = nent;
436 kvm_update_kvm_cpuid_base(vcpu);
437 kvm_vcpu_after_set_cpuid(vcpu);
442 /* when an old userspace process fills a new kernel module */
443 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
444 struct kvm_cpuid *cpuid,
445 struct kvm_cpuid_entry __user *entries)
448 struct kvm_cpuid_entry *e = NULL;
449 struct kvm_cpuid_entry2 *e2 = NULL;
451 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
455 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent));
459 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT);
465 for (i = 0; i < cpuid->nent; i++) {
466 e2[i].function = e[i].function;
467 e2[i].eax = e[i].eax;
468 e2[i].ebx = e[i].ebx;
469 e2[i].ecx = e[i].ecx;
470 e2[i].edx = e[i].edx;
473 e2[i].padding[0] = 0;
474 e2[i].padding[1] = 0;
475 e2[i].padding[2] = 0;
478 r = kvm_set_cpuid(vcpu, e2, cpuid->nent);
488 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
489 struct kvm_cpuid2 *cpuid,
490 struct kvm_cpuid_entry2 __user *entries)
492 struct kvm_cpuid_entry2 *e2 = NULL;
495 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
499 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent));
504 r = kvm_set_cpuid(vcpu, e2, cpuid->nent);
511 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
512 struct kvm_cpuid2 *cpuid,
513 struct kvm_cpuid_entry2 __user *entries)
518 if (cpuid->nent < vcpu->arch.cpuid_nent)
521 if (copy_to_user(entries, vcpu->arch.cpuid_entries,
522 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
527 cpuid->nent = vcpu->arch.cpuid_nent;
531 /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */
532 static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf)
534 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32);
535 struct kvm_cpuid_entry2 entry;
537 reverse_cpuid_check(leaf);
539 cpuid_count(cpuid.function, cpuid.index,
540 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx);
542 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg);
545 static __always_inline
546 void kvm_cpu_cap_init_scattered(enum kvm_only_cpuid_leafs leaf, u32 mask)
548 /* Use kvm_cpu_cap_mask for non-scattered leafs. */
549 BUILD_BUG_ON(leaf < NCAPINTS);
551 kvm_cpu_caps[leaf] = mask;
553 __kvm_cpu_cap_mask(leaf);
556 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask)
558 /* Use kvm_cpu_cap_init_scattered for scattered leafs. */
559 BUILD_BUG_ON(leaf >= NCAPINTS);
561 kvm_cpu_caps[leaf] &= mask;
563 __kvm_cpu_cap_mask(leaf);
566 void kvm_set_cpu_caps(void)
569 unsigned int f_gbpages = F(GBPAGES);
570 unsigned int f_lm = F(LM);
571 unsigned int f_xfd = F(XFD);
573 unsigned int f_gbpages = 0;
574 unsigned int f_lm = 0;
575 unsigned int f_xfd = 0;
577 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps));
579 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) >
580 sizeof(boot_cpu_data.x86_capability));
582 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability,
583 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)));
585 kvm_cpu_cap_mask(CPUID_1_ECX,
587 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not*
588 * advertised to guests via CPUID!
590 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
591 0 /* DS-CPL, VMX, SMX, EST */ |
592 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
593 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) |
594 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
595 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
596 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
599 /* KVM emulates x2apic in software irrespective of host support. */
600 kvm_cpu_cap_set(X86_FEATURE_X2APIC);
602 kvm_cpu_cap_mask(CPUID_1_EDX,
603 F(FPU) | F(VME) | F(DE) | F(PSE) |
604 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
605 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
606 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
607 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) |
608 0 /* Reserved, DS, ACPI */ | F(MMX) |
609 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
610 0 /* HTT, TM, Reserved, PBE */
613 kvm_cpu_cap_mask(CPUID_7_0_EBX,
614 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) |
615 F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) |
616 F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) |
617 F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) |
618 F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) |
619 F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) |
622 kvm_cpu_cap_mask(CPUID_7_ECX,
623 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) |
624 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
625 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
626 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ |
627 F(SGX_LC) | F(BUS_LOCK_DETECT)
629 /* Set LA57 based on hardware capability. */
630 if (cpuid_ecx(7) & F(LA57))
631 kvm_cpu_cap_set(X86_FEATURE_LA57);
634 * PKU not yet implemented for shadow paging and requires OSPKE
635 * to be set on the host. Clear it if that is not the case
637 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE))
638 kvm_cpu_cap_clear(X86_FEATURE_PKU);
640 kvm_cpu_cap_mask(CPUID_7_EDX,
641 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
642 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
643 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
644 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) |
645 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16)
648 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
649 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST);
650 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES);
652 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS))
653 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL);
654 if (boot_cpu_has(X86_FEATURE_STIBP))
655 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP);
656 if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
657 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
659 kvm_cpu_cap_mask(CPUID_7_1_EAX,
660 F(AVX_VNNI) | F(AVX512_BF16)
663 kvm_cpu_cap_mask(CPUID_D_1_EAX,
664 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd
667 kvm_cpu_cap_init_scattered(CPUID_12_EAX,
671 kvm_cpu_cap_mask(CPUID_8000_0001_ECX,
672 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
673 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
674 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) |
675 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) |
676 F(TOPOEXT) | 0 /* PERFCTR_CORE */
679 kvm_cpu_cap_mask(CPUID_8000_0001_EDX,
680 F(FPU) | F(VME) | F(DE) | F(PSE) |
681 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
682 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
683 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
684 F(PAT) | F(PSE36) | 0 /* Reserved */ |
685 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
686 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) |
687 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW)
690 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64))
691 kvm_cpu_cap_set(X86_FEATURE_GBPAGES);
693 kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
694 F(CLZERO) | F(XSAVEERPTR) |
695 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
696 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
697 __feature_bit(KVM_X86_FEATURE_PSFD)
701 * AMD has separate bits for each SPEC_CTRL bit.
702 * arch/x86/kernel/cpu/bugs.c is kind enough to
703 * record that in cpufeatures so use them.
705 if (boot_cpu_has(X86_FEATURE_IBPB))
706 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB);
707 if (boot_cpu_has(X86_FEATURE_IBRS))
708 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS);
709 if (boot_cpu_has(X86_FEATURE_STIBP))
710 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP);
711 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
712 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD);
713 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
714 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO);
716 * The preference is to use SPEC CTRL MSR instead of the
719 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
720 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
721 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
724 * Hide all SVM features by default, SVM will set the cap bits for
725 * features it emulates and/or exposes for L1.
727 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0);
729 kvm_cpu_cap_mask(CPUID_8000_001F_EAX,
730 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) |
733 kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
734 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
735 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
740 * Hide RDTSCP and RDPID if either feature is reported as supported but
741 * probing MSR_TSC_AUX failed. This is purely a sanity check and
742 * should never happen, but the guest will likely crash if RDTSCP or
743 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in
744 * the past. For example, the sanity check may fire if this instance of
745 * KVM is running as L1 on top of an older, broken KVM.
747 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) ||
748 kvm_cpu_cap_has(X86_FEATURE_RDPID)) &&
749 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) {
750 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
751 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
754 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps);
756 struct kvm_cpuid_array {
757 struct kvm_cpuid_entry2 *entries;
762 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array,
763 u32 function, u32 index)
765 struct kvm_cpuid_entry2 *entry;
767 if (array->nent >= array->maxnent)
770 entry = &array->entries[array->nent++];
772 memset(entry, 0, sizeof(*entry));
773 entry->function = function;
774 entry->index = index;
775 switch (function & 0xC0000000) {
777 /* Hypervisor leaves are always synthesized by __do_cpuid_func. */
782 * 0x80000021 is sometimes synthesized by __do_cpuid_func, which
783 * would result in out-of-bounds calls to do_host_cpuid.
786 static int max_cpuid_80000000;
787 if (!READ_ONCE(max_cpuid_80000000))
788 WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000));
789 if (function > READ_ONCE(max_cpuid_80000000))
798 cpuid_count(entry->function, entry->index,
799 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
801 if (cpuid_function_is_indexed(function))
802 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
807 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func)
809 struct kvm_cpuid_entry2 *entry;
811 if (array->nent >= array->maxnent)
814 entry = &array->entries[array->nent];
815 entry->function = func;
825 entry->ecx = F(MOVBE);
829 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
831 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
832 entry->ecx = F(RDPID);
842 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
844 struct kvm_cpuid_entry2 *entry;
847 /* all calls to cpuid_count() should be made on the same cpu */
852 entry = do_host_cpuid(array, function, 0);
858 /* Limited to the highest leaf implemented in KVM. */
859 entry->eax = min(entry->eax, 0x1fU);
862 cpuid_entry_override(entry, CPUID_1_EDX);
863 cpuid_entry_override(entry, CPUID_1_ECX);
867 * On ancient CPUs, function 2 entries are STATEFUL. That is,
868 * CPUID(function=2, index=0) may return different results each
869 * time, with the least-significant byte in EAX enumerating the
870 * number of times software should do CPUID(2, 0).
872 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less
873 * idiotic. Intel's SDM states that EAX & 0xff "will always
874 * return 01H. Software should ignore this value and not
875 * interpret it as an informational descriptor", while AMD's
876 * APM states that CPUID(2) is reserved.
878 * WARN if a frankenstein CPU that supports virtualization and
879 * a stateful CPUID.0x2 is encountered.
881 WARN_ON_ONCE((entry->eax & 0xff) > 1);
883 /* functions 4 and 0x8000001d have additional index. */
887 * Read entries until the cache type in the previous entry is
888 * zero, i.e. indicates an invalid entry.
890 for (i = 1; entry->eax & 0x1f; ++i) {
891 entry = do_host_cpuid(array, function, i);
896 case 6: /* Thermal management */
897 entry->eax = 0x4; /* allow ARAT */
902 /* function 7 has additional index. */
904 entry->eax = min(entry->eax, 1u);
905 cpuid_entry_override(entry, CPUID_7_0_EBX);
906 cpuid_entry_override(entry, CPUID_7_ECX);
907 cpuid_entry_override(entry, CPUID_7_EDX);
909 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */
910 if (entry->eax == 1) {
911 entry = do_host_cpuid(array, function, 1);
915 cpuid_entry_override(entry, CPUID_7_1_EAX);
921 case 0xa: { /* Architectural Performance Monitoring */
922 union cpuid10_eax eax;
923 union cpuid10_edx edx;
925 if (!static_cpu_has(X86_FEATURE_ARCH_PERFMON)) {
926 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
930 eax.split.version_id = kvm_pmu_cap.version;
931 eax.split.num_counters = kvm_pmu_cap.num_counters_gp;
932 eax.split.bit_width = kvm_pmu_cap.bit_width_gp;
933 eax.split.mask_length = kvm_pmu_cap.events_mask_len;
934 edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed;
935 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed;
937 if (kvm_pmu_cap.version)
938 edx.split.anythread_deprecated = 1;
939 edx.split.reserved1 = 0;
940 edx.split.reserved2 = 0;
942 entry->eax = eax.full;
943 entry->ebx = kvm_pmu_cap.events_mask;
945 entry->edx = edx.full;
949 * Per Intel's SDM, the 0x1f is a superset of 0xb,
950 * thus they can be handled by common code.
955 * Populate entries until the level type (ECX[15:8]) of the
956 * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is
957 * the starting entry, filled by the primary do_host_cpuid().
959 for (i = 1; entry->ecx & 0xff00; ++i) {
960 entry = do_host_cpuid(array, function, i);
966 u64 permitted_xcr0 = kvm_caps.supported_xcr0 & xstate_get_guest_group_perm();
967 u64 permitted_xss = kvm_caps.supported_xss;
969 entry->eax &= permitted_xcr0;
970 entry->ebx = xstate_required_size(permitted_xcr0, false);
971 entry->ecx = entry->ebx;
972 entry->edx &= permitted_xcr0 >> 32;
976 entry = do_host_cpuid(array, function, 1);
980 cpuid_entry_override(entry, CPUID_D_1_EAX);
981 if (entry->eax & (F(XSAVES)|F(XSAVEC)))
982 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss,
985 WARN_ON_ONCE(permitted_xss != 0);
988 entry->ecx &= permitted_xss;
989 entry->edx &= permitted_xss >> 32;
991 for (i = 2; i < 64; ++i) {
993 if (permitted_xcr0 & BIT_ULL(i))
995 else if (permitted_xss & BIT_ULL(i))
1000 entry = do_host_cpuid(array, function, i);
1005 * The supported check above should have filtered out
1006 * invalid sub-leafs. Only valid sub-leafs should
1007 * reach this point, and they should have a non-zero
1008 * save state size. Furthermore, check whether the
1009 * processor agrees with permitted_xcr0/permitted_xss
1010 * on whether this is an XCR0- or IA32_XSS-managed area.
1012 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) {
1017 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
1018 entry->ecx &= ~BIT_ULL(2);
1025 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) {
1026 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1031 * Index 0: Sub-features, MISCSELECT (a.k.a extended features)
1032 * and max enclave sizes. The SGX sub-features and MISCSELECT
1033 * are restricted by kernel and KVM capabilities (like most
1034 * feature flags), while enclave size is unrestricted.
1036 cpuid_entry_override(entry, CPUID_12_EAX);
1037 entry->ebx &= SGX_MISC_EXINFO;
1039 entry = do_host_cpuid(array, function, 1);
1044 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la
1045 * feature flags. Advertise all supported flags, including
1046 * privileged attributes that require explicit opt-in from
1047 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is
1048 * expected to derive it from supported XCR0.
1050 entry->eax &= SGX_ATTR_DEBUG | SGX_ATTR_MODE64BIT |
1051 SGX_ATTR_PROVISIONKEY | SGX_ATTR_EINITTOKENKEY |
1057 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) {
1058 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1062 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
1063 if (!do_host_cpuid(array, function, i))
1067 /* Intel AMX TILE */
1069 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {
1070 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1074 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
1075 if (!do_host_cpuid(array, function, i))
1079 case 0x1e: /* TMUL information */
1080 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {
1081 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1085 case KVM_CPUID_SIGNATURE: {
1086 const u32 *sigptr = (const u32 *)KVM_SIGNATURE;
1087 entry->eax = KVM_CPUID_FEATURES;
1088 entry->ebx = sigptr[0];
1089 entry->ecx = sigptr[1];
1090 entry->edx = sigptr[2];
1093 case KVM_CPUID_FEATURES:
1094 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
1095 (1 << KVM_FEATURE_NOP_IO_DELAY) |
1096 (1 << KVM_FEATURE_CLOCKSOURCE2) |
1097 (1 << KVM_FEATURE_ASYNC_PF) |
1098 (1 << KVM_FEATURE_PV_EOI) |
1099 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) |
1100 (1 << KVM_FEATURE_PV_UNHALT) |
1101 (1 << KVM_FEATURE_PV_TLB_FLUSH) |
1102 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) |
1103 (1 << KVM_FEATURE_PV_SEND_IPI) |
1104 (1 << KVM_FEATURE_POLL_CONTROL) |
1105 (1 << KVM_FEATURE_PV_SCHED_YIELD) |
1106 (1 << KVM_FEATURE_ASYNC_PF_INT);
1108 if (sched_info_on())
1109 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
1116 entry->eax = min(entry->eax, 0x80000021);
1118 * Serializing LFENCE is reported in a multitude of ways, and
1119 * NullSegClearsBase is not reported in CPUID on Zen2; help
1120 * userspace by providing the CPUID leaf ourselves.
1122 * However, only do it if the host has CPUID leaf 0x8000001d.
1123 * QEMU thinks that it can query the host blindly for that
1124 * CPUID leaf if KVM reports that it supports 0x8000001d or
1125 * above. The processor merrily returns values from the
1126 * highest Intel leaf which QEMU tries to use as the guest's
1127 * 0x8000001d. Even worse, this can result in an infinite
1128 * loop if said highest leaf has no subleaves indexed by ECX.
1130 if (entry->eax >= 0x8000001d &&
1131 (static_cpu_has(X86_FEATURE_LFENCE_RDTSC)
1132 || !static_cpu_has_bug(X86_BUG_NULL_SEG)))
1133 entry->eax = max(entry->eax, 0x80000021);
1136 cpuid_entry_override(entry, CPUID_8000_0001_EDX);
1137 cpuid_entry_override(entry, CPUID_8000_0001_ECX);
1140 /* L2 cache and TLB: pass through host info. */
1142 case 0x80000007: /* Advanced power management */
1143 /* invariant TSC is CPUID.80000007H:EDX[8] */
1144 entry->edx &= (1 << 8);
1145 /* mask against host */
1146 entry->edx &= boot_cpu_data.x86_power;
1147 entry->eax = entry->ebx = entry->ecx = 0;
1150 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
1151 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
1152 unsigned phys_as = entry->eax & 0xff;
1155 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as
1156 * the guest operates in the same PA space as the host, i.e.
1157 * reductions in MAXPHYADDR for memory encryption affect shadow
1160 * If TDP is enabled but an explicit guest MAXPHYADDR is not
1161 * provided, use the raw bare metal MAXPHYADDR as reductions to
1162 * the HPAs do not affect GPAs.
1165 g_phys_as = boot_cpu_data.x86_phys_bits;
1166 else if (!g_phys_as)
1167 g_phys_as = phys_as;
1169 entry->eax = g_phys_as | (virt_as << 8);
1171 cpuid_entry_override(entry, CPUID_8000_0008_EBX);
1175 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) {
1176 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1179 entry->eax = 1; /* SVM revision 1 */
1180 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
1181 ASID emulation to nested SVM */
1182 entry->ecx = 0; /* Reserved */
1183 cpuid_entry_override(entry, CPUID_8000_000A_EDX);
1186 entry->ecx = entry->edx = 0;
1192 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) {
1193 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1195 cpuid_entry_override(entry, CPUID_8000_001F_EAX);
1198 * Enumerate '0' for "PA bits reduction", the adjusted
1199 * MAXPHYADDR is enumerated directly (see 0x80000008).
1201 entry->ebx &= ~GENMASK(11, 6);
1205 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1208 entry->ebx = entry->ecx = entry->edx = 0;
1210 * Pass down these bits:
1211 * EAX 0 NNDBP, Processor ignores nested data breakpoints
1212 * EAX 2 LAS, LFENCE always serializing
1213 * EAX 6 NSCB, Null selector clear base
1215 * Other defined bits are for MSRs that KVM does not expose:
1216 * EAX 3 SPCL, SMM page configuration lock
1217 * EAX 13 PCMSR, Prefetch control MSR
1219 entry->eax &= BIT(0) | BIT(2) | BIT(6);
1220 if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC))
1221 entry->eax |= BIT(2);
1222 if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
1223 entry->eax |= BIT(6);
1225 /*Add support for Centaur's CPUID instruction*/
1227 /*Just support up to 0xC0000004 now*/
1228 entry->eax = min(entry->eax, 0xC0000004);
1231 cpuid_entry_override(entry, CPUID_C000_0001_EDX);
1233 case 3: /* Processor serial number */
1234 case 5: /* MONITOR/MWAIT */
1239 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1251 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func,
1254 if (type == KVM_GET_EMULATED_CPUID)
1255 return __do_cpuid_func_emulated(array, func);
1257 return __do_cpuid_func(array, func);
1260 #define CENTAUR_CPUID_SIGNATURE 0xC0000000
1262 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func,
1268 if (func == CENTAUR_CPUID_SIGNATURE &&
1269 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR)
1272 r = do_cpuid_func(array, func, type);
1276 limit = array->entries[array->nent - 1].eax;
1277 for (func = func + 1; func <= limit; ++func) {
1278 r = do_cpuid_func(array, func, type);
1286 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries,
1287 __u32 num_entries, unsigned int ioctl_type)
1292 if (ioctl_type != KVM_GET_EMULATED_CPUID)
1296 * We want to make sure that ->padding is being passed clean from
1297 * userspace in case we want to use it for something in the future.
1299 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we
1300 * have to give ourselves satisfied only with the emulated side. /me
1303 for (i = 0; i < num_entries; i++) {
1304 if (copy_from_user(pad, entries[i].padding, sizeof(pad)))
1307 if (pad[0] || pad[1] || pad[2])
1313 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid,
1314 struct kvm_cpuid_entry2 __user *entries,
1317 static const u32 funcs[] = {
1318 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE,
1321 struct kvm_cpuid_array array = {
1326 if (cpuid->nent < 1)
1328 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1329 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
1331 if (sanity_check_entries(entries, cpuid->nent, type))
1334 array.entries = kvcalloc(sizeof(struct kvm_cpuid_entry2), cpuid->nent, GFP_KERNEL);
1338 array.maxnent = cpuid->nent;
1340 for (i = 0; i < ARRAY_SIZE(funcs); i++) {
1341 r = get_cpuid_func(&array, funcs[i], type);
1345 cpuid->nent = array.nent;
1347 if (copy_to_user(entries, array.entries,
1348 array.nent * sizeof(struct kvm_cpuid_entry2)))
1352 kvfree(array.entries);
1356 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry_index(struct kvm_vcpu *vcpu,
1357 u32 function, u32 index)
1359 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent,
1362 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry_index);
1364 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
1367 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent,
1368 function, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
1370 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
1373 * Intel CPUID semantics treats any query for an out-of-range leaf as if the
1374 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics
1375 * returns all zeroes for any undefined leaf, whether or not the leaf is in
1376 * range. Centaur/VIA follows Intel semantics.
1378 * A leaf is considered out-of-range if its function is higher than the maximum
1379 * supported leaf of its associated class or if its associated class does not
1382 * There are three primary classes to be considered, with their respective
1383 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary
1384 * class exists if a guest CPUID entry for its <base> leaf exists. For a given
1385 * class, CPUID.<base>.EAX contains the max supported leaf for the class.
1387 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff
1388 * - Hypervisor: 0x40000000 - 0x4fffffff
1389 * - Extended: 0x80000000 - 0xbfffffff
1390 * - Centaur: 0xc0000000 - 0xcfffffff
1392 * The Hypervisor class is further subdivided into sub-classes that each act as
1393 * their own independent class associated with a 0x100 byte range. E.g. if Qemu
1394 * is advertising support for both HyperV and KVM, the resulting Hypervisor
1395 * CPUID sub-classes are:
1397 * - HyperV: 0x40000000 - 0x400000ff
1398 * - KVM: 0x40000100 - 0x400001ff
1400 static struct kvm_cpuid_entry2 *
1401 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index)
1403 struct kvm_cpuid_entry2 *basic, *class;
1404 u32 function = *fn_ptr;
1406 basic = kvm_find_cpuid_entry(vcpu, 0);
1410 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) ||
1411 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx))
1414 if (function >= 0x40000000 && function <= 0x4fffffff)
1415 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00);
1416 else if (function >= 0xc0000000)
1417 class = kvm_find_cpuid_entry(vcpu, 0xc0000000);
1419 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000);
1421 if (class && function <= class->eax)
1425 * Leaf specific adjustments are also applied when redirecting to the
1426 * max basic entry, e.g. if the max basic leaf is 0xb but there is no
1427 * entry for CPUID.0xb.index (see below), then the output value for EDX
1428 * needs to be pulled from CPUID.0xb.1.
1430 *fn_ptr = basic->eax;
1433 * The class does not exist or the requested function is out of range;
1434 * the effective CPUID entry is the max basic leaf. Note, the index of
1435 * the original requested leaf is observed!
1437 return kvm_find_cpuid_entry_index(vcpu, basic->eax, index);
1440 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx,
1441 u32 *ecx, u32 *edx, bool exact_only)
1443 u32 orig_function = *eax, function = *eax, index = *ecx;
1444 struct kvm_cpuid_entry2 *entry;
1445 bool exact, used_max_basic = false;
1447 entry = kvm_find_cpuid_entry_index(vcpu, function, index);
1450 if (!entry && !exact_only) {
1451 entry = get_out_of_range_cpuid_entry(vcpu, &function, index);
1452 used_max_basic = !!entry;
1460 if (function == 7 && index == 0) {
1462 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) &&
1463 (data & TSX_CTRL_CPUID_CLEAR))
1464 *ebx &= ~(F(RTM) | F(HLE));
1467 *eax = *ebx = *ecx = *edx = 0;
1469 * When leaf 0BH or 1FH is defined, CL is pass-through
1470 * and EDX is always the x2APIC ID, even for undefined
1471 * subleaves. Index 1 will exist iff the leaf is
1472 * implemented, so we pass through CL iff leaf 1
1473 * exists. EDX can be copied from any existing index.
1475 if (function == 0xb || function == 0x1f) {
1476 entry = kvm_find_cpuid_entry_index(vcpu, function, 1);
1478 *ecx = index & 0xff;
1483 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact,
1487 EXPORT_SYMBOL_GPL(kvm_cpuid);
1489 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
1491 u32 eax, ebx, ecx, edx;
1493 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0))
1496 eax = kvm_rax_read(vcpu);
1497 ecx = kvm_rcx_read(vcpu);
1498 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false);
1499 kvm_rax_write(vcpu, eax);
1500 kvm_rbx_write(vcpu, ebx);
1501 kvm_rcx_write(vcpu, ecx);
1502 kvm_rdx_write(vcpu, edx);
1503 return kvm_skip_emulated_instruction(vcpu);
1505 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);