1 // SPDX-License-Identifier: GPL-2.0
3 * check TSC synchronization.
5 * Copyright (C) 2006, Red Hat, Inc., Ingo Molnar
7 * We check whether all boot CPUs have their TSC's synchronized,
8 * print a warning if not and turn off the TSC clock-source.
10 * The warp-check is point-to-point between two CPUs, the CPU
11 * initiating the bootup is the 'source CPU', the freshly booting
12 * CPU is the 'target CPU'.
14 * Only two CPUs may participate - they can enter in any order.
15 * ( The serial nature of the boot logic and the CPU hotplug lock
16 * protects against more than 2 CPUs entering this code. )
18 #include <linux/topology.h>
19 #include <linux/spinlock.h>
20 #include <linux/kernel.h>
21 #include <linux/smp.h>
22 #include <linux/nmi.h>
28 unsigned long nextcheck;
32 static DEFINE_PER_CPU(struct tsc_adjust, tsc_adjust);
33 static struct timer_list tsc_sync_check_timer;
36 * TSC's on different sockets may be reset asynchronously.
37 * This may cause the TSC ADJUST value on socket 0 to be NOT 0.
39 bool __read_mostly tsc_async_resets;
41 void mark_tsc_async_resets(char *reason)
45 tsc_async_resets = true;
46 pr_info("tsc: Marking TSC async resets true due to %s\n", reason);
49 void tsc_verify_tsc_adjust(bool resume)
51 struct tsc_adjust *adj = this_cpu_ptr(&tsc_adjust);
54 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
57 /* Skip unnecessary error messages if TSC already unstable */
58 if (check_tsc_unstable())
61 /* Rate limit the MSR check */
62 if (!resume && time_before(jiffies, adj->nextcheck))
65 adj->nextcheck = jiffies + HZ;
67 rdmsrl(MSR_IA32_TSC_ADJUST, curval);
68 if (adj->adjusted == curval)
71 /* Restore the original value */
72 wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted);
74 if (!adj->warned || resume) {
75 pr_warn(FW_BUG "TSC ADJUST differs: CPU%u %lld --> %lld. Restoring\n",
76 smp_processor_id(), adj->adjusted, curval);
82 * Normally the tsc_sync will be checked every time system enters idle
83 * state, but there is still caveat that a system won't enter idle,
84 * either because it's too busy or configured purposely to not enter
87 * So setup a periodic timer (every 10 minutes) to make sure the check
91 #define SYNC_CHECK_INTERVAL (HZ * 600)
93 static void tsc_sync_check_timer_fn(struct timer_list *unused)
97 tsc_verify_tsc_adjust(false);
99 /* Run the check for all onlined CPUs in turn */
100 next_cpu = cpumask_next(raw_smp_processor_id(), cpu_online_mask);
101 if (next_cpu >= nr_cpu_ids)
102 next_cpu = cpumask_first(cpu_online_mask);
104 tsc_sync_check_timer.expires += SYNC_CHECK_INTERVAL;
105 add_timer_on(&tsc_sync_check_timer, next_cpu);
108 static int __init start_sync_check_timer(void)
110 if (!cpu_feature_enabled(X86_FEATURE_TSC_ADJUST) || tsc_clocksource_reliable)
113 timer_setup(&tsc_sync_check_timer, tsc_sync_check_timer_fn, 0);
114 tsc_sync_check_timer.expires = jiffies + SYNC_CHECK_INTERVAL;
115 add_timer(&tsc_sync_check_timer);
119 late_initcall(start_sync_check_timer);
121 static void tsc_sanitize_first_cpu(struct tsc_adjust *cur, s64 bootval,
122 unsigned int cpu, bool bootcpu)
125 * First online CPU in a package stores the boot value in the
126 * adjustment value. This value might change later via the sync
127 * mechanism. If that fails we still can yell about boot values not
130 * On the boot cpu we just force set the ADJUST value to 0 if it's
131 * non zero. We don't do that on non boot cpus because physical
132 * hotplug should have set the ADJUST register to a value > 0 so
133 * the TSC is in sync with the already running cpus.
135 * Also don't force the ADJUST value to zero if that is a valid value
136 * for socket 0 as determined by the system arch. This is required
137 * when multiple sockets are reset asynchronously with each other
138 * and socket 0 may not have an TSC ADJUST value of 0.
140 if (bootcpu && bootval != 0) {
141 if (likely(!tsc_async_resets)) {
142 pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n",
144 wrmsrl(MSR_IA32_TSC_ADJUST, 0);
147 pr_info("TSC ADJUST: CPU%u: %lld NOT forced to 0\n",
151 cur->adjusted = bootval;
155 bool __init tsc_store_and_check_tsc_adjust(bool bootcpu)
157 struct tsc_adjust *cur = this_cpu_ptr(&tsc_adjust);
160 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
163 /* Skip unnecessary error messages if TSC already unstable */
164 if (check_tsc_unstable())
167 rdmsrl(MSR_IA32_TSC_ADJUST, bootval);
168 cur->bootval = bootval;
169 cur->nextcheck = jiffies + HZ;
170 tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(), bootcpu);
174 #else /* !CONFIG_SMP */
177 * Store and check the TSC ADJUST MSR if available
179 bool tsc_store_and_check_tsc_adjust(bool bootcpu)
181 struct tsc_adjust *ref, *cur = this_cpu_ptr(&tsc_adjust);
182 unsigned int refcpu, cpu = smp_processor_id();
183 struct cpumask *mask;
186 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
189 rdmsrl(MSR_IA32_TSC_ADJUST, bootval);
190 cur->bootval = bootval;
191 cur->nextcheck = jiffies + HZ;
195 * If a non-zero TSC value for socket 0 may be valid then the default
196 * adjusted value cannot assumed to be zero either.
198 if (tsc_async_resets)
199 cur->adjusted = bootval;
202 * Check whether this CPU is the first in a package to come up. In
203 * this case do not check the boot value against another package
204 * because the new package might have been physically hotplugged,
205 * where TSC_ADJUST is expected to be different. When called on the
206 * boot CPU topology_core_cpumask() might not be available yet.
208 mask = topology_core_cpumask(cpu);
209 refcpu = mask ? cpumask_any_but(mask, cpu) : nr_cpu_ids;
211 if (refcpu >= nr_cpu_ids) {
212 tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(),
217 ref = per_cpu_ptr(&tsc_adjust, refcpu);
219 * Compare the boot value and complain if it differs in the
222 if (bootval != ref->bootval)
223 printk_once(FW_BUG "TSC ADJUST differs within socket(s), fixing all errors\n");
226 * The TSC_ADJUST values in a package must be the same. If the boot
227 * value on this newly upcoming CPU differs from the adjustment
228 * value of the already online CPU in this package, set it to that
231 if (bootval != ref->adjusted) {
232 cur->adjusted = ref->adjusted;
233 wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted);
236 * We have the TSCs forced to be in sync on this package. Skip sync
243 * Entry/exit counters that make sure that both CPUs
244 * run the measurement code at once:
246 static atomic_t start_count;
247 static atomic_t stop_count;
248 static atomic_t test_runs;
251 * We use a raw spinlock in this exceptional case, because
252 * we want to have the fastest, inlined, non-debug version
253 * of a critical section, to be able to prove TSC time-warps:
255 static arch_spinlock_t sync_lock = __ARCH_SPIN_LOCK_UNLOCKED;
257 static cycles_t last_tsc;
258 static cycles_t max_warp;
260 static int random_warps;
263 * TSC-warp measurement loop running on both CPUs. This is not called
264 * if there is no TSC.
266 static cycles_t check_tsc_warp(unsigned int timeout)
268 cycles_t start, now, prev, end, cur_max_warp = 0;
269 int i, cur_warps = 0;
271 start = rdtsc_ordered();
273 * The measurement runs for 'timeout' msecs:
275 end = start + (cycles_t) tsc_khz * timeout;
279 * We take the global lock, measure TSC, save the
280 * previous TSC that was measured (possibly on
281 * another CPU) and update the previous TSC timestamp.
283 arch_spin_lock(&sync_lock);
285 now = rdtsc_ordered();
287 arch_spin_unlock(&sync_lock);
290 * Be nice every now and then (and also check whether
291 * measurement is done [we also insert a 10 million
292 * loops safety exit, so we dont lock up in case the
293 * TSC readout is totally broken]):
295 if (unlikely(!(i & 7))) {
296 if (now > end || i > 10000000)
299 touch_nmi_watchdog();
302 * Outside the critical section we can now see whether
303 * we saw a time-warp of the TSC going backwards:
305 if (unlikely(prev > now)) {
306 arch_spin_lock(&sync_lock);
307 max_warp = max(max_warp, prev - now);
308 cur_max_warp = max_warp;
310 * Check whether this bounces back and forth. Only
311 * one CPU should observe time going backwards.
313 if (cur_warps != nr_warps)
316 cur_warps = nr_warps;
317 arch_spin_unlock(&sync_lock);
321 "Warning: zero tsc calibration delta: %Ld [max: %Ld]\n",
322 now-start, end-start);
327 * If the target CPU coming online doesn't have any of its core-siblings
328 * online, a timeout of 20msec will be used for the TSC-warp measurement
329 * loop. Otherwise a smaller timeout of 2msec will be used, as we have some
330 * information about this socket already (and this information grows as we
331 * have more and more logical-siblings in that socket).
333 * Ideally we should be able to skip the TSC sync check on the other
334 * core-siblings, if the first logical CPU in a socket passed the sync test.
335 * But as the TSC is per-logical CPU and can potentially be modified wrongly
336 * by the bios, TSC sync test for smaller duration should be able
337 * to catch such errors. Also this will catch the condition where all the
338 * cores in the socket don't get reset at the same time.
340 static inline unsigned int loop_timeout(int cpu)
342 return (cpumask_weight(topology_core_cpumask(cpu)) > 1) ? 2 : 20;
346 * The freshly booted CPU initiates this via an async SMP function call.
348 static void check_tsc_sync_source(void *__cpu)
350 unsigned int cpu = (unsigned long)__cpu;
354 * Set the maximum number of test runs to
355 * 1 if the CPU does not provide the TSC_ADJUST MSR
356 * 3 if the MSR is available, so the target can try to adjust
358 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
359 atomic_set(&test_runs, 1);
361 atomic_set(&test_runs, 3);
363 /* Wait for the target to start. */
364 while (atomic_read(&start_count) != cpus - 1)
368 * Trigger the target to continue into the measurement too:
370 atomic_inc(&start_count);
372 check_tsc_warp(loop_timeout(cpu));
374 while (atomic_read(&stop_count) != cpus-1)
378 * If the test was successful set the number of runs to zero and
379 * stop. If not, decrement the number of runs an check if we can
380 * retry. In case of random warps no retry is attempted.
383 atomic_set(&test_runs, 0);
385 pr_debug("TSC synchronization [CPU#%d -> CPU#%u]: passed\n",
386 smp_processor_id(), cpu);
388 } else if (atomic_dec_and_test(&test_runs) || random_warps) {
389 /* Force it to 0 if random warps brought us here */
390 atomic_set(&test_runs, 0);
392 pr_warn("TSC synchronization [CPU#%d -> CPU#%u]:\n",
393 smp_processor_id(), cpu);
394 pr_warn("Measured %Ld cycles TSC warp between CPUs, "
395 "turning off TSC clock.\n", max_warp);
397 pr_warn("TSC warped randomly between CPUs\n");
398 mark_tsc_unstable("check_tsc_sync_source failed");
402 * Reset it - just in case we boot another CPU later:
404 atomic_set(&start_count, 0);
411 * Let the target continue with the bootup:
413 atomic_inc(&stop_count);
416 * Retry, if there is a chance to do so.
418 if (atomic_read(&test_runs) > 0)
423 * Freshly booted CPUs call into this:
425 void check_tsc_sync_target(void)
427 struct tsc_adjust *cur = this_cpu_ptr(&tsc_adjust);
428 unsigned int cpu = smp_processor_id();
429 cycles_t cur_max_warp, gbl_max_warp;
432 /* Also aborts if there is no TSC. */
433 if (unsynchronized_tsc())
437 * Store, verify and sanitize the TSC adjust register. If
438 * successful skip the test.
440 * The test is also skipped when the TSC is marked reliable. This
441 * is true for SoCs which have no fallback clocksource. On these
442 * SoCs the TSC is frequency synchronized, but still the TSC ADJUST
443 * register might have been wreckaged by the BIOS..
445 if (tsc_store_and_check_tsc_adjust(false) || tsc_clocksource_reliable)
448 /* Kick the control CPU into the TSC synchronization function */
449 smp_call_function_single(cpumask_first(cpu_online_mask), check_tsc_sync_source,
450 (unsigned long *)(unsigned long)cpu, 0);
453 * Register this CPU's participation and wait for the
454 * source CPU to start the measurement:
456 atomic_inc(&start_count);
457 while (atomic_read(&start_count) != cpus)
460 cur_max_warp = check_tsc_warp(loop_timeout(cpu));
463 * Store the maximum observed warp value for a potential retry:
465 gbl_max_warp = max_warp;
470 atomic_inc(&stop_count);
473 * Wait for the source CPU to print stuff:
475 while (atomic_read(&stop_count) != cpus)
479 * Reset it for the next sync test:
481 atomic_set(&stop_count, 0);
484 * Check the number of remaining test runs. If not zero, the test
485 * failed and a retry with adjusted TSC is possible. If zero the
486 * test was either successful or failed terminally.
488 if (!atomic_read(&test_runs))
492 * If the warp value of this CPU is 0, then the other CPU
493 * observed time going backwards so this TSC was ahead and
494 * needs to move backwards.
497 cur_max_warp = -gbl_max_warp;
500 * Add the result to the previous adjustment value.
502 * The adjustment value is slightly off by the overhead of the
503 * sync mechanism (observed values are ~200 TSC cycles), but this
504 * really depends on CPU, node distance and frequency. So
505 * compensating for this is hard to get right. Experiments show
506 * that the warp is not longer detectable when the observed warp
507 * value is used. In the worst case the adjustment needs to go
508 * through a 3rd run for fine tuning.
510 cur->adjusted += cur_max_warp;
512 pr_warn("TSC ADJUST compensate: CPU%u observed %lld warp. Adjust: %lld\n",
513 cpu, cur_max_warp, cur->adjusted);
515 wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted);
520 #endif /* CONFIG_SMP */