2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
51 #include <linux/stackprotector.h>
52 #include <linux/gfp.h>
59 #include <asm/trampoline.h>
62 #include <asm/pgtable.h>
63 #include <asm/tlbflush.h>
65 #include <asm/mwait.h>
67 #include <asm/setup.h>
68 #include <asm/uv/uv.h>
69 #include <linux/mc146818rtc.h>
71 #include <asm/smpboot_hooks.h>
72 #include <asm/i8259.h>
75 u8 apicid_2_node[MAX_APICID];
78 /* State of each CPU */
79 DEFINE_PER_CPU(int, cpu_state) = { 0 };
81 /* Store all idle threads, this can be reused instead of creating
82 * a new thread. Also avoids complicated thread destroy functionality
85 #ifdef CONFIG_HOTPLUG_CPU
87 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
88 * removed after init for !CONFIG_HOTPLUG_CPU.
90 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
91 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
92 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
95 * We need this for trampoline_base protection from concurrent accesses when
96 * off- and onlining cores wildly.
98 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
100 void cpu_hotplug_driver_lock()
102 mutex_lock(&x86_cpu_hotplug_driver_mutex);
105 void cpu_hotplug_driver_unlock()
107 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
110 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
111 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
113 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
114 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
115 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
118 /* Number of siblings per CPU package */
119 int smp_num_siblings = 1;
120 EXPORT_SYMBOL(smp_num_siblings);
122 /* Last level cache ID of each logical CPU */
123 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
125 /* representing HT siblings of each logical CPU */
126 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
127 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
129 /* representing HT and core siblings of each logical CPU */
130 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
131 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
133 /* Per CPU bogomips and other parameters */
134 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
135 EXPORT_PER_CPU_SYMBOL(cpu_info);
137 atomic_t init_deasserted;
139 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
140 /* which node each logical CPU is on */
141 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
142 EXPORT_SYMBOL(cpu_to_node_map);
144 /* set up a mapping between cpu and node. */
145 static void map_cpu_to_node(int cpu, int node)
147 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node);
148 cpumask_set_cpu(cpu, node_to_cpumask_map[node]);
149 cpu_to_node_map[cpu] = node;
152 /* undo a mapping between cpu and node. */
153 static void unmap_cpu_to_node(int cpu)
157 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu);
158 for (node = 0; node < MAX_NUMNODES; node++)
159 cpumask_clear_cpu(cpu, node_to_cpumask_map[node]);
160 cpu_to_node_map[cpu] = 0;
162 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */
163 #define map_cpu_to_node(cpu, node) ({})
164 #define unmap_cpu_to_node(cpu) ({})
168 static int boot_cpu_logical_apicid;
170 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly =
171 { [0 ... NR_CPUS-1] = BAD_APICID };
173 static void map_cpu_to_logical_apicid(void)
175 int cpu = smp_processor_id();
176 int apicid = logical_smp_processor_id();
177 int node = apic->apicid_to_node(apicid);
179 if (!node_online(node))
180 node = first_online_node;
182 cpu_2_logical_apicid[cpu] = apicid;
183 map_cpu_to_node(cpu, node);
186 void numa_remove_cpu(int cpu)
188 cpu_2_logical_apicid[cpu] = BAD_APICID;
189 unmap_cpu_to_node(cpu);
192 #define map_cpu_to_logical_apicid() do {} while (0)
196 * Report back to the Boot Processor.
199 static void __cpuinit smp_callin(void)
202 unsigned long timeout;
205 * If waken up by an INIT in an 82489DX configuration
206 * we may get here before an INIT-deassert IPI reaches
207 * our local APIC. We have to wait for the IPI or we'll
208 * lock up on an APIC access.
210 if (apic->wait_for_init_deassert)
211 apic->wait_for_init_deassert(&init_deasserted);
214 * (This works even if the APIC is not enabled.)
216 phys_id = read_apic_id();
217 cpuid = smp_processor_id();
218 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
219 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
222 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
225 * STARTUP IPIs are fragile beasts as they might sometimes
226 * trigger some glue motherboard logic. Complete APIC bus
227 * silence for 1 second, this overestimates the time the
228 * boot CPU is spending to send the up to 2 STARTUP IPIs
229 * by a factor of two. This should be enough.
233 * Waiting 2s total for startup (udelay is not yet working)
235 timeout = jiffies + 2*HZ;
236 while (time_before(jiffies, timeout)) {
238 * Has the boot CPU finished it's STARTUP sequence?
240 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
245 if (!time_before(jiffies, timeout)) {
246 panic("%s: CPU%d started up but did not get a callout!\n",
251 * the boot CPU has finished the init stage and is spinning
252 * on callin_map until we finish. We are free to set up this
253 * CPU, first the APIC. (this is probably redundant on most
257 pr_debug("CALLIN, before setup_local_APIC().\n");
258 if (apic->smp_callin_clear_local_apic)
259 apic->smp_callin_clear_local_apic();
261 end_local_APIC_setup();
262 map_cpu_to_logical_apicid();
265 * Need to setup vector mappings before we enable interrupts.
267 setup_vector_irq(smp_processor_id());
271 * Need to enable IRQs because it can take longer and then
272 * the NMI watchdog might kill us.
277 pr_debug("Stack at about %p\n", &cpuid);
280 * Save our processor parameters
282 smp_store_cpu_info(cpuid);
284 notify_cpu_starting(cpuid);
287 * Allow the master to continue.
289 cpumask_set_cpu(cpuid, cpu_callin_mask);
293 * Activate a secondary processor.
295 notrace static void __cpuinit start_secondary(void *unused)
298 * Don't put *anything* before cpu_init(), SMP booting is too
299 * fragile that we want to limit the things done here to the
300 * most necessary things.
305 * Switch away from the trampoline page-table
307 * Do this before cpu_init() because it needs to access per-cpu
308 * data which may not be mapped in the trampoline page-table.
310 load_cr3(swapper_pg_dir);
318 /* otherwise gcc will move up smp_processor_id before the cpu_init */
321 * Check TSC synchronization with the BP:
323 check_tsc_sync_target();
325 if (nmi_watchdog == NMI_IO_APIC) {
327 enable_NMI_through_LVT0();
328 legacy_pic->unmask(0);
331 /* This must be done before setting cpu_online_mask */
332 set_cpu_sibling_map(raw_smp_processor_id());
336 * We need to hold call_lock, so there is no inconsistency
337 * between the time smp_call_function() determines number of
338 * IPI recipients, and the time when the determination is made
339 * for which cpus receive the IPI. Holding this
340 * lock helps us to not include this cpu in a currently in progress
341 * smp_call_function().
343 * We need to hold vector_lock so there the set of online cpus
344 * does not change while we are assigning vectors to cpus. Holding
345 * this lock ensures we don't half assign or remove an irq from a cpu.
349 set_cpu_online(smp_processor_id(), true);
350 unlock_vector_lock();
352 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
353 x86_platform.nmi_init();
355 /* enable local interrupts */
358 /* to prevent fake stack check failure in clock setup */
359 boot_init_stack_canary();
361 x86_cpuinit.setup_percpu_clockev();
367 #ifdef CONFIG_CPUMASK_OFFSTACK
368 /* In this case, llc_shared_map is a pointer to a cpumask. */
369 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst,
370 const struct cpuinfo_x86 *src)
372 struct cpumask *llc = dst->llc_shared_map;
374 dst->llc_shared_map = llc;
377 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst,
378 const struct cpuinfo_x86 *src)
382 #endif /* CONFIG_CPUMASK_OFFSTACK */
385 * The bootstrap kernel entry code has set these up. Save them for
389 void __cpuinit smp_store_cpu_info(int id)
391 struct cpuinfo_x86 *c = &cpu_data(id);
393 copy_cpuinfo_x86(c, &boot_cpu_data);
396 identify_secondary_cpu(c);
399 static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
401 struct cpuinfo_x86 *c1 = &cpu_data(cpu1);
402 struct cpuinfo_x86 *c2 = &cpu_data(cpu2);
404 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2));
405 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1));
406 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2));
407 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1));
408 cpumask_set_cpu(cpu1, c2->llc_shared_map);
409 cpumask_set_cpu(cpu2, c1->llc_shared_map);
413 void __cpuinit set_cpu_sibling_map(int cpu)
416 struct cpuinfo_x86 *c = &cpu_data(cpu);
418 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
420 if (smp_num_siblings > 1) {
421 for_each_cpu(i, cpu_sibling_setup_mask) {
422 struct cpuinfo_x86 *o = &cpu_data(i);
424 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
425 if (c->phys_proc_id == o->phys_proc_id &&
426 c->compute_unit_id == o->compute_unit_id)
427 link_thread_siblings(cpu, i);
428 } else if (c->phys_proc_id == o->phys_proc_id &&
429 c->cpu_core_id == o->cpu_core_id) {
430 link_thread_siblings(cpu, i);
434 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
437 cpumask_set_cpu(cpu, c->llc_shared_map);
439 if (current_cpu_data.x86_max_cores == 1) {
440 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
445 for_each_cpu(i, cpu_sibling_setup_mask) {
446 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
447 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
448 cpumask_set_cpu(i, c->llc_shared_map);
449 cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map);
451 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
452 cpumask_set_cpu(i, cpu_core_mask(cpu));
453 cpumask_set_cpu(cpu, cpu_core_mask(i));
455 * Does this new cpu bringup a new core?
457 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
459 * for each core in package, increment
460 * the booted_cores for this new cpu
462 if (cpumask_first(cpu_sibling_mask(i)) == i)
465 * increment the core count for all
466 * the other cpus in this package
469 cpu_data(i).booted_cores++;
470 } else if (i != cpu && !c->booted_cores)
471 c->booted_cores = cpu_data(i).booted_cores;
476 /* maps the cpu to the sched domain representing multi-core */
477 const struct cpumask *cpu_coregroup_mask(int cpu)
479 struct cpuinfo_x86 *c = &cpu_data(cpu);
481 * For perf, we return last level cache shared map.
482 * And for power savings, we return cpu_core_map
484 if ((sched_mc_power_savings || sched_smt_power_savings) &&
485 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
486 return cpu_core_mask(cpu);
488 return c->llc_shared_map;
491 static void impress_friends(void)
494 unsigned long bogosum = 0;
496 * Allow the user to impress friends.
498 pr_debug("Before bogomips.\n");
499 for_each_possible_cpu(cpu)
500 if (cpumask_test_cpu(cpu, cpu_callout_mask))
501 bogosum += cpu_data(cpu).loops_per_jiffy;
503 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
506 (bogosum/(5000/HZ))%100);
508 pr_debug("Before bogocount - setting activated=1.\n");
511 void __inquire_remote_apic(int apicid)
513 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
514 char *names[] = { "ID", "VERSION", "SPIV" };
518 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
520 for (i = 0; i < ARRAY_SIZE(regs); i++) {
521 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
526 status = safe_apic_wait_icr_idle();
529 "a previous APIC delivery may have failed\n");
531 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
536 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
537 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
540 case APIC_ICR_RR_VALID:
541 status = apic_read(APIC_RRR);
542 printk(KERN_CONT "%08x\n", status);
545 printk(KERN_CONT "failed\n");
551 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
552 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
553 * won't ... remember to clear down the APIC, etc later.
556 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
558 unsigned long send_status, accept_status = 0;
562 /* Boot on the stack */
563 /* Kick the second */
564 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
566 pr_debug("Waiting for send to finish...\n");
567 send_status = safe_apic_wait_icr_idle();
570 * Give the other CPU some time to accept the IPI.
573 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
574 maxlvt = lapic_get_maxlvt();
575 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
576 apic_write(APIC_ESR, 0);
577 accept_status = (apic_read(APIC_ESR) & 0xEF);
579 pr_debug("NMI sent.\n");
582 printk(KERN_ERR "APIC never delivered???\n");
584 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
586 return (send_status | accept_status);
590 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
592 unsigned long send_status, accept_status = 0;
593 int maxlvt, num_starts, j;
595 maxlvt = lapic_get_maxlvt();
598 * Be paranoid about clearing APIC errors.
600 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
601 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
602 apic_write(APIC_ESR, 0);
606 pr_debug("Asserting INIT.\n");
609 * Turn INIT on target chip
614 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
617 pr_debug("Waiting for send to finish...\n");
618 send_status = safe_apic_wait_icr_idle();
622 pr_debug("Deasserting INIT.\n");
626 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
628 pr_debug("Waiting for send to finish...\n");
629 send_status = safe_apic_wait_icr_idle();
632 atomic_set(&init_deasserted, 1);
635 * Should we send STARTUP IPIs ?
637 * Determine this based on the APIC version.
638 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
640 if (APIC_INTEGRATED(apic_version[phys_apicid]))
646 * Paravirt / VMI wants a startup IPI hook here to set up the
647 * target processor state.
649 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
650 (unsigned long)stack_start.sp);
653 * Run STARTUP IPI loop.
655 pr_debug("#startup loops: %d.\n", num_starts);
657 for (j = 1; j <= num_starts; j++) {
658 pr_debug("Sending STARTUP #%d.\n", j);
659 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
660 apic_write(APIC_ESR, 0);
662 pr_debug("After apic_write.\n");
669 /* Boot on the stack */
670 /* Kick the second */
671 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
675 * Give the other CPU some time to accept the IPI.
679 pr_debug("Startup point 1.\n");
681 pr_debug("Waiting for send to finish...\n");
682 send_status = safe_apic_wait_icr_idle();
685 * Give the other CPU some time to accept the IPI.
688 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
689 apic_write(APIC_ESR, 0);
690 accept_status = (apic_read(APIC_ESR) & 0xEF);
691 if (send_status || accept_status)
694 pr_debug("After Startup.\n");
697 printk(KERN_ERR "APIC never delivered???\n");
699 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
701 return (send_status | accept_status);
705 struct work_struct work;
706 struct task_struct *idle;
707 struct completion done;
711 static void __cpuinit do_fork_idle(struct work_struct *work)
713 struct create_idle *c_idle =
714 container_of(work, struct create_idle, work);
716 c_idle->idle = fork_idle(c_idle->cpu);
717 complete(&c_idle->done);
720 /* reduce the number of lines printed when booting a large cpu count system */
721 static void __cpuinit announce_cpu(int cpu, int apicid)
723 static int current_node = -1;
724 int node = early_cpu_to_node(cpu);
726 if (system_state == SYSTEM_BOOTING) {
727 if (node != current_node) {
728 if (current_node > (-1))
731 pr_info("Booting Node %3d, Processors ", node);
733 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
736 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
741 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
742 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
743 * Returns zero if CPU booted OK, else error code from
744 * ->wakeup_secondary_cpu.
746 static int __cpuinit do_boot_cpu(int apicid, int cpu)
748 unsigned long boot_error = 0;
749 unsigned long start_ip;
751 struct create_idle c_idle = {
753 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
756 INIT_WORK_ON_STACK(&c_idle.work, do_fork_idle);
758 alternatives_smp_switch(1);
760 c_idle.idle = get_idle_for_cpu(cpu);
763 * We can't use kernel_thread since we must avoid to
764 * reschedule the child.
767 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
768 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
769 init_idle(c_idle.idle, cpu);
773 schedule_work(&c_idle.work);
774 wait_for_completion(&c_idle.done);
776 if (IS_ERR(c_idle.idle)) {
777 printk("failed fork for CPU %d\n", cpu);
778 destroy_work_on_stack(&c_idle.work);
779 return PTR_ERR(c_idle.idle);
782 set_idle_for_cpu(cpu, c_idle.idle);
784 per_cpu(current_task, cpu) = c_idle.idle;
786 /* Stack for startup_32 can be just as for start_secondary onwards */
788 initial_page_table = __pa(&trampoline_pg_dir);
790 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
791 initial_gs = per_cpu_offset(cpu);
792 per_cpu(kernel_stack, cpu) =
793 (unsigned long)task_stack_page(c_idle.idle) -
794 KERNEL_STACK_OFFSET + THREAD_SIZE;
796 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
797 initial_code = (unsigned long)start_secondary;
798 stack_start.sp = (void *) c_idle.idle->thread.sp;
800 /* start_ip had better be page-aligned! */
801 start_ip = setup_trampoline();
803 /* So we see what's up */
804 announce_cpu(cpu, apicid);
807 * This grunge runs the startup process for
808 * the targeted processor.
811 atomic_set(&init_deasserted, 0);
813 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
815 pr_debug("Setting warm reset code and vector.\n");
817 smpboot_setup_warm_reset_vector(start_ip);
819 * Be paranoid about clearing APIC errors.
821 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
822 apic_write(APIC_ESR, 0);
828 * Kick the secondary CPU. Use the method in the APIC driver
829 * if it's defined - or use an INIT boot APIC message otherwise:
831 if (apic->wakeup_secondary_cpu)
832 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
834 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
838 * allow APs to start initializing.
840 pr_debug("Before Callout %d.\n", cpu);
841 cpumask_set_cpu(cpu, cpu_callout_mask);
842 pr_debug("After Callout %d.\n", cpu);
845 * Wait 5s total for a response
847 for (timeout = 0; timeout < 50000; timeout++) {
848 if (cpumask_test_cpu(cpu, cpu_callin_mask))
849 break; /* It has booted */
852 * Allow other tasks to run while we wait for the
853 * AP to come online. This also gives a chance
854 * for the MTRR work(triggered by the AP coming online)
855 * to be completed in the stop machine context.
860 if (cpumask_test_cpu(cpu, cpu_callin_mask))
861 pr_debug("CPU%d: has booted.\n", cpu);
864 if (*((volatile unsigned char *)trampoline_base)
866 /* trampoline started but...? */
867 pr_err("CPU%d: Stuck ??\n", cpu);
869 /* trampoline code not run */
870 pr_err("CPU%d: Not responding.\n", cpu);
871 if (apic->inquire_remote_apic)
872 apic->inquire_remote_apic(apicid);
877 /* Try to put things back the way they were before ... */
878 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
880 /* was set by do_boot_cpu() */
881 cpumask_clear_cpu(cpu, cpu_callout_mask);
883 /* was set by cpu_init() */
884 cpumask_clear_cpu(cpu, cpu_initialized_mask);
886 set_cpu_present(cpu, false);
887 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
890 /* mark "stuck" area as not stuck */
891 *((volatile unsigned long *)trampoline_base) = 0;
893 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
895 * Cleanup possible dangling ends...
897 smpboot_restore_warm_reset_vector();
900 destroy_work_on_stack(&c_idle.work);
904 int __cpuinit native_cpu_up(unsigned int cpu)
906 int apicid = apic->cpu_present_to_apicid(cpu);
910 WARN_ON(irqs_disabled());
912 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
914 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
915 !physid_isset(apicid, phys_cpu_present_map)) {
916 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
921 * Already booted CPU?
923 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
924 pr_debug("do_boot_cpu %d Already started\n", cpu);
929 * Save current MTRR state in case it was changed since early boot
930 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
934 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
936 err = do_boot_cpu(apicid, cpu);
939 pr_debug("do_boot_cpu failed %d\n", err);
944 * Check TSC synchronization with the AP (keep irqs disabled
947 local_irq_save(flags);
948 check_tsc_sync_source(cpu);
949 local_irq_restore(flags);
951 while (!cpu_online(cpu)) {
953 touch_nmi_watchdog();
960 * Fall back to non SMP mode after errors.
962 * RED-PEN audit/test this more. I bet there is more state messed up here.
964 static __init void disable_smp(void)
966 init_cpu_present(cpumask_of(0));
967 init_cpu_possible(cpumask_of(0));
968 smpboot_clear_io_apic_irqs();
970 if (smp_found_config)
971 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
973 physid_set_mask_of_physid(0, &phys_cpu_present_map);
974 map_cpu_to_logical_apicid();
975 cpumask_set_cpu(0, cpu_sibling_mask(0));
976 cpumask_set_cpu(0, cpu_core_mask(0));
980 * Various sanity checks.
982 static int __init smp_sanity_check(unsigned max_cpus)
986 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
987 if (def_to_bigsmp && nr_cpu_ids > 8) {
992 "More than 8 CPUs detected - skipping them.\n"
993 "Use CONFIG_X86_BIGSMP.\n");
996 for_each_present_cpu(cpu) {
998 set_cpu_present(cpu, false);
1003 for_each_possible_cpu(cpu) {
1005 set_cpu_possible(cpu, false);
1013 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1015 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1016 hard_smp_processor_id());
1018 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1022 * If we couldn't find an SMP configuration at boot time,
1023 * get out of here now!
1025 if (!smp_found_config && !acpi_lapic) {
1027 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1029 if (APIC_init_uniprocessor())
1030 printk(KERN_NOTICE "Local APIC not detected."
1031 " Using dummy APIC emulation.\n");
1036 * Should not be necessary because the MP table should list the boot
1037 * CPU too, but we do it for the sake of robustness anyway.
1039 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1041 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1042 boot_cpu_physical_apicid);
1043 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1048 * If we couldn't find a local APIC, then get out of here now!
1050 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1052 if (!disable_apic) {
1053 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1054 boot_cpu_physical_apicid);
1055 pr_err("... forcing use of dummy APIC emulation."
1056 "(tell your hw vendor)\n");
1058 smpboot_clear_io_apic();
1059 arch_disable_smp_support();
1063 verify_local_APIC();
1066 * If SMP should be disabled, then really disable it!
1069 printk(KERN_INFO "SMP mode deactivated.\n");
1070 smpboot_clear_io_apic();
1072 localise_nmi_watchdog();
1076 end_local_APIC_setup();
1083 static void __init smp_cpu_index_default(void)
1086 struct cpuinfo_x86 *c;
1088 for_each_possible_cpu(i) {
1090 /* mark all to hotplug */
1091 c->cpu_index = nr_cpu_ids;
1096 * Prepare for SMP bootup. The MP table or ACPI has been read
1097 * earlier. Just do some sanity checking here and enable APIC mode.
1099 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1104 smp_cpu_index_default();
1105 current_cpu_data = boot_cpu_data;
1106 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1109 * Setup boot CPU information
1111 smp_store_cpu_info(0); /* Final full version of the data */
1112 #ifdef CONFIG_X86_32
1113 boot_cpu_logical_apicid = logical_smp_processor_id();
1115 current_thread_info()->cpu = 0; /* needed? */
1116 for_each_possible_cpu(i) {
1117 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1118 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1119 zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL);
1121 set_cpu_sibling_map(0);
1124 if (smp_sanity_check(max_cpus) < 0) {
1125 printk(KERN_INFO "SMP disabled\n");
1130 default_setup_apic_routing();
1133 if (read_apic_id() != boot_cpu_physical_apicid) {
1134 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1135 read_apic_id(), boot_cpu_physical_apicid);
1136 /* Or can we switch back to PIC here? */
1143 * Switch from PIC to APIC mode.
1148 * Enable IO APIC before setting up error vector
1150 if (!skip_ioapic_setup && nr_ioapics)
1153 end_local_APIC_setup();
1155 map_cpu_to_logical_apicid();
1157 if (apic->setup_portio_remap)
1158 apic->setup_portio_remap();
1160 smpboot_setup_io_apic();
1162 * Set up local APIC timer on boot CPU.
1165 printk(KERN_INFO "CPU%d: ", 0);
1166 print_cpu_info(&cpu_data(0));
1167 x86_init.timers.setup_percpu_clockev();
1172 set_mtrr_aps_delayed_init();
1177 void arch_enable_nonboot_cpus_begin(void)
1179 set_mtrr_aps_delayed_init();
1182 void arch_enable_nonboot_cpus_end(void)
1188 * Early setup to make printk work.
1190 void __init native_smp_prepare_boot_cpu(void)
1192 int me = smp_processor_id();
1193 switch_to_new_gdt(me);
1194 /* already set me in cpu_online_mask in boot_cpu_init() */
1195 cpumask_set_cpu(me, cpu_callout_mask);
1196 per_cpu(cpu_state, me) = CPU_ONLINE;
1199 void __init native_smp_cpus_done(unsigned int max_cpus)
1201 pr_debug("Boot done.\n");
1204 #ifdef CONFIG_X86_IO_APIC
1205 setup_ioapic_dest();
1207 check_nmi_watchdog();
1211 static int __initdata setup_possible_cpus = -1;
1212 static int __init _setup_possible_cpus(char *str)
1214 get_option(&str, &setup_possible_cpus);
1217 early_param("possible_cpus", _setup_possible_cpus);
1221 * cpu_possible_mask should be static, it cannot change as cpu's
1222 * are onlined, or offlined. The reason is per-cpu data-structures
1223 * are allocated by some modules at init time, and dont expect to
1224 * do this dynamically on cpu arrival/departure.
1225 * cpu_present_mask on the other hand can change dynamically.
1226 * In case when cpu_hotplug is not compiled, then we resort to current
1227 * behaviour, which is cpu_possible == cpu_present.
1230 * Three ways to find out the number of additional hotplug CPUs:
1231 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1232 * - The user can overwrite it with possible_cpus=NUM
1233 * - Otherwise don't reserve additional CPUs.
1234 * We do this because additional CPUs waste a lot of memory.
1237 __init void prefill_possible_map(void)
1241 /* no processor from mptable or madt */
1242 if (!num_processors)
1245 i = setup_max_cpus ?: 1;
1246 if (setup_possible_cpus == -1) {
1247 possible = num_processors;
1248 #ifdef CONFIG_HOTPLUG_CPU
1250 possible += disabled_cpus;
1256 possible = setup_possible_cpus;
1258 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1260 /* nr_cpu_ids could be reduced via nr_cpus= */
1261 if (possible > nr_cpu_ids) {
1263 "%d Processors exceeds NR_CPUS limit of %d\n",
1264 possible, nr_cpu_ids);
1265 possible = nr_cpu_ids;
1268 #ifdef CONFIG_HOTPLUG_CPU
1269 if (!setup_max_cpus)
1273 "%d Processors exceeds max_cpus limit of %u\n",
1274 possible, setup_max_cpus);
1278 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1279 possible, max_t(int, possible - num_processors, 0));
1281 for (i = 0; i < possible; i++)
1282 set_cpu_possible(i, true);
1283 for (; i < NR_CPUS; i++)
1284 set_cpu_possible(i, false);
1286 nr_cpu_ids = possible;
1289 #ifdef CONFIG_HOTPLUG_CPU
1291 static void remove_siblinginfo(int cpu)
1294 struct cpuinfo_x86 *c = &cpu_data(cpu);
1296 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1297 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1299 * last thread sibling in this cpu core going down
1301 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1302 cpu_data(sibling).booted_cores--;
1305 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1306 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1307 cpumask_clear(cpu_sibling_mask(cpu));
1308 cpumask_clear(cpu_core_mask(cpu));
1309 c->phys_proc_id = 0;
1311 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1314 static void __ref remove_cpu_from_maps(int cpu)
1316 set_cpu_online(cpu, false);
1317 cpumask_clear_cpu(cpu, cpu_callout_mask);
1318 cpumask_clear_cpu(cpu, cpu_callin_mask);
1319 /* was set by cpu_init() */
1320 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1321 numa_remove_cpu(cpu);
1324 void cpu_disable_common(void)
1326 int cpu = smp_processor_id();
1328 remove_siblinginfo(cpu);
1330 /* It's now safe to remove this processor from the online map */
1332 remove_cpu_from_maps(cpu);
1333 unlock_vector_lock();
1337 int native_cpu_disable(void)
1339 int cpu = smp_processor_id();
1342 * Perhaps use cpufreq to drop frequency, but that could go
1343 * into generic code.
1345 * We won't take down the boot processor on i386 due to some
1346 * interrupts only being able to be serviced by the BSP.
1347 * Especially so if we're not using an IOAPIC -zwane
1352 if (nmi_watchdog == NMI_LOCAL_APIC)
1353 stop_apic_nmi_watchdog(NULL);
1356 cpu_disable_common();
1360 void native_cpu_die(unsigned int cpu)
1362 /* We don't do anything here: idle task is faking death itself. */
1365 for (i = 0; i < 10; i++) {
1366 /* They ack this in play_dead by setting CPU_DEAD */
1367 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1368 if (system_state == SYSTEM_RUNNING)
1369 pr_info("CPU %u is now offline\n", cpu);
1371 if (1 == num_online_cpus())
1372 alternatives_smp_switch(0);
1377 pr_err("CPU %u didn't die...\n", cpu);
1380 void play_dead_common(void)
1383 reset_lazy_tlbstate();
1384 irq_ctx_exit(raw_smp_processor_id());
1385 c1e_remove_cpu(raw_smp_processor_id());
1389 __get_cpu_var(cpu_state) = CPU_DEAD;
1392 * With physical CPU hotplug, we should halt the cpu
1394 local_irq_disable();
1398 * We need to flush the caches before going to sleep, lest we have
1399 * dirty data in our caches when we come back up.
1401 static inline void mwait_play_dead(void)
1403 unsigned int eax, ebx, ecx, edx;
1404 unsigned int highest_cstate = 0;
1405 unsigned int highest_subcstate = 0;
1409 if (!cpu_has(¤t_cpu_data, X86_FEATURE_MWAIT))
1411 if (!cpu_has(¤t_cpu_data, X86_FEATURE_CLFLSH))
1413 if (current_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1416 eax = CPUID_MWAIT_LEAF;
1418 native_cpuid(&eax, &ebx, &ecx, &edx);
1421 * eax will be 0 if EDX enumeration is not valid.
1422 * Initialized below to cstate, sub_cstate value when EDX is valid.
1424 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1427 edx >>= MWAIT_SUBSTATE_SIZE;
1428 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1429 if (edx & MWAIT_SUBSTATE_MASK) {
1431 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1434 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1435 (highest_subcstate - 1);
1439 * This should be a memory location in a cache line which is
1440 * unlikely to be touched by other processors. The actual
1441 * content is immaterial as it is not actually modified in any way.
1443 mwait_ptr = ¤t_thread_info()->flags;
1449 * The CLFLUSH is a workaround for erratum AAI65 for
1450 * the Xeon 7400 series. It's not clear it is actually
1451 * needed, but it should be harmless in either case.
1452 * The WBINVD is insufficient due to the spurious-wakeup
1453 * case where we return around the loop.
1456 __monitor(mwait_ptr, 0, 0);
1462 static inline void hlt_play_dead(void)
1464 if (current_cpu_data.x86 >= 4)
1472 void native_play_dead(void)
1475 tboot_shutdown(TB_SHUTDOWN_WFS);
1477 mwait_play_dead(); /* Only returns on failure */
1481 #else /* ... !CONFIG_HOTPLUG_CPU */
1482 int native_cpu_disable(void)
1487 void native_cpu_die(unsigned int cpu)
1489 /* We said "no" in __cpu_disable */
1493 void native_play_dead(void)