2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/sched/topology.h>
49 #include <linux/sched/hotplug.h>
50 #include <linux/sched/task_stack.h>
51 #include <linux/percpu.h>
52 #include <linux/bootmem.h>
53 #include <linux/err.h>
54 #include <linux/nmi.h>
55 #include <linux/tboot.h>
56 #include <linux/stackprotector.h>
57 #include <linux/gfp.h>
58 #include <linux/cpuidle.h>
64 #include <asm/realmode.h>
67 #include <asm/pgtable.h>
68 #include <asm/tlbflush.h>
70 #include <asm/mwait.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/internal.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
78 #include <asm/realmode.h>
80 #include <asm/qspinlock.h>
82 /* Number of siblings per CPU package */
83 int smp_num_siblings = 1;
84 EXPORT_SYMBOL(smp_num_siblings);
86 /* Last level cache ID of each logical CPU */
87 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
89 /* representing HT siblings of each logical CPU */
90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
91 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
93 /* representing HT and core siblings of each logical CPU */
94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
95 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
99 /* Per CPU bogomips and other parameters */
100 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
101 EXPORT_PER_CPU_SYMBOL(cpu_info);
103 /* Logical package management. We might want to allocate that dynamically */
104 unsigned int __max_logical_packages __read_mostly;
105 EXPORT_SYMBOL(__max_logical_packages);
106 static unsigned int logical_packages __read_mostly;
108 /* Maximum number of SMT threads on any online core */
109 int __max_smt_threads __read_mostly;
111 /* Flag to indicate if a complete sched domain rebuild is required */
112 bool x86_topology_update;
114 int arch_update_cpu_topology(void)
116 int retval = x86_topology_update;
118 x86_topology_update = false;
122 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
126 spin_lock_irqsave(&rtc_lock, flags);
127 CMOS_WRITE(0xa, 0xf);
128 spin_unlock_irqrestore(&rtc_lock, flags);
131 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
134 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
139 static inline void smpboot_restore_warm_reset_vector(void)
144 * Install writable page 0 entry to set BIOS data area.
149 * Paranoid: Set warm reset code and vector here back
152 spin_lock_irqsave(&rtc_lock, flags);
154 spin_unlock_irqrestore(&rtc_lock, flags);
156 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
160 * Report back to the Boot Processor during boot time or to the caller processor
163 static void smp_callin(void)
168 * If waken up by an INIT in an 82489DX configuration
169 * cpu_callout_mask guarantees we don't get here before
170 * an INIT_deassert IPI reaches our local APIC, so it is
171 * now safe to touch our local APIC.
173 cpuid = smp_processor_id();
176 * (This works even if the APIC is not enabled.)
178 phys_id = read_apic_id();
181 * the boot CPU has finished the init stage and is spinning
182 * on callin_map until we finish. We are free to set up this
183 * CPU, first the APIC. (this is probably redundant on most
189 * Save our processor parameters. Note: this information
190 * is needed for clock calibration.
192 smp_store_cpu_info(cpuid);
195 * The topology information must be up to date before
196 * calibrate_delay() and notify_cpu_starting().
198 set_cpu_sibling_map(raw_smp_processor_id());
202 * Update loops_per_jiffy in cpu_data. Previous call to
203 * smp_store_cpu_info() stored a value that is close but not as
204 * accurate as the value just calculated.
207 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
208 pr_debug("Stack at about %p\n", &cpuid);
212 notify_cpu_starting(cpuid);
215 * Allow the master to continue.
217 cpumask_set_cpu(cpuid, cpu_callin_mask);
220 static int cpu0_logical_apicid;
221 static int enable_start_cpu0;
223 * Activate a secondary processor.
225 static void notrace start_secondary(void *unused)
228 * Don't put *anything* except direct CPU state initialization
229 * before cpu_init(), SMP booting is too fragile that we want to
230 * limit the things done here to the most necessary things.
232 if (boot_cpu_has(X86_FEATURE_PCID))
233 __write_cr4(__read_cr4() | X86_CR4_PCIDE);
236 /* switch away from the initial page table */
237 load_cr3(swapper_pg_dir);
242 x86_cpuinit.early_percpu_clock_init();
246 enable_start_cpu0 = 0;
248 /* otherwise gcc will move up smp_processor_id before the cpu_init */
251 * Check TSC synchronization with the boot CPU:
253 check_tsc_sync_target();
256 * Lock vector_lock, set CPU online and bring the vector
257 * allocator online. Online must be set with vector_lock held
258 * to prevent a concurrent irq setup/teardown from seeing a
259 * half valid vector space.
262 set_cpu_online(smp_processor_id(), true);
264 unlock_vector_lock();
265 cpu_set_state_online(smp_processor_id());
266 x86_platform.nmi_init();
268 /* enable local interrupts */
271 /* to prevent fake stack check failure in clock setup */
272 boot_init_stack_canary();
274 x86_cpuinit.setup_percpu_clockev();
277 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
281 * topology_phys_to_logical_pkg - Map a physical package id to a logical
283 * Returns logical package id or -1 if not found
285 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
289 for_each_possible_cpu(cpu) {
290 struct cpuinfo_x86 *c = &cpu_data(cpu);
292 if (c->initialized && c->phys_proc_id == phys_pkg)
293 return c->logical_proc_id;
297 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
300 * topology_update_package_map - Update the physical to logical package map
301 * @pkg: The physical package id as retrieved via CPUID
302 * @cpu: The cpu for which this is updated
304 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
308 /* Already available somewhere? */
309 new = topology_phys_to_logical_pkg(pkg);
313 new = logical_packages++;
315 pr_info("CPU %u Converting physical %u to logical package %u\n",
319 cpu_data(cpu).logical_proc_id = new;
323 void __init smp_store_boot_cpu_info(void)
325 int id = 0; /* CPU 0 */
326 struct cpuinfo_x86 *c = &cpu_data(id);
330 topology_update_package_map(c->phys_proc_id, id);
331 c->initialized = true;
335 * The bootstrap kernel entry code has set these up. Save them for
338 void smp_store_cpu_info(int id)
340 struct cpuinfo_x86 *c = &cpu_data(id);
342 /* Copy boot_cpu_data only on the first bringup */
347 * During boot time, CPU0 has this setup already. Save the info when
348 * bringing up AP or offlined CPU0.
350 identify_secondary_cpu(c);
351 c->initialized = true;
355 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
357 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
359 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
363 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
365 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
367 return !WARN_ONCE(!topology_same_node(c, o),
368 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
369 "[node: %d != %d]. Ignoring dependency.\n",
370 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
373 #define link_mask(mfunc, c1, c2) \
375 cpumask_set_cpu((c1), mfunc(c2)); \
376 cpumask_set_cpu((c2), mfunc(c1)); \
379 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
381 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
382 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
384 if (c->phys_proc_id == o->phys_proc_id &&
385 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
386 if (c->cpu_core_id == o->cpu_core_id)
387 return topology_sane(c, o, "smt");
389 if ((c->cu_id != 0xff) &&
390 (o->cu_id != 0xff) &&
391 (c->cu_id == o->cu_id))
392 return topology_sane(c, o, "smt");
395 } else if (c->phys_proc_id == o->phys_proc_id &&
396 c->cpu_core_id == o->cpu_core_id) {
397 return topology_sane(c, o, "smt");
403 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
405 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
407 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
408 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
409 return topology_sane(c, o, "llc");
415 * Unlike the other levels, we do not enforce keeping a
416 * multicore group inside a NUMA node. If this happens, we will
417 * discard the MC level of the topology later.
419 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
421 if (c->phys_proc_id == o->phys_proc_id)
426 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
427 static inline int x86_sched_itmt_flags(void)
429 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
432 #ifdef CONFIG_SCHED_MC
433 static int x86_core_flags(void)
435 return cpu_core_flags() | x86_sched_itmt_flags();
438 #ifdef CONFIG_SCHED_SMT
439 static int x86_smt_flags(void)
441 return cpu_smt_flags() | x86_sched_itmt_flags();
446 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
447 #ifdef CONFIG_SCHED_SMT
448 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
450 #ifdef CONFIG_SCHED_MC
451 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
456 static struct sched_domain_topology_level x86_topology[] = {
457 #ifdef CONFIG_SCHED_SMT
458 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
460 #ifdef CONFIG_SCHED_MC
461 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
463 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
468 * Set if a package/die has multiple NUMA nodes inside.
469 * AMD Magny-Cours and Intel Cluster-on-Die have this.
471 static bool x86_has_numa_in_package;
473 void set_cpu_sibling_map(int cpu)
475 bool has_smt = smp_num_siblings > 1;
476 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
477 struct cpuinfo_x86 *c = &cpu_data(cpu);
478 struct cpuinfo_x86 *o;
481 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
484 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
485 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
486 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
491 for_each_cpu(i, cpu_sibling_setup_mask) {
494 if ((i == cpu) || (has_smt && match_smt(c, o)))
495 link_mask(topology_sibling_cpumask, cpu, i);
497 if ((i == cpu) || (has_mp && match_llc(c, o)))
498 link_mask(cpu_llc_shared_mask, cpu, i);
503 * This needs a separate iteration over the cpus because we rely on all
504 * topology_sibling_cpumask links to be set-up.
506 for_each_cpu(i, cpu_sibling_setup_mask) {
509 if ((i == cpu) || (has_mp && match_die(c, o))) {
510 link_mask(topology_core_cpumask, cpu, i);
513 * Does this new cpu bringup a new core?
516 topology_sibling_cpumask(cpu)) == 1) {
518 * for each core in package, increment
519 * the booted_cores for this new cpu
522 topology_sibling_cpumask(i)) == i)
525 * increment the core count for all
526 * the other cpus in this package
529 cpu_data(i).booted_cores++;
530 } else if (i != cpu && !c->booted_cores)
531 c->booted_cores = cpu_data(i).booted_cores;
533 if (match_die(c, o) && !topology_same_node(c, o))
534 x86_has_numa_in_package = true;
537 threads = cpumask_weight(topology_sibling_cpumask(cpu));
538 if (threads > __max_smt_threads)
539 __max_smt_threads = threads;
542 /* maps the cpu to the sched domain representing multi-core */
543 const struct cpumask *cpu_coregroup_mask(int cpu)
545 return cpu_llc_shared_mask(cpu);
548 static void impress_friends(void)
551 unsigned long bogosum = 0;
553 * Allow the user to impress friends.
555 pr_debug("Before bogomips\n");
556 for_each_possible_cpu(cpu)
557 if (cpumask_test_cpu(cpu, cpu_callout_mask))
558 bogosum += cpu_data(cpu).loops_per_jiffy;
559 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
562 (bogosum/(5000/HZ))%100);
564 pr_debug("Before bogocount - setting activated=1\n");
567 void __inquire_remote_apic(int apicid)
569 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
570 const char * const names[] = { "ID", "VERSION", "SPIV" };
574 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
576 for (i = 0; i < ARRAY_SIZE(regs); i++) {
577 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
582 status = safe_apic_wait_icr_idle();
584 pr_cont("a previous APIC delivery may have failed\n");
586 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
591 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
592 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
595 case APIC_ICR_RR_VALID:
596 status = apic_read(APIC_RRR);
597 pr_cont("%08x\n", status);
606 * The Multiprocessor Specification 1.4 (1997) example code suggests
607 * that there should be a 10ms delay between the BSP asserting INIT
608 * and de-asserting INIT, when starting a remote processor.
609 * But that slows boot and resume on modern processors, which include
610 * many cores and don't require that delay.
612 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
613 * Modern processor families are quirked to remove the delay entirely.
615 #define UDELAY_10MS_DEFAULT 10000
617 static unsigned int init_udelay = UINT_MAX;
619 static int __init cpu_init_udelay(char *str)
621 get_option(&str, &init_udelay);
625 early_param("cpu_init_udelay", cpu_init_udelay);
627 static void __init smp_quirk_init_udelay(void)
629 /* if cmdline changed it from default, leave it alone */
630 if (init_udelay != UINT_MAX)
633 /* if modern processor, use no delay */
634 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
635 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
639 /* else, use legacy delay */
640 init_udelay = UDELAY_10MS_DEFAULT;
644 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
645 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
646 * won't ... remember to clear down the APIC, etc later.
649 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
651 unsigned long send_status, accept_status = 0;
655 /* Boot on the stack */
656 /* Kick the second */
657 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
659 pr_debug("Waiting for send to finish...\n");
660 send_status = safe_apic_wait_icr_idle();
663 * Give the other CPU some time to accept the IPI.
666 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
667 maxlvt = lapic_get_maxlvt();
668 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
669 apic_write(APIC_ESR, 0);
670 accept_status = (apic_read(APIC_ESR) & 0xEF);
672 pr_debug("NMI sent\n");
675 pr_err("APIC never delivered???\n");
677 pr_err("APIC delivery error (%lx)\n", accept_status);
679 return (send_status | accept_status);
683 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
685 unsigned long send_status = 0, accept_status = 0;
686 int maxlvt, num_starts, j;
688 maxlvt = lapic_get_maxlvt();
691 * Be paranoid about clearing APIC errors.
693 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
694 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
695 apic_write(APIC_ESR, 0);
699 pr_debug("Asserting INIT\n");
702 * Turn INIT on target chip
707 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
710 pr_debug("Waiting for send to finish...\n");
711 send_status = safe_apic_wait_icr_idle();
715 pr_debug("Deasserting INIT\n");
719 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
721 pr_debug("Waiting for send to finish...\n");
722 send_status = safe_apic_wait_icr_idle();
727 * Should we send STARTUP IPIs ?
729 * Determine this based on the APIC version.
730 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
732 if (APIC_INTEGRATED(boot_cpu_apic_version))
738 * Run STARTUP IPI loop.
740 pr_debug("#startup loops: %d\n", num_starts);
742 for (j = 1; j <= num_starts; j++) {
743 pr_debug("Sending STARTUP #%d\n", j);
744 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
745 apic_write(APIC_ESR, 0);
747 pr_debug("After apic_write\n");
754 /* Boot on the stack */
755 /* Kick the second */
756 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
760 * Give the other CPU some time to accept the IPI.
762 if (init_udelay == 0)
767 pr_debug("Startup point 1\n");
769 pr_debug("Waiting for send to finish...\n");
770 send_status = safe_apic_wait_icr_idle();
773 * Give the other CPU some time to accept the IPI.
775 if (init_udelay == 0)
780 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
781 apic_write(APIC_ESR, 0);
782 accept_status = (apic_read(APIC_ESR) & 0xEF);
783 if (send_status || accept_status)
786 pr_debug("After Startup\n");
789 pr_err("APIC never delivered???\n");
791 pr_err("APIC delivery error (%lx)\n", accept_status);
793 return (send_status | accept_status);
796 /* reduce the number of lines printed when booting a large cpu count system */
797 static void announce_cpu(int cpu, int apicid)
799 static int current_node = -1;
800 int node = early_cpu_to_node(cpu);
801 static int width, node_width;
804 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
807 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
810 printk(KERN_INFO "x86: Booting SMP configuration:\n");
812 if (system_state < SYSTEM_RUNNING) {
813 if (node != current_node) {
814 if (current_node > (-1))
818 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
819 node_width - num_digits(node), " ", node);
822 /* Add padding for the BSP */
824 pr_cont("%*s", width + 1, " ");
826 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
829 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
833 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
837 cpu = smp_processor_id();
838 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
845 * Wake up AP by INIT, INIT, STARTUP sequence.
847 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
848 * boot-strap code which is not a desired behavior for waking up BSP. To
849 * void the boot-strap code, wake up CPU0 by NMI instead.
851 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
852 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
853 * We'll change this code in the future to wake up hard offlined CPU0 if
854 * real platform and request are available.
857 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
858 int *cpu0_nmi_registered)
866 * Wake up AP by INIT, INIT, STARTUP sequence.
869 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
874 * Wake up BSP by nmi.
876 * Register a NMI handler to help wake up CPU0.
878 boot_error = register_nmi_handler(NMI_LOCAL,
879 wakeup_cpu0_nmi, 0, "wake_cpu0");
882 enable_start_cpu0 = 1;
883 *cpu0_nmi_registered = 1;
884 if (apic->dest_logical == APIC_DEST_LOGICAL)
885 id = cpu0_logical_apicid;
888 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
897 void common_cpu_up(unsigned int cpu, struct task_struct *idle)
899 /* Just in case we booted with a single CPU. */
900 alternatives_enable_smp();
902 per_cpu(current_task, cpu) = idle;
905 /* Stack for startup_32 can be just as for start_secondary onwards */
907 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
909 initial_gs = per_cpu_offset(cpu);
914 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
915 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
916 * Returns zero if CPU booted OK, else error code from
917 * ->wakeup_secondary_cpu.
919 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
920 int *cpu0_nmi_registered)
922 volatile u32 *trampoline_status =
923 (volatile u32 *) __va(real_mode_header->trampoline_status);
924 /* start_ip had better be page-aligned! */
925 unsigned long start_ip = real_mode_header->trampoline_start;
927 unsigned long boot_error = 0;
928 unsigned long timeout;
930 idle->thread.sp = (unsigned long)task_pt_regs(idle);
931 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
932 initial_code = (unsigned long)start_secondary;
933 initial_stack = idle->thread.sp;
936 * Enable the espfix hack for this CPU
938 #ifdef CONFIG_X86_ESPFIX64
942 /* So we see what's up */
943 announce_cpu(cpu, apicid);
946 * This grunge runs the startup process for
947 * the targeted processor.
950 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
952 pr_debug("Setting warm reset code and vector.\n");
954 smpboot_setup_warm_reset_vector(start_ip);
956 * Be paranoid about clearing APIC errors.
958 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
959 apic_write(APIC_ESR, 0);
965 * AP might wait on cpu_callout_mask in cpu_init() with
966 * cpu_initialized_mask set if previous attempt to online
967 * it timed-out. Clear cpu_initialized_mask so that after
968 * INIT/SIPI it could start with a clean state.
970 cpumask_clear_cpu(cpu, cpu_initialized_mask);
974 * Wake up a CPU in difference cases:
975 * - Use the method in the APIC driver if it's defined
977 * - Use an INIT boot APIC message for APs or NMI for BSP.
979 if (apic->wakeup_secondary_cpu)
980 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
982 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
983 cpu0_nmi_registered);
987 * Wait 10s total for first sign of life from AP
990 timeout = jiffies + 10*HZ;
991 while (time_before(jiffies, timeout)) {
992 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
994 * Tell AP to proceed with initialization
996 cpumask_set_cpu(cpu, cpu_callout_mask);
1006 * Wait till AP completes initial initialization
1008 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1010 * Allow other tasks to run while we wait for the
1011 * AP to come online. This also gives a chance
1012 * for the MTRR work(triggered by the AP coming online)
1013 * to be completed in the stop machine context.
1019 /* mark "stuck" area as not stuck */
1020 *trampoline_status = 0;
1022 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1024 * Cleanup possible dangling ends...
1026 smpboot_restore_warm_reset_vector();
1032 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1034 int apicid = apic->cpu_present_to_apicid(cpu);
1035 int cpu0_nmi_registered = 0;
1036 unsigned long flags;
1039 lockdep_assert_irqs_enabled();
1041 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1043 if (apicid == BAD_APICID ||
1044 !physid_isset(apicid, phys_cpu_present_map) ||
1045 !apic->apic_id_valid(apicid)) {
1046 pr_err("%s: bad cpu %d\n", __func__, cpu);
1051 * Already booted CPU?
1053 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1054 pr_debug("do_boot_cpu %d Already started\n", cpu);
1059 * Save current MTRR state in case it was changed since early boot
1060 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1064 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1065 err = cpu_check_up_prepare(cpu);
1066 if (err && err != -EBUSY)
1069 /* the FPU context is blank, nobody can own it */
1070 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1072 common_cpu_up(cpu, tidle);
1074 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1076 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1082 * Check TSC synchronization with the AP (keep irqs disabled
1085 local_irq_save(flags);
1086 check_tsc_sync_source(cpu);
1087 local_irq_restore(flags);
1089 while (!cpu_online(cpu)) {
1091 touch_nmi_watchdog();
1096 * Clean up the nmi handler. Do this after the callin and callout sync
1097 * to avoid impact of possible long unregister time.
1099 if (cpu0_nmi_registered)
1100 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1106 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1108 void arch_disable_smp_support(void)
1110 disable_ioapic_support();
1114 * Fall back to non SMP mode after errors.
1116 * RED-PEN audit/test this more. I bet there is more state messed up here.
1118 static __init void disable_smp(void)
1120 pr_info("SMP disabled\n");
1122 disable_ioapic_support();
1124 init_cpu_present(cpumask_of(0));
1125 init_cpu_possible(cpumask_of(0));
1127 if (smp_found_config)
1128 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1130 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1131 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1132 cpumask_set_cpu(0, topology_core_cpumask(0));
1136 * Various sanity checks.
1138 static void __init smp_sanity_check(void)
1142 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1143 if (def_to_bigsmp && nr_cpu_ids > 8) {
1147 pr_warn("More than 8 CPUs detected - skipping them\n"
1148 "Use CONFIG_X86_BIGSMP\n");
1151 for_each_present_cpu(cpu) {
1153 set_cpu_present(cpu, false);
1158 for_each_possible_cpu(cpu) {
1160 set_cpu_possible(cpu, false);
1168 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1169 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1170 hard_smp_processor_id());
1172 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1176 * Should not be necessary because the MP table should list the boot
1177 * CPU too, but we do it for the sake of robustness anyway.
1179 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1180 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1181 boot_cpu_physical_apicid);
1182 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1187 static void __init smp_cpu_index_default(void)
1190 struct cpuinfo_x86 *c;
1192 for_each_possible_cpu(i) {
1194 /* mark all to hotplug */
1195 c->cpu_index = nr_cpu_ids;
1199 static void __init smp_get_logical_apicid(void)
1202 cpu0_logical_apicid = apic_read(APIC_LDR);
1204 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1208 * Prepare for SMP bootup.
1209 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1210 * for common interface support.
1212 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1216 smp_cpu_index_default();
1219 * Setup boot CPU information
1221 smp_store_boot_cpu_info(); /* Final full version of the data */
1222 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1225 for_each_possible_cpu(i) {
1226 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1227 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1228 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1232 * Set 'default' x86 topology, this matches default_topology() in that
1233 * it has NUMA nodes as a topology level. See also
1234 * native_smp_cpus_done().
1236 * Must be done before set_cpus_sibling_map() is ran.
1238 set_sched_topology(x86_topology);
1240 set_cpu_sibling_map(0);
1244 switch (apic_intr_mode) {
1246 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1249 case APIC_SYMMETRIC_IO_NO_ROUTING:
1251 /* Setup local timer */
1252 x86_init.timers.setup_percpu_clockev();
1254 case APIC_VIRTUAL_WIRE:
1255 case APIC_SYMMETRIC_IO:
1259 /* Setup local timer */
1260 x86_init.timers.setup_percpu_clockev();
1262 smp_get_logical_apicid();
1265 print_cpu_info(&cpu_data(0));
1267 native_pv_lock_init();
1271 set_mtrr_aps_delayed_init();
1273 smp_quirk_init_udelay();
1276 void arch_enable_nonboot_cpus_begin(void)
1278 set_mtrr_aps_delayed_init();
1281 void arch_enable_nonboot_cpus_end(void)
1287 * Early setup to make printk work.
1289 void __init native_smp_prepare_boot_cpu(void)
1291 int me = smp_processor_id();
1292 switch_to_new_gdt(me);
1293 /* already set me in cpu_online_mask in boot_cpu_init() */
1294 cpumask_set_cpu(me, cpu_callout_mask);
1295 cpu_set_state_online(me);
1298 void __init native_smp_cpus_done(unsigned int max_cpus)
1302 pr_debug("Boot done\n");
1304 * Today neither Intel nor AMD support heterogenous systems so
1305 * extrapolate the boot cpu's data to all packages.
1307 ncpus = cpu_data(0).booted_cores * smp_num_siblings;
1308 __max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus);
1309 pr_info("Max logical packages: %u\n", __max_logical_packages);
1311 if (x86_has_numa_in_package)
1312 set_sched_topology(x86_numa_in_package_topology);
1319 static int __initdata setup_possible_cpus = -1;
1320 static int __init _setup_possible_cpus(char *str)
1322 get_option(&str, &setup_possible_cpus);
1325 early_param("possible_cpus", _setup_possible_cpus);
1329 * cpu_possible_mask should be static, it cannot change as cpu's
1330 * are onlined, or offlined. The reason is per-cpu data-structures
1331 * are allocated by some modules at init time, and dont expect to
1332 * do this dynamically on cpu arrival/departure.
1333 * cpu_present_mask on the other hand can change dynamically.
1334 * In case when cpu_hotplug is not compiled, then we resort to current
1335 * behaviour, which is cpu_possible == cpu_present.
1338 * Three ways to find out the number of additional hotplug CPUs:
1339 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1340 * - The user can overwrite it with possible_cpus=NUM
1341 * - Otherwise don't reserve additional CPUs.
1342 * We do this because additional CPUs waste a lot of memory.
1345 __init void prefill_possible_map(void)
1349 /* No boot processor was found in mptable or ACPI MADT */
1350 if (!num_processors) {
1351 if (boot_cpu_has(X86_FEATURE_APIC)) {
1352 int apicid = boot_cpu_physical_apicid;
1353 int cpu = hard_smp_processor_id();
1355 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1357 /* Make sure boot cpu is enumerated */
1358 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1359 apic->apic_id_valid(apicid))
1360 generic_processor_info(apicid, boot_cpu_apic_version);
1363 if (!num_processors)
1367 i = setup_max_cpus ?: 1;
1368 if (setup_possible_cpus == -1) {
1369 possible = num_processors;
1370 #ifdef CONFIG_HOTPLUG_CPU
1372 possible += disabled_cpus;
1378 possible = setup_possible_cpus;
1380 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1382 /* nr_cpu_ids could be reduced via nr_cpus= */
1383 if (possible > nr_cpu_ids) {
1384 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1385 possible, nr_cpu_ids);
1386 possible = nr_cpu_ids;
1389 #ifdef CONFIG_HOTPLUG_CPU
1390 if (!setup_max_cpus)
1393 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1394 possible, setup_max_cpus);
1398 nr_cpu_ids = possible;
1400 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1401 possible, max_t(int, possible - num_processors, 0));
1403 reset_cpu_possible_mask();
1405 for (i = 0; i < possible; i++)
1406 set_cpu_possible(i, true);
1409 #ifdef CONFIG_HOTPLUG_CPU
1411 /* Recompute SMT state for all CPUs on offline */
1412 static void recompute_smt_state(void)
1414 int max_threads, cpu;
1417 for_each_online_cpu (cpu) {
1418 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1420 if (threads > max_threads)
1421 max_threads = threads;
1423 __max_smt_threads = max_threads;
1426 static void remove_siblinginfo(int cpu)
1429 struct cpuinfo_x86 *c = &cpu_data(cpu);
1431 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1432 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1434 * last thread sibling in this cpu core going down
1436 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1437 cpu_data(sibling).booted_cores--;
1440 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1441 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1442 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1443 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1444 cpumask_clear(cpu_llc_shared_mask(cpu));
1445 cpumask_clear(topology_sibling_cpumask(cpu));
1446 cpumask_clear(topology_core_cpumask(cpu));
1447 c->phys_proc_id = 0;
1449 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1450 recompute_smt_state();
1453 static void remove_cpu_from_maps(int cpu)
1455 set_cpu_online(cpu, false);
1456 cpumask_clear_cpu(cpu, cpu_callout_mask);
1457 cpumask_clear_cpu(cpu, cpu_callin_mask);
1458 /* was set by cpu_init() */
1459 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1460 numa_remove_cpu(cpu);
1463 void cpu_disable_common(void)
1465 int cpu = smp_processor_id();
1467 remove_siblinginfo(cpu);
1469 /* It's now safe to remove this processor from the online map */
1471 remove_cpu_from_maps(cpu);
1472 unlock_vector_lock();
1477 int native_cpu_disable(void)
1481 ret = lapic_can_unplug_cpu();
1486 cpu_disable_common();
1491 int common_cpu_die(unsigned int cpu)
1495 /* We don't do anything here: idle task is faking death itself. */
1497 /* They ack this in play_dead() by setting CPU_DEAD */
1498 if (cpu_wait_death(cpu, 5)) {
1499 if (system_state == SYSTEM_RUNNING)
1500 pr_info("CPU %u is now offline\n", cpu);
1502 pr_err("CPU %u didn't die...\n", cpu);
1509 void native_cpu_die(unsigned int cpu)
1511 common_cpu_die(cpu);
1514 void play_dead_common(void)
1519 (void)cpu_report_death();
1522 * With physical CPU hotplug, we should halt the cpu
1524 local_irq_disable();
1527 static bool wakeup_cpu0(void)
1529 if (smp_processor_id() == 0 && enable_start_cpu0)
1536 * We need to flush the caches before going to sleep, lest we have
1537 * dirty data in our caches when we come back up.
1539 static inline void mwait_play_dead(void)
1541 unsigned int eax, ebx, ecx, edx;
1542 unsigned int highest_cstate = 0;
1543 unsigned int highest_subcstate = 0;
1547 if (!this_cpu_has(X86_FEATURE_MWAIT))
1549 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1551 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1554 eax = CPUID_MWAIT_LEAF;
1556 native_cpuid(&eax, &ebx, &ecx, &edx);
1559 * eax will be 0 if EDX enumeration is not valid.
1560 * Initialized below to cstate, sub_cstate value when EDX is valid.
1562 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1565 edx >>= MWAIT_SUBSTATE_SIZE;
1566 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1567 if (edx & MWAIT_SUBSTATE_MASK) {
1569 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1572 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1573 (highest_subcstate - 1);
1577 * This should be a memory location in a cache line which is
1578 * unlikely to be touched by other processors. The actual
1579 * content is immaterial as it is not actually modified in any way.
1581 mwait_ptr = ¤t_thread_info()->flags;
1587 * The CLFLUSH is a workaround for erratum AAI65 for
1588 * the Xeon 7400 series. It's not clear it is actually
1589 * needed, but it should be harmless in either case.
1590 * The WBINVD is insufficient due to the spurious-wakeup
1591 * case where we return around the loop.
1596 __monitor(mwait_ptr, 0, 0);
1600 * If NMI wants to wake up CPU0, start CPU0.
1607 void hlt_play_dead(void)
1609 if (__this_cpu_read(cpu_info.x86) >= 4)
1615 * If NMI wants to wake up CPU0, start CPU0.
1622 void native_play_dead(void)
1625 tboot_shutdown(TB_SHUTDOWN_WFS);
1627 mwait_play_dead(); /* Only returns on failure */
1628 if (cpuidle_play_dead())
1632 #else /* ... !CONFIG_HOTPLUG_CPU */
1633 int native_cpu_disable(void)
1638 void native_cpu_die(unsigned int cpu)
1640 /* We said "no" in __cpu_disable */
1644 void native_play_dead(void)