1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3 #include <linux/errno.h>
4 #include <linux/kernel.h>
7 #include <linux/prctl.h>
8 #include <linux/slab.h>
9 #include <linux/sched.h>
10 #include <linux/module.h>
12 #include <linux/clockchips.h>
13 #include <linux/random.h>
14 #include <linux/user-return-notifier.h>
15 #include <linux/dmi.h>
16 #include <linux/utsname.h>
17 #include <linux/stackprotector.h>
18 #include <linux/tick.h>
19 #include <linux/cpuidle.h>
20 #include <trace/events/power.h>
21 #include <linux/hw_breakpoint.h>
24 #include <asm/syscalls.h>
26 #include <asm/uaccess.h>
28 #include <asm/fpu-internal.h>
29 #include <asm/debugreg.h>
33 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
34 * no more per-task TSS's. The TSS size is kept cacheline-aligned
35 * so they are allowed to end up in the .data..cacheline_aligned
36 * section. Since TSS's are completely CPU-local, we want them
37 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
39 DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;
42 static DEFINE_PER_CPU(unsigned char, is_idle);
43 static ATOMIC_NOTIFIER_HEAD(idle_notifier);
45 void idle_notifier_register(struct notifier_block *n)
47 atomic_notifier_chain_register(&idle_notifier, n);
49 EXPORT_SYMBOL_GPL(idle_notifier_register);
51 void idle_notifier_unregister(struct notifier_block *n)
53 atomic_notifier_chain_unregister(&idle_notifier, n);
55 EXPORT_SYMBOL_GPL(idle_notifier_unregister);
58 struct kmem_cache *task_xstate_cachep;
59 EXPORT_SYMBOL_GPL(task_xstate_cachep);
62 * this gets called so that we can store lazy state into memory and copy the
63 * current task into the new thread.
65 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
72 if (fpu_allocated(&src->thread.fpu)) {
73 memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
74 ret = fpu_alloc(&dst->thread.fpu);
77 fpu_copy(&dst->thread.fpu, &src->thread.fpu);
82 void free_thread_xstate(struct task_struct *tsk)
84 fpu_free(&tsk->thread.fpu);
87 void arch_release_task_struct(struct task_struct *tsk)
89 free_thread_xstate(tsk);
92 void arch_task_cache_init(void)
95 kmem_cache_create("task_xstate", xstate_size,
96 __alignof__(union thread_xstate),
97 SLAB_PANIC | SLAB_NOTRACK, NULL);
101 * Free current thread data structures etc..
103 void exit_thread(void)
105 struct task_struct *me = current;
106 struct thread_struct *t = &me->thread;
107 unsigned long *bp = t->io_bitmap_ptr;
110 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
112 t->io_bitmap_ptr = NULL;
113 clear_thread_flag(TIF_IO_BITMAP);
115 * Careful, clear this in the TSS too:
117 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
118 t->io_bitmap_max = 0;
126 void show_regs_common(void)
128 const char *vendor, *product, *board;
130 vendor = dmi_get_system_info(DMI_SYS_VENDOR);
133 product = dmi_get_system_info(DMI_PRODUCT_NAME);
137 /* Board Name is optional */
138 board = dmi_get_system_info(DMI_BOARD_NAME);
140 printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s %s%s%s\n",
141 current->pid, current->comm, print_tainted(),
142 init_utsname()->release,
143 (int)strcspn(init_utsname()->version, " "),
144 init_utsname()->version,
150 void flush_thread(void)
152 struct task_struct *tsk = current;
154 flush_ptrace_hw_breakpoint(tsk);
155 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
159 static void hard_disable_TSC(void)
161 write_cr4(read_cr4() | X86_CR4_TSD);
164 void disable_TSC(void)
167 if (!test_and_set_thread_flag(TIF_NOTSC))
169 * Must flip the CPU state synchronously with
170 * TIF_NOTSC in the current running context.
176 static void hard_enable_TSC(void)
178 write_cr4(read_cr4() & ~X86_CR4_TSD);
181 static void enable_TSC(void)
184 if (test_and_clear_thread_flag(TIF_NOTSC))
186 * Must flip the CPU state synchronously with
187 * TIF_NOTSC in the current running context.
193 int get_tsc_mode(unsigned long adr)
197 if (test_thread_flag(TIF_NOTSC))
198 val = PR_TSC_SIGSEGV;
202 return put_user(val, (unsigned int __user *)adr);
205 int set_tsc_mode(unsigned int val)
207 if (val == PR_TSC_SIGSEGV)
209 else if (val == PR_TSC_ENABLE)
217 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
218 struct tss_struct *tss)
220 struct thread_struct *prev, *next;
222 prev = &prev_p->thread;
223 next = &next_p->thread;
225 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
226 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
227 unsigned long debugctl = get_debugctlmsr();
229 debugctl &= ~DEBUGCTLMSR_BTF;
230 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
231 debugctl |= DEBUGCTLMSR_BTF;
233 update_debugctlmsr(debugctl);
236 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
237 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
238 /* prev and next are different */
239 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
245 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
247 * Copy the relevant range of the IO bitmap.
248 * Normally this is 128 bytes or less:
250 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
251 max(prev->io_bitmap_max, next->io_bitmap_max));
252 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
254 * Clear any possible leftover bits:
256 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
258 propagate_user_return_notify(prev_p, next_p);
261 int sys_fork(struct pt_regs *regs)
263 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
267 * This is trivial, and on the face of it looks like it
268 * could equally well be done in user mode.
270 * Not so, for quite unobvious reasons - register pressure.
271 * In user mode vfork() cannot have a stack frame, and if
272 * done by calling the "clone()" system call directly, you
273 * do not have enough call-clobbered registers to hold all
274 * the information you need.
276 int sys_vfork(struct pt_regs *regs)
278 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
283 sys_clone(unsigned long clone_flags, unsigned long newsp,
284 void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
288 return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
292 * This gets run with %si containing the
293 * function to call, and %di containing
296 extern void kernel_thread_helper(void);
299 * Create a kernel thread
301 int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
305 memset(®s, 0, sizeof(regs));
307 regs.si = (unsigned long) fn;
308 regs.di = (unsigned long) arg;
313 regs.fs = __KERNEL_PERCPU;
314 regs.gs = __KERNEL_STACK_CANARY;
316 regs.ss = __KERNEL_DS;
320 regs.ip = (unsigned long) kernel_thread_helper;
321 regs.cs = __KERNEL_CS | get_kernel_rpl();
322 regs.flags = X86_EFLAGS_IF | X86_EFLAGS_BIT1;
324 /* Ok, create the new process.. */
325 return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL);
327 EXPORT_SYMBOL(kernel_thread);
330 * sys_execve() executes a new program.
332 long sys_execve(const char __user *name,
333 const char __user *const __user *argv,
334 const char __user *const __user *envp, struct pt_regs *regs)
339 filename = getname(name);
340 error = PTR_ERR(filename);
341 if (IS_ERR(filename))
343 error = do_execve(filename, argv, envp, regs);
347 /* Make sure we don't return using sysenter.. */
348 set_thread_flag(TIF_IRET);
357 * Idle related variables and functions
359 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
360 EXPORT_SYMBOL(boot_option_idle_override);
363 * Powermanagement idle function, if any..
365 void (*pm_idle)(void);
366 #ifdef CONFIG_APM_MODULE
367 EXPORT_SYMBOL(pm_idle);
370 static inline int hlt_use_halt(void)
376 static inline void play_dead(void)
383 void enter_idle(void)
385 this_cpu_write(is_idle, 1);
386 atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
389 static void __exit_idle(void)
391 if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
393 atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
396 /* Called from interrupts to signify idle end */
399 /* idle loop has pid 0 */
407 * The idle thread. There's no useful work to be
408 * done, so just try to conserve power and have a
409 * low exit latency (ie sit in a loop waiting for
410 * somebody to say that they'd like to reschedule)
415 * If we're the non-boot CPU, nothing set the stack canary up
416 * for us. CPU0 already has it initialized but no harm in
417 * doing it again. This is a good place for updating it, as
418 * we wont ever return from this function (so the invalid
419 * canaries already on the stack wont ever trigger).
421 boot_init_stack_canary();
422 current_thread_info()->status |= TS_POLLING;
425 tick_nohz_idle_enter();
427 while (!need_resched()) {
430 if (cpu_is_offline(smp_processor_id()))
434 * Idle routines should keep interrupts disabled
435 * from here on, until they go to idle.
436 * Otherwise, idle callbacks can misfire.
443 /* Don't trace irqs off for idle */
444 stop_critical_timings();
446 /* enter_idle() needs rcu for notifiers */
449 if (cpuidle_idle_call())
453 start_critical_timings();
455 /* In many cases the interrupt that ended idle
456 has already called exit_idle. But some idle
457 loops can be woken up without interrupt. */
461 tick_nohz_idle_exit();
462 preempt_enable_no_resched();
469 * We use this if we don't have any better
472 void default_idle(void)
474 if (hlt_use_halt()) {
475 trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id());
476 trace_cpu_idle_rcuidle(1, smp_processor_id());
477 current_thread_info()->status &= ~TS_POLLING;
479 * TS_POLLING-cleared state must be visible before we
485 safe_halt(); /* enables interrupts racelessly */
488 current_thread_info()->status |= TS_POLLING;
489 trace_power_end_rcuidle(smp_processor_id());
490 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
493 /* loop is done by the caller */
497 #ifdef CONFIG_APM_MODULE
498 EXPORT_SYMBOL(default_idle);
501 bool set_pm_idle_to_default(void)
503 bool ret = !!pm_idle;
505 pm_idle = default_idle;
509 void stop_this_cpu(void *dummy)
515 set_cpu_online(smp_processor_id(), false);
516 disable_local_APIC();
519 if (hlt_works(smp_processor_id()))
524 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
525 static void mwait_idle(void)
527 if (!need_resched()) {
528 trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id());
529 trace_cpu_idle_rcuidle(1, smp_processor_id());
530 if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
531 clflush((void *)¤t_thread_info()->flags);
533 __monitor((void *)¤t_thread_info()->flags, 0, 0);
539 trace_power_end_rcuidle(smp_processor_id());
540 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
546 * On SMP it's slightly faster (but much more power-consuming!)
547 * to poll the ->work.need_resched flag instead of waiting for the
548 * cross-CPU IPI to arrive. Use this option with caution.
550 static void poll_idle(void)
552 trace_power_start_rcuidle(POWER_CSTATE, 0, smp_processor_id());
553 trace_cpu_idle_rcuidle(0, smp_processor_id());
555 while (!need_resched())
557 trace_power_end_rcuidle(smp_processor_id());
558 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
562 * mwait selection logic:
564 * It depends on the CPU. For AMD CPUs that support MWAIT this is
565 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
566 * then depend on a clock divisor and current Pstate of the core. If
567 * all cores of a processor are in halt state (C1) the processor can
568 * enter the C1E (C1 enhanced) state. If mwait is used this will never
571 * idle=mwait overrides this decision and forces the usage of mwait.
574 #define MWAIT_INFO 0x05
575 #define MWAIT_ECX_EXTENDED_INFO 0x01
576 #define MWAIT_EDX_C1 0xf0
578 int mwait_usable(const struct cpuinfo_x86 *c)
580 u32 eax, ebx, ecx, edx;
582 /* Use mwait if idle=mwait boot option is given */
583 if (boot_option_idle_override == IDLE_FORCE_MWAIT)
587 * Any idle= boot option other than idle=mwait means that we must not
588 * use mwait. Eg: idle=halt or idle=poll or idle=nomwait
590 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
593 if (c->cpuid_level < MWAIT_INFO)
596 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
597 /* Check, whether EDX has extended info about MWAIT */
598 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
602 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
605 return (edx & MWAIT_EDX_C1);
608 bool amd_e400_c1e_detected;
609 EXPORT_SYMBOL(amd_e400_c1e_detected);
611 static cpumask_var_t amd_e400_c1e_mask;
613 void amd_e400_remove_cpu(int cpu)
615 if (amd_e400_c1e_mask != NULL)
616 cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
620 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
621 * pending message MSR. If we detect C1E, then we handle it the same
622 * way as C3 power states (local apic timer and TSC stop)
624 static void amd_e400_idle(void)
629 if (!amd_e400_c1e_detected) {
632 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
634 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
635 amd_e400_c1e_detected = true;
636 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
637 mark_tsc_unstable("TSC halt in AMD C1E");
638 pr_info("System has AMD C1E enabled\n");
642 if (amd_e400_c1e_detected) {
643 int cpu = smp_processor_id();
645 if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
646 cpumask_set_cpu(cpu, amd_e400_c1e_mask);
648 * Force broadcast so ACPI can not interfere.
650 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
652 pr_info("Switch to broadcast mode on CPU%d\n", cpu);
654 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
659 * The switch back from broadcast mode needs to be
660 * called with interrupts disabled.
663 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
669 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
672 if (pm_idle == poll_idle && smp_num_siblings > 1) {
673 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
679 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
681 * One CPU supports mwait => All CPUs supports mwait
683 pr_info("using mwait in idle threads\n");
684 pm_idle = mwait_idle;
685 } else if (cpu_has_amd_erratum(amd_erratum_400)) {
686 /* E400: APIC timer interrupt does not wake up CPU from C1e */
687 pr_info("using AMD E400 aware idle routine\n");
688 pm_idle = amd_e400_idle;
690 pm_idle = default_idle;
693 void __init init_amd_e400_c1e_mask(void)
695 /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
696 if (pm_idle == amd_e400_idle)
697 zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
700 static int __init idle_setup(char *str)
705 if (!strcmp(str, "poll")) {
706 pr_info("using polling idle threads\n");
708 boot_option_idle_override = IDLE_POLL;
709 } else if (!strcmp(str, "mwait")) {
710 boot_option_idle_override = IDLE_FORCE_MWAIT;
711 WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n");
712 } else if (!strcmp(str, "halt")) {
714 * When the boot option of idle=halt is added, halt is
715 * forced to be used for CPU idle. In such case CPU C2/C3
716 * won't be used again.
717 * To continue to load the CPU idle driver, don't touch
718 * the boot_option_idle_override.
720 pm_idle = default_idle;
721 boot_option_idle_override = IDLE_HALT;
722 } else if (!strcmp(str, "nomwait")) {
724 * If the boot option of "idle=nomwait" is added,
725 * it means that mwait will be disabled for CPU C2/C3
726 * states. In such case it won't touch the variable
727 * of boot_option_idle_override.
729 boot_option_idle_override = IDLE_NOMWAIT;
735 early_param("idle", idle_setup);
737 unsigned long arch_align_stack(unsigned long sp)
739 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
740 sp -= get_random_int() % 8192;
744 unsigned long arch_randomize_brk(struct mm_struct *mm)
746 unsigned long range_end = mm->brk + 0x02000000;
747 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;