1 // SPDX-License-Identifier: GPL-2.0
2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
4 #include <linux/errno.h>
5 #include <linux/kernel.h>
8 #include <linux/prctl.h>
9 #include <linux/slab.h>
10 #include <linux/sched.h>
11 #include <linux/sched/idle.h>
12 #include <linux/sched/debug.h>
13 #include <linux/sched/task.h>
14 #include <linux/sched/task_stack.h>
15 #include <linux/init.h>
16 #include <linux/export.h>
18 #include <linux/tick.h>
19 #include <linux/random.h>
20 #include <linux/user-return-notifier.h>
21 #include <linux/dmi.h>
22 #include <linux/utsname.h>
23 #include <linux/stackprotector.h>
24 #include <linux/cpuidle.h>
25 #include <trace/events/power.h>
26 #include <linux/hw_breakpoint.h>
29 #include <asm/syscalls.h>
30 #include <linux/uaccess.h>
31 #include <asm/mwait.h>
32 #include <asm/fpu/internal.h>
33 #include <asm/debugreg.h>
35 #include <asm/tlbflush.h>
38 #include <asm/switch_to.h>
40 #include <asm/prctl.h>
41 #include <asm/spec-ctrl.h>
44 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
45 * no more per-task TSS's. The TSS size is kept cacheline-aligned
46 * so they are allowed to end up in the .data..cacheline_aligned
47 * section. Since TSS's are completely CPU-local, we want them
48 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
50 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
53 * .sp0 is only used when entering ring 0 from a lower
54 * privilege level. Since the init task never runs anything
55 * but ring 0 code, there is no need for a valid value here.
58 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
62 * .sp1 is cpu_current_top_of_stack. The init task never
63 * runs user code, but cpu_current_top_of_stack should still
64 * be well defined before the first context switch.
66 .sp1 = TOP_OF_INIT_STACK,
72 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
77 * Note that the .io_bitmap member must be extra-big. This is because
78 * the CPU will access an additional byte beyond the end of the IO
79 * permission bitmap. The extra byte must be all 1 bits, and must
80 * be within the limit.
82 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 },
85 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
87 DEFINE_PER_CPU(bool, __tss_limit_invalid);
88 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
91 * this gets called so that we can store lazy state into memory and copy the
92 * current task into the new thread.
94 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
96 memcpy(dst, src, arch_task_struct_size);
98 dst->thread.vm86 = NULL;
101 return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
105 * Free current thread data structures etc..
107 void exit_thread(struct task_struct *tsk)
109 struct thread_struct *t = &tsk->thread;
110 unsigned long *bp = t->io_bitmap_ptr;
111 struct fpu *fpu = &t->fpu;
114 struct tss_struct *tss = &per_cpu(cpu_tss_rw, get_cpu());
116 t->io_bitmap_ptr = NULL;
117 clear_thread_flag(TIF_IO_BITMAP);
119 * Careful, clear this in the TSS too:
121 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
122 t->io_bitmap_max = 0;
132 void flush_thread(void)
134 struct task_struct *tsk = current;
136 flush_ptrace_hw_breakpoint(tsk);
137 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
139 fpu__clear(&tsk->thread.fpu);
142 void disable_TSC(void)
145 if (!test_and_set_thread_flag(TIF_NOTSC))
147 * Must flip the CPU state synchronously with
148 * TIF_NOTSC in the current running context.
150 cr4_set_bits(X86_CR4_TSD);
154 static void enable_TSC(void)
157 if (test_and_clear_thread_flag(TIF_NOTSC))
159 * Must flip the CPU state synchronously with
160 * TIF_NOTSC in the current running context.
162 cr4_clear_bits(X86_CR4_TSD);
166 int get_tsc_mode(unsigned long adr)
170 if (test_thread_flag(TIF_NOTSC))
171 val = PR_TSC_SIGSEGV;
175 return put_user(val, (unsigned int __user *)adr);
178 int set_tsc_mode(unsigned int val)
180 if (val == PR_TSC_SIGSEGV)
182 else if (val == PR_TSC_ENABLE)
190 DEFINE_PER_CPU(u64, msr_misc_features_shadow);
192 static void set_cpuid_faulting(bool on)
196 msrval = this_cpu_read(msr_misc_features_shadow);
197 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
198 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
199 this_cpu_write(msr_misc_features_shadow, msrval);
200 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
203 static void disable_cpuid(void)
206 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
208 * Must flip the CPU state synchronously with
209 * TIF_NOCPUID in the current running context.
211 set_cpuid_faulting(true);
216 static void enable_cpuid(void)
219 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
221 * Must flip the CPU state synchronously with
222 * TIF_NOCPUID in the current running context.
224 set_cpuid_faulting(false);
229 static int get_cpuid_mode(void)
231 return !test_thread_flag(TIF_NOCPUID);
234 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
236 if (!static_cpu_has(X86_FEATURE_CPUID_FAULT))
248 * Called immediately after a successful exec.
250 void arch_setup_new_exec(void)
252 /* If cpuid was previously disabled for this task, re-enable it. */
253 if (test_thread_flag(TIF_NOCPUID))
257 static inline void switch_to_bitmap(struct tss_struct *tss,
258 struct thread_struct *prev,
259 struct thread_struct *next,
260 unsigned long tifp, unsigned long tifn)
262 if (tifn & _TIF_IO_BITMAP) {
264 * Copy the relevant range of the IO bitmap.
265 * Normally this is 128 bytes or less:
267 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
268 max(prev->io_bitmap_max, next->io_bitmap_max));
270 * Make sure that the TSS limit is correct for the CPU
271 * to notice the IO bitmap.
274 } else if (tifp & _TIF_IO_BITMAP) {
276 * Clear any possible leftover bits:
278 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
282 static __always_inline void __speculative_store_bypass_update(unsigned long tifn)
286 if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
287 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
288 wrmsrl(MSR_AMD64_LS_CFG, msr);
290 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn);
291 wrmsrl(MSR_IA32_SPEC_CTRL, msr);
295 void speculative_store_bypass_update(void)
297 __speculative_store_bypass_update(current_thread_info()->flags);
300 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
301 struct tss_struct *tss)
303 struct thread_struct *prev, *next;
304 unsigned long tifp, tifn;
306 prev = &prev_p->thread;
307 next = &next_p->thread;
309 tifn = READ_ONCE(task_thread_info(next_p)->flags);
310 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
311 switch_to_bitmap(tss, prev, next, tifp, tifn);
313 propagate_user_return_notify(prev_p, next_p);
315 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
316 arch_has_block_step()) {
317 unsigned long debugctl, msk;
319 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
320 debugctl &= ~DEBUGCTLMSR_BTF;
321 msk = tifn & _TIF_BLOCKSTEP;
322 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
323 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
326 if ((tifp ^ tifn) & _TIF_NOTSC)
327 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
329 if ((tifp ^ tifn) & _TIF_NOCPUID)
330 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
332 if ((tifp ^ tifn) & _TIF_SSBD)
333 __speculative_store_bypass_update(tifn);
337 * Idle related variables and functions
339 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
340 EXPORT_SYMBOL(boot_option_idle_override);
342 static void (*x86_idle)(void);
345 static inline void play_dead(void)
351 void arch_cpu_idle_enter(void)
353 tsc_verify_tsc_adjust(false);
357 void arch_cpu_idle_dead(void)
363 * Called from the generic idle code.
365 void arch_cpu_idle(void)
371 * We use this if we don't have any better idle routine..
373 void __cpuidle default_idle(void)
375 trace_cpu_idle_rcuidle(1, smp_processor_id());
377 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
379 #ifdef CONFIG_APM_MODULE
380 EXPORT_SYMBOL(default_idle);
384 bool xen_set_default_idle(void)
386 bool ret = !!x86_idle;
388 x86_idle = default_idle;
394 void stop_this_cpu(void *dummy)
400 set_cpu_online(smp_processor_id(), false);
401 disable_local_APIC();
402 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
405 * Use wbinvd on processors that support SME. This provides support
406 * for performing a successful kexec when going from SME inactive
407 * to SME active (or vice-versa). The cache must be cleared so that
408 * if there are entries with the same physical address, both with and
409 * without the encryption bit, they don't race each other when flushed
410 * and potentially end up with the wrong entry being committed to
413 if (boot_cpu_has(X86_FEATURE_SME))
417 * Use native_halt() so that memory contents don't change
418 * (stack usage and variables) after possibly issuing the
419 * native_wbinvd() above.
426 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
427 * states (local apic timer and TSC stop).
429 static void amd_e400_idle(void)
432 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
433 * gets set after static_cpu_has() places have been converted via
436 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
441 tick_broadcast_enter();
446 * The switch back from broadcast mode needs to be called with
447 * interrupts disabled.
450 tick_broadcast_exit();
455 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
456 * We can't rely on cpuidle installing MWAIT, because it will not load
457 * on systems that support only C1 -- so the boot default must be MWAIT.
459 * Some AMD machines are the opposite, they depend on using HALT.
461 * So for default C1, which is used during boot until cpuidle loads,
462 * use MWAIT-C1 on Intel HW that has it, else use HALT.
464 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
466 if (c->x86_vendor != X86_VENDOR_INTEL)
469 if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR))
476 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
477 * with interrupts enabled and no flags, which is backwards compatible with the
478 * original MWAIT implementation.
480 static __cpuidle void mwait_idle(void)
482 if (!current_set_polling_and_test()) {
483 trace_cpu_idle_rcuidle(1, smp_processor_id());
484 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
486 clflush((void *)¤t_thread_info()->flags);
490 __monitor((void *)¤t_thread_info()->flags, 0, 0);
495 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
499 __current_clr_polling();
502 void select_idle_routine(const struct cpuinfo_x86 *c)
505 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
506 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
508 if (x86_idle || boot_option_idle_override == IDLE_POLL)
511 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
512 pr_info("using AMD E400 aware idle routine\n");
513 x86_idle = amd_e400_idle;
514 } else if (prefer_mwait_c1_over_halt(c)) {
515 pr_info("using mwait in idle threads\n");
516 x86_idle = mwait_idle;
518 x86_idle = default_idle;
521 void amd_e400_c1e_apic_setup(void)
523 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
524 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
526 tick_broadcast_force();
531 void __init arch_post_acpi_subsys_init(void)
535 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
539 * AMD E400 detection needs to happen after ACPI has been enabled. If
540 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
541 * MSR_K8_INT_PENDING_MSG.
543 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
544 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
547 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
549 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
550 mark_tsc_unstable("TSC halt in AMD C1E");
551 pr_info("System has AMD C1E enabled\n");
554 static int __init idle_setup(char *str)
559 if (!strcmp(str, "poll")) {
560 pr_info("using polling idle threads\n");
561 boot_option_idle_override = IDLE_POLL;
562 cpu_idle_poll_ctrl(true);
563 } else if (!strcmp(str, "halt")) {
565 * When the boot option of idle=halt is added, halt is
566 * forced to be used for CPU idle. In such case CPU C2/C3
567 * won't be used again.
568 * To continue to load the CPU idle driver, don't touch
569 * the boot_option_idle_override.
571 x86_idle = default_idle;
572 boot_option_idle_override = IDLE_HALT;
573 } else if (!strcmp(str, "nomwait")) {
575 * If the boot option of "idle=nomwait" is added,
576 * it means that mwait will be disabled for CPU C2/C3
577 * states. In such case it won't touch the variable
578 * of boot_option_idle_override.
580 boot_option_idle_override = IDLE_NOMWAIT;
586 early_param("idle", idle_setup);
588 unsigned long arch_align_stack(unsigned long sp)
590 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
591 sp -= get_random_int() % 8192;
595 unsigned long arch_randomize_brk(struct mm_struct *mm)
597 return randomize_page(mm->brk, 0x02000000);
601 * Called from fs/proc with a reference on @p to find the function
602 * which called into schedule(). This needs to be done carefully
603 * because the task might wake up and we might look at a stack
606 unsigned long get_wchan(struct task_struct *p)
608 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
611 if (!p || p == current || p->state == TASK_RUNNING)
614 if (!try_get_task_stack(p))
617 start = (unsigned long)task_stack_page(p);
622 * Layout of the stack page:
624 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
626 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
628 * ----------- bottom = start
630 * The tasks stack pointer points at the location where the
631 * framepointer is stored. The data on the stack is:
632 * ... IP FP ... IP FP
634 * We need to read FP and IP, so we need to adjust the upper
635 * bound by another unsigned long.
637 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
638 top -= 2 * sizeof(unsigned long);
641 sp = READ_ONCE(p->thread.sp);
642 if (sp < bottom || sp > top)
645 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
647 if (fp < bottom || fp > top)
649 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
650 if (!in_sched_functions(ip)) {
654 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
655 } while (count++ < 16 && p->state != TASK_RUNNING);
662 long do_arch_prctl_common(struct task_struct *task, int option,
663 unsigned long cpuid_enabled)
667 return get_cpuid_mode();
669 return set_cpuid_mode(task, cpuid_enabled);