1 #include <linux/errno.h>
2 #include <linux/kernel.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <linux/user-return-notifier.h>
13 #include <linux/dmi.h>
14 #include <linux/utsname.h>
15 #include <trace/events/power.h>
16 #include <linux/hw_breakpoint.h>
18 #include <asm/system.h>
20 #include <asm/syscalls.h>
22 #include <asm/uaccess.h>
24 #include <asm/fpu-internal.h>
25 #include <asm/debugreg.h>
27 struct kmem_cache *task_xstate_cachep;
28 EXPORT_SYMBOL_GPL(task_xstate_cachep);
30 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
35 if (fpu_allocated(&src->thread.fpu)) {
36 memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
37 ret = fpu_alloc(&dst->thread.fpu);
40 fpu_copy(&dst->thread.fpu, &src->thread.fpu);
45 void free_thread_xstate(struct task_struct *tsk)
47 fpu_free(&tsk->thread.fpu);
50 void free_thread_info(struct thread_info *ti)
52 free_thread_xstate(ti->task);
53 free_pages((unsigned long)ti, THREAD_ORDER);
56 void arch_task_cache_init(void)
59 kmem_cache_create("task_xstate", xstate_size,
60 __alignof__(union thread_xstate),
61 SLAB_PANIC | SLAB_NOTRACK, NULL);
65 * Free current thread data structures etc..
67 void exit_thread(void)
69 struct task_struct *me = current;
70 struct thread_struct *t = &me->thread;
71 unsigned long *bp = t->io_bitmap_ptr;
74 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
76 t->io_bitmap_ptr = NULL;
77 clear_thread_flag(TIF_IO_BITMAP);
79 * Careful, clear this in the TSS too:
81 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
88 void show_regs(struct pt_regs *regs)
91 show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs), 0);
94 void show_regs_common(void)
96 const char *vendor, *product, *board;
98 vendor = dmi_get_system_info(DMI_SYS_VENDOR);
101 product = dmi_get_system_info(DMI_PRODUCT_NAME);
105 /* Board Name is optional */
106 board = dmi_get_system_info(DMI_BOARD_NAME);
108 printk(KERN_CONT "\n");
109 printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s",
110 current->pid, current->comm, print_tainted(),
111 init_utsname()->release,
112 (int)strcspn(init_utsname()->version, " "),
113 init_utsname()->version);
114 printk(KERN_CONT " %s %s", vendor, product);
116 printk(KERN_CONT "/%s", board);
117 printk(KERN_CONT "\n");
120 void flush_thread(void)
122 struct task_struct *tsk = current;
124 flush_ptrace_hw_breakpoint(tsk);
125 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
127 * Forget coprocessor state..
129 tsk->fpu_counter = 0;
134 static void hard_disable_TSC(void)
136 write_cr4(read_cr4() | X86_CR4_TSD);
139 void disable_TSC(void)
142 if (!test_and_set_thread_flag(TIF_NOTSC))
144 * Must flip the CPU state synchronously with
145 * TIF_NOTSC in the current running context.
151 static void hard_enable_TSC(void)
153 write_cr4(read_cr4() & ~X86_CR4_TSD);
156 static void enable_TSC(void)
159 if (test_and_clear_thread_flag(TIF_NOTSC))
161 * Must flip the CPU state synchronously with
162 * TIF_NOTSC in the current running context.
168 int get_tsc_mode(unsigned long adr)
172 if (test_thread_flag(TIF_NOTSC))
173 val = PR_TSC_SIGSEGV;
177 return put_user(val, (unsigned int __user *)adr);
180 int set_tsc_mode(unsigned int val)
182 if (val == PR_TSC_SIGSEGV)
184 else if (val == PR_TSC_ENABLE)
192 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
193 struct tss_struct *tss)
195 struct thread_struct *prev, *next;
197 prev = &prev_p->thread;
198 next = &next_p->thread;
200 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
201 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
202 unsigned long debugctl = get_debugctlmsr();
204 debugctl &= ~DEBUGCTLMSR_BTF;
205 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
206 debugctl |= DEBUGCTLMSR_BTF;
208 update_debugctlmsr(debugctl);
211 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
212 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
213 /* prev and next are different */
214 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
220 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
222 * Copy the relevant range of the IO bitmap.
223 * Normally this is 128 bytes or less:
225 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
226 max(prev->io_bitmap_max, next->io_bitmap_max));
227 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
229 * Clear any possible leftover bits:
231 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
233 propagate_user_return_notify(prev_p, next_p);
236 int sys_fork(struct pt_regs *regs)
238 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
242 * This is trivial, and on the face of it looks like it
243 * could equally well be done in user mode.
245 * Not so, for quite unobvious reasons - register pressure.
246 * In user mode vfork() cannot have a stack frame, and if
247 * done by calling the "clone()" system call directly, you
248 * do not have enough call-clobbered registers to hold all
249 * the information you need.
251 int sys_vfork(struct pt_regs *regs)
253 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
258 sys_clone(unsigned long clone_flags, unsigned long newsp,
259 void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
263 return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
267 * This gets run with %si containing the
268 * function to call, and %di containing
271 extern void kernel_thread_helper(void);
274 * Create a kernel thread
276 int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
280 memset(®s, 0, sizeof(regs));
282 regs.si = (unsigned long) fn;
283 regs.di = (unsigned long) arg;
288 regs.fs = __KERNEL_PERCPU;
289 regs.gs = __KERNEL_STACK_CANARY;
291 regs.ss = __KERNEL_DS;
295 regs.ip = (unsigned long) kernel_thread_helper;
296 regs.cs = __KERNEL_CS | get_kernel_rpl();
297 regs.flags = X86_EFLAGS_IF | X86_EFLAGS_BIT1;
299 /* Ok, create the new process.. */
300 return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL);
302 EXPORT_SYMBOL(kernel_thread);
305 * sys_execve() executes a new program.
307 long sys_execve(const char __user *name,
308 const char __user *const __user *argv,
309 const char __user *const __user *envp, struct pt_regs *regs)
314 filename = getname(name);
315 error = PTR_ERR(filename);
316 if (IS_ERR(filename))
318 error = do_execve(filename, argv, envp, regs);
322 /* Make sure we don't return using sysenter.. */
323 set_thread_flag(TIF_IRET);
332 * Idle related variables and functions
334 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
335 EXPORT_SYMBOL(boot_option_idle_override);
338 * Powermanagement idle function, if any..
340 void (*pm_idle)(void);
341 #ifdef CONFIG_APM_MODULE
342 EXPORT_SYMBOL(pm_idle);
347 * This halt magic was a workaround for ancient floppy DMA
348 * wreckage. It should be safe to remove.
350 static int hlt_counter;
351 void disable_hlt(void)
355 EXPORT_SYMBOL(disable_hlt);
357 void enable_hlt(void)
361 EXPORT_SYMBOL(enable_hlt);
363 static inline int hlt_use_halt(void)
365 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
368 static inline int hlt_use_halt(void)
375 * We use this if we don't have any better
378 void default_idle(void)
380 if (hlt_use_halt()) {
381 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
382 trace_cpu_idle(1, smp_processor_id());
383 current_thread_info()->status &= ~TS_POLLING;
385 * TS_POLLING-cleared state must be visible before we
391 safe_halt(); /* enables interrupts racelessly */
394 current_thread_info()->status |= TS_POLLING;
395 trace_power_end(smp_processor_id());
396 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
399 /* loop is done by the caller */
403 #ifdef CONFIG_APM_MODULE
404 EXPORT_SYMBOL(default_idle);
407 bool set_pm_idle_to_default(void)
409 bool ret = !!pm_idle;
411 pm_idle = default_idle;
415 void stop_this_cpu(void *dummy)
421 set_cpu_online(smp_processor_id(), false);
422 disable_local_APIC();
425 if (hlt_works(smp_processor_id()))
430 static void do_nothing(void *unused)
435 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
436 * pm_idle and update to new pm_idle value. Required while changing pm_idle
437 * handler on SMP systems.
439 * Caller must have changed pm_idle to the new value before the call. Old
440 * pm_idle value will not be used by any CPU after the return of this function.
442 void cpu_idle_wait(void)
445 /* kick all the CPUs so that they exit out of pm_idle */
446 smp_call_function(do_nothing, NULL, 1);
448 EXPORT_SYMBOL_GPL(cpu_idle_wait);
450 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
451 static void mwait_idle(void)
453 if (!need_resched()) {
454 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
455 trace_cpu_idle(1, smp_processor_id());
456 if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
457 clflush((void *)¤t_thread_info()->flags);
459 __monitor((void *)¤t_thread_info()->flags, 0, 0);
465 trace_power_end(smp_processor_id());
466 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
472 * On SMP it's slightly faster (but much more power-consuming!)
473 * to poll the ->work.need_resched flag instead of waiting for the
474 * cross-CPU IPI to arrive. Use this option with caution.
476 static void poll_idle(void)
478 trace_power_start(POWER_CSTATE, 0, smp_processor_id());
479 trace_cpu_idle(0, smp_processor_id());
481 while (!need_resched())
483 trace_power_end(smp_processor_id());
484 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
488 * mwait selection logic:
490 * It depends on the CPU. For AMD CPUs that support MWAIT this is
491 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
492 * then depend on a clock divisor and current Pstate of the core. If
493 * all cores of a processor are in halt state (C1) the processor can
494 * enter the C1E (C1 enhanced) state. If mwait is used this will never
497 * idle=mwait overrides this decision and forces the usage of mwait.
500 #define MWAIT_INFO 0x05
501 #define MWAIT_ECX_EXTENDED_INFO 0x01
502 #define MWAIT_EDX_C1 0xf0
504 int mwait_usable(const struct cpuinfo_x86 *c)
506 u32 eax, ebx, ecx, edx;
508 if (boot_option_idle_override == IDLE_FORCE_MWAIT)
511 if (c->cpuid_level < MWAIT_INFO)
514 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
515 /* Check, whether EDX has extended info about MWAIT */
516 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
520 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
523 return (edx & MWAIT_EDX_C1);
526 bool amd_e400_c1e_detected;
527 EXPORT_SYMBOL(amd_e400_c1e_detected);
529 static cpumask_var_t amd_e400_c1e_mask;
531 void amd_e400_remove_cpu(int cpu)
533 if (amd_e400_c1e_mask != NULL)
534 cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
538 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
539 * pending message MSR. If we detect C1E, then we handle it the same
540 * way as C3 power states (local apic timer and TSC stop)
542 static void amd_e400_idle(void)
547 if (!amd_e400_c1e_detected) {
550 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
552 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
553 amd_e400_c1e_detected = true;
554 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
555 mark_tsc_unstable("TSC halt in AMD C1E");
556 printk(KERN_INFO "System has AMD C1E enabled\n");
560 if (amd_e400_c1e_detected) {
561 int cpu = smp_processor_id();
563 if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
564 cpumask_set_cpu(cpu, amd_e400_c1e_mask);
566 * Force broadcast so ACPI can not interfere.
568 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
570 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
573 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
578 * The switch back from broadcast mode needs to be
579 * called with interrupts disabled.
582 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
588 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
591 if (pm_idle == poll_idle && smp_num_siblings > 1) {
592 printk_once(KERN_WARNING "WARNING: polling idle and HT enabled,"
593 " performance may degrade.\n");
599 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
601 * One CPU supports mwait => All CPUs supports mwait
603 printk(KERN_INFO "using mwait in idle threads.\n");
604 pm_idle = mwait_idle;
605 } else if (cpu_has_amd_erratum(amd_erratum_400)) {
606 /* E400: APIC timer interrupt does not wake up CPU from C1e */
607 printk(KERN_INFO "using AMD E400 aware idle routine\n");
608 pm_idle = amd_e400_idle;
610 pm_idle = default_idle;
613 void __init init_amd_e400_c1e_mask(void)
615 /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
616 if (pm_idle == amd_e400_idle)
617 zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
620 static int __init idle_setup(char *str)
625 if (!strcmp(str, "poll")) {
626 printk("using polling idle threads.\n");
628 boot_option_idle_override = IDLE_POLL;
629 } else if (!strcmp(str, "mwait")) {
630 boot_option_idle_override = IDLE_FORCE_MWAIT;
631 WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n");
632 } else if (!strcmp(str, "halt")) {
634 * When the boot option of idle=halt is added, halt is
635 * forced to be used for CPU idle. In such case CPU C2/C3
636 * won't be used again.
637 * To continue to load the CPU idle driver, don't touch
638 * the boot_option_idle_override.
640 pm_idle = default_idle;
641 boot_option_idle_override = IDLE_HALT;
642 } else if (!strcmp(str, "nomwait")) {
644 * If the boot option of "idle=nomwait" is added,
645 * it means that mwait will be disabled for CPU C2/C3
646 * states. In such case it won't touch the variable
647 * of boot_option_idle_override.
649 boot_option_idle_override = IDLE_NOMWAIT;
655 early_param("idle", idle_setup);
657 unsigned long arch_align_stack(unsigned long sp)
659 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
660 sp -= get_random_int() % 8192;
664 unsigned long arch_randomize_brk(struct mm_struct *mm)
666 unsigned long range_end = mm->brk + 0x02000000;
667 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;