1 #include <linux/errno.h>
2 #include <linux/kernel.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <trace/events/power.h>
13 #include <linux/hw_breakpoint.h>
14 #include <asm/system.h>
16 #include <asm/syscalls.h>
18 #include <asm/uaccess.h>
21 #include <asm/debugreg.h>
23 unsigned long idle_halt;
24 EXPORT_SYMBOL(idle_halt);
25 unsigned long idle_nomwait;
26 EXPORT_SYMBOL(idle_nomwait);
28 struct kmem_cache *task_xstate_cachep;
30 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
33 if (src->thread.xstate) {
34 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
36 if (!dst->thread.xstate)
38 WARN_ON((unsigned long)dst->thread.xstate & 15);
39 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
44 void free_thread_xstate(struct task_struct *tsk)
46 if (tsk->thread.xstate) {
47 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
48 tsk->thread.xstate = NULL;
51 WARN(tsk->thread.ds_ctx, "leaking DS context\n");
54 void free_thread_info(struct thread_info *ti)
56 free_thread_xstate(ti->task);
57 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
60 void arch_task_cache_init(void)
63 kmem_cache_create("task_xstate", xstate_size,
64 __alignof__(union thread_xstate),
65 SLAB_PANIC | SLAB_NOTRACK, NULL);
69 * Free current thread data structures etc..
71 void exit_thread(void)
73 struct task_struct *me = current;
74 struct thread_struct *t = &me->thread;
75 unsigned long *bp = t->io_bitmap_ptr;
78 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
80 t->io_bitmap_ptr = NULL;
81 clear_thread_flag(TIF_IO_BITMAP);
83 * Careful, clear this in the TSS too:
85 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
92 void flush_thread(void)
94 struct task_struct *tsk = current;
97 if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
98 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
99 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
100 clear_tsk_thread_flag(tsk, TIF_IA32);
102 set_tsk_thread_flag(tsk, TIF_IA32);
103 current_thread_info()->status |= TS_COMPAT;
108 flush_ptrace_hw_breakpoint(tsk);
109 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
111 * Forget coprocessor state..
113 tsk->fpu_counter = 0;
118 static void hard_disable_TSC(void)
120 write_cr4(read_cr4() | X86_CR4_TSD);
123 void disable_TSC(void)
126 if (!test_and_set_thread_flag(TIF_NOTSC))
128 * Must flip the CPU state synchronously with
129 * TIF_NOTSC in the current running context.
135 static void hard_enable_TSC(void)
137 write_cr4(read_cr4() & ~X86_CR4_TSD);
140 static void enable_TSC(void)
143 if (test_and_clear_thread_flag(TIF_NOTSC))
145 * Must flip the CPU state synchronously with
146 * TIF_NOTSC in the current running context.
152 int get_tsc_mode(unsigned long adr)
156 if (test_thread_flag(TIF_NOTSC))
157 val = PR_TSC_SIGSEGV;
161 return put_user(val, (unsigned int __user *)adr);
164 int set_tsc_mode(unsigned int val)
166 if (val == PR_TSC_SIGSEGV)
168 else if (val == PR_TSC_ENABLE)
176 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
177 struct tss_struct *tss)
179 struct thread_struct *prev, *next;
181 prev = &prev_p->thread;
182 next = &next_p->thread;
184 if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
185 test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
186 ds_switch_to(prev_p, next_p);
187 else if (next->debugctlmsr != prev->debugctlmsr)
188 update_debugctlmsr(next->debugctlmsr);
190 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
191 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
192 /* prev and next are different */
193 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
199 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
201 * Copy the relevant range of the IO bitmap.
202 * Normally this is 128 bytes or less:
204 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
205 max(prev->io_bitmap_max, next->io_bitmap_max));
206 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
208 * Clear any possible leftover bits:
210 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
214 int sys_fork(struct pt_regs *regs)
216 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
220 * This is trivial, and on the face of it looks like it
221 * could equally well be done in user mode.
223 * Not so, for quite unobvious reasons - register pressure.
224 * In user mode vfork() cannot have a stack frame, and if
225 * done by calling the "clone()" system call directly, you
226 * do not have enough call-clobbered registers to hold all
227 * the information you need.
229 int sys_vfork(struct pt_regs *regs)
231 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
237 * Idle related variables and functions
239 unsigned long boot_option_idle_override = 0;
240 EXPORT_SYMBOL(boot_option_idle_override);
243 * Powermanagement idle function, if any..
245 void (*pm_idle)(void);
246 EXPORT_SYMBOL(pm_idle);
250 * This halt magic was a workaround for ancient floppy DMA
251 * wreckage. It should be safe to remove.
253 static int hlt_counter;
254 void disable_hlt(void)
258 EXPORT_SYMBOL(disable_hlt);
260 void enable_hlt(void)
264 EXPORT_SYMBOL(enable_hlt);
266 static inline int hlt_use_halt(void)
268 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
271 static inline int hlt_use_halt(void)
278 * We use this if we don't have any better
281 void default_idle(void)
283 if (hlt_use_halt()) {
284 trace_power_start(POWER_CSTATE, 1);
285 current_thread_info()->status &= ~TS_POLLING;
287 * TS_POLLING-cleared state must be visible before we
293 safe_halt(); /* enables interrupts racelessly */
296 current_thread_info()->status |= TS_POLLING;
299 /* loop is done by the caller */
303 #ifdef CONFIG_APM_MODULE
304 EXPORT_SYMBOL(default_idle);
307 void stop_this_cpu(void *dummy)
313 set_cpu_online(smp_processor_id(), false);
314 disable_local_APIC();
317 if (hlt_works(smp_processor_id()))
322 static void do_nothing(void *unused)
327 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
328 * pm_idle and update to new pm_idle value. Required while changing pm_idle
329 * handler on SMP systems.
331 * Caller must have changed pm_idle to the new value before the call. Old
332 * pm_idle value will not be used by any CPU after the return of this function.
334 void cpu_idle_wait(void)
337 /* kick all the CPUs so that they exit out of pm_idle */
338 smp_call_function(do_nothing, NULL, 1);
340 EXPORT_SYMBOL_GPL(cpu_idle_wait);
343 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
344 * which can obviate IPI to trigger checking of need_resched.
345 * We execute MONITOR against need_resched and enter optimized wait state
346 * through MWAIT. Whenever someone changes need_resched, we would be woken
347 * up from MWAIT (without an IPI).
349 * New with Core Duo processors, MWAIT can take some hints based on CPU
352 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
354 trace_power_start(POWER_CSTATE, (ax>>4)+1);
355 if (!need_resched()) {
356 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
357 clflush((void *)¤t_thread_info()->flags);
359 __monitor((void *)¤t_thread_info()->flags, 0, 0);
366 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
367 static void mwait_idle(void)
369 if (!need_resched()) {
370 trace_power_start(POWER_CSTATE, 1);
371 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
372 clflush((void *)¤t_thread_info()->flags);
374 __monitor((void *)¤t_thread_info()->flags, 0, 0);
385 * On SMP it's slightly faster (but much more power-consuming!)
386 * to poll the ->work.need_resched flag instead of waiting for the
387 * cross-CPU IPI to arrive. Use this option with caution.
389 static void poll_idle(void)
391 trace_power_start(POWER_CSTATE, 0);
393 while (!need_resched())
399 * mwait selection logic:
401 * It depends on the CPU. For AMD CPUs that support MWAIT this is
402 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
403 * then depend on a clock divisor and current Pstate of the core. If
404 * all cores of a processor are in halt state (C1) the processor can
405 * enter the C1E (C1 enhanced) state. If mwait is used this will never
408 * idle=mwait overrides this decision and forces the usage of mwait.
410 static int __cpuinitdata force_mwait;
412 #define MWAIT_INFO 0x05
413 #define MWAIT_ECX_EXTENDED_INFO 0x01
414 #define MWAIT_EDX_C1 0xf0
416 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
418 u32 eax, ebx, ecx, edx;
423 if (c->cpuid_level < MWAIT_INFO)
426 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
427 /* Check, whether EDX has extended info about MWAIT */
428 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
432 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
435 return (edx & MWAIT_EDX_C1);
439 * Check for AMD CPUs, which have potentially C1E support
441 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
443 if (c->x86_vendor != X86_VENDOR_AMD)
449 /* Family 0x0f models < rev F do not have C1E */
450 if (c->x86 == 0x0f && c->x86_model < 0x40)
456 static cpumask_var_t c1e_mask;
457 static int c1e_detected;
459 void c1e_remove_cpu(int cpu)
461 if (c1e_mask != NULL)
462 cpumask_clear_cpu(cpu, c1e_mask);
466 * C1E aware idle routine. We check for C1E active in the interrupt
467 * pending message MSR. If we detect C1E, then we handle it the same
468 * way as C3 power states (local apic timer and TSC stop)
470 static void c1e_idle(void)
478 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
479 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
481 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
482 mark_tsc_unstable("TSC halt in AMD C1E");
483 printk(KERN_INFO "System has AMD C1E enabled\n");
484 set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
489 int cpu = smp_processor_id();
491 if (!cpumask_test_cpu(cpu, c1e_mask)) {
492 cpumask_set_cpu(cpu, c1e_mask);
494 * Force broadcast so ACPI can not interfere.
496 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
498 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
501 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
506 * The switch back from broadcast mode needs to be
507 * called with interrupts disabled.
510 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
516 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
519 if (pm_idle == poll_idle && smp_num_siblings > 1) {
520 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
521 " performance may degrade.\n");
527 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
529 * One CPU supports mwait => All CPUs supports mwait
531 printk(KERN_INFO "using mwait in idle threads.\n");
532 pm_idle = mwait_idle;
533 } else if (check_c1e_idle(c)) {
534 printk(KERN_INFO "using C1E aware idle routine\n");
537 pm_idle = default_idle;
540 void __init init_c1e_mask(void)
542 /* If we're using c1e_idle, we need to allocate c1e_mask. */
543 if (pm_idle == c1e_idle)
544 zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
547 static int __init idle_setup(char *str)
552 if (!strcmp(str, "poll")) {
553 printk("using polling idle threads.\n");
555 } else if (!strcmp(str, "mwait"))
557 else if (!strcmp(str, "halt")) {
559 * When the boot option of idle=halt is added, halt is
560 * forced to be used for CPU idle. In such case CPU C2/C3
561 * won't be used again.
562 * To continue to load the CPU idle driver, don't touch
563 * the boot_option_idle_override.
565 pm_idle = default_idle;
568 } else if (!strcmp(str, "nomwait")) {
570 * If the boot option of "idle=nomwait" is added,
571 * it means that mwait will be disabled for CPU C2/C3
572 * states. In such case it won't touch the variable
573 * of boot_option_idle_override.
580 boot_option_idle_override = 1;
583 early_param("idle", idle_setup);
585 unsigned long arch_align_stack(unsigned long sp)
587 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
588 sp -= get_random_int() % 8192;
592 unsigned long arch_randomize_brk(struct mm_struct *mm)
594 unsigned long range_end = mm->brk + 0x02000000;
595 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;