2 * Dynamic DMA mapping support for AMD Hammer.
4 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
5 * This allows to use PCI devices that only support 32bit addresses on systems
8 * See Documentation/DMA-mapping.txt for the interface specification.
10 * Copyright 2002 Andi Kleen, SuSE Labs.
11 * Subject to the GNU General Public License v2 only.
14 #include <linux/types.h>
15 #include <linux/ctype.h>
16 #include <linux/agp_backend.h>
17 #include <linux/init.h>
19 #include <linux/string.h>
20 #include <linux/spinlock.h>
21 #include <linux/pci.h>
22 #include <linux/module.h>
23 #include <linux/topology.h>
24 #include <linux/interrupt.h>
25 #include <linux/bitops.h>
26 #include <linux/kdebug.h>
27 #include <linux/scatterlist.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/sysdev.h>
31 #include <asm/atomic.h>
33 #include <asm/pgtable.h>
34 #include <asm/proto.h>
35 #include <asm/iommu.h>
37 #include <asm/cacheflush.h>
38 #include <asm/swiotlb.h>
42 static unsigned long iommu_bus_base; /* GART remapping area (physical) */
43 static unsigned long iommu_size; /* size of remapping area bytes */
44 static unsigned long iommu_pages; /* .. and in pages */
46 static u32 *iommu_gatt_base; /* Remapping table */
49 * If this is disabled the IOMMU will use an optimized flushing strategy
50 * of only flushing when an mapping is reused. With it true the GART is
51 * flushed for every mapping. Problem is that doing the lazy flush seems
52 * to trigger bugs with some popular PCI cards, in particular 3ware (but
53 * has been also also seen with Qlogic at least).
55 static int iommu_fullflush = 1;
57 /* Allocation bitmap for the remapping area: */
58 static DEFINE_SPINLOCK(iommu_bitmap_lock);
59 /* Guarded by iommu_bitmap_lock: */
60 static unsigned long *iommu_gart_bitmap;
62 static u32 gart_unmapped_entry;
65 #define GPTE_COHERENT 2
66 #define GPTE_ENCODE(x) \
67 (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
68 #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
70 #define EMERGENCY_PAGES 32 /* = 128KB */
73 #define AGPEXTERN extern
78 /* backdoor interface to AGP driver */
79 AGPEXTERN int agp_memory_reserved;
80 AGPEXTERN __u32 *agp_gatt_table;
82 static unsigned long next_bit; /* protected by iommu_bitmap_lock */
83 static bool need_flush; /* global flush state. set for each gart wrap */
85 static unsigned long alloc_iommu(struct device *dev, int size,
86 unsigned long align_mask)
88 unsigned long offset, flags;
89 unsigned long boundary_size;
90 unsigned long base_index;
92 base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev),
93 PAGE_SIZE) >> PAGE_SHIFT;
94 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
95 PAGE_SIZE) >> PAGE_SHIFT;
97 spin_lock_irqsave(&iommu_bitmap_lock, flags);
98 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit,
99 size, base_index, boundary_size, align_mask);
102 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0,
103 size, base_index, boundary_size,
107 next_bit = offset+size;
108 if (next_bit >= iommu_pages) {
115 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
120 static void free_iommu(unsigned long offset, int size)
124 spin_lock_irqsave(&iommu_bitmap_lock, flags);
125 iommu_area_free(iommu_gart_bitmap, offset, size);
126 if (offset >= next_bit)
127 next_bit = offset + size;
128 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
132 * Use global flush state to avoid races with multiple flushers.
134 static void flush_gart(void)
138 spin_lock_irqsave(&iommu_bitmap_lock, flags);
143 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
146 #ifdef CONFIG_IOMMU_LEAK
148 #define SET_LEAK(x) \
150 if (iommu_leak_tab) \
151 iommu_leak_tab[x] = __builtin_return_address(0);\
154 #define CLEAR_LEAK(x) \
156 if (iommu_leak_tab) \
157 iommu_leak_tab[x] = NULL; \
160 /* Debugging aid for drivers that don't free their IOMMU tables */
161 static void **iommu_leak_tab;
162 static int leak_trace;
163 static int iommu_leak_pages = 20;
165 static void dump_leak(void)
170 if (dump || !iommu_leak_tab)
173 show_stack(NULL, NULL);
175 /* Very crude. dump some from the end of the table too */
176 printk(KERN_DEBUG "Dumping %d pages from end of IOMMU:\n",
178 for (i = 0; i < iommu_leak_pages; i += 2) {
179 printk(KERN_DEBUG "%lu: ", iommu_pages-i);
180 printk_address((unsigned long) iommu_leak_tab[iommu_pages-i],
182 printk(KERN_CONT "%c", (i+1)%2 == 0 ? '\n' : ' ');
184 printk(KERN_DEBUG "\n");
188 # define CLEAR_LEAK(x)
191 static void iommu_full(struct device *dev, size_t size, int dir)
194 * Ran out of IOMMU space for this operation. This is very bad.
195 * Unfortunately the drivers cannot handle this operation properly.
196 * Return some non mapped prereserved space in the aperture and
197 * let the Northbridge deal with it. This will result in garbage
198 * in the IO operation. When the size exceeds the prereserved space
199 * memory corruption will occur or random memory will be DMAed
200 * out. Hopefully no network devices use single mappings that big.
203 dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size);
205 if (size > PAGE_SIZE*EMERGENCY_PAGES) {
206 if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL)
207 panic("PCI-DMA: Memory would be corrupted\n");
208 if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
210 "PCI-DMA: Random memory would be DMAed\n");
212 #ifdef CONFIG_IOMMU_LEAK
218 need_iommu(struct device *dev, unsigned long addr, size_t size)
220 return force_iommu ||
221 !is_buffer_dma_capable(*dev->dma_mask, addr, size);
225 nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
227 return !is_buffer_dma_capable(*dev->dma_mask, addr, size);
230 /* Map a single continuous physical area into the IOMMU.
231 * Caller needs to check if the iommu is needed and flush.
233 static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
234 size_t size, int dir, unsigned long align_mask)
236 unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE);
237 unsigned long iommu_page = alloc_iommu(dev, npages, align_mask);
240 if (iommu_page == -1) {
241 if (!nonforced_iommu(dev, phys_mem, size))
243 if (panic_on_overflow)
244 panic("dma_map_area overflow %lu bytes\n", size);
245 iommu_full(dev, size, dir);
246 return bad_dma_address;
249 for (i = 0; i < npages; i++) {
250 iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem);
251 SET_LEAK(iommu_page + i);
252 phys_mem += PAGE_SIZE;
254 return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
257 /* Map a single area into the IOMMU */
258 static dma_addr_t gart_map_page(struct device *dev, struct page *page,
259 unsigned long offset, size_t size,
260 enum dma_data_direction dir,
261 struct dma_attrs *attrs)
264 phys_addr_t paddr = page_to_phys(page) + offset;
267 dev = &x86_dma_fallback_dev;
269 if (!need_iommu(dev, paddr, size))
272 bus = dma_map_area(dev, paddr, size, dir, 0);
278 static dma_addr_t gart_map_single(struct device *dev, phys_addr_t paddr,
279 size_t size, int dir)
281 return gart_map_page(dev, pfn_to_page(paddr >> PAGE_SHIFT),
282 paddr & ~PAGE_MASK, size, dir, NULL);
286 * Free a DMA mapping.
288 static void gart_unmap_page(struct device *dev, dma_addr_t dma_addr,
289 size_t size, enum dma_data_direction dir,
290 struct dma_attrs *attrs)
292 unsigned long iommu_page;
296 if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE ||
297 dma_addr >= iommu_bus_base + iommu_size)
300 iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
301 npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
302 for (i = 0; i < npages; i++) {
303 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
304 CLEAR_LEAK(iommu_page + i);
306 free_iommu(iommu_page, npages);
309 static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr,
310 size_t size, int direction)
312 gart_unmap_page(dev, dma_addr, size, direction, NULL);
316 * Wrapper for pci_unmap_single working with scatterlists.
319 gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
321 struct scatterlist *s;
324 for_each_sg(sg, s, nents, i) {
325 if (!s->dma_length || !s->length)
327 gart_unmap_single(dev, s->dma_address, s->dma_length, dir);
331 /* Fallback for dma_map_sg in case of overflow */
332 static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
335 struct scatterlist *s;
338 #ifdef CONFIG_IOMMU_DEBUG
339 printk(KERN_DEBUG "dma_map_sg overflow\n");
342 for_each_sg(sg, s, nents, i) {
343 unsigned long addr = sg_phys(s);
345 if (nonforced_iommu(dev, addr, s->length)) {
346 addr = dma_map_area(dev, addr, s->length, dir, 0);
347 if (addr == bad_dma_address) {
349 gart_unmap_sg(dev, sg, i, dir);
351 sg[0].dma_length = 0;
355 s->dma_address = addr;
356 s->dma_length = s->length;
363 /* Map multiple scatterlist entries continuous into the first. */
364 static int __dma_map_cont(struct device *dev, struct scatterlist *start,
365 int nelems, struct scatterlist *sout,
368 unsigned long iommu_start = alloc_iommu(dev, pages, 0);
369 unsigned long iommu_page = iommu_start;
370 struct scatterlist *s;
373 if (iommu_start == -1)
376 for_each_sg(start, s, nelems, i) {
377 unsigned long pages, addr;
378 unsigned long phys_addr = s->dma_address;
380 BUG_ON(s != start && s->offset);
382 sout->dma_address = iommu_bus_base;
383 sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
384 sout->dma_length = s->length;
386 sout->dma_length += s->length;
390 pages = iommu_num_pages(s->offset, s->length, PAGE_SIZE);
392 iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
393 SET_LEAK(iommu_page);
398 BUG_ON(iommu_page - iommu_start != pages);
404 dma_map_cont(struct device *dev, struct scatterlist *start, int nelems,
405 struct scatterlist *sout, unsigned long pages, int need)
409 sout->dma_address = start->dma_address;
410 sout->dma_length = start->length;
413 return __dma_map_cont(dev, start, nelems, sout, pages);
417 * DMA map all entries in a scatterlist.
418 * Merge chunks that have page aligned sizes into a continuous mapping.
421 gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
423 struct scatterlist *s, *ps, *start_sg, *sgmap;
424 int need = 0, nextneed, i, out, start;
425 unsigned long pages = 0;
426 unsigned int seg_size;
427 unsigned int max_seg_size;
433 dev = &x86_dma_fallback_dev;
437 start_sg = sgmap = sg;
439 max_seg_size = dma_get_max_seg_size(dev);
440 ps = NULL; /* shut up gcc */
441 for_each_sg(sg, s, nents, i) {
442 dma_addr_t addr = sg_phys(s);
444 s->dma_address = addr;
445 BUG_ON(s->length == 0);
447 nextneed = need_iommu(dev, addr, s->length);
449 /* Handle the previous not yet processed entries */
452 * Can only merge when the last chunk ends on a
453 * page boundary and the new one doesn't have an
456 if (!iommu_merge || !nextneed || !need || s->offset ||
457 (s->length + seg_size > max_seg_size) ||
458 (ps->offset + ps->length) % PAGE_SIZE) {
459 if (dma_map_cont(dev, start_sg, i - start,
460 sgmap, pages, need) < 0)
464 sgmap = sg_next(sgmap);
471 seg_size += s->length;
473 pages += iommu_num_pages(s->offset, s->length, PAGE_SIZE);
476 if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0)
481 sgmap = sg_next(sgmap);
482 sgmap->dma_length = 0;
488 gart_unmap_sg(dev, sg, out, dir);
490 /* When it was forced or merged try again in a dumb way */
491 if (force_iommu || iommu_merge) {
492 out = dma_map_sg_nonforce(dev, sg, nents, dir);
496 if (panic_on_overflow)
497 panic("dma_map_sg: overflow on %lu pages\n", pages);
499 iommu_full(dev, pages << PAGE_SHIFT, dir);
500 for_each_sg(sg, s, nents, i)
501 s->dma_address = bad_dma_address;
505 /* allocate and map a coherent mapping */
507 gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
511 unsigned long align_mask;
514 if (force_iommu && !(flag & GFP_DMA)) {
515 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
516 page = alloc_pages(flag | __GFP_ZERO, get_order(size));
520 align_mask = (1UL << get_order(size)) - 1;
521 paddr = dma_map_area(dev, page_to_phys(page), size,
522 DMA_BIDIRECTIONAL, align_mask);
525 if (paddr != bad_dma_address) {
527 return page_address(page);
529 __free_pages(page, get_order(size));
531 return dma_generic_alloc_coherent(dev, size, dma_addr, flag);
536 /* free a coherent mapping */
538 gart_free_coherent(struct device *dev, size_t size, void *vaddr,
541 gart_unmap_single(dev, dma_addr, size, DMA_BIDIRECTIONAL);
542 free_pages((unsigned long)vaddr, get_order(size));
547 static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
552 iommu_size = aper_size;
557 a = aper + iommu_size;
558 iommu_size -= round_up(a, PMD_PAGE_SIZE) - a;
560 if (iommu_size < 64*1024*1024) {
562 "PCI-DMA: Warning: Small IOMMU %luMB."
563 " Consider increasing the AGP aperture in BIOS\n",
570 static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
572 unsigned aper_size = 0, aper_base_32, aper_order;
575 pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
576 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
577 aper_order = (aper_order >> 1) & 7;
579 aper_base = aper_base_32 & 0x7fff;
582 aper_size = (32 * 1024 * 1024) << aper_order;
583 if (aper_base + aper_size > 0x100000000UL || !aper_size)
590 static void enable_gart_translations(void)
594 for (i = 0; i < num_k8_northbridges; i++) {
595 struct pci_dev *dev = k8_northbridges[i];
597 enable_gart_translation(dev, __pa(agp_gatt_table));
602 * If fix_up_north_bridges is set, the north bridges have to be fixed up on
603 * resume in the same way as they are handled in gart_iommu_hole_init().
605 static bool fix_up_north_bridges;
606 static u32 aperture_order;
607 static u32 aperture_alloc;
609 void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
611 fix_up_north_bridges = true;
612 aperture_order = aper_order;
613 aperture_alloc = aper_alloc;
616 static int gart_resume(struct sys_device *dev)
618 printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n");
620 if (fix_up_north_bridges) {
623 printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n");
625 for (i = 0; i < num_k8_northbridges; i++) {
626 struct pci_dev *dev = k8_northbridges[i];
629 * Don't enable translations just yet. That is the next
630 * step. Restore the pre-suspend aperture settings.
632 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL,
633 aperture_order << 1);
634 pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE,
635 aperture_alloc >> 25);
639 enable_gart_translations();
644 static int gart_suspend(struct sys_device *dev, pm_message_t state)
649 static struct sysdev_class gart_sysdev_class = {
651 .suspend = gart_suspend,
652 .resume = gart_resume,
656 static struct sys_device device_gart = {
658 .cls = &gart_sysdev_class,
662 * Private Northbridge GATT initialization in case we cannot use the
663 * AGP driver for some reason.
665 static __init int init_k8_gatt(struct agp_kern_info *info)
667 unsigned aper_size, gatt_size, new_aper_size;
668 unsigned aper_base, new_aper_base;
673 printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
674 aper_size = aper_base = info->aper_size = 0;
676 for (i = 0; i < num_k8_northbridges; i++) {
677 dev = k8_northbridges[i];
678 new_aper_base = read_aperture(dev, &new_aper_size);
683 aper_size = new_aper_size;
684 aper_base = new_aper_base;
686 if (aper_size != new_aper_size || aper_base != new_aper_base)
691 info->aper_base = aper_base;
692 info->aper_size = aper_size >> 20;
694 gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
695 gatt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
696 get_order(gatt_size));
698 panic("Cannot allocate GATT table");
699 if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
700 panic("Could not set GART PTEs to uncacheable pages");
702 agp_gatt_table = gatt;
704 enable_gart_translations();
706 error = sysdev_class_register(&gart_sysdev_class);
708 error = sysdev_register(&device_gart);
710 panic("Could not register gart_sysdev -- "
711 "would corrupt data on next suspend");
715 printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n",
716 aper_base, aper_size>>10);
721 /* Should not happen anymore */
722 printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n"
723 KERN_WARNING "falling back to iommu=soft.\n");
727 static struct dma_mapping_ops gart_dma_ops = {
728 .map_single = gart_map_single,
729 .unmap_single = gart_unmap_single,
730 .map_sg = gart_map_sg,
731 .unmap_sg = gart_unmap_sg,
732 .map_page = gart_map_page,
733 .unmap_page = gart_unmap_page,
734 .alloc_coherent = gart_alloc_coherent,
735 .free_coherent = gart_free_coherent,
738 void gart_iommu_shutdown(void)
743 if (no_agp && (dma_ops != &gart_dma_ops))
746 for (i = 0; i < num_k8_northbridges; i++) {
749 dev = k8_northbridges[i];
750 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
754 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
758 void __init gart_iommu_init(void)
760 struct agp_kern_info info;
761 unsigned long iommu_start;
762 unsigned long aper_base, aper_size;
763 unsigned long start_pfn, end_pfn;
764 unsigned long scratch;
767 if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0)
770 #ifndef CONFIG_AGP_AMD64
773 /* Makefile puts PCI initialization via subsys_initcall first. */
774 /* Add other K8 AGP bridge drivers here */
776 (agp_amd64_init() < 0) ||
777 (agp_copy_info(agp_bridge, &info) < 0);
783 /* Did we detect a different HW IOMMU? */
784 if (iommu_detected && !gart_iommu_aperture)
788 (!force_iommu && max_pfn <= MAX_DMA32_PFN) ||
789 !gart_iommu_aperture ||
790 (no_agp && init_k8_gatt(&info) < 0)) {
791 if (max_pfn > MAX_DMA32_PFN) {
792 printk(KERN_WARNING "More than 4GB of memory "
793 "but GART IOMMU not available.\n");
794 printk(KERN_WARNING "falling back to iommu=soft.\n");
799 /* need to map that range */
800 aper_size = info.aper_size << 20;
801 aper_base = info.aper_base;
802 end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
803 if (end_pfn > max_low_pfn_mapped) {
804 start_pfn = (aper_base>>PAGE_SHIFT);
805 init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
808 printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n");
809 iommu_size = check_iommu_size(info.aper_base, aper_size);
810 iommu_pages = iommu_size >> PAGE_SHIFT;
812 iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO,
813 get_order(iommu_pages/8));
814 if (!iommu_gart_bitmap)
815 panic("Cannot allocate iommu bitmap\n");
817 #ifdef CONFIG_IOMMU_LEAK
819 iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL|__GFP_ZERO,
820 get_order(iommu_pages*sizeof(void *)));
823 "PCI-DMA: Cannot allocate leak trace area\n");
828 * Out of IOMMU space handling.
829 * Reserve some invalid pages at the beginning of the GART.
831 iommu_area_reserve(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
833 agp_memory_reserved = iommu_size;
835 "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
838 iommu_start = aper_size - iommu_size;
839 iommu_bus_base = info.aper_base + iommu_start;
840 bad_dma_address = iommu_bus_base;
841 iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
844 * Unmap the IOMMU part of the GART. The alias of the page is
845 * always mapped with cache enabled and there is no full cache
846 * coherency across the GART remapping. The unmapping avoids
847 * automatic prefetches from the CPU allocating cache lines in
848 * there. All CPU accesses are done via the direct mapping to
849 * the backing memory. The GART address is only used by PCI
852 set_memory_np((unsigned long)__va(iommu_bus_base),
853 iommu_size >> PAGE_SHIFT);
855 * Tricky. The GART table remaps the physical memory range,
856 * so the CPU wont notice potential aliases and if the memory
857 * is remapped to UC later on, we might surprise the PCI devices
858 * with a stray writeout of a cacheline. So play it sure and
859 * do an explicit, full-scale wbinvd() _after_ having marked all
860 * the pages as Not-Present:
865 * Try to workaround a bug (thanks to BenH):
866 * Set unmapped entries to a scratch page instead of 0.
867 * Any prefetches that hit unmapped entries won't get an bus abort
868 * then. (P2P bridge may be prefetching on DMA reads).
870 scratch = get_zeroed_page(GFP_KERNEL);
872 panic("Cannot allocate iommu scratch page");
873 gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
874 for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
875 iommu_gatt_base[i] = gart_unmapped_entry;
878 dma_ops = &gart_dma_ops;
881 void __init gart_parse_options(char *p)
885 #ifdef CONFIG_IOMMU_LEAK
886 if (!strncmp(p, "leak", 4)) {
891 if (isdigit(*p) && get_option(&p, &arg))
892 iommu_leak_pages = arg;
895 if (isdigit(*p) && get_option(&p, &arg))
897 if (!strncmp(p, "fullflush", 8))
899 if (!strncmp(p, "nofullflush", 11))
901 if (!strncmp(p, "noagp", 5))
903 if (!strncmp(p, "noaperture", 10))
905 /* duplicated from pci-dma.c */
906 if (!strncmp(p, "force", 5))
907 gart_iommu_aperture_allowed = 1;
908 if (!strncmp(p, "allowed", 7))
909 gart_iommu_aperture_allowed = 1;
910 if (!strncmp(p, "memaper", 7)) {
911 fallback_aper_force = 1;
915 if (get_option(&p, &arg))
916 fallback_aper_order = arg;