2 * AMD CPU Microcode Update Driver for Linux
3 * Copyright (C) 2008 Advanced Micro Devices Inc.
5 * Author: Peter Oruba <peter.oruba@amd.com>
8 * Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
10 * This driver allows to upgrade microcode on AMD
11 * family 0x10 and 0x11 processors.
13 * Licensed under the terms of the GNU General Public
14 * License version 2. See file COPYING for details.
16 #include <linux/firmware.h>
17 #include <linux/pci_ids.h>
18 #include <linux/uaccess.h>
19 #include <linux/vmalloc.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
24 #include <asm/microcode.h>
25 #include <asm/processor.h>
28 MODULE_DESCRIPTION("AMD Microcode Update Driver");
29 MODULE_AUTHOR("Peter Oruba");
30 MODULE_LICENSE("GPL v2");
32 #define UCODE_MAGIC 0x00414d44
33 #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
34 #define UCODE_UCODE_TYPE 0x00000001
36 const struct firmware *firmware;
37 static int supported_cpu;
39 struct equiv_cpu_entry {
41 u32 fixed_errata_mask;
42 u32 fixed_errata_compare;
45 } __attribute__((packed));
47 struct microcode_header_amd {
53 u32 mc_patch_data_checksum;
62 } __attribute__((packed));
64 struct microcode_amd {
65 struct microcode_header_amd hdr;
69 #define UCODE_MAX_SIZE 2048
70 #define UCODE_CONTAINER_SECTION_HDR 8
71 #define UCODE_CONTAINER_HEADER_SIZE 12
73 static struct equiv_cpu_entry *equiv_cpu_table;
75 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
82 memset(csig, 0, sizeof(*csig));
83 rdmsr(MSR_AMD64_PATCH_LEVEL, csig->rev, dummy);
84 pr_info("microcode: CPU%d: patch_level=0x%x\n", cpu, csig->rev);
88 static int get_matching_microcode(int cpu, void *mc, int rev)
90 struct microcode_header_amd *mc_header = mc;
91 unsigned int current_cpu_id;
95 BUG_ON(equiv_cpu_table == NULL);
96 current_cpu_id = cpuid_eax(0x00000001);
98 while (equiv_cpu_table[i].installed_cpu != 0) {
99 if (current_cpu_id == equiv_cpu_table[i].installed_cpu) {
100 equiv_cpu_id = equiv_cpu_table[i].equiv_cpu;
109 if (mc_header->processor_rev_id != equiv_cpu_id)
112 /* ucode might be chipset specific -- currently we don't support this */
113 if (mc_header->nb_dev_id || mc_header->sb_dev_id) {
114 pr_err(KERN_ERR "microcode: CPU%d: loading of chipset "
115 "specific code not yet supported\n", cpu);
119 if (mc_header->patch_id <= rev)
125 static int apply_microcode_amd(int cpu)
128 int cpu_num = raw_smp_processor_id();
129 struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
130 struct microcode_amd *mc_amd = uci->mc;
132 /* We should bind the task to the CPU */
133 BUG_ON(cpu_num != cpu);
138 wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
139 /* get patch id after patching */
140 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
142 /* check current patch id and patch's id for match */
143 if (rev != mc_amd->hdr.patch_id) {
144 pr_err("microcode: CPU%d: update failed "
145 "(for patch_level=0x%x)\n", cpu, mc_amd->hdr.patch_id);
149 pr_info("microcode: CPU%d: updated (new patch_level=0x%x)\n", cpu, rev);
150 uci->cpu_sig.rev = rev;
155 static int get_ucode_data(void *to, const u8 *from, size_t n)
162 get_next_ucode(const u8 *buf, unsigned int size, unsigned int *mc_size)
164 unsigned int total_size;
165 u8 section_hdr[UCODE_CONTAINER_SECTION_HDR];
168 if (get_ucode_data(section_hdr, buf, UCODE_CONTAINER_SECTION_HDR))
171 if (section_hdr[0] != UCODE_UCODE_TYPE) {
172 pr_err("microcode: error: invalid type field in "
173 "container file section header\n");
177 total_size = (unsigned long) (section_hdr[4] + (section_hdr[5] << 8));
179 if (total_size > size || total_size > UCODE_MAX_SIZE) {
180 pr_err("microcode: error: size mismatch\n");
184 mc = vmalloc(UCODE_MAX_SIZE);
186 memset(mc, 0, UCODE_MAX_SIZE);
187 if (get_ucode_data(mc, buf + UCODE_CONTAINER_SECTION_HDR,
192 *mc_size = total_size + UCODE_CONTAINER_SECTION_HDR;
197 static int install_equiv_cpu_table(const u8 *buf)
199 u8 *container_hdr[UCODE_CONTAINER_HEADER_SIZE];
200 unsigned int *buf_pos = (unsigned int *)container_hdr;
203 if (get_ucode_data(&container_hdr, buf, UCODE_CONTAINER_HEADER_SIZE))
208 if (buf_pos[1] != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
209 pr_err("microcode: error: invalid type field in "
210 "container file section header\n");
214 equiv_cpu_table = (struct equiv_cpu_entry *) vmalloc(size);
215 if (!equiv_cpu_table) {
216 pr_err("microcode: failed to allocate equivalent CPU table\n");
220 buf += UCODE_CONTAINER_HEADER_SIZE;
221 if (get_ucode_data(equiv_cpu_table, buf, size)) {
222 vfree(equiv_cpu_table);
226 return size + UCODE_CONTAINER_HEADER_SIZE; /* add header length */
229 static void free_equiv_cpu_table(void)
231 vfree(equiv_cpu_table);
232 equiv_cpu_table = NULL;
235 static enum ucode_state
236 generic_load_microcode(int cpu, const u8 *data, size_t size)
238 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
239 const u8 *ucode_ptr = data;
242 int new_rev = uci->cpu_sig.rev;
243 unsigned int leftover;
244 unsigned long offset;
245 enum ucode_state state = UCODE_OK;
247 offset = install_equiv_cpu_table(ucode_ptr);
249 pr_err("microcode: failed to create equivalent cpu table\n");
254 leftover = size - offset;
257 unsigned int uninitialized_var(mc_size);
258 struct microcode_header_amd *mc_header;
260 mc = get_next_ucode(ucode_ptr, leftover, &mc_size);
264 mc_header = (struct microcode_header_amd *)mc;
265 if (get_matching_microcode(cpu, mc, new_rev)) {
267 new_rev = mc_header->patch_id;
272 ucode_ptr += mc_size;
280 pr_debug("microcode: CPU%d found a matching microcode "
281 "update with version 0x%x (current=0x%x)\n",
282 cpu, new_rev, uci->cpu_sig.rev);
288 state = UCODE_NFOUND;
290 free_equiv_cpu_table();
295 static enum ucode_state request_microcode_fw(int cpu, struct device *device)
297 enum ucode_state ret;
299 if (firmware == NULL)
302 if (*(u32 *)firmware->data != UCODE_MAGIC) {
303 pr_err("microcode: invalid UCODE_MAGIC (0x%08x)\n",
304 *(u32 *)firmware->data);
308 ret = generic_load_microcode(cpu, firmware->data, firmware->size);
313 static enum ucode_state
314 request_microcode_user(int cpu, const void __user *buf, size_t size)
316 pr_info("microcode: AMD microcode update via "
317 "/dev/cpu/microcode not supported\n");
321 static void microcode_fini_cpu_amd(int cpu)
323 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
329 void init_microcode_amd(struct device *device)
331 const char *fw_name = "amd-ucode/microcode_amd.bin";
332 struct cpuinfo_x86 *c = &boot_cpu_data;
334 WARN_ON(c->x86_vendor != X86_VENDOR_AMD);
337 pr_warning("microcode: AMD CPU family 0x%x not supported\n",
343 if (request_firmware(&firmware, fw_name, device))
344 pr_err("microcode: failed to load file %s\n", fw_name);
347 void fini_microcode_amd(void)
349 release_firmware(firmware);
352 static struct microcode_ops microcode_amd_ops = {
353 .init = init_microcode_amd,
354 .fini = fini_microcode_amd,
355 .request_microcode_user = request_microcode_user,
356 .request_microcode_fw = request_microcode_fw,
357 .collect_cpu_info = collect_cpu_info_amd,
358 .apply_microcode = apply_microcode_amd,
359 .microcode_fini_cpu = microcode_fini_cpu_amd,
362 struct microcode_ops * __init init_amd_microcode(void)
364 return µcode_amd_ops;