2 * AMD CPU Microcode Update Driver for Linux
3 * Copyright (C) 2008-2011 Advanced Micro Devices Inc.
5 * Author: Peter Oruba <peter.oruba@amd.com>
8 * Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
11 * Andreas Herrmann <andreas.herrmann3@amd.com>
12 * Borislav Petkov <borislav.petkov@amd.com>
14 * This driver allows to upgrade microcode on F10h AMD
17 * Licensed under the terms of the GNU General Public
18 * License version 2. See file COPYING for details.
21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23 #include <linux/firmware.h>
24 #include <linux/pci_ids.h>
25 #include <linux/uaccess.h>
26 #include <linux/vmalloc.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
31 #include <asm/microcode.h>
32 #include <asm/processor.h>
35 MODULE_DESCRIPTION("AMD Microcode Update Driver");
36 MODULE_AUTHOR("Peter Oruba");
37 MODULE_LICENSE("GPL v2");
39 #define UCODE_MAGIC 0x00414d44
40 #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
41 #define UCODE_UCODE_TYPE 0x00000001
43 struct equiv_cpu_entry {
45 u32 fixed_errata_mask;
46 u32 fixed_errata_compare;
49 } __attribute__((packed));
51 struct microcode_header_amd {
57 u32 mc_patch_data_checksum;
66 } __attribute__((packed));
68 struct microcode_amd {
69 struct microcode_header_amd hdr;
73 #define SECTION_HDR_SIZE 8
74 #define CONTAINER_HDR_SZ 12
76 static struct equiv_cpu_entry *equiv_cpu_table;
79 struct list_head plist;
85 static LIST_HEAD(pcache);
87 static u16 find_equiv_id(unsigned int cpu)
89 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
95 while (equiv_cpu_table[i].installed_cpu != 0) {
96 if (uci->cpu_sig.sig == equiv_cpu_table[i].installed_cpu)
97 return equiv_cpu_table[i].equiv_cpu;
104 static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
108 BUG_ON(!equiv_cpu_table);
110 while (equiv_cpu_table[i].equiv_cpu != 0) {
111 if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
112 return equiv_cpu_table[i].installed_cpu;
119 * a small, trivial cache of per-family ucode patches
121 static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
123 struct ucode_patch *p;
125 list_for_each_entry(p, &pcache, plist)
126 if (p->equiv_cpu == equiv_cpu)
131 static void update_cache(struct ucode_patch *new_patch)
133 struct ucode_patch *p;
135 list_for_each_entry(p, &pcache, plist) {
136 if (p->equiv_cpu == new_patch->equiv_cpu) {
137 if (p->patch_id >= new_patch->patch_id)
138 /* we already have the latest patch */
141 list_replace(&p->plist, &new_patch->plist);
147 /* no patch found, add it */
148 list_add_tail(&new_patch->plist, &pcache);
151 static void free_cache(void)
153 struct ucode_patch *p, *tmp;
155 list_for_each_entry_safe(p, tmp, &pcache, plist) {
156 __list_del(p->plist.prev, p->plist.next);
162 static struct ucode_patch *find_patch(unsigned int cpu)
166 equiv_id = find_equiv_id(cpu);
170 return cache_find_patch(equiv_id);
173 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
175 struct cpuinfo_x86 *c = &cpu_data(cpu);
177 csig->sig = cpuid_eax(0x00000001);
178 csig->rev = c->microcode;
179 pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
184 static unsigned int verify_patch_size(int cpu, u32 patch_size,
187 struct cpuinfo_x86 *c = &cpu_data(cpu);
190 #define F1XH_MPB_MAX_SIZE 2048
191 #define F14H_MPB_MAX_SIZE 1824
192 #define F15H_MPB_MAX_SIZE 4096
196 max_size = F14H_MPB_MAX_SIZE;
199 max_size = F15H_MPB_MAX_SIZE;
202 max_size = F1XH_MPB_MAX_SIZE;
206 if (patch_size > min_t(u32, size, max_size)) {
207 pr_err("patch size mismatch\n");
214 static int apply_microcode_amd(int cpu)
216 struct cpuinfo_x86 *c = &cpu_data(cpu);
217 struct microcode_amd *mc_amd;
218 struct ucode_cpu_info *uci;
219 struct ucode_patch *p;
222 BUG_ON(raw_smp_processor_id() != cpu);
224 uci = ucode_cpu_info + cpu;
233 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
235 /* need to apply patch? */
236 if (rev >= mc_amd->hdr.patch_id) {
241 wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
243 /* verify patch application was successful */
244 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
245 if (rev != mc_amd->hdr.patch_id) {
246 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
247 cpu, mc_amd->hdr.patch_id);
251 pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
252 uci->cpu_sig.rev = rev;
258 static int install_equiv_cpu_table(const u8 *buf)
260 unsigned int *ibuf = (unsigned int *)buf;
261 unsigned int type = ibuf[1];
262 unsigned int size = ibuf[2];
264 if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
265 pr_err("empty section/"
266 "invalid type field in container file section header\n");
270 equiv_cpu_table = vmalloc(size);
271 if (!equiv_cpu_table) {
272 pr_err("failed to allocate equivalent CPU table\n");
276 memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
278 /* add header length */
279 return size + CONTAINER_HDR_SZ;
282 static void free_equiv_cpu_table(void)
284 vfree(equiv_cpu_table);
285 equiv_cpu_table = NULL;
288 static void cleanup(void)
290 free_equiv_cpu_table();
295 * We return the current size even if some of the checks failed so that
296 * we can skip over the next patch. If we return a negative value, we
297 * signal a grave error like a memory allocation has failed and the
298 * driver cannot continue functioning normally. In such cases, we tear
299 * down everything we've used up so far and exit.
301 static int verify_and_add_patch(unsigned int cpu, u8 *fw, unsigned int leftover)
303 struct cpuinfo_x86 *c = &cpu_data(cpu);
304 struct microcode_header_amd *mc_hdr;
305 struct ucode_patch *patch;
306 unsigned int patch_size, crnt_size, ret;
310 patch_size = *(u32 *)(fw + 4);
311 crnt_size = patch_size + SECTION_HDR_SIZE;
312 mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
313 proc_id = mc_hdr->processor_rev_id;
315 proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
317 pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
321 /* check if patch is for the current family */
322 proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
323 if (proc_fam != c->x86)
326 if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
327 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
332 ret = verify_patch_size(cpu, patch_size, leftover);
334 pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
338 patch = kzalloc(sizeof(*patch), GFP_KERNEL);
340 pr_err("Patch allocation failure.\n");
344 patch->data = kzalloc(patch_size, GFP_KERNEL);
346 pr_err("Patch data allocation failure.\n");
351 /* All looks ok, copy patch... */
352 memcpy(patch->data, fw + SECTION_HDR_SIZE, patch_size);
353 INIT_LIST_HEAD(&patch->plist);
354 patch->patch_id = mc_hdr->patch_id;
355 patch->equiv_cpu = proc_id;
357 /* ... and add to cache. */
363 static enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size)
365 enum ucode_state ret = UCODE_ERROR;
366 unsigned int leftover;
371 offset = install_equiv_cpu_table(data);
373 pr_err("failed to create equivalent cpu table\n");
377 leftover = size - offset;
379 if (*(u32 *)fw != UCODE_UCODE_TYPE) {
380 pr_err("invalid type field in container file section header\n");
381 free_equiv_cpu_table();
386 crnt_size = verify_and_add_patch(cpu, fw, leftover);
391 leftover -= crnt_size;
398 * AMD microcode firmware naming convention, up to family 15h they are in
401 * amd-ucode/microcode_amd.bin
403 * This legacy file is always smaller than 2K in size.
405 * Beginning with family 15h, they are in family-specific firmware files:
407 * amd-ucode/microcode_amd_fam15h.bin
408 * amd-ucode/microcode_amd_fam16h.bin
411 * These might be larger than 2K.
413 static enum ucode_state request_microcode_amd(int cpu, struct device *device,
416 char fw_name[36] = "amd-ucode/microcode_amd.bin";
417 struct cpuinfo_x86 *c = &cpu_data(cpu);
418 enum ucode_state ret = UCODE_NFOUND;
419 const struct firmware *fw;
421 /* reload ucode container only on the boot cpu */
422 if (!refresh_fw || c->cpu_index != boot_cpu_data.cpu_index)
426 snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
428 if (request_firmware(&fw, (const char *)fw_name, device)) {
429 pr_err("failed to load file %s\n", fw_name);
434 if (*(u32 *)fw->data != UCODE_MAGIC) {
435 pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
439 /* free old equiv table */
440 free_equiv_cpu_table();
442 ret = load_microcode_amd(cpu, fw->data, fw->size);
447 release_firmware(fw);
453 static enum ucode_state
454 request_microcode_user(int cpu, const void __user *buf, size_t size)
459 static void microcode_fini_cpu_amd(int cpu)
461 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
466 static struct microcode_ops microcode_amd_ops = {
467 .request_microcode_user = request_microcode_user,
468 .request_microcode_fw = request_microcode_amd,
469 .collect_cpu_info = collect_cpu_info_amd,
470 .apply_microcode = apply_microcode_amd,
471 .microcode_fini_cpu = microcode_fini_cpu_amd,
474 struct microcode_ops * __init init_amd_microcode(void)
476 struct cpuinfo_x86 *c = &cpu_data(0);
478 if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
479 pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
483 return µcode_amd_ops;
486 void __exit exit_amd_microcode(void)