2 * Common interrupt code for 32 and 64 bit
5 #include <linux/interrupt.h>
6 #include <linux/kernel_stat.h>
8 #include <linux/seq_file.h>
10 #include <linux/ftrace.h>
11 #include <linux/delay.h>
14 #include <asm/io_apic.h>
18 #include <asm/hw_irq.h>
20 atomic_t irq_err_count;
22 /* Function pointer for generic interrupt vector handling */
23 void (*x86_platform_ipi_callback)(void) = NULL;
26 * 'what should we do if we get a hw irq event on an illegal vector'.
27 * each architecture has to answer this themselves.
29 void ack_bad_irq(unsigned int irq)
31 if (printk_ratelimit())
32 pr_err("unexpected IRQ trap at vector %02x\n", irq);
35 * Currently unexpected vectors happen only on SMP and APIC.
36 * We _must_ ack these because every local APIC has only N
37 * irq slots per priority level, and a 'hanging, unacked' IRQ
38 * holds up an irq slot - in excessive cases (when multiple
39 * unexpected vectors occur) that might lock up the APIC
41 * But only ack when the APIC is enabled -AK
46 #define irq_stats(x) (&per_cpu(irq_stat, x))
48 * /proc/interrupts printing for arch specific interrupts
50 int arch_show_interrupts(struct seq_file *p, int prec)
54 seq_printf(p, "%*s: ", prec, "NMI");
55 for_each_online_cpu(j)
56 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
57 seq_printf(p, " Non-maskable interrupts\n");
58 #ifdef CONFIG_X86_LOCAL_APIC
59 seq_printf(p, "%*s: ", prec, "LOC");
60 for_each_online_cpu(j)
61 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
62 seq_printf(p, " Local timer interrupts\n");
64 seq_printf(p, "%*s: ", prec, "SPU");
65 for_each_online_cpu(j)
66 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
67 seq_printf(p, " Spurious interrupts\n");
68 seq_printf(p, "%*s: ", prec, "PMI");
69 for_each_online_cpu(j)
70 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
71 seq_printf(p, " Performance monitoring interrupts\n");
72 seq_printf(p, "%*s: ", prec, "IWI");
73 for_each_online_cpu(j)
74 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
75 seq_printf(p, " IRQ work interrupts\n");
77 if (x86_platform_ipi_callback) {
78 seq_printf(p, "%*s: ", prec, "PLT");
79 for_each_online_cpu(j)
80 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
81 seq_printf(p, " Platform interrupts\n");
84 seq_printf(p, "%*s: ", prec, "RES");
85 for_each_online_cpu(j)
86 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
87 seq_printf(p, " Rescheduling interrupts\n");
88 seq_printf(p, "%*s: ", prec, "CAL");
89 for_each_online_cpu(j)
90 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
91 seq_printf(p, " Function call interrupts\n");
92 seq_printf(p, "%*s: ", prec, "TLB");
93 for_each_online_cpu(j)
94 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
95 seq_printf(p, " TLB shootdowns\n");
97 #ifdef CONFIG_X86_THERMAL_VECTOR
98 seq_printf(p, "%*s: ", prec, "TRM");
99 for_each_online_cpu(j)
100 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
101 seq_printf(p, " Thermal event interrupts\n");
103 #ifdef CONFIG_X86_MCE_THRESHOLD
104 seq_printf(p, "%*s: ", prec, "THR");
105 for_each_online_cpu(j)
106 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
107 seq_printf(p, " Threshold APIC interrupts\n");
109 #ifdef CONFIG_X86_MCE
110 seq_printf(p, "%*s: ", prec, "MCE");
111 for_each_online_cpu(j)
112 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
113 seq_printf(p, " Machine check exceptions\n");
114 seq_printf(p, "%*s: ", prec, "MCP");
115 for_each_online_cpu(j)
116 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
117 seq_printf(p, " Machine check polls\n");
119 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
120 #if defined(CONFIG_X86_IO_APIC)
121 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
129 u64 arch_irq_stat_cpu(unsigned int cpu)
131 u64 sum = irq_stats(cpu)->__nmi_count;
133 #ifdef CONFIG_X86_LOCAL_APIC
134 sum += irq_stats(cpu)->apic_timer_irqs;
135 sum += irq_stats(cpu)->irq_spurious_count;
136 sum += irq_stats(cpu)->apic_perf_irqs;
137 sum += irq_stats(cpu)->apic_irq_work_irqs;
139 if (x86_platform_ipi_callback)
140 sum += irq_stats(cpu)->x86_platform_ipis;
142 sum += irq_stats(cpu)->irq_resched_count;
143 sum += irq_stats(cpu)->irq_call_count;
144 sum += irq_stats(cpu)->irq_tlb_count;
146 #ifdef CONFIG_X86_THERMAL_VECTOR
147 sum += irq_stats(cpu)->irq_thermal_count;
149 #ifdef CONFIG_X86_MCE_THRESHOLD
150 sum += irq_stats(cpu)->irq_threshold_count;
152 #ifdef CONFIG_X86_MCE
153 sum += per_cpu(mce_exception_count, cpu);
154 sum += per_cpu(mce_poll_count, cpu);
159 u64 arch_irq_stat(void)
161 u64 sum = atomic_read(&irq_err_count);
163 #ifdef CONFIG_X86_IO_APIC
164 sum += atomic_read(&irq_mis_count);
171 * do_IRQ handles all normal device IRQ's (the special
172 * SMP cross-CPU interrupts have their own specific
175 unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
177 struct pt_regs *old_regs = set_irq_regs(regs);
179 /* high bit used in ret_from_ code */
180 unsigned vector = ~regs->orig_ax;
186 irq = __this_cpu_read(vector_irq[vector]);
188 if (!handle_irq(irq, regs)) {
191 if (printk_ratelimit())
192 pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n",
193 __func__, smp_processor_id(), vector, irq);
198 set_irq_regs(old_regs);
203 * Handler for X86_PLATFORM_IPI_VECTOR.
205 void smp_x86_platform_ipi(struct pt_regs *regs)
207 struct pt_regs *old_regs = set_irq_regs(regs);
215 inc_irq_stat(x86_platform_ipis);
217 if (x86_platform_ipi_callback)
218 x86_platform_ipi_callback();
222 set_irq_regs(old_regs);
225 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
227 #ifdef CONFIG_HOTPLUG_CPU
228 /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
229 void fixup_irqs(void)
231 unsigned int irq, vector;
233 struct irq_desc *desc;
234 struct irq_data *data;
235 struct irq_chip *chip;
237 for_each_irq_desc(irq, desc) {
238 int break_affinity = 0;
239 int set_affinity = 1;
240 const struct cpumask *affinity;
247 /* interrupt's are disabled at this point */
248 raw_spin_lock(&desc->lock);
250 data = irq_desc_get_irq_data(desc);
251 affinity = data->affinity;
252 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
253 cpumask_subset(affinity, cpu_online_mask)) {
254 raw_spin_unlock(&desc->lock);
259 * Complete the irq move. This cpu is going down and for
260 * non intr-remapping case, we can't wait till this interrupt
261 * arrives at this cpu before completing the irq move.
263 irq_force_complete_move(irq);
265 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
267 affinity = cpu_all_mask;
270 chip = irq_data_get_irq_chip(data);
271 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
272 chip->irq_mask(data);
274 if (chip->irq_set_affinity)
275 chip->irq_set_affinity(data, affinity, true);
276 else if (!(warned++))
279 if (!irqd_can_move_in_process_context(data) && chip->irq_unmask)
280 chip->irq_unmask(data);
282 raw_spin_unlock(&desc->lock);
284 if (break_affinity && set_affinity)
285 printk("Broke affinity for irq %i\n", irq);
286 else if (!set_affinity)
287 printk("Cannot set affinity for irq %i\n", irq);
291 * We can remove mdelay() and then send spuriuous interrupts to
292 * new cpu targets for all the irqs that were handled previously by
293 * this cpu. While it works, I have seen spurious interrupt messages
294 * (nothing wrong but still...).
296 * So for now, retain mdelay(1) and check the IRR and then send those
297 * interrupts to new targets as this cpu is already offlined...
301 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
304 if (__this_cpu_read(vector_irq[vector]) < 0)
307 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
308 if (irr & (1 << (vector % 32))) {
309 irq = __this_cpu_read(vector_irq[vector]);
311 desc = irq_to_desc(irq);
312 data = irq_desc_get_irq_data(desc);
313 chip = irq_data_get_irq_chip(data);
314 raw_spin_lock(&desc->lock);
315 if (chip->irq_retrigger)
316 chip->irq_retrigger(data);
317 raw_spin_unlock(&desc->lock);