2 * Common interrupt code for 32 and 64 bit
5 #include <linux/interrupt.h>
6 #include <linux/kernel_stat.h>
8 #include <linux/seq_file.h>
10 #include <linux/ftrace.h>
11 #include <linux/delay.h>
12 #include <linux/export.h>
15 #include <asm/io_apic.h>
18 #include <asm/hw_irq.h>
21 #define CREATE_TRACE_POINTS
22 #include <asm/trace/irq_vectors.h>
24 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
25 EXPORT_PER_CPU_SYMBOL(irq_stat);
27 DEFINE_PER_CPU(struct pt_regs *, irq_regs);
28 EXPORT_PER_CPU_SYMBOL(irq_regs);
30 atomic_t irq_err_count;
33 * 'what should we do if we get a hw irq event on an illegal vector'.
34 * each architecture has to answer this themselves.
36 void ack_bad_irq(unsigned int irq)
38 if (printk_ratelimit())
39 pr_err("unexpected IRQ trap at vector %02x\n", irq);
42 * Currently unexpected vectors happen only on SMP and APIC.
43 * We _must_ ack these because every local APIC has only N
44 * irq slots per priority level, and a 'hanging, unacked' IRQ
45 * holds up an irq slot - in excessive cases (when multiple
46 * unexpected vectors occur) that might lock up the APIC
48 * But only ack when the APIC is enabled -AK
53 #define irq_stats(x) (&per_cpu(irq_stat, x))
55 * /proc/interrupts printing for arch specific interrupts
57 int arch_show_interrupts(struct seq_file *p, int prec)
61 seq_printf(p, "%*s: ", prec, "NMI");
62 for_each_online_cpu(j)
63 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
64 seq_puts(p, " Non-maskable interrupts\n");
65 #ifdef CONFIG_X86_LOCAL_APIC
66 seq_printf(p, "%*s: ", prec, "LOC");
67 for_each_online_cpu(j)
68 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
69 seq_puts(p, " Local timer interrupts\n");
71 seq_printf(p, "%*s: ", prec, "SPU");
72 for_each_online_cpu(j)
73 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
74 seq_puts(p, " Spurious interrupts\n");
75 seq_printf(p, "%*s: ", prec, "PMI");
76 for_each_online_cpu(j)
77 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
78 seq_puts(p, " Performance monitoring interrupts\n");
79 seq_printf(p, "%*s: ", prec, "IWI");
80 for_each_online_cpu(j)
81 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
82 seq_puts(p, " IRQ work interrupts\n");
83 seq_printf(p, "%*s: ", prec, "RTR");
84 for_each_online_cpu(j)
85 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
86 seq_puts(p, " APIC ICR read retries\n");
87 if (x86_platform_ipi_callback) {
88 seq_printf(p, "%*s: ", prec, "PLT");
89 for_each_online_cpu(j)
90 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
91 seq_puts(p, " Platform interrupts\n");
95 seq_printf(p, "%*s: ", prec, "RES");
96 for_each_online_cpu(j)
97 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
98 seq_puts(p, " Rescheduling interrupts\n");
99 seq_printf(p, "%*s: ", prec, "CAL");
100 for_each_online_cpu(j)
101 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
102 seq_puts(p, " Function call interrupts\n");
103 seq_printf(p, "%*s: ", prec, "TLB");
104 for_each_online_cpu(j)
105 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
106 seq_puts(p, " TLB shootdowns\n");
108 #ifdef CONFIG_X86_THERMAL_VECTOR
109 seq_printf(p, "%*s: ", prec, "TRM");
110 for_each_online_cpu(j)
111 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
112 seq_puts(p, " Thermal event interrupts\n");
114 #ifdef CONFIG_X86_MCE_THRESHOLD
115 seq_printf(p, "%*s: ", prec, "THR");
116 for_each_online_cpu(j)
117 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
118 seq_puts(p, " Threshold APIC interrupts\n");
120 #ifdef CONFIG_X86_MCE_AMD
121 seq_printf(p, "%*s: ", prec, "DFR");
122 for_each_online_cpu(j)
123 seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
124 seq_puts(p, " Deferred Error APIC interrupts\n");
126 #ifdef CONFIG_X86_MCE
127 seq_printf(p, "%*s: ", prec, "MCE");
128 for_each_online_cpu(j)
129 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
130 seq_puts(p, " Machine check exceptions\n");
131 seq_printf(p, "%*s: ", prec, "MCP");
132 for_each_online_cpu(j)
133 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
134 seq_puts(p, " Machine check polls\n");
136 #if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
137 if (test_bit(HYPERVISOR_CALLBACK_VECTOR, system_vectors)) {
138 seq_printf(p, "%*s: ", prec, "HYP");
139 for_each_online_cpu(j)
140 seq_printf(p, "%10u ",
141 irq_stats(j)->irq_hv_callback_count);
142 seq_puts(p, " Hypervisor callback interrupts\n");
145 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
146 #if defined(CONFIG_X86_IO_APIC)
147 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
149 #ifdef CONFIG_HAVE_KVM
150 seq_printf(p, "%*s: ", prec, "PIN");
151 for_each_online_cpu(j)
152 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
153 seq_puts(p, " Posted-interrupt notification event\n");
155 seq_printf(p, "%*s: ", prec, "NPI");
156 for_each_online_cpu(j)
157 seq_printf(p, "%10u ",
158 irq_stats(j)->kvm_posted_intr_nested_ipis);
159 seq_puts(p, " Nested posted-interrupt event\n");
161 seq_printf(p, "%*s: ", prec, "PIW");
162 for_each_online_cpu(j)
163 seq_printf(p, "%10u ",
164 irq_stats(j)->kvm_posted_intr_wakeup_ipis);
165 seq_puts(p, " Posted-interrupt wakeup event\n");
173 u64 arch_irq_stat_cpu(unsigned int cpu)
175 u64 sum = irq_stats(cpu)->__nmi_count;
177 #ifdef CONFIG_X86_LOCAL_APIC
178 sum += irq_stats(cpu)->apic_timer_irqs;
179 sum += irq_stats(cpu)->irq_spurious_count;
180 sum += irq_stats(cpu)->apic_perf_irqs;
181 sum += irq_stats(cpu)->apic_irq_work_irqs;
182 sum += irq_stats(cpu)->icr_read_retry_count;
183 if (x86_platform_ipi_callback)
184 sum += irq_stats(cpu)->x86_platform_ipis;
187 sum += irq_stats(cpu)->irq_resched_count;
188 sum += irq_stats(cpu)->irq_call_count;
190 #ifdef CONFIG_X86_THERMAL_VECTOR
191 sum += irq_stats(cpu)->irq_thermal_count;
193 #ifdef CONFIG_X86_MCE_THRESHOLD
194 sum += irq_stats(cpu)->irq_threshold_count;
196 #ifdef CONFIG_X86_MCE
197 sum += per_cpu(mce_exception_count, cpu);
198 sum += per_cpu(mce_poll_count, cpu);
203 u64 arch_irq_stat(void)
205 u64 sum = atomic_read(&irq_err_count);
211 * do_IRQ handles all normal device IRQ's (the special
212 * SMP cross-CPU interrupts have their own specific
215 __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
217 struct pt_regs *old_regs = set_irq_regs(regs);
218 struct irq_desc * desc;
219 /* high bit used in ret_from_ code */
220 unsigned vector = ~regs->orig_ax;
224 /* entering_irq() tells RCU that we're not quiescent. Check it. */
225 RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
227 desc = __this_cpu_read(vector_irq[vector]);
229 if (!handle_irq(desc, regs)) {
232 if (desc != VECTOR_RETRIGGERED) {
233 pr_emerg_ratelimited("%s: %d.%d No irq handler for vector\n",
234 __func__, smp_processor_id(),
237 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
243 set_irq_regs(old_regs);
247 #ifdef CONFIG_X86_LOCAL_APIC
248 /* Function pointer for generic interrupt vector handling */
249 void (*x86_platform_ipi_callback)(void) = NULL;
251 * Handler for X86_PLATFORM_IPI_VECTOR.
253 __visible void __irq_entry smp_x86_platform_ipi(struct pt_regs *regs)
255 struct pt_regs *old_regs = set_irq_regs(regs);
258 trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
259 inc_irq_stat(x86_platform_ipis);
260 if (x86_platform_ipi_callback)
261 x86_platform_ipi_callback();
262 trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
264 set_irq_regs(old_regs);
268 #ifdef CONFIG_HAVE_KVM
269 static void dummy_handler(void) {}
270 static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
272 void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
275 kvm_posted_intr_wakeup_handler = handler;
277 kvm_posted_intr_wakeup_handler = dummy_handler;
279 EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
282 * Handler for POSTED_INTERRUPT_VECTOR.
284 __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
286 struct pt_regs *old_regs = set_irq_regs(regs);
289 inc_irq_stat(kvm_posted_intr_ipis);
291 set_irq_regs(old_regs);
295 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
297 __visible void smp_kvm_posted_intr_wakeup_ipi(struct pt_regs *regs)
299 struct pt_regs *old_regs = set_irq_regs(regs);
302 inc_irq_stat(kvm_posted_intr_wakeup_ipis);
303 kvm_posted_intr_wakeup_handler();
305 set_irq_regs(old_regs);
309 * Handler for POSTED_INTERRUPT_NESTED_VECTOR.
311 __visible void smp_kvm_posted_intr_nested_ipi(struct pt_regs *regs)
313 struct pt_regs *old_regs = set_irq_regs(regs);
316 inc_irq_stat(kvm_posted_intr_nested_ipis);
318 set_irq_regs(old_regs);
323 #ifdef CONFIG_HOTPLUG_CPU
324 /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
325 void fixup_irqs(void)
327 unsigned int irr, vector;
328 struct irq_desc *desc;
329 struct irq_data *data;
330 struct irq_chip *chip;
332 irq_migrate_all_off_this_cpu();
335 * We can remove mdelay() and then send spuriuous interrupts to
336 * new cpu targets for all the irqs that were handled previously by
337 * this cpu. While it works, I have seen spurious interrupt messages
338 * (nothing wrong but still...).
340 * So for now, retain mdelay(1) and check the IRR and then send those
341 * interrupts to new targets as this cpu is already offlined...
346 * We can walk the vector array of this cpu without holding
347 * vector_lock because the cpu is already marked !online, so
348 * nothing else will touch it.
350 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
351 if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
354 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
355 if (irr & (1 << (vector % 32))) {
356 desc = __this_cpu_read(vector_irq[vector]);
358 raw_spin_lock(&desc->lock);
359 data = irq_desc_get_irq_data(desc);
360 chip = irq_data_get_irq_chip(data);
361 if (chip->irq_retrigger) {
362 chip->irq_retrigger(data);
363 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
365 raw_spin_unlock(&desc->lock);
367 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
368 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);