2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/mc146818rtc.h>
29 #include <linux/compiler.h>
30 #include <linux/acpi.h>
31 #include <linux/module.h>
32 #include <linux/sysdev.h>
33 #include <linux/pci.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
43 #include <asm/timer.h>
44 #include <asm/i8259.h>
46 #include <asm/msidef.h>
47 #include <asm/hypertransport.h>
49 #include <mach_apic.h>
50 #include <mach_apicdef.h>
52 int (*ioapic_renumber_irq)(int ioapic, int irq);
53 atomic_t irq_mis_count;
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58 static DEFINE_SPINLOCK(ioapic_lock);
59 static DEFINE_SPINLOCK(vector_lock);
61 int timer_through_8259 __initdata;
64 * Is the SiS APIC rmw bug present ?
65 * -1 = don't know, 0 = no, 1 = yes
67 int sis_apic_bug = -1;
70 * # of IRQ routing registers
72 int nr_ioapic_registers[MAX_IO_APICS];
74 /* I/O APIC entries */
75 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
78 /* MP IRQ source entries */
79 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
81 /* # of MP IRQ source entries */
84 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
85 int mp_bus_id_to_type[MAX_MP_BUSSES];
88 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
90 static int disable_timer_pin_1 __initdata;
93 * Rough estimation of how many shared IRQs there are, can
96 #define MAX_PLUS_SHARED_IRQS NR_IRQS
97 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
100 * This is performance-critical, we want to do it O(1)
102 * the indexing order of this array favors 1:1 mappings
103 * between pins and IRQs.
106 static struct irq_pin_list {
108 } irq_2_pin[PIN_MAP_SIZE];
112 unsigned int unused[3];
116 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
118 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
119 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
122 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
124 struct io_apic __iomem *io_apic = io_apic_base(apic);
125 writel(reg, &io_apic->index);
126 return readl(&io_apic->data);
129 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
131 struct io_apic __iomem *io_apic = io_apic_base(apic);
132 writel(reg, &io_apic->index);
133 writel(value, &io_apic->data);
137 * Re-write a value: to be used for read-modify-write
138 * cycles where the read already set up the index register.
140 * Older SiS APIC requires we rewrite the index register
142 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
144 volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
146 writel(reg, &io_apic->index);
147 writel(value, &io_apic->data);
151 struct { u32 w1, w2; };
152 struct IO_APIC_route_entry entry;
155 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
157 union entry_union eu;
159 spin_lock_irqsave(&ioapic_lock, flags);
160 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
161 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
162 spin_unlock_irqrestore(&ioapic_lock, flags);
167 * When we write a new IO APIC routing entry, we need to write the high
168 * word first! If the mask bit in the low word is clear, we will enable
169 * the interrupt, and we need to make sure the entry is fully populated
170 * before that happens.
173 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
175 union entry_union eu;
177 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
178 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
181 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
184 spin_lock_irqsave(&ioapic_lock, flags);
185 __ioapic_write_entry(apic, pin, e);
186 spin_unlock_irqrestore(&ioapic_lock, flags);
190 * When we mask an IO APIC routing entry, we need to write the low
191 * word first, in order to set the mask bit before we change the
194 static void ioapic_mask_entry(int apic, int pin)
197 union entry_union eu = { .entry.mask = 1 };
199 spin_lock_irqsave(&ioapic_lock, flags);
200 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
201 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
202 spin_unlock_irqrestore(&ioapic_lock, flags);
206 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
207 * shared ISA-space IRQs, so we have to support them. We are super
208 * fast in the common case, and fast for shared ISA-space IRQs.
210 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
212 static int first_free_entry = NR_IRQS;
213 struct irq_pin_list *entry = irq_2_pin + irq;
216 entry = irq_2_pin + entry->next;
218 if (entry->pin != -1) {
219 entry->next = first_free_entry;
220 entry = irq_2_pin + entry->next;
221 if (++first_free_entry >= PIN_MAP_SIZE)
222 panic("io_apic.c: whoops");
229 * Reroute an IRQ to a different pin.
231 static void __init replace_pin_at_irq(unsigned int irq,
232 int oldapic, int oldpin,
233 int newapic, int newpin)
235 struct irq_pin_list *entry = irq_2_pin + irq;
238 if (entry->apic == oldapic && entry->pin == oldpin) {
239 entry->apic = newapic;
244 entry = irq_2_pin + entry->next;
248 static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable)
250 struct irq_pin_list *entry = irq_2_pin + irq;
251 unsigned int pin, reg;
257 reg = io_apic_read(entry->apic, 0x10 + pin*2);
260 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
263 entry = irq_2_pin + entry->next;
268 static void __mask_IO_APIC_irq(unsigned int irq)
270 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
274 static void __unmask_IO_APIC_irq(unsigned int irq)
276 __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED);
279 /* mask = 1, trigger = 0 */
280 static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
282 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
283 IO_APIC_REDIR_LEVEL_TRIGGER);
286 /* mask = 0, trigger = 1 */
287 static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
289 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
290 IO_APIC_REDIR_MASKED);
293 static void mask_IO_APIC_irq(unsigned int irq)
297 spin_lock_irqsave(&ioapic_lock, flags);
298 __mask_IO_APIC_irq(irq);
299 spin_unlock_irqrestore(&ioapic_lock, flags);
302 static void unmask_IO_APIC_irq(unsigned int irq)
306 spin_lock_irqsave(&ioapic_lock, flags);
307 __unmask_IO_APIC_irq(irq);
308 spin_unlock_irqrestore(&ioapic_lock, flags);
311 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
313 struct IO_APIC_route_entry entry;
315 /* Check delivery_mode to be sure we're not clearing an SMI pin */
316 entry = ioapic_read_entry(apic, pin);
317 if (entry.delivery_mode == dest_SMI)
321 * Disable it in the IO-APIC irq-routing table:
323 ioapic_mask_entry(apic, pin);
326 static void clear_IO_APIC(void)
330 for (apic = 0; apic < nr_ioapics; apic++)
331 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
332 clear_IO_APIC_pin(apic, pin);
336 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
340 struct irq_pin_list *entry = irq_2_pin + irq;
341 unsigned int apicid_value;
344 cpus_and(tmp, cpumask, cpu_online_map);
348 cpus_and(cpumask, tmp, CPU_MASK_ALL);
350 apicid_value = cpu_mask_to_apicid(cpumask);
351 /* Prepare to do the io_apic_write */
352 apicid_value = apicid_value << 24;
353 spin_lock_irqsave(&ioapic_lock, flags);
358 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
361 entry = irq_2_pin + entry->next;
363 irq_desc[irq].affinity = cpumask;
364 spin_unlock_irqrestore(&ioapic_lock, flags);
367 #if defined(CONFIG_IRQBALANCE)
368 # include <asm/processor.h> /* kernel_thread() */
369 # include <linux/kernel_stat.h> /* kstat */
370 # include <linux/slab.h> /* kmalloc() */
371 # include <linux/timer.h>
373 #define IRQBALANCE_CHECK_ARCH -999
374 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
375 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
376 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
377 #define BALANCED_IRQ_LESS_DELTA (HZ)
379 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
380 static int physical_balance __read_mostly;
381 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
383 static struct irq_cpu_info {
384 unsigned long *last_irq;
385 unsigned long *irq_delta;
387 } irq_cpu_data[NR_CPUS];
389 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
390 #define LAST_CPU_IRQ(cpu, irq) (irq_cpu_data[cpu].last_irq[irq])
391 #define IRQ_DELTA(cpu, irq) (irq_cpu_data[cpu].irq_delta[irq])
393 #define IDLE_ENOUGH(cpu,now) \
394 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
396 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
398 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
400 static cpumask_t balance_irq_affinity[NR_IRQS] = {
401 [0 ... NR_IRQS-1] = CPU_MASK_ALL
404 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
406 balance_irq_affinity[irq] = mask;
409 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
410 unsigned long now, int direction)
418 if (unlikely(cpu == curr_cpu))
421 if (direction == 1) {
430 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu, allowed_mask) ||
431 (search_idle && !IDLE_ENOUGH(cpu, now)));
436 static inline void balance_irq(int cpu, int irq)
438 unsigned long now = jiffies;
439 cpumask_t allowed_mask;
440 unsigned int new_cpu;
442 if (irqbalance_disabled)
445 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
446 new_cpu = move(cpu, allowed_mask, now, 1);
448 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
451 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
455 for_each_online_cpu(i) {
456 for (j = 0; j < NR_IRQS; j++) {
457 if (!irq_desc[j].action)
459 /* Is it a significant load ? */
460 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i), j) <
461 useful_load_threshold)
466 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
467 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
471 static void do_irq_balance(void)
474 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
475 unsigned long move_this_load = 0;
476 int max_loaded = 0, min_loaded = 0;
478 unsigned long useful_load_threshold = balanced_irq_interval + 10;
480 int tmp_loaded, first_attempt = 1;
481 unsigned long tmp_cpu_irq;
482 unsigned long imbalance = 0;
483 cpumask_t allowed_mask, target_cpu_mask, tmp;
485 for_each_possible_cpu(i) {
490 package_index = CPU_TO_PACKAGEINDEX(i);
491 for (j = 0; j < NR_IRQS; j++) {
492 unsigned long value_now, delta;
493 /* Is this an active IRQ or balancing disabled ? */
494 if (!irq_desc[j].action || irq_balancing_disabled(j))
496 if (package_index == i)
497 IRQ_DELTA(package_index, j) = 0;
498 /* Determine the total count per processor per IRQ */
499 value_now = (unsigned long) kstat_cpu(i).irqs[j];
501 /* Determine the activity per processor per IRQ */
502 delta = value_now - LAST_CPU_IRQ(i, j);
504 /* Update last_cpu_irq[][] for the next time */
505 LAST_CPU_IRQ(i, j) = value_now;
507 /* Ignore IRQs whose rate is less than the clock */
508 if (delta < useful_load_threshold)
510 /* update the load for the processor or package total */
511 IRQ_DELTA(package_index, j) += delta;
513 /* Keep track of the higher numbered sibling as well */
514 if (i != package_index)
517 * We have sibling A and sibling B in the package
519 * cpu_irq[A] = load for cpu A + load for cpu B
520 * cpu_irq[B] = load for cpu B
522 CPU_IRQ(package_index) += delta;
525 /* Find the least loaded processor package */
526 for_each_online_cpu(i) {
527 if (i != CPU_TO_PACKAGEINDEX(i))
529 if (min_cpu_irq > CPU_IRQ(i)) {
530 min_cpu_irq = CPU_IRQ(i);
534 max_cpu_irq = ULONG_MAX;
538 * Look for heaviest loaded processor.
539 * We may come back to get the next heaviest loaded processor.
540 * Skip processors with trivial loads.
544 for_each_online_cpu(i) {
545 if (i != CPU_TO_PACKAGEINDEX(i))
547 if (max_cpu_irq <= CPU_IRQ(i))
549 if (tmp_cpu_irq < CPU_IRQ(i)) {
550 tmp_cpu_irq = CPU_IRQ(i);
555 if (tmp_loaded == -1) {
557 * In the case of small number of heavy interrupt sources,
558 * loading some of the cpus too much. We use Ingo's original
559 * approach to rotate them around.
561 if (!first_attempt && imbalance >= useful_load_threshold) {
562 rotate_irqs_among_cpus(useful_load_threshold);
565 goto not_worth_the_effort;
568 first_attempt = 0; /* heaviest search */
569 max_cpu_irq = tmp_cpu_irq; /* load */
570 max_loaded = tmp_loaded; /* processor */
571 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
574 * if imbalance is less than approx 10% of max load, then
575 * observe diminishing returns action. - quit
577 if (imbalance < (max_cpu_irq >> 3))
578 goto not_worth_the_effort;
581 /* if we select an IRQ to move that can't go where we want, then
582 * see if there is another one to try.
586 for (j = 0; j < NR_IRQS; j++) {
587 /* Is this an active IRQ? */
588 if (!irq_desc[j].action)
590 if (imbalance <= IRQ_DELTA(max_loaded, j))
592 /* Try to find the IRQ that is closest to the imbalance
593 * without going over.
595 if (move_this_load < IRQ_DELTA(max_loaded, j)) {
596 move_this_load = IRQ_DELTA(max_loaded, j);
600 if (selected_irq == -1)
603 imbalance = move_this_load;
605 /* For physical_balance case, we accumulated both load
606 * values in the one of the siblings cpu_irq[],
607 * to use the same code for physical and logical processors
608 * as much as possible.
610 * NOTE: the cpu_irq[] array holds the sum of the load for
611 * sibling A and sibling B in the slot for the lowest numbered
612 * sibling (A), _AND_ the load for sibling B in the slot for
613 * the higher numbered sibling.
615 * We seek the least loaded sibling by making the comparison
618 load = CPU_IRQ(min_loaded) >> 1;
619 for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
620 if (load > CPU_IRQ(j)) {
621 /* This won't change cpu_sibling_map[min_loaded] */
627 cpus_and(allowed_mask,
629 balance_irq_affinity[selected_irq]);
630 target_cpu_mask = cpumask_of_cpu(min_loaded);
631 cpus_and(tmp, target_cpu_mask, allowed_mask);
633 if (!cpus_empty(tmp)) {
634 /* mark for change destination */
635 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
637 /* Since we made a change, come back sooner to
638 * check for more variation.
640 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
641 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
646 not_worth_the_effort:
648 * if we did not find an IRQ to move, then adjust the time interval
651 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
652 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
656 static int balanced_irq(void *unused)
659 unsigned long prev_balance_time = jiffies;
660 long time_remaining = balanced_irq_interval;
662 /* push everything to CPU 0 to give us a starting point. */
663 for (i = 0 ; i < NR_IRQS ; i++) {
664 irq_desc[i].pending_mask = cpumask_of_cpu(0);
665 set_pending_irq(i, cpumask_of_cpu(0));
670 time_remaining = schedule_timeout_interruptible(time_remaining);
672 if (time_after(jiffies,
673 prev_balance_time+balanced_irq_interval)) {
676 prev_balance_time = jiffies;
677 time_remaining = balanced_irq_interval;
684 static int __init balanced_irq_init(void)
687 struct cpuinfo_x86 *c;
690 cpus_shift_right(tmp, cpu_online_map, 2);
692 /* When not overwritten by the command line ask subarchitecture. */
693 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
694 irqbalance_disabled = NO_BALANCE_IRQ;
695 if (irqbalance_disabled)
698 /* disable irqbalance completely if there is only one processor online */
699 if (num_online_cpus() < 2) {
700 irqbalance_disabled = 1;
704 * Enable physical balance only if more than 1 physical processor
707 if (smp_num_siblings > 1 && !cpus_empty(tmp))
708 physical_balance = 1;
710 for_each_online_cpu(i) {
711 irq_cpu_data[i].irq_delta = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
712 irq_cpu_data[i].last_irq = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
713 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
714 printk(KERN_ERR "balanced_irq_init: out of memory");
719 printk(KERN_INFO "Starting balanced_irq\n");
720 if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
722 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
724 for_each_possible_cpu(i) {
725 kfree(irq_cpu_data[i].irq_delta);
726 irq_cpu_data[i].irq_delta = NULL;
727 kfree(irq_cpu_data[i].last_irq);
728 irq_cpu_data[i].last_irq = NULL;
733 int __devinit irqbalance_disable(char *str)
735 irqbalance_disabled = 1;
739 __setup("noirqbalance", irqbalance_disable);
741 late_initcall(balanced_irq_init);
742 #endif /* CONFIG_IRQBALANCE */
743 #endif /* CONFIG_SMP */
746 void send_IPI_self(int vector)
753 apic_wait_icr_idle();
754 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
756 * Send the IPI. The write to APIC_ICR fires this off.
758 apic_write_around(APIC_ICR, cfg);
760 #endif /* !CONFIG_SMP */
764 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
765 * specific CPU-side IRQs.
769 static int pirq_entries [MAX_PIRQS];
770 static int pirqs_enabled;
771 int skip_ioapic_setup;
773 static int __init ioapic_pirq_setup(char *str)
776 int ints[MAX_PIRQS+1];
778 get_options(str, ARRAY_SIZE(ints), ints);
780 for (i = 0; i < MAX_PIRQS; i++)
781 pirq_entries[i] = -1;
784 apic_printk(APIC_VERBOSE, KERN_INFO
785 "PIRQ redirection, working around broken MP-BIOS.\n");
787 if (ints[0] < MAX_PIRQS)
790 for (i = 0; i < max; i++) {
791 apic_printk(APIC_VERBOSE, KERN_DEBUG
792 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
794 * PIRQs are mapped upside down, usually.
796 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
801 __setup("pirq=", ioapic_pirq_setup);
804 * Find the IRQ entry number of a certain pin.
806 static int find_irq_entry(int apic, int pin, int type)
810 for (i = 0; i < mp_irq_entries; i++)
811 if (mp_irqs[i].mp_irqtype == type &&
812 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
813 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
814 mp_irqs[i].mp_dstirq == pin)
821 * Find the pin to which IRQ[irq] (ISA) is connected
823 static int __init find_isa_irq_pin(int irq, int type)
827 for (i = 0; i < mp_irq_entries; i++) {
828 int lbus = mp_irqs[i].mp_srcbus;
830 if (test_bit(lbus, mp_bus_not_pci) &&
831 (mp_irqs[i].mp_irqtype == type) &&
832 (mp_irqs[i].mp_srcbusirq == irq))
834 return mp_irqs[i].mp_dstirq;
839 static int __init find_isa_irq_apic(int irq, int type)
843 for (i = 0; i < mp_irq_entries; i++) {
844 int lbus = mp_irqs[i].mp_srcbus;
846 if (test_bit(lbus, mp_bus_not_pci) &&
847 (mp_irqs[i].mp_irqtype == type) &&
848 (mp_irqs[i].mp_srcbusirq == irq))
851 if (i < mp_irq_entries) {
853 for (apic = 0; apic < nr_ioapics; apic++) {
854 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
863 * Find a specific PCI IRQ entry.
864 * Not an __init, possibly needed by modules
866 static int pin_2_irq(int idx, int apic, int pin);
868 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
870 int apic, i, best_guess = -1;
872 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
873 "slot:%d, pin:%d.\n", bus, slot, pin);
874 if (test_bit(bus, mp_bus_not_pci)) {
875 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
878 for (i = 0; i < mp_irq_entries; i++) {
879 int lbus = mp_irqs[i].mp_srcbus;
881 for (apic = 0; apic < nr_ioapics; apic++)
882 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
883 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
886 if (!test_bit(lbus, mp_bus_not_pci) &&
887 !mp_irqs[i].mp_irqtype &&
889 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
890 int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq);
892 if (!(apic || IO_APIC_IRQ(irq)))
895 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
898 * Use the first all-but-pin matching entry as a
899 * best-guess fuzzy result for broken mptables.
907 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
910 * This function currently is only a helper for the i386 smp boot process where
911 * we need to reprogram the ioredtbls to cater for the cpus which have come online
912 * so mask in all cases should simply be TARGET_CPUS
915 void __init setup_ioapic_dest(void)
917 int pin, ioapic, irq, irq_entry;
919 if (skip_ioapic_setup == 1)
922 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
923 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
924 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
927 irq = pin_2_irq(irq_entry, ioapic, pin);
928 set_ioapic_affinity_irq(irq, TARGET_CPUS);
935 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
937 * EISA Edge/Level control register, ELCR
939 static int EISA_ELCR(unsigned int irq)
942 unsigned int port = 0x4d0 + (irq >> 3);
943 return (inb(port) >> (irq & 7)) & 1;
945 apic_printk(APIC_VERBOSE, KERN_INFO
946 "Broken MPtable reports ISA irq %d\n", irq);
951 /* ISA interrupts are always polarity zero edge triggered,
952 * when listed as conforming in the MP table. */
954 #define default_ISA_trigger(idx) (0)
955 #define default_ISA_polarity(idx) (0)
957 /* EISA interrupts are always polarity zero and can be edge or level
958 * trigger depending on the ELCR value. If an interrupt is listed as
959 * EISA conforming in the MP table, that means its trigger type must
960 * be read in from the ELCR */
962 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
963 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
965 /* PCI interrupts are always polarity one level triggered,
966 * when listed as conforming in the MP table. */
968 #define default_PCI_trigger(idx) (1)
969 #define default_PCI_polarity(idx) (1)
971 /* MCA interrupts are always polarity zero level triggered,
972 * when listed as conforming in the MP table. */
974 #define default_MCA_trigger(idx) (1)
975 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
977 static int MPBIOS_polarity(int idx)
979 int bus = mp_irqs[idx].mp_srcbus;
983 * Determine IRQ line polarity (high active or low active):
985 switch (mp_irqs[idx].mp_irqflag & 3) {
986 case 0: /* conforms, ie. bus-type dependent polarity */
988 polarity = test_bit(bus, mp_bus_not_pci)?
989 default_ISA_polarity(idx):
990 default_PCI_polarity(idx);
993 case 1: /* high active */
998 case 2: /* reserved */
1000 printk(KERN_WARNING "broken BIOS!!\n");
1004 case 3: /* low active */
1009 default: /* invalid */
1011 printk(KERN_WARNING "broken BIOS!!\n");
1019 static int MPBIOS_trigger(int idx)
1021 int bus = mp_irqs[idx].mp_srcbus;
1025 * Determine IRQ trigger mode (edge or level sensitive):
1027 switch ((mp_irqs[idx].mp_irqflag>>2) & 3) {
1028 case 0: /* conforms, ie. bus-type dependent */
1030 trigger = test_bit(bus, mp_bus_not_pci)?
1031 default_ISA_trigger(idx):
1032 default_PCI_trigger(idx);
1033 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1034 switch (mp_bus_id_to_type[bus]) {
1035 case MP_BUS_ISA: /* ISA pin */
1037 /* set before the switch */
1040 case MP_BUS_EISA: /* EISA pin */
1042 trigger = default_EISA_trigger(idx);
1045 case MP_BUS_PCI: /* PCI pin */
1047 /* set before the switch */
1050 case MP_BUS_MCA: /* MCA pin */
1052 trigger = default_MCA_trigger(idx);
1057 printk(KERN_WARNING "broken BIOS!!\n");
1070 case 2: /* reserved */
1072 printk(KERN_WARNING "broken BIOS!!\n");
1081 default: /* invalid */
1083 printk(KERN_WARNING "broken BIOS!!\n");
1091 static inline int irq_polarity(int idx)
1093 return MPBIOS_polarity(idx);
1096 static inline int irq_trigger(int idx)
1098 return MPBIOS_trigger(idx);
1101 static int pin_2_irq(int idx, int apic, int pin)
1104 int bus = mp_irqs[idx].mp_srcbus;
1107 * Debugging check, we are in big trouble if this message pops up!
1109 if (mp_irqs[idx].mp_dstirq != pin)
1110 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1112 if (test_bit(bus, mp_bus_not_pci))
1113 irq = mp_irqs[idx].mp_srcbusirq;
1116 * PCI IRQs are mapped in order
1120 irq += nr_ioapic_registers[i++];
1124 * For MPS mode, so far only needed by ES7000 platform
1126 if (ioapic_renumber_irq)
1127 irq = ioapic_renumber_irq(apic, irq);
1131 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1133 if ((pin >= 16) && (pin <= 23)) {
1134 if (pirq_entries[pin-16] != -1) {
1135 if (!pirq_entries[pin-16]) {
1136 apic_printk(APIC_VERBOSE, KERN_DEBUG
1137 "disabling PIRQ%d\n", pin-16);
1139 irq = pirq_entries[pin-16];
1140 apic_printk(APIC_VERBOSE, KERN_DEBUG
1141 "using PIRQ%d -> IRQ %d\n",
1149 static inline int IO_APIC_irq_trigger(int irq)
1153 for (apic = 0; apic < nr_ioapics; apic++) {
1154 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1155 idx = find_irq_entry(apic, pin, mp_INT);
1156 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1157 return irq_trigger(idx);
1161 * nonexistent IRQs are edge default
1166 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1167 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1169 static int __assign_irq_vector(int irq)
1171 static int current_vector = FIRST_DEVICE_VECTOR, current_offset;
1174 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1176 if (irq_vector[irq] > 0)
1177 return irq_vector[irq];
1179 vector = current_vector;
1180 offset = current_offset;
1183 if (vector >= first_system_vector) {
1184 offset = (offset + 1) % 8;
1185 vector = FIRST_DEVICE_VECTOR + offset;
1187 if (vector == current_vector)
1189 if (test_and_set_bit(vector, used_vectors))
1192 current_vector = vector;
1193 current_offset = offset;
1194 irq_vector[irq] = vector;
1199 static int assign_irq_vector(int irq)
1201 unsigned long flags;
1204 spin_lock_irqsave(&vector_lock, flags);
1205 vector = __assign_irq_vector(irq);
1206 spin_unlock_irqrestore(&vector_lock, flags);
1210 static struct irq_chip ioapic_chip;
1212 #define IOAPIC_AUTO -1
1213 #define IOAPIC_EDGE 0
1214 #define IOAPIC_LEVEL 1
1216 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1218 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1219 trigger == IOAPIC_LEVEL) {
1220 irq_desc[irq].status |= IRQ_LEVEL;
1221 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1222 handle_fasteoi_irq, "fasteoi");
1224 irq_desc[irq].status &= ~IRQ_LEVEL;
1225 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1226 handle_edge_irq, "edge");
1228 set_intr_gate(vector, interrupt[irq]);
1231 static void __init setup_IO_APIC_irqs(void)
1233 struct IO_APIC_route_entry entry;
1234 int apic, pin, idx, irq, first_notcon = 1, vector;
1236 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1238 for (apic = 0; apic < nr_ioapics; apic++) {
1239 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1242 * add it to the IO-APIC irq-routing table:
1244 memset(&entry, 0, sizeof(entry));
1246 entry.delivery_mode = INT_DELIVERY_MODE;
1247 entry.dest_mode = INT_DEST_MODE;
1248 entry.mask = 0; /* enable IRQ */
1249 entry.dest.logical.logical_dest =
1250 cpu_mask_to_apicid(TARGET_CPUS);
1252 idx = find_irq_entry(apic, pin, mp_INT);
1255 apic_printk(APIC_VERBOSE, KERN_DEBUG
1256 " IO-APIC (apicid-pin) %d-%d",
1257 mp_ioapics[apic].mp_apicid,
1261 apic_printk(APIC_VERBOSE, ", %d-%d",
1262 mp_ioapics[apic].mp_apicid, pin);
1266 if (!first_notcon) {
1267 apic_printk(APIC_VERBOSE, " not connected.\n");
1271 entry.trigger = irq_trigger(idx);
1272 entry.polarity = irq_polarity(idx);
1274 if (irq_trigger(idx)) {
1279 irq = pin_2_irq(idx, apic, pin);
1281 * skip adding the timer int on secondary nodes, which causes
1282 * a small but painful rift in the time-space continuum
1284 if (multi_timer_check(apic, irq))
1287 add_pin_to_irq(irq, apic, pin);
1289 if (!apic && !IO_APIC_IRQ(irq))
1292 if (IO_APIC_IRQ(irq)) {
1293 vector = assign_irq_vector(irq);
1294 entry.vector = vector;
1295 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1297 if (!apic && (irq < 16))
1298 disable_8259A_irq(irq);
1300 ioapic_write_entry(apic, pin, entry);
1305 apic_printk(APIC_VERBOSE, " not connected.\n");
1309 * Set up the timer pin, possibly with the 8259A-master behind.
1311 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1314 struct IO_APIC_route_entry entry;
1316 memset(&entry, 0, sizeof(entry));
1319 * We use logical delivery to get the timer IRQ
1322 entry.dest_mode = INT_DEST_MODE;
1323 entry.mask = 1; /* mask IRQ now */
1324 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1325 entry.delivery_mode = INT_DELIVERY_MODE;
1328 entry.vector = vector;
1331 * The timer IRQ doesn't have to know that behind the
1332 * scene we may have a 8259A-master in AEOI mode ...
1334 ioapic_register_intr(0, vector, IOAPIC_EDGE);
1337 * Add it to the IO-APIC irq-routing table:
1339 ioapic_write_entry(apic, pin, entry);
1342 void __init print_IO_APIC(void)
1345 union IO_APIC_reg_00 reg_00;
1346 union IO_APIC_reg_01 reg_01;
1347 union IO_APIC_reg_02 reg_02;
1348 union IO_APIC_reg_03 reg_03;
1349 unsigned long flags;
1351 if (apic_verbosity == APIC_QUIET)
1354 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1355 for (i = 0; i < nr_ioapics; i++)
1356 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1357 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1360 * We are a bit conservative about what we expect. We have to
1361 * know about every hardware change ASAP.
1363 printk(KERN_INFO "testing the IO APIC.......................\n");
1365 for (apic = 0; apic < nr_ioapics; apic++) {
1367 spin_lock_irqsave(&ioapic_lock, flags);
1368 reg_00.raw = io_apic_read(apic, 0);
1369 reg_01.raw = io_apic_read(apic, 1);
1370 if (reg_01.bits.version >= 0x10)
1371 reg_02.raw = io_apic_read(apic, 2);
1372 if (reg_01.bits.version >= 0x20)
1373 reg_03.raw = io_apic_read(apic, 3);
1374 spin_unlock_irqrestore(&ioapic_lock, flags);
1376 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1377 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1378 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1379 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1380 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1382 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1383 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1385 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1386 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1389 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1390 * but the value of reg_02 is read as the previous read register
1391 * value, so ignore it if reg_02 == reg_01.
1393 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1394 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1395 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1399 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1400 * or reg_03, but the value of reg_0[23] is read as the previous read
1401 * register value, so ignore it if reg_03 == reg_0[12].
1403 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1404 reg_03.raw != reg_01.raw) {
1405 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1406 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1409 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1411 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1412 " Stat Dest Deli Vect: \n");
1414 for (i = 0; i <= reg_01.bits.entries; i++) {
1415 struct IO_APIC_route_entry entry;
1417 entry = ioapic_read_entry(apic, i);
1419 printk(KERN_DEBUG " %02x %03X %02X ",
1421 entry.dest.logical.logical_dest,
1422 entry.dest.physical.physical_dest
1425 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1430 entry.delivery_status,
1432 entry.delivery_mode,
1437 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1438 for (i = 0; i < NR_IRQS; i++) {
1439 struct irq_pin_list *entry = irq_2_pin + i;
1442 printk(KERN_DEBUG "IRQ%d ", i);
1444 printk("-> %d:%d", entry->apic, entry->pin);
1447 entry = irq_2_pin + entry->next;
1452 printk(KERN_INFO ".................................... done.\n");
1459 static void print_APIC_bitfield(int base)
1464 if (apic_verbosity == APIC_QUIET)
1467 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1468 for (i = 0; i < 8; i++) {
1469 v = apic_read(base + i*0x10);
1470 for (j = 0; j < 32; j++) {
1480 void /*__init*/ print_local_APIC(void *dummy)
1482 unsigned int v, ver, maxlvt;
1484 if (apic_verbosity == APIC_QUIET)
1487 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1488 smp_processor_id(), hard_smp_processor_id());
1489 v = apic_read(APIC_ID);
1490 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v,
1491 GET_APIC_ID(read_apic_id()));
1492 v = apic_read(APIC_LVR);
1493 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1494 ver = GET_APIC_VERSION(v);
1495 maxlvt = lapic_get_maxlvt();
1497 v = apic_read(APIC_TASKPRI);
1498 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1500 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1501 v = apic_read(APIC_ARBPRI);
1502 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1503 v & APIC_ARBPRI_MASK);
1504 v = apic_read(APIC_PROCPRI);
1505 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1508 v = apic_read(APIC_EOI);
1509 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1510 v = apic_read(APIC_RRR);
1511 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1512 v = apic_read(APIC_LDR);
1513 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1514 v = apic_read(APIC_DFR);
1515 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1516 v = apic_read(APIC_SPIV);
1517 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1519 printk(KERN_DEBUG "... APIC ISR field:\n");
1520 print_APIC_bitfield(APIC_ISR);
1521 printk(KERN_DEBUG "... APIC TMR field:\n");
1522 print_APIC_bitfield(APIC_TMR);
1523 printk(KERN_DEBUG "... APIC IRR field:\n");
1524 print_APIC_bitfield(APIC_IRR);
1526 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1527 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1528 apic_write(APIC_ESR, 0);
1529 v = apic_read(APIC_ESR);
1530 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1533 v = apic_read(APIC_ICR);
1534 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1535 v = apic_read(APIC_ICR2);
1536 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1538 v = apic_read(APIC_LVTT);
1539 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1541 if (maxlvt > 3) { /* PC is LVT#4. */
1542 v = apic_read(APIC_LVTPC);
1543 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1545 v = apic_read(APIC_LVT0);
1546 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1547 v = apic_read(APIC_LVT1);
1548 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1550 if (maxlvt > 2) { /* ERR is LVT#3. */
1551 v = apic_read(APIC_LVTERR);
1552 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1555 v = apic_read(APIC_TMICT);
1556 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1557 v = apic_read(APIC_TMCCT);
1558 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1559 v = apic_read(APIC_TDCR);
1560 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1564 void print_all_local_APICs(void)
1566 on_each_cpu(print_local_APIC, NULL, 1, 1);
1569 void /*__init*/ print_PIC(void)
1572 unsigned long flags;
1574 if (apic_verbosity == APIC_QUIET)
1577 printk(KERN_DEBUG "\nprinting PIC contents\n");
1579 spin_lock_irqsave(&i8259A_lock, flags);
1581 v = inb(0xa1) << 8 | inb(0x21);
1582 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1584 v = inb(0xa0) << 8 | inb(0x20);
1585 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1589 v = inb(0xa0) << 8 | inb(0x20);
1593 spin_unlock_irqrestore(&i8259A_lock, flags);
1595 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1597 v = inb(0x4d1) << 8 | inb(0x4d0);
1598 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1603 static void __init enable_IO_APIC(void)
1605 union IO_APIC_reg_01 reg_01;
1606 int i8259_apic, i8259_pin;
1608 unsigned long flags;
1610 for (i = 0; i < PIN_MAP_SIZE; i++) {
1611 irq_2_pin[i].pin = -1;
1612 irq_2_pin[i].next = 0;
1615 for (i = 0; i < MAX_PIRQS; i++)
1616 pirq_entries[i] = -1;
1619 * The number of IO-APIC IRQ registers (== #pins):
1621 for (apic = 0; apic < nr_ioapics; apic++) {
1622 spin_lock_irqsave(&ioapic_lock, flags);
1623 reg_01.raw = io_apic_read(apic, 1);
1624 spin_unlock_irqrestore(&ioapic_lock, flags);
1625 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1627 for (apic = 0; apic < nr_ioapics; apic++) {
1629 /* See if any of the pins is in ExtINT mode */
1630 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1631 struct IO_APIC_route_entry entry;
1632 entry = ioapic_read_entry(apic, pin);
1635 /* If the interrupt line is enabled and in ExtInt mode
1636 * I have found the pin where the i8259 is connected.
1638 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1639 ioapic_i8259.apic = apic;
1640 ioapic_i8259.pin = pin;
1646 /* Look to see what if the MP table has reported the ExtINT */
1647 /* If we could not find the appropriate pin by looking at the ioapic
1648 * the i8259 probably is not connected the ioapic but give the
1649 * mptable a chance anyway.
1651 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1652 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1653 /* Trust the MP table if nothing is setup in the hardware */
1654 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1655 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1656 ioapic_i8259.pin = i8259_pin;
1657 ioapic_i8259.apic = i8259_apic;
1659 /* Complain if the MP table and the hardware disagree */
1660 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1661 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1663 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1667 * Do not trust the IO-APIC being empty at bootup
1673 * Not an __init, needed by the reboot code
1675 void disable_IO_APIC(void)
1678 * Clear the IO-APIC before rebooting:
1683 * If the i8259 is routed through an IOAPIC
1684 * Put that IOAPIC in virtual wire mode
1685 * so legacy interrupts can be delivered.
1687 if (ioapic_i8259.pin != -1) {
1688 struct IO_APIC_route_entry entry;
1690 memset(&entry, 0, sizeof(entry));
1691 entry.mask = 0; /* Enabled */
1692 entry.trigger = 0; /* Edge */
1694 entry.polarity = 0; /* High */
1695 entry.delivery_status = 0;
1696 entry.dest_mode = 0; /* Physical */
1697 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1699 entry.dest.physical.physical_dest =
1700 GET_APIC_ID(read_apic_id());
1703 * Add it to the IO-APIC irq-routing table:
1705 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1707 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1711 * function to set the IO-APIC physical IDs based on the
1712 * values stored in the MPC table.
1714 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1717 static void __init setup_ioapic_ids_from_mpc(void)
1719 union IO_APIC_reg_00 reg_00;
1720 physid_mask_t phys_id_present_map;
1723 unsigned char old_id;
1724 unsigned long flags;
1726 #ifdef CONFIG_X86_NUMAQ
1732 * Don't check I/O APIC IDs for xAPIC systems. They have
1733 * no meaning without the serial APIC bus.
1735 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1736 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1739 * This is broken; anything with a real cpu count has to
1740 * circumvent this idiocy regardless.
1742 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1745 * Set the IOAPIC ID to the value stored in the MPC table.
1747 for (apic = 0; apic < nr_ioapics; apic++) {
1749 /* Read the register 0 value */
1750 spin_lock_irqsave(&ioapic_lock, flags);
1751 reg_00.raw = io_apic_read(apic, 0);
1752 spin_unlock_irqrestore(&ioapic_lock, flags);
1754 old_id = mp_ioapics[apic].mp_apicid;
1756 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1757 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1758 apic, mp_ioapics[apic].mp_apicid);
1759 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1761 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1765 * Sanity check, is the ID really free? Every APIC in a
1766 * system must have a unique ID or we get lots of nice
1767 * 'stuck on smp_invalidate_needed IPI wait' messages.
1769 if (check_apicid_used(phys_id_present_map,
1770 mp_ioapics[apic].mp_apicid)) {
1771 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1772 apic, mp_ioapics[apic].mp_apicid);
1773 for (i = 0; i < get_physical_broadcast(); i++)
1774 if (!physid_isset(i, phys_id_present_map))
1776 if (i >= get_physical_broadcast())
1777 panic("Max APIC ID exceeded!\n");
1778 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1780 physid_set(i, phys_id_present_map);
1781 mp_ioapics[apic].mp_apicid = i;
1784 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1785 apic_printk(APIC_VERBOSE, "Setting %d in the "
1786 "phys_id_present_map\n",
1787 mp_ioapics[apic].mp_apicid);
1788 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1793 * We need to adjust the IRQ routing table
1794 * if the ID changed.
1796 if (old_id != mp_ioapics[apic].mp_apicid)
1797 for (i = 0; i < mp_irq_entries; i++)
1798 if (mp_irqs[i].mp_dstapic == old_id)
1799 mp_irqs[i].mp_dstapic
1800 = mp_ioapics[apic].mp_apicid;
1803 * Read the right value from the MPC table and
1804 * write it into the ID register.
1806 apic_printk(APIC_VERBOSE, KERN_INFO
1807 "...changing IO-APIC physical APIC ID to %d ...",
1808 mp_ioapics[apic].mp_apicid);
1810 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1811 spin_lock_irqsave(&ioapic_lock, flags);
1812 io_apic_write(apic, 0, reg_00.raw);
1813 spin_unlock_irqrestore(&ioapic_lock, flags);
1818 spin_lock_irqsave(&ioapic_lock, flags);
1819 reg_00.raw = io_apic_read(apic, 0);
1820 spin_unlock_irqrestore(&ioapic_lock, flags);
1821 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1822 printk("could not set ID!\n");
1824 apic_printk(APIC_VERBOSE, " ok.\n");
1828 int no_timer_check __initdata;
1830 static int __init notimercheck(char *s)
1835 __setup("no_timer_check", notimercheck);
1838 * There is a nasty bug in some older SMP boards, their mptable lies
1839 * about the timer IRQ. We do the following to work around the situation:
1841 * - timer IRQ defaults to IO-APIC IRQ
1842 * - if this function detects that timer IRQs are defunct, then we fall
1843 * back to ISA timer IRQs
1845 static int __init timer_irq_works(void)
1847 unsigned long t1 = jiffies;
1848 unsigned long flags;
1853 local_save_flags(flags);
1855 /* Let ten ticks pass... */
1856 mdelay((10 * 1000) / HZ);
1857 local_irq_restore(flags);
1860 * Expect a few ticks at least, to be sure some possible
1861 * glue logic does not lock up after one or two first
1862 * ticks in a non-ExtINT mode. Also the local APIC
1863 * might have cached one ExtINT interrupt. Finally, at
1864 * least one tick may be lost due to delays.
1866 if (time_after(jiffies, t1 + 4))
1873 * In the SMP+IOAPIC case it might happen that there are an unspecified
1874 * number of pending IRQ events unhandled. These cases are very rare,
1875 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1876 * better to do it this way as thus we do not have to be aware of
1877 * 'pending' interrupts in the IRQ path, except at this point.
1880 * Edge triggered needs to resend any interrupt
1881 * that was delayed but this is now handled in the device
1888 * Starting up a edge-triggered IO-APIC interrupt is
1889 * nasty - we need to make sure that we get the edge.
1890 * If it is already asserted for some reason, we need
1891 * return 1 to indicate that is was pending.
1893 * This is not complete - we should be able to fake
1894 * an edge even if it isn't on the 8259A...
1896 * (We do this for level-triggered IRQs too - it cannot hurt.)
1898 static unsigned int startup_ioapic_irq(unsigned int irq)
1900 int was_pending = 0;
1901 unsigned long flags;
1903 spin_lock_irqsave(&ioapic_lock, flags);
1905 disable_8259A_irq(irq);
1906 if (i8259A_irq_pending(irq))
1909 __unmask_IO_APIC_irq(irq);
1910 spin_unlock_irqrestore(&ioapic_lock, flags);
1915 static void ack_ioapic_irq(unsigned int irq)
1917 move_native_irq(irq);
1921 static void ack_ioapic_quirk_irq(unsigned int irq)
1926 move_native_irq(irq);
1928 * It appears there is an erratum which affects at least version 0x11
1929 * of I/O APIC (that's the 82093AA and cores integrated into various
1930 * chipsets). Under certain conditions a level-triggered interrupt is
1931 * erroneously delivered as edge-triggered one but the respective IRR
1932 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1933 * message but it will never arrive and further interrupts are blocked
1934 * from the source. The exact reason is so far unknown, but the
1935 * phenomenon was observed when two consecutive interrupt requests
1936 * from a given source get delivered to the same CPU and the source is
1937 * temporarily disabled in between.
1939 * A workaround is to simulate an EOI message manually. We achieve it
1940 * by setting the trigger mode to edge and then to level when the edge
1941 * trigger mode gets detected in the TMR of a local APIC for a
1942 * level-triggered interrupt. We mask the source for the time of the
1943 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1944 * The idea is from Manfred Spraul. --macro
1946 i = irq_vector[irq];
1948 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1952 if (!(v & (1 << (i & 0x1f)))) {
1953 atomic_inc(&irq_mis_count);
1954 spin_lock(&ioapic_lock);
1955 __mask_and_edge_IO_APIC_irq(irq);
1956 __unmask_and_level_IO_APIC_irq(irq);
1957 spin_unlock(&ioapic_lock);
1961 static int ioapic_retrigger_irq(unsigned int irq)
1963 send_IPI_self(irq_vector[irq]);
1968 static struct irq_chip ioapic_chip __read_mostly = {
1970 .startup = startup_ioapic_irq,
1971 .mask = mask_IO_APIC_irq,
1972 .unmask = unmask_IO_APIC_irq,
1973 .ack = ack_ioapic_irq,
1974 .eoi = ack_ioapic_quirk_irq,
1976 .set_affinity = set_ioapic_affinity_irq,
1978 .retrigger = ioapic_retrigger_irq,
1982 static inline void init_IO_APIC_traps(void)
1987 * NOTE! The local APIC isn't very good at handling
1988 * multiple interrupts at the same interrupt level.
1989 * As the interrupt level is determined by taking the
1990 * vector number and shifting that right by 4, we
1991 * want to spread these out a bit so that they don't
1992 * all fall in the same interrupt level.
1994 * Also, we've got to be careful not to trash gate
1995 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1997 for (irq = 0; irq < NR_IRQS ; irq++) {
1998 if (IO_APIC_IRQ(irq) && !irq_vector[irq]) {
2000 * Hmm.. We don't have an entry for this,
2001 * so default to an old-fashioned 8259
2002 * interrupt if we can..
2005 make_8259A_irq(irq);
2007 /* Strange. Oh, well.. */
2008 irq_desc[irq].chip = &no_irq_chip;
2014 * The local APIC irq-chip implementation:
2017 static void ack_apic(unsigned int irq)
2022 static void mask_lapic_irq(unsigned int irq)
2026 v = apic_read(APIC_LVT0);
2027 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2030 static void unmask_lapic_irq(unsigned int irq)
2034 v = apic_read(APIC_LVT0);
2035 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2038 static struct irq_chip lapic_chip __read_mostly = {
2039 .name = "local-APIC",
2040 .mask = mask_lapic_irq,
2041 .unmask = unmask_lapic_irq,
2045 static void __init setup_nmi(void)
2048 * Dirty trick to enable the NMI watchdog ...
2049 * We put the 8259A master into AEOI mode and
2050 * unmask on all local APICs LVT0 as NMI.
2052 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2053 * is from Maciej W. Rozycki - so we do not have to EOI from
2054 * the NMI handler or the timer interrupt.
2056 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2058 enable_NMI_through_LVT0();
2060 apic_printk(APIC_VERBOSE, " done.\n");
2064 * This looks a bit hackish but it's about the only one way of sending
2065 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2066 * not support the ExtINT mode, unfortunately. We need to send these
2067 * cycles as some i82489DX-based boards have glue logic that keeps the
2068 * 8259A interrupt line asserted until INTA. --macro
2070 static inline void __init unlock_ExtINT_logic(void)
2073 struct IO_APIC_route_entry entry0, entry1;
2074 unsigned char save_control, save_freq_select;
2076 pin = find_isa_irq_pin(8, mp_INT);
2081 apic = find_isa_irq_apic(8, mp_INT);
2087 entry0 = ioapic_read_entry(apic, pin);
2088 clear_IO_APIC_pin(apic, pin);
2090 memset(&entry1, 0, sizeof(entry1));
2092 entry1.dest_mode = 0; /* physical delivery */
2093 entry1.mask = 0; /* unmask IRQ now */
2094 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2095 entry1.delivery_mode = dest_ExtINT;
2096 entry1.polarity = entry0.polarity;
2100 ioapic_write_entry(apic, pin, entry1);
2102 save_control = CMOS_READ(RTC_CONTROL);
2103 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2104 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2106 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2111 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2115 CMOS_WRITE(save_control, RTC_CONTROL);
2116 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2117 clear_IO_APIC_pin(apic, pin);
2119 ioapic_write_entry(apic, pin, entry0);
2123 * This code may look a bit paranoid, but it's supposed to cooperate with
2124 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2125 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2126 * fanatically on his truly buggy board.
2128 static inline void __init check_timer(void)
2130 int apic1, pin1, apic2, pin2;
2134 unsigned long flags;
2136 local_irq_save(flags);
2138 ver = apic_read(APIC_LVR);
2139 ver = GET_APIC_VERSION(ver);
2142 * get/set the timer IRQ vector:
2144 disable_8259A_irq(0);
2145 vector = assign_irq_vector(0);
2146 set_intr_gate(vector, interrupt[0]);
2149 * As IRQ0 is to be enabled in the 8259A, the virtual
2150 * wire has to be disabled in the local APIC. Also
2151 * timer interrupts need to be acknowledged manually in
2152 * the 8259A for the i82489DX when using the NMI
2153 * watchdog as that APIC treats NMIs as level-triggered.
2154 * The AEOI mode will finish them in the 8259A
2157 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2159 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2161 pin1 = find_isa_irq_pin(0, mp_INT);
2162 apic1 = find_isa_irq_apic(0, mp_INT);
2163 pin2 = ioapic_i8259.pin;
2164 apic2 = ioapic_i8259.apic;
2166 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2167 vector, apic1, pin1, apic2, pin2);
2170 * Some BIOS writers are clueless and report the ExtINTA
2171 * I/O APIC input from the cascaded 8259A as the timer
2172 * interrupt input. So just in case, if only one pin
2173 * was found above, try it both directly and through the
2180 } else if (pin2 == -1) {
2187 * Ok, does IRQ0 through the IOAPIC work?
2190 add_pin_to_irq(0, apic1, pin1);
2191 setup_timer_IRQ0_pin(apic1, pin1, vector);
2193 unmask_IO_APIC_irq(0);
2194 if (timer_irq_works()) {
2195 if (nmi_watchdog == NMI_IO_APIC) {
2197 enable_8259A_irq(0);
2199 if (disable_timer_pin_1 > 0)
2200 clear_IO_APIC_pin(0, pin1);
2203 clear_IO_APIC_pin(apic1, pin1);
2205 printk(KERN_ERR "..MP-BIOS bug: "
2206 "8254 timer not connected to IO-APIC\n");
2208 printk(KERN_INFO "...trying to set up timer (IRQ0) "
2209 "through the 8259A ... ");
2210 printk("\n..... (found pin %d) ...", pin2);
2212 * legacy devices should be connected to IO APIC #0
2214 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2215 setup_timer_IRQ0_pin(apic2, pin2, vector);
2216 unmask_IO_APIC_irq(0);
2217 enable_8259A_irq(0);
2218 if (timer_irq_works()) {
2220 timer_through_8259 = 1;
2221 if (nmi_watchdog == NMI_IO_APIC) {
2222 disable_8259A_irq(0);
2224 enable_8259A_irq(0);
2229 * Cleanup, just in case ...
2231 disable_8259A_irq(0);
2232 clear_IO_APIC_pin(apic2, pin2);
2233 printk(" failed.\n");
2236 if (nmi_watchdog == NMI_IO_APIC) {
2237 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2238 nmi_watchdog = NMI_NONE;
2242 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2244 set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2246 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2247 enable_8259A_irq(0);
2249 if (timer_irq_works()) {
2250 printk(" works.\n");
2253 disable_8259A_irq(0);
2254 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2255 printk(" failed.\n");
2257 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2261 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2263 unlock_ExtINT_logic();
2265 if (timer_irq_works()) {
2266 printk(" works.\n");
2269 printk(" failed :(.\n");
2270 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2271 "report. Then try booting with the 'noapic' option");
2273 local_irq_restore(flags);
2278 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2279 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2280 * Linux doesn't really care, as it's not actually used
2281 * for any interrupt handling anyway.
2283 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2285 void __init setup_IO_APIC(void)
2289 /* Reserve all the system vectors. */
2290 for (i = first_system_vector; i < NR_VECTORS; i++)
2291 set_bit(i, used_vectors);
2296 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2298 io_apic_irqs = ~PIC_IRQS;
2300 printk("ENABLING IO-APIC IRQs\n");
2303 * Set up IO-APIC IRQ routing.
2306 setup_ioapic_ids_from_mpc();
2308 setup_IO_APIC_irqs();
2309 init_IO_APIC_traps();
2316 * Called after all the initialization is done. If we didnt find any
2317 * APIC bugs then we can allow the modify fast path
2320 static int __init io_apic_bug_finalize(void)
2322 if (sis_apic_bug == -1)
2327 late_initcall(io_apic_bug_finalize);
2329 struct sysfs_ioapic_data {
2330 struct sys_device dev;
2331 struct IO_APIC_route_entry entry[0];
2333 static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS];
2335 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2337 struct IO_APIC_route_entry *entry;
2338 struct sysfs_ioapic_data *data;
2341 data = container_of(dev, struct sysfs_ioapic_data, dev);
2342 entry = data->entry;
2343 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2344 entry[i] = ioapic_read_entry(dev->id, i);
2349 static int ioapic_resume(struct sys_device *dev)
2351 struct IO_APIC_route_entry *entry;
2352 struct sysfs_ioapic_data *data;
2353 unsigned long flags;
2354 union IO_APIC_reg_00 reg_00;
2357 data = container_of(dev, struct sysfs_ioapic_data, dev);
2358 entry = data->entry;
2360 spin_lock_irqsave(&ioapic_lock, flags);
2361 reg_00.raw = io_apic_read(dev->id, 0);
2362 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2363 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2364 io_apic_write(dev->id, 0, reg_00.raw);
2366 spin_unlock_irqrestore(&ioapic_lock, flags);
2367 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2368 ioapic_write_entry(dev->id, i, entry[i]);
2373 static struct sysdev_class ioapic_sysdev_class = {
2375 .suspend = ioapic_suspend,
2376 .resume = ioapic_resume,
2379 static int __init ioapic_init_sysfs(void)
2381 struct sys_device *dev;
2382 int i, size, error = 0;
2384 error = sysdev_class_register(&ioapic_sysdev_class);
2388 for (i = 0; i < nr_ioapics; i++) {
2389 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2390 * sizeof(struct IO_APIC_route_entry);
2391 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2392 if (!mp_ioapic_data[i]) {
2393 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2396 dev = &mp_ioapic_data[i]->dev;
2398 dev->cls = &ioapic_sysdev_class;
2399 error = sysdev_register(dev);
2401 kfree(mp_ioapic_data[i]);
2402 mp_ioapic_data[i] = NULL;
2403 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2411 device_initcall(ioapic_init_sysfs);
2414 * Dynamic irq allocate and deallocation
2416 int create_irq(void)
2418 /* Allocate an unused irq */
2419 int irq, new, vector = 0;
2420 unsigned long flags;
2423 spin_lock_irqsave(&vector_lock, flags);
2424 for (new = (NR_IRQS - 1); new >= 0; new--) {
2425 if (platform_legacy_irq(new))
2427 if (irq_vector[new] != 0)
2429 vector = __assign_irq_vector(new);
2430 if (likely(vector > 0))
2434 spin_unlock_irqrestore(&vector_lock, flags);
2437 set_intr_gate(vector, interrupt[irq]);
2438 dynamic_irq_init(irq);
2443 void destroy_irq(unsigned int irq)
2445 unsigned long flags;
2447 dynamic_irq_cleanup(irq);
2449 spin_lock_irqsave(&vector_lock, flags);
2450 clear_bit(irq_vector[irq], used_vectors);
2451 irq_vector[irq] = 0;
2452 spin_unlock_irqrestore(&vector_lock, flags);
2456 * MSI message composition
2458 #ifdef CONFIG_PCI_MSI
2459 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2464 vector = assign_irq_vector(irq);
2466 dest = cpu_mask_to_apicid(TARGET_CPUS);
2468 msg->address_hi = MSI_ADDR_BASE_HI;
2471 ((INT_DEST_MODE == 0) ?
2472 MSI_ADDR_DEST_MODE_PHYSICAL:
2473 MSI_ADDR_DEST_MODE_LOGICAL) |
2474 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2475 MSI_ADDR_REDIRECTION_CPU:
2476 MSI_ADDR_REDIRECTION_LOWPRI) |
2477 MSI_ADDR_DEST_ID(dest);
2480 MSI_DATA_TRIGGER_EDGE |
2481 MSI_DATA_LEVEL_ASSERT |
2482 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2483 MSI_DATA_DELIVERY_FIXED:
2484 MSI_DATA_DELIVERY_LOWPRI) |
2485 MSI_DATA_VECTOR(vector);
2491 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2498 cpus_and(tmp, mask, cpu_online_map);
2499 if (cpus_empty(tmp))
2502 vector = assign_irq_vector(irq);
2506 dest = cpu_mask_to_apicid(mask);
2508 read_msi_msg(irq, &msg);
2510 msg.data &= ~MSI_DATA_VECTOR_MASK;
2511 msg.data |= MSI_DATA_VECTOR(vector);
2512 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2513 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2515 write_msi_msg(irq, &msg);
2516 irq_desc[irq].affinity = mask;
2518 #endif /* CONFIG_SMP */
2521 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2522 * which implement the MSI or MSI-X Capability Structure.
2524 static struct irq_chip msi_chip = {
2526 .unmask = unmask_msi_irq,
2527 .mask = mask_msi_irq,
2528 .ack = ack_ioapic_irq,
2530 .set_affinity = set_msi_irq_affinity,
2532 .retrigger = ioapic_retrigger_irq,
2535 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2543 ret = msi_compose_msg(dev, irq, &msg);
2549 set_irq_msi(irq, desc);
2550 write_msi_msg(irq, &msg);
2552 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2558 void arch_teardown_msi_irq(unsigned int irq)
2563 #endif /* CONFIG_PCI_MSI */
2566 * Hypertransport interrupt support
2568 #ifdef CONFIG_HT_IRQ
2572 static void target_ht_irq(unsigned int irq, unsigned int dest)
2574 struct ht_irq_msg msg;
2575 fetch_ht_irq_msg(irq, &msg);
2577 msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2578 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2580 msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2581 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2583 write_ht_irq_msg(irq, &msg);
2586 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2591 cpus_and(tmp, mask, cpu_online_map);
2592 if (cpus_empty(tmp))
2595 cpus_and(mask, tmp, CPU_MASK_ALL);
2597 dest = cpu_mask_to_apicid(mask);
2599 target_ht_irq(irq, dest);
2600 irq_desc[irq].affinity = mask;
2604 static struct irq_chip ht_irq_chip = {
2606 .mask = mask_ht_irq,
2607 .unmask = unmask_ht_irq,
2608 .ack = ack_ioapic_irq,
2610 .set_affinity = set_ht_irq_affinity,
2612 .retrigger = ioapic_retrigger_irq,
2615 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2619 vector = assign_irq_vector(irq);
2621 struct ht_irq_msg msg;
2626 cpu_set(vector >> 8, tmp);
2627 dest = cpu_mask_to_apicid(tmp);
2629 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2633 HT_IRQ_LOW_DEST_ID(dest) |
2634 HT_IRQ_LOW_VECTOR(vector) |
2635 ((INT_DEST_MODE == 0) ?
2636 HT_IRQ_LOW_DM_PHYSICAL :
2637 HT_IRQ_LOW_DM_LOGICAL) |
2638 HT_IRQ_LOW_RQEOI_EDGE |
2639 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2640 HT_IRQ_LOW_MT_FIXED :
2641 HT_IRQ_LOW_MT_ARBITRATED) |
2642 HT_IRQ_LOW_IRQ_MASKED;
2644 write_ht_irq_msg(irq, &msg);
2646 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2647 handle_edge_irq, "edge");
2651 #endif /* CONFIG_HT_IRQ */
2653 /* --------------------------------------------------------------------------
2654 ACPI-based IOAPIC Configuration
2655 -------------------------------------------------------------------------- */
2659 int __init io_apic_get_unique_id(int ioapic, int apic_id)
2661 union IO_APIC_reg_00 reg_00;
2662 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2664 unsigned long flags;
2668 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2669 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2670 * supports up to 16 on one shared APIC bus.
2672 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2673 * advantage of new APIC bus architecture.
2676 if (physids_empty(apic_id_map))
2677 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2679 spin_lock_irqsave(&ioapic_lock, flags);
2680 reg_00.raw = io_apic_read(ioapic, 0);
2681 spin_unlock_irqrestore(&ioapic_lock, flags);
2683 if (apic_id >= get_physical_broadcast()) {
2684 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2685 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2686 apic_id = reg_00.bits.ID;
2690 * Every APIC in a system must have a unique ID or we get lots of nice
2691 * 'stuck on smp_invalidate_needed IPI wait' messages.
2693 if (check_apicid_used(apic_id_map, apic_id)) {
2695 for (i = 0; i < get_physical_broadcast(); i++) {
2696 if (!check_apicid_used(apic_id_map, i))
2700 if (i == get_physical_broadcast())
2701 panic("Max apic_id exceeded!\n");
2703 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2704 "trying %d\n", ioapic, apic_id, i);
2709 tmp = apicid_to_cpu_present(apic_id);
2710 physids_or(apic_id_map, apic_id_map, tmp);
2712 if (reg_00.bits.ID != apic_id) {
2713 reg_00.bits.ID = apic_id;
2715 spin_lock_irqsave(&ioapic_lock, flags);
2716 io_apic_write(ioapic, 0, reg_00.raw);
2717 reg_00.raw = io_apic_read(ioapic, 0);
2718 spin_unlock_irqrestore(&ioapic_lock, flags);
2721 if (reg_00.bits.ID != apic_id) {
2722 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2727 apic_printk(APIC_VERBOSE, KERN_INFO
2728 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2734 int __init io_apic_get_version(int ioapic)
2736 union IO_APIC_reg_01 reg_01;
2737 unsigned long flags;
2739 spin_lock_irqsave(&ioapic_lock, flags);
2740 reg_01.raw = io_apic_read(ioapic, 1);
2741 spin_unlock_irqrestore(&ioapic_lock, flags);
2743 return reg_01.bits.version;
2747 int __init io_apic_get_redir_entries(int ioapic)
2749 union IO_APIC_reg_01 reg_01;
2750 unsigned long flags;
2752 spin_lock_irqsave(&ioapic_lock, flags);
2753 reg_01.raw = io_apic_read(ioapic, 1);
2754 spin_unlock_irqrestore(&ioapic_lock, flags);
2756 return reg_01.bits.entries;
2760 int io_apic_set_pci_routing(int ioapic, int pin, int irq, int edge_level, int active_high_low)
2762 struct IO_APIC_route_entry entry;
2764 if (!IO_APIC_IRQ(irq)) {
2765 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2771 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2772 * Note that we mask (disable) IRQs now -- these get enabled when the
2773 * corresponding device driver registers for this IRQ.
2776 memset(&entry, 0, sizeof(entry));
2778 entry.delivery_mode = INT_DELIVERY_MODE;
2779 entry.dest_mode = INT_DEST_MODE;
2780 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2781 entry.trigger = edge_level;
2782 entry.polarity = active_high_low;
2786 * IRQs < 16 are already in the irq_2_pin[] map
2789 add_pin_to_irq(irq, ioapic, pin);
2791 entry.vector = assign_irq_vector(irq);
2793 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2794 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2795 mp_ioapics[ioapic].mp_apicid, pin, entry.vector, irq,
2796 edge_level, active_high_low);
2798 ioapic_register_intr(irq, entry.vector, edge_level);
2800 if (!ioapic && (irq < 16))
2801 disable_8259A_irq(irq);
2803 ioapic_write_entry(ioapic, pin, entry);
2808 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2812 if (skip_ioapic_setup)
2815 for (i = 0; i < mp_irq_entries; i++)
2816 if (mp_irqs[i].mp_irqtype == mp_INT &&
2817 mp_irqs[i].mp_srcbusirq == bus_irq)
2819 if (i >= mp_irq_entries)
2822 *trigger = irq_trigger(i);
2823 *polarity = irq_polarity(i);
2827 #endif /* CONFIG_ACPI */
2829 static int __init parse_disable_timer_pin_1(char *arg)
2831 disable_timer_pin_1 = 1;
2834 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2836 static int __init parse_enable_timer_pin_1(char *arg)
2838 disable_timer_pin_1 = -1;
2841 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2843 static int __init parse_noapic(char *arg)
2845 /* disable IO-APIC */
2846 disable_ioapic_setup();
2849 early_param("noapic", parse_noapic);