arch/x86/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/pci.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34 #include <linux/msi.h>
  35 #include <linux/htirq.h>
  36 #include <linux/freezer.h>
  37 #include <linux/kthread.h>
  38 #include <linux/jiffies.h>      /* time_after() */
  39 #ifdef CONFIG_ACPI
  40 #include <acpi/acpi_bus.h>
  41 #endif
  42 #include <linux/bootmem.h>
  43 #include <linux/dmar.h>
  44 #include <linux/hpet.h>
  45
  46 #include <asm/idle.h>
  47 #include <asm/io.h>
  48 #include <asm/smp.h>
  49 #include <asm/cpu.h>
  50 #include <asm/desc.h>
  51 #include <asm/proto.h>
  52 #include <asm/acpi.h>
  53 #include <asm/dma.h>
  54 #include <asm/timer.h>
  55 #include <asm/i8259.h>
  56 #include <asm/nmi.h>
  57 #include <asm/msidef.h>
  58 #include <asm/hypertransport.h>
  59 #include <asm/setup.h>
  60 #include <asm/irq_remapping.h>
  61 #include <asm/hpet.h>
  62 #include <asm/uv/uv_hub.h>
  63 #include <asm/uv/uv_irq.h>
  64
  65 #include <mach_ipi.h>
  66 #include <mach_apic.h>
  67 #include <mach_apicdef.h>
  68
  69 #define __apicdebuginit(type) static type __init
  70
  71 /*
  72  *      Is the SiS APIC rmw bug present ?
  73  *      -1 = don't know, 0 = no, 1 = yes
  74  */
  75 int sis_apic_bug = -1;
  76
  77 static DEFINE_SPINLOCK(ioapic_lock);
  78 static DEFINE_SPINLOCK(vector_lock);
  79
  80 /*
  81  * # of IRQ routing registers
  82  */
  83 int nr_ioapic_registers[MAX_IO_APICS];
  84
  85 /* I/O APIC entries */
  86 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
  87 int nr_ioapics;
  88
  89 /* MP IRQ source entries */
  90 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
  91
  92 /* # of MP IRQ source entries */
  93 int mp_irq_entries;
  94
  95 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
  96 int mp_bus_id_to_type[MAX_MP_BUSSES];
  97 #endif
  98
  99 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
 100
 101 int skip_ioapic_setup;
 102
 103 static int __init parse_noapic(char *str)
 104 {
 105         /* disable IO-APIC */
 106         disable_ioapic_setup();
 107         return 0;
 108 }
 109 early_param("noapic", parse_noapic);
 110
 111 struct irq_pin_list;
 112
 113 /*
 114  * This is performance-critical, we want to do it O(1)
 115  *
 116  * the indexing order of this array favors 1:1 mappings
 117  * between pins and IRQs.
 118  */
 119
 120 struct irq_pin_list {
 121         int apic, pin;
 122         struct irq_pin_list *next;
 123 };
 124
 125 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
 126 {
 127         struct irq_pin_list *pin;
 128         int node;
 129
 130         node = cpu_to_node(cpu);
 131
 132         pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
 133
 134         return pin;
 135 }
 136
 137 struct irq_cfg {
 138         struct irq_pin_list *irq_2_pin;
 139         cpumask_var_t domain;
 140         cpumask_var_t old_domain;
 141         unsigned move_cleanup_count;
 142         u8 vector;
 143         u8 move_in_progress : 1;
 144 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 145         u8 move_desc_pending : 1;
 146 #endif
 147 };
 148
 149 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
 150 #ifdef CONFIG_SPARSE_IRQ
 151 static struct irq_cfg irq_cfgx[] = {
 152 #else
 153 static struct irq_cfg irq_cfgx[NR_IRQS] = {
 154 #endif
 155         [0]  = { .vector = IRQ0_VECTOR,  },
 156         [1]  = { .vector = IRQ1_VECTOR,  },
 157         [2]  = { .vector = IRQ2_VECTOR,  },
 158         [3]  = { .vector = IRQ3_VECTOR,  },
 159         [4]  = { .vector = IRQ4_VECTOR,  },
 160         [5]  = { .vector = IRQ5_VECTOR,  },
 161         [6]  = { .vector = IRQ6_VECTOR,  },
 162         [7]  = { .vector = IRQ7_VECTOR,  },
 163         [8]  = { .vector = IRQ8_VECTOR,  },
 164         [9]  = { .vector = IRQ9_VECTOR,  },
 165         [10] = { .vector = IRQ10_VECTOR, },
 166         [11] = { .vector = IRQ11_VECTOR, },
 167         [12] = { .vector = IRQ12_VECTOR, },
 168         [13] = { .vector = IRQ13_VECTOR, },
 169         [14] = { .vector = IRQ14_VECTOR, },
 170         [15] = { .vector = IRQ15_VECTOR, },
 171 };
 172
 173 int __init arch_early_irq_init(void)
 174 {
 175         struct irq_cfg *cfg;
 176         struct irq_desc *desc;
 177         int count;
 178         int i;
 179
 180         cfg = irq_cfgx;
 181         count = ARRAY_SIZE(irq_cfgx);
 182
 183         for (i = 0; i < count; i++) {
 184                 desc = irq_to_desc(i);
 185                 desc->chip_data = &cfg[i];
 186                 alloc_bootmem_cpumask_var(&cfg[i].domain);
 187                 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
 188                 if (i < NR_IRQS_LEGACY)
 189                         cpumask_setall(cfg[i].domain);
 190         }
 191
 192         return 0;
 193 }
 194
 195 #ifdef CONFIG_SPARSE_IRQ
 196 static struct irq_cfg *irq_cfg(unsigned int irq)
 197 {
 198         struct irq_cfg *cfg = NULL;
 199         struct irq_desc *desc;
 200
 201         desc = irq_to_desc(irq);
 202         if (desc)
 203                 cfg = desc->chip_data;
 204
 205         return cfg;
 206 }
 207
 208 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
 209 {
 210         struct irq_cfg *cfg;
 211         int node;
 212
 213         node = cpu_to_node(cpu);
 214
 215         cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
 216         if (cfg) {
 217                 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
 218                         kfree(cfg);
 219                         cfg = NULL;
 220                 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
 221                                                           GFP_ATOMIC, node)) {
 222                         free_cpumask_var(cfg->domain);
 223                         kfree(cfg);
 224                         cfg = NULL;
 225                 } else {
 226                         cpumask_clear(cfg->domain);
 227                         cpumask_clear(cfg->old_domain);
 228                 }
 229         }
 230
 231         return cfg;
 232 }
 233
 234 int arch_init_chip_data(struct irq_desc *desc, int cpu)
 235 {
 236         struct irq_cfg *cfg;
 237
 238         cfg = desc->chip_data;
 239         if (!cfg) {
 240                 desc->chip_data = get_one_free_irq_cfg(cpu);
 241                 if (!desc->chip_data) {
 242                         printk(KERN_ERR "can not alloc irq_cfg\n");
 243                         BUG_ON(1);
 244                 }
 245         }
 246
 247         return 0;
 248 }
 249
 250 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 251
 252 static void
 253 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
 254 {
 255         struct irq_pin_list *old_entry, *head, *tail, *entry;
 256
 257         cfg->irq_2_pin = NULL;
 258         old_entry = old_cfg->irq_2_pin;
 259         if (!old_entry)
 260                 return;
 261
 262         entry = get_one_free_irq_2_pin(cpu);
 263         if (!entry)
 264                 return;
 265
 266         entry->apic     = old_entry->apic;
 267         entry->pin      = old_entry->pin;
 268         head            = entry;
 269         tail            = entry;
 270         old_entry       = old_entry->next;
 271         while (old_entry) {
 272                 entry = get_one_free_irq_2_pin(cpu);
 273                 if (!entry) {
 274                         entry = head;
 275                         while (entry) {
 276                                 head = entry->next;
 277                                 kfree(entry);
 278                                 entry = head;
 279                         }
 280                         /* still use the old one */
 281                         return;
 282                 }
 283                 entry->apic     = old_entry->apic;
 284                 entry->pin      = old_entry->pin;
 285                 tail->next      = entry;
 286                 tail            = entry;
 287                 old_entry       = old_entry->next;
 288         }
 289
 290         tail->next = NULL;
 291         cfg->irq_2_pin = head;
 292 }
 293
 294 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
 295 {
 296         struct irq_pin_list *entry, *next;
 297
 298         if (old_cfg->irq_2_pin == cfg->irq_2_pin)
 299                 return;
 300
 301         entry = old_cfg->irq_2_pin;
 302
 303         while (entry) {
 304                 next = entry->next;
 305                 kfree(entry);
 306                 entry = next;
 307         }
 308         old_cfg->irq_2_pin = NULL;
 309 }
 310
 311 void arch_init_copy_chip_data(struct irq_desc *old_desc,
 312                                  struct irq_desc *desc, int cpu)
 313 {
 314         struct irq_cfg *cfg;
 315         struct irq_cfg *old_cfg;
 316
 317         cfg = get_one_free_irq_cfg(cpu);
 318
 319         if (!cfg)
 320                 return;
 321
 322         desc->chip_data = cfg;
 323
 324         old_cfg = old_desc->chip_data;
 325
 326         memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
 327
 328         init_copy_irq_2_pin(old_cfg, cfg, cpu);
 329 }
 330
 331 static void free_irq_cfg(struct irq_cfg *old_cfg)
 332 {
 333         kfree(old_cfg);
 334 }
 335
 336 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
 337 {
 338         struct irq_cfg *old_cfg, *cfg;
 339
 340         old_cfg = old_desc->chip_data;
 341         cfg = desc->chip_data;
 342
 343         if (old_cfg == cfg)
 344                 return;
 345
 346         if (old_cfg) {
 347                 free_irq_2_pin(old_cfg, cfg);
 348                 free_irq_cfg(old_cfg);
 349                 old_desc->chip_data = NULL;
 350         }
 351 }
 352
 353 static void
 354 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 355 {
 356         struct irq_cfg *cfg = desc->chip_data;
 357
 358         if (!cfg->move_in_progress) {
 359                 /* it means that domain is not changed */
 360                 if (!cpumask_intersects(desc->affinity, mask))
 361                         cfg->move_desc_pending = 1;
 362         }
 363 }
 364 #endif
 365
 366 #else
 367 static struct irq_cfg *irq_cfg(unsigned int irq)
 368 {
 369         return irq < nr_irqs ? irq_cfgx + irq : NULL;
 370 }
 371
 372 #endif
 373
 374 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
 375 static inline void
 376 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 377 {
 378 }
 379 #endif
 380
 381 struct io_apic {
 382         unsigned int index;
 383         unsigned int unused[3];
 384         unsigned int data;
 385 };
 386
 387 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 388 {
 389         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 390                 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
 391 }
 392
 393 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 394 {
 395         struct io_apic __iomem *io_apic = io_apic_base(apic);
 396         writel(reg, &io_apic->index);
 397         return readl(&io_apic->data);
 398 }
 399
 400 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 401 {
 402         struct io_apic __iomem *io_apic = io_apic_base(apic);
 403         writel(reg, &io_apic->index);
 404         writel(value, &io_apic->data);
 405 }
 406
 407 /*
 408  * Re-write a value: to be used for read-modify-write
 409  * cycles where the read already set up the index register.
 410  *
 411  * Older SiS APIC requires we rewrite the index register
 412  */
 413 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 414 {
 415         struct io_apic __iomem *io_apic = io_apic_base(apic);
 416
 417         if (sis_apic_bug)
 418                 writel(reg, &io_apic->index);
 419         writel(value, &io_apic->data);
 420 }
 421
 422 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
 423 {
 424         struct irq_pin_list *entry;
 425         unsigned long flags;
 426
 427         spin_lock_irqsave(&ioapic_lock, flags);
 428         entry = cfg->irq_2_pin;
 429         for (;;) {
 430                 unsigned int reg;
 431                 int pin;
 432
 433                 if (!entry)
 434                         break;
 435                 pin = entry->pin;
 436                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 437                 /* Is the remote IRR bit set? */
 438                 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
 439                         spin_unlock_irqrestore(&ioapic_lock, flags);
 440                         return true;
 441                 }
 442                 if (!entry->next)
 443                         break;
 444                 entry = entry->next;
 445         }
 446         spin_unlock_irqrestore(&ioapic_lock, flags);
 447
 448         return false;
 449 }
 450
 451 union entry_union {
 452         struct { u32 w1, w2; };
 453         struct IO_APIC_route_entry entry;
 454 };
 455
 456 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 457 {
 458         union entry_union eu;
 459         unsigned long flags;
 460         spin_lock_irqsave(&ioapic_lock, flags);
 461         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 462         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 463         spin_unlock_irqrestore(&ioapic_lock, flags);
 464         return eu.entry;
 465 }
 466
 467 /*
 468  * When we write a new IO APIC routing entry, we need to write the high
 469  * word first! If the mask bit in the low word is clear, we will enable
 470  * the interrupt, and we need to make sure the entry is fully populated
 471  * before that happens.
 472  */
 473 static void
 474 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 475 {
 476         union entry_union eu;
 477         eu.entry = e;
 478         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 479         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 480 }
 481
 482 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 483 {
 484         unsigned long flags;
 485         spin_lock_irqsave(&ioapic_lock, flags);
 486         __ioapic_write_entry(apic, pin, e);
 487         spin_unlock_irqrestore(&ioapic_lock, flags);
 488 }
 489
 490 /*
 491  * When we mask an IO APIC routing entry, we need to write the low
 492  * word first, in order to set the mask bit before we change the
 493  * high bits!
 494  */
 495 static void ioapic_mask_entry(int apic, int pin)
 496 {
 497         unsigned long flags;
 498         union entry_union eu = { .entry.mask = 1 };
 499
 500         spin_lock_irqsave(&ioapic_lock, flags);
 501         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 502         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 503         spin_unlock_irqrestore(&ioapic_lock, flags);
 504 }
 505
 506 #ifdef CONFIG_SMP
 507 static void send_cleanup_vector(struct irq_cfg *cfg)
 508 {
 509         cpumask_var_t cleanup_mask;
 510
 511         if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
 512                 unsigned int i;
 513                 cfg->move_cleanup_count = 0;
 514                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
 515                         cfg->move_cleanup_count++;
 516                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
 517                         apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
 518         } else {
 519                 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
 520                 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
 521                 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
 522                 free_cpumask_var(cleanup_mask);
 523         }
 524         cfg->move_in_progress = 0;
 525 }
 526
 527 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
 528 {
 529         int apic, pin;
 530         struct irq_pin_list *entry;
 531         u8 vector = cfg->vector;
 532
 533         entry = cfg->irq_2_pin;
 534         for (;;) {
 535                 unsigned int reg;
 536
 537                 if (!entry)
 538                         break;
 539
 540                 apic = entry->apic;
 541                 pin = entry->pin;
 542 #ifdef CONFIG_INTR_REMAP
 543                 /*
 544                  * With interrupt-remapping, destination information comes
 545                  * from interrupt-remapping table entry.
 546                  */
 547                 if (!irq_remapped(irq))
 548                         io_apic_write(apic, 0x11 + pin*2, dest);
 549 #else
 550                 io_apic_write(apic, 0x11 + pin*2, dest);
 551 #endif
 552                 reg = io_apic_read(apic, 0x10 + pin*2);
 553                 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
 554                 reg |= vector;
 555                 io_apic_modify(apic, 0x10 + pin*2, reg);
 556                 if (!entry->next)
 557                         break;
 558                 entry = entry->next;
 559         }
 560 }
 561
 562 static int
 563 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
 564
 565 /*
 566  * Either sets desc->affinity to a valid value, and returns
 567  * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
 568  * leaves desc->affinity untouched.
 569  */
 570 static unsigned int
 571 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
 572 {
 573         struct irq_cfg *cfg;
 574         unsigned int irq;
 575
 576         if (!cpumask_intersects(mask, cpu_online_mask))
 577                 return BAD_APICID;
 578
 579         irq = desc->irq;
 580         cfg = desc->chip_data;
 581         if (assign_irq_vector(irq, cfg, mask))
 582                 return BAD_APICID;
 583
 584         cpumask_and(desc->affinity, cfg->domain, mask);
 585         set_extra_move_desc(desc, mask);
 586
 587         return apic->cpu_mask_to_apicid_and(desc->affinity, cpu_online_mask);
 588 }
 589
 590 static void
 591 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
 592 {
 593         struct irq_cfg *cfg;
 594         unsigned long flags;
 595         unsigned int dest;
 596         unsigned int irq;
 597
 598         irq = desc->irq;
 599         cfg = desc->chip_data;
 600
 601         spin_lock_irqsave(&ioapic_lock, flags);
 602         dest = set_desc_affinity(desc, mask);
 603         if (dest != BAD_APICID) {
 604                 /* Only the high 8 bits are valid. */
 605                 dest = SET_APIC_LOGICAL_ID(dest);
 606                 __target_IO_APIC_irq(irq, dest, cfg);
 607         }
 608         spin_unlock_irqrestore(&ioapic_lock, flags);
 609 }
 610
 611 static void
 612 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
 613 {
 614         struct irq_desc *desc;
 615
 616         desc = irq_to_desc(irq);
 617
 618         set_ioapic_affinity_irq_desc(desc, mask);
 619 }
 620 #endif /* CONFIG_SMP */
 621
 622 /*
 623  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 624  * shared ISA-space IRQs, so we have to support them. We are super
 625  * fast in the common case, and fast for shared ISA-space IRQs.
 626  */
 627 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
 628 {
 629         struct irq_pin_list *entry;
 630
 631         entry = cfg->irq_2_pin;
 632         if (!entry) {
 633                 entry = get_one_free_irq_2_pin(cpu);
 634                 if (!entry) {
 635                         printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
 636                                         apic, pin);
 637                         return;
 638                 }
 639                 cfg->irq_2_pin = entry;
 640                 entry->apic = apic;
 641                 entry->pin = pin;
 642                 return;
 643         }
 644
 645         while (entry->next) {
 646                 /* not again, please */
 647                 if (entry->apic == apic && entry->pin == pin)
 648                         return;
 649
 650                 entry = entry->next;
 651         }
 652
 653         entry->next = get_one_free_irq_2_pin(cpu);
 654         entry = entry->next;
 655         entry->apic = apic;
 656         entry->pin = pin;
 657 }
 658
 659 /*
 660  * Reroute an IRQ to a different pin.
 661  */
 662 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
 663                                       int oldapic, int oldpin,
 664                                       int newapic, int newpin)
 665 {
 666         struct irq_pin_list *entry = cfg->irq_2_pin;
 667         int replaced = 0;
 668
 669         while (entry) {
 670                 if (entry->apic == oldapic && entry->pin == oldpin) {
 671                         entry->apic = newapic;
 672                         entry->pin = newpin;
 673                         replaced = 1;
 674                         /* every one is different, right? */
 675                         break;
 676                 }
 677                 entry = entry->next;
 678         }
 679
 680         /* why? call replace before add? */
 681         if (!replaced)
 682                 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
 683 }
 684
 685 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
 686                                 int mask_and, int mask_or,
 687                                 void (*final)(struct irq_pin_list *entry))
 688 {
 689         int pin;
 690         struct irq_pin_list *entry;
 691
 692         for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
 693                 unsigned int reg;
 694                 pin = entry->pin;
 695                 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
 696                 reg &= mask_and;
 697                 reg |= mask_or;
 698                 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
 699                 if (final)
 700                         final(entry);
 701         }
 702 }
 703
 704 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
 705 {
 706         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
 707 }
 708
 709 #ifdef CONFIG_X86_64
 710 static void io_apic_sync(struct irq_pin_list *entry)
 711 {
 712         /*
 713          * Synchronize the IO-APIC and the CPU by doing
 714          * a dummy read from the IO-APIC
 715          */
 716         struct io_apic __iomem *io_apic;
 717         io_apic = io_apic_base(entry->apic);
 718         readl(&io_apic->data);
 719 }
 720
 721 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 722 {
 723         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
 724 }
 725 #else /* CONFIG_X86_32 */
 726 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 727 {
 728         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
 729 }
 730
 731 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
 732 {
 733         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
 734                         IO_APIC_REDIR_MASKED, NULL);
 735 }
 736
 737 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
 738 {
 739         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
 740                         IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
 741 }
 742 #endif /* CONFIG_X86_32 */
 743
 744 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
 745 {
 746         struct irq_cfg *cfg = desc->chip_data;
 747         unsigned long flags;
 748
 749         BUG_ON(!cfg);
 750
 751         spin_lock_irqsave(&ioapic_lock, flags);
 752         __mask_IO_APIC_irq(cfg);
 753         spin_unlock_irqrestore(&ioapic_lock, flags);
 754 }
 755
 756 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
 757 {
 758         struct irq_cfg *cfg = desc->chip_data;
 759         unsigned long flags;
 760
 761         spin_lock_irqsave(&ioapic_lock, flags);
 762         __unmask_IO_APIC_irq(cfg);
 763         spin_unlock_irqrestore(&ioapic_lock, flags);
 764 }
 765
 766 static void mask_IO_APIC_irq(unsigned int irq)
 767 {
 768         struct irq_desc *desc = irq_to_desc(irq);
 769
 770         mask_IO_APIC_irq_desc(desc);
 771 }
 772 static void unmask_IO_APIC_irq(unsigned int irq)
 773 {
 774         struct irq_desc *desc = irq_to_desc(irq);
 775
 776         unmask_IO_APIC_irq_desc(desc);
 777 }
 778
 779 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 780 {
 781         struct IO_APIC_route_entry entry;
 782
 783         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 784         entry = ioapic_read_entry(apic, pin);
 785         if (entry.delivery_mode == dest_SMI)
 786                 return;
 787         /*
 788          * Disable it in the IO-APIC irq-routing table:
 789          */
 790         ioapic_mask_entry(apic, pin);
 791 }
 792
 793 static void clear_IO_APIC (void)
 794 {
 795         int apic, pin;
 796
 797         for (apic = 0; apic < nr_ioapics; apic++)
 798                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 799                         clear_IO_APIC_pin(apic, pin);
 800 }
 801
 802 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
 803 void default_send_IPI_self(int vector)
 804 {
 805         unsigned int cfg;
 806
 807         /*
 808          * Wait for idle.
 809          */
 810         apic_wait_icr_idle();
 811         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | apic->dest_logical;
 812         /*
 813          * Send the IPI. The write to APIC_ICR fires this off.
 814          */
 815         apic_write(APIC_ICR, cfg);
 816 }
 817 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
 818
 819 #ifdef CONFIG_X86_32
 820 /*
 821  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 822  * specific CPU-side IRQs.
 823  */
 824
 825 #define MAX_PIRQS 8
 826 static int pirq_entries [MAX_PIRQS];
 827 static int pirqs_enabled;
 828
 829 static int __init ioapic_pirq_setup(char *str)
 830 {
 831         int i, max;
 832         int ints[MAX_PIRQS+1];
 833
 834         get_options(str, ARRAY_SIZE(ints), ints);
 835
 836         for (i = 0; i < MAX_PIRQS; i++)
 837                 pirq_entries[i] = -1;
 838
 839         pirqs_enabled = 1;
 840         apic_printk(APIC_VERBOSE, KERN_INFO
 841                         "PIRQ redirection, working around broken MP-BIOS.\n");
 842         max = MAX_PIRQS;
 843         if (ints[0] < MAX_PIRQS)
 844                 max = ints[0];
 845
 846         for (i = 0; i < max; i++) {
 847                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 848                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 849                 /*
 850                  * PIRQs are mapped upside down, usually.
 851                  */
 852                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 853         }
 854         return 1;
 855 }
 856
 857 __setup("pirq=", ioapic_pirq_setup);
 858 #endif /* CONFIG_X86_32 */
 859
 860 #ifdef CONFIG_INTR_REMAP
 861 /* I/O APIC RTE contents at the OS boot up */
 862 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
 863
 864 /*
 865  * Saves and masks all the unmasked IO-APIC RTE's
 866  */
 867 int save_mask_IO_APIC_setup(void)
 868 {
 869         union IO_APIC_reg_01 reg_01;
 870         unsigned long flags;
 871         int apic, pin;
 872
 873         /*
 874          * The number of IO-APIC IRQ registers (== #pins):
 875          */
 876         for (apic = 0; apic < nr_ioapics; apic++) {
 877                 spin_lock_irqsave(&ioapic_lock, flags);
 878                 reg_01.raw = io_apic_read(apic, 1);
 879                 spin_unlock_irqrestore(&ioapic_lock, flags);
 880                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
 881         }
 882
 883         for (apic = 0; apic < nr_ioapics; apic++) {
 884                 early_ioapic_entries[apic] =
 885                         kzalloc(sizeof(struct IO_APIC_route_entry) *
 886                                 nr_ioapic_registers[apic], GFP_KERNEL);
 887                 if (!early_ioapic_entries[apic])
 888                         goto nomem;
 889         }
 890
 891         for (apic = 0; apic < nr_ioapics; apic++)
 892                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 893                         struct IO_APIC_route_entry entry;
 894
 895                         entry = early_ioapic_entries[apic][pin] =
 896                                 ioapic_read_entry(apic, pin);
 897                         if (!entry.mask) {
 898                                 entry.mask = 1;
 899                                 ioapic_write_entry(apic, pin, entry);
 900                         }
 901                 }
 902
 903         return 0;
 904
 905 nomem:
 906         while (apic >= 0)
 907                 kfree(early_ioapic_entries[apic--]);
 908         memset(early_ioapic_entries, 0,
 909                 ARRAY_SIZE(early_ioapic_entries));
 910
 911         return -ENOMEM;
 912 }
 913
 914 void restore_IO_APIC_setup(void)
 915 {
 916         int apic, pin;
 917
 918         for (apic = 0; apic < nr_ioapics; apic++) {
 919                 if (!early_ioapic_entries[apic])
 920                         break;
 921                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 922                         ioapic_write_entry(apic, pin,
 923                                            early_ioapic_entries[apic][pin]);
 924                 kfree(early_ioapic_entries[apic]);
 925                 early_ioapic_entries[apic] = NULL;
 926         }
 927 }
 928
 929 void reinit_intr_remapped_IO_APIC(int intr_remapping)
 930 {
 931         /*
 932          * for now plain restore of previous settings.
 933          * TBD: In the case of OS enabling interrupt-remapping,
 934          * IO-APIC RTE's need to be setup to point to interrupt-remapping
 935          * table entries. for now, do a plain restore, and wait for
 936          * the setup_IO_APIC_irqs() to do proper initialization.
 937          */
 938         restore_IO_APIC_setup();
 939 }
 940 #endif
 941
 942 /*
 943  * Find the IRQ entry number of a certain pin.
 944  */
 945 static int find_irq_entry(int apic, int pin, int type)
 946 {
 947         int i;
 948
 949         for (i = 0; i < mp_irq_entries; i++)
 950                 if (mp_irqs[i].irqtype == type &&
 951                     (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
 952                      mp_irqs[i].dstapic == MP_APIC_ALL) &&
 953                     mp_irqs[i].dstirq == pin)
 954                         return i;
 955
 956         return -1;
 957 }
 958
 959 /*
 960  * Find the pin to which IRQ[irq] (ISA) is connected
 961  */
 962 static int __init find_isa_irq_pin(int irq, int type)
 963 {
 964         int i;
 965
 966         for (i = 0; i < mp_irq_entries; i++) {
 967                 int lbus = mp_irqs[i].srcbus;
 968
 969                 if (test_bit(lbus, mp_bus_not_pci) &&
 970                     (mp_irqs[i].irqtype == type) &&
 971                     (mp_irqs[i].srcbusirq == irq))
 972
 973                         return mp_irqs[i].dstirq;
 974         }
 975         return -1;
 976 }
 977
 978 static int __init find_isa_irq_apic(int irq, int type)
 979 {
 980         int i;
 981
 982         for (i = 0; i < mp_irq_entries; i++) {
 983                 int lbus = mp_irqs[i].srcbus;
 984
 985                 if (test_bit(lbus, mp_bus_not_pci) &&
 986                     (mp_irqs[i].irqtype == type) &&
 987                     (mp_irqs[i].srcbusirq == irq))
 988                         break;
 989         }
 990         if (i < mp_irq_entries) {
 991                 int apic;
 992                 for(apic = 0; apic < nr_ioapics; apic++) {
 993                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
 994                                 return apic;
 995                 }
 996         }
 997
 998         return -1;
 999 }
1000
1001 /*
1002  * Find a specific PCI IRQ entry.
1003  * Not an __init, possibly needed by modules
1004  */
1005 static int pin_2_irq(int idx, int apic, int pin);
1006
1007 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1008 {
1009         int apic, i, best_guess = -1;
1010
1011         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1012                 bus, slot, pin);
1013         if (test_bit(bus, mp_bus_not_pci)) {
1014                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1015                 return -1;
1016         }
1017         for (i = 0; i < mp_irq_entries; i++) {
1018                 int lbus = mp_irqs[i].srcbus;
1019
1020                 for (apic = 0; apic < nr_ioapics; apic++)
1021                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1022                             mp_irqs[i].dstapic == MP_APIC_ALL)
1023                                 break;
1024
1025                 if (!test_bit(lbus, mp_bus_not_pci) &&
1026                     !mp_irqs[i].irqtype &&
1027                     (bus == lbus) &&
1028                     (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1029                         int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1030
1031                         if (!(apic || IO_APIC_IRQ(irq)))
1032                                 continue;
1033
1034                         if (pin == (mp_irqs[i].srcbusirq & 3))
1035                                 return irq;
1036                         /*
1037                          * Use the first all-but-pin matching entry as a
1038                          * best-guess fuzzy result for broken mptables.
1039                          */
1040                         if (best_guess < 0)
1041                                 best_guess = irq;
1042                 }
1043         }
1044         return best_guess;
1045 }
1046
1047 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1048
1049 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1050 /*
1051  * EISA Edge/Level control register, ELCR
1052  */
1053 static int EISA_ELCR(unsigned int irq)
1054 {
1055         if (irq < NR_IRQS_LEGACY) {
1056                 unsigned int port = 0x4d0 + (irq >> 3);
1057                 return (inb(port) >> (irq & 7)) & 1;
1058         }
1059         apic_printk(APIC_VERBOSE, KERN_INFO
1060                         "Broken MPtable reports ISA irq %d\n", irq);
1061         return 0;
1062 }
1063
1064 #endif
1065
1066 /* ISA interrupts are always polarity zero edge triggered,
1067  * when listed as conforming in the MP table. */
1068
1069 #define default_ISA_trigger(idx)        (0)
1070 #define default_ISA_polarity(idx)       (0)
1071
1072 /* EISA interrupts are always polarity zero and can be edge or level
1073  * trigger depending on the ELCR value.  If an interrupt is listed as
1074  * EISA conforming in the MP table, that means its trigger type must
1075  * be read in from the ELCR */
1076
1077 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].srcbusirq))
1078 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
1079
1080 /* PCI interrupts are always polarity one level triggered,
1081  * when listed as conforming in the MP table. */
1082
1083 #define default_PCI_trigger(idx)        (1)
1084 #define default_PCI_polarity(idx)       (1)
1085
1086 /* MCA interrupts are always polarity zero level triggered,
1087  * when listed as conforming in the MP table. */
1088
1089 #define default_MCA_trigger(idx)        (1)
1090 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
1091
1092 static int MPBIOS_polarity(int idx)
1093 {
1094         int bus = mp_irqs[idx].srcbus;
1095         int polarity;
1096
1097         /*
1098          * Determine IRQ line polarity (high active or low active):
1099          */
1100         switch (mp_irqs[idx].irqflag & 3)
1101         {
1102                 case 0: /* conforms, ie. bus-type dependent polarity */
1103                         if (test_bit(bus, mp_bus_not_pci))
1104                                 polarity = default_ISA_polarity(idx);
1105                         else
1106                                 polarity = default_PCI_polarity(idx);
1107                         break;
1108                 case 1: /* high active */
1109                 {
1110                         polarity = 0;
1111                         break;
1112                 }
1113                 case 2: /* reserved */
1114                 {
1115                         printk(KERN_WARNING "broken BIOS!!\n");
1116                         polarity = 1;
1117                         break;
1118                 }
1119                 case 3: /* low active */
1120                 {
1121                         polarity = 1;
1122                         break;
1123                 }
1124                 default: /* invalid */
1125                 {
1126                         printk(KERN_WARNING "broken BIOS!!\n");
1127                         polarity = 1;
1128                         break;
1129                 }
1130         }
1131         return polarity;
1132 }
1133
1134 static int MPBIOS_trigger(int idx)
1135 {
1136         int bus = mp_irqs[idx].srcbus;
1137         int trigger;
1138
1139         /*
1140          * Determine IRQ trigger mode (edge or level sensitive):
1141          */
1142         switch ((mp_irqs[idx].irqflag>>2) & 3)
1143         {
1144                 case 0: /* conforms, ie. bus-type dependent */
1145                         if (test_bit(bus, mp_bus_not_pci))
1146                                 trigger = default_ISA_trigger(idx);
1147                         else
1148                                 trigger = default_PCI_trigger(idx);
1149 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1150                         switch (mp_bus_id_to_type[bus]) {
1151                                 case MP_BUS_ISA: /* ISA pin */
1152                                 {
1153                                         /* set before the switch */
1154                                         break;
1155                                 }
1156                                 case MP_BUS_EISA: /* EISA pin */
1157                                 {
1158                                         trigger = default_EISA_trigger(idx);
1159                                         break;
1160                                 }
1161                                 case MP_BUS_PCI: /* PCI pin */
1162                                 {
1163                                         /* set before the switch */
1164                                         break;
1165                                 }
1166                                 case MP_BUS_MCA: /* MCA pin */
1167                                 {
1168                                         trigger = default_MCA_trigger(idx);
1169                                         break;
1170                                 }
1171                                 default:
1172                                 {
1173                                         printk(KERN_WARNING "broken BIOS!!\n");
1174                                         trigger = 1;
1175                                         break;
1176                                 }
1177                         }
1178 #endif
1179                         break;
1180                 case 1: /* edge */
1181                 {
1182                         trigger = 0;
1183                         break;
1184                 }
1185                 case 2: /* reserved */
1186                 {
1187                         printk(KERN_WARNING "broken BIOS!!\n");
1188                         trigger = 1;
1189                         break;
1190                 }
1191                 case 3: /* level */
1192                 {
1193                         trigger = 1;
1194                         break;
1195                 }
1196                 default: /* invalid */
1197                 {
1198                         printk(KERN_WARNING "broken BIOS!!\n");
1199                         trigger = 0;
1200                         break;
1201                 }
1202         }
1203         return trigger;
1204 }
1205
1206 static inline int irq_polarity(int idx)
1207 {
1208         return MPBIOS_polarity(idx);
1209 }
1210
1211 static inline int irq_trigger(int idx)
1212 {
1213         return MPBIOS_trigger(idx);
1214 }
1215
1216 int (*ioapic_renumber_irq)(int ioapic, int irq);
1217 static int pin_2_irq(int idx, int apic, int pin)
1218 {
1219         int irq, i;
1220         int bus = mp_irqs[idx].srcbus;
1221
1222         /*
1223          * Debugging check, we are in big trouble if this message pops up!
1224          */
1225         if (mp_irqs[idx].dstirq != pin)
1226                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1227
1228         if (test_bit(bus, mp_bus_not_pci)) {
1229                 irq = mp_irqs[idx].srcbusirq;
1230         } else {
1231                 /*
1232                  * PCI IRQs are mapped in order
1233                  */
1234                 i = irq = 0;
1235                 while (i < apic)
1236                         irq += nr_ioapic_registers[i++];
1237                 irq += pin;
1238                 /*
1239                  * For MPS mode, so far only needed by ES7000 platform
1240                  */
1241                 if (ioapic_renumber_irq)
1242                         irq = ioapic_renumber_irq(apic, irq);
1243         }
1244
1245 #ifdef CONFIG_X86_32
1246         /*
1247          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1248          */
1249         if ((pin >= 16) && (pin <= 23)) {
1250                 if (pirq_entries[pin-16] != -1) {
1251                         if (!pirq_entries[pin-16]) {
1252                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1253                                                 "disabling PIRQ%d\n", pin-16);
1254                         } else {
1255                                 irq = pirq_entries[pin-16];
1256                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1257                                                 "using PIRQ%d -> IRQ %d\n",
1258                                                 pin-16, irq);
1259                         }
1260                 }
1261         }
1262 #endif
1263
1264         return irq;
1265 }
1266
1267 void lock_vector_lock(void)
1268 {
1269         /* Used to the online set of cpus does not change
1270          * during assign_irq_vector.
1271          */
1272         spin_lock(&vector_lock);
1273 }
1274
1275 void unlock_vector_lock(void)
1276 {
1277         spin_unlock(&vector_lock);
1278 }
1279
1280 static int
1281 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1282 {
1283         /*
1284          * NOTE! The local APIC isn't very good at handling
1285          * multiple interrupts at the same interrupt level.
1286          * As the interrupt level is determined by taking the
1287          * vector number and shifting that right by 4, we
1288          * want to spread these out a bit so that they don't
1289          * all fall in the same interrupt level.
1290          *
1291          * Also, we've got to be careful not to trash gate
1292          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1293          */
1294         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1295         unsigned int old_vector;
1296         int cpu, err;
1297         cpumask_var_t tmp_mask;
1298
1299         if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1300                 return -EBUSY;
1301
1302         if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1303                 return -ENOMEM;
1304
1305         old_vector = cfg->vector;
1306         if (old_vector) {
1307                 cpumask_and(tmp_mask, mask, cpu_online_mask);
1308                 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1309                 if (!cpumask_empty(tmp_mask)) {
1310                         free_cpumask_var(tmp_mask);
1311                         return 0;
1312                 }
1313         }
1314
1315         /* Only try and allocate irqs on cpus that are present */
1316         err = -ENOSPC;
1317         for_each_cpu_and(cpu, mask, cpu_online_mask) {
1318                 int new_cpu;
1319                 int vector, offset;
1320
1321                 apic->vector_allocation_domain(cpu, tmp_mask);
1322
1323                 vector = current_vector;
1324                 offset = current_offset;
1325 next:
1326                 vector += 8;
1327                 if (vector >= first_system_vector) {
1328                         /* If out of vectors on large boxen, must share them. */
1329                         offset = (offset + 1) % 8;
1330                         vector = FIRST_DEVICE_VECTOR + offset;
1331                 }
1332                 if (unlikely(current_vector == vector))
1333                         continue;
1334
1335                 if (test_bit(vector, used_vectors))
1336                         goto next;
1337
1338                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1339                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1340                                 goto next;
1341                 /* Found one! */
1342                 current_vector = vector;
1343                 current_offset = offset;
1344                 if (old_vector) {
1345                         cfg->move_in_progress = 1;
1346                         cpumask_copy(cfg->old_domain, cfg->domain);
1347                 }
1348                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1349                         per_cpu(vector_irq, new_cpu)[vector] = irq;
1350                 cfg->vector = vector;
1351                 cpumask_copy(cfg->domain, tmp_mask);
1352                 err = 0;
1353                 break;
1354         }
1355         free_cpumask_var(tmp_mask);
1356         return err;
1357 }
1358
1359 static int
1360 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1361 {
1362         int err;
1363         unsigned long flags;
1364
1365         spin_lock_irqsave(&vector_lock, flags);
1366         err = __assign_irq_vector(irq, cfg, mask);
1367         spin_unlock_irqrestore(&vector_lock, flags);
1368         return err;
1369 }
1370
1371 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1372 {
1373         int cpu, vector;
1374
1375         BUG_ON(!cfg->vector);
1376
1377         vector = cfg->vector;
1378         for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1379                 per_cpu(vector_irq, cpu)[vector] = -1;
1380
1381         cfg->vector = 0;
1382         cpumask_clear(cfg->domain);
1383
1384         if (likely(!cfg->move_in_progress))
1385                 return;
1386         for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1387                 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1388                                                                 vector++) {
1389                         if (per_cpu(vector_irq, cpu)[vector] != irq)
1390                                 continue;
1391                         per_cpu(vector_irq, cpu)[vector] = -1;
1392                         break;
1393                 }
1394         }
1395         cfg->move_in_progress = 0;
1396 }
1397
1398 void __setup_vector_irq(int cpu)
1399 {
1400         /* Initialize vector_irq on a new cpu */
1401         /* This function must be called with vector_lock held */
1402         int irq, vector;
1403         struct irq_cfg *cfg;
1404         struct irq_desc *desc;
1405
1406         /* Mark the inuse vectors */
1407         for_each_irq_desc(irq, desc) {
1408                 cfg = desc->chip_data;
1409                 if (!cpumask_test_cpu(cpu, cfg->domain))
1410                         continue;
1411                 vector = cfg->vector;
1412                 per_cpu(vector_irq, cpu)[vector] = irq;
1413         }
1414         /* Mark the free vectors */
1415         for (vector = 0; vector < NR_VECTORS; ++vector) {
1416                 irq = per_cpu(vector_irq, cpu)[vector];
1417                 if (irq < 0)
1418                         continue;
1419
1420                 cfg = irq_cfg(irq);
1421                 if (!cpumask_test_cpu(cpu, cfg->domain))
1422                         per_cpu(vector_irq, cpu)[vector] = -1;
1423         }
1424 }
1425
1426 static struct irq_chip ioapic_chip;
1427 #ifdef CONFIG_INTR_REMAP
1428 static struct irq_chip ir_ioapic_chip;
1429 #endif
1430
1431 #define IOAPIC_AUTO     -1
1432 #define IOAPIC_EDGE     0
1433 #define IOAPIC_LEVEL    1
1434
1435 #ifdef CONFIG_X86_32
1436 static inline int IO_APIC_irq_trigger(int irq)
1437 {
1438         int apic, idx, pin;
1439
1440         for (apic = 0; apic < nr_ioapics; apic++) {
1441                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1442                         idx = find_irq_entry(apic, pin, mp_INT);
1443                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1444                                 return irq_trigger(idx);
1445                 }
1446         }
1447         /*
1448          * nonexistent IRQs are edge default
1449          */
1450         return 0;
1451 }
1452 #else
1453 static inline int IO_APIC_irq_trigger(int irq)
1454 {
1455         return 1;
1456 }
1457 #endif
1458
1459 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1460 {
1461
1462         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1463             trigger == IOAPIC_LEVEL)
1464                 desc->status |= IRQ_LEVEL;
1465         else
1466                 desc->status &= ~IRQ_LEVEL;
1467
1468 #ifdef CONFIG_INTR_REMAP
1469         if (irq_remapped(irq)) {
1470                 desc->status |= IRQ_MOVE_PCNTXT;
1471                 if (trigger)
1472                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1473                                                       handle_fasteoi_irq,
1474                                                      "fasteoi");
1475                 else
1476                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1477                                                       handle_edge_irq, "edge");
1478                 return;
1479         }
1480 #endif
1481         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1482             trigger == IOAPIC_LEVEL)
1483                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1484                                               handle_fasteoi_irq,
1485                                               "fasteoi");
1486         else
1487                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1488                                               handle_edge_irq, "edge");
1489 }
1490
1491 static int setup_ioapic_entry(int apic_id, int irq,
1492                               struct IO_APIC_route_entry *entry,
1493                               unsigned int destination, int trigger,
1494                               int polarity, int vector)
1495 {
1496         /*
1497          * add it to the IO-APIC irq-routing table:
1498          */
1499         memset(entry,0,sizeof(*entry));
1500
1501 #ifdef CONFIG_INTR_REMAP
1502         if (intr_remapping_enabled) {
1503                 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1504                 struct irte irte;
1505                 struct IR_IO_APIC_route_entry *ir_entry =
1506                         (struct IR_IO_APIC_route_entry *) entry;
1507                 int index;
1508
1509                 if (!iommu)
1510                         panic("No mapping iommu for ioapic %d\n", apic_id);
1511
1512                 index = alloc_irte(iommu, irq, 1);
1513                 if (index < 0)
1514                         panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1515
1516                 memset(&irte, 0, sizeof(irte));
1517
1518                 irte.present = 1;
1519                 irte.dst_mode = apic->irq_dest_mode;
1520                 irte.trigger_mode = trigger;
1521                 irte.dlvry_mode = apic->irq_delivery_mode;
1522                 irte.vector = vector;
1523                 irte.dest_id = IRTE_DEST(destination);
1524
1525                 modify_irte(irq, &irte);
1526
1527                 ir_entry->index2 = (index >> 15) & 0x1;
1528                 ir_entry->zero = 0;
1529                 ir_entry->format = 1;
1530                 ir_entry->index = (index & 0x7fff);
1531         } else
1532 #endif
1533         {
1534                 entry->delivery_mode = apic->irq_delivery_mode;
1535                 entry->dest_mode = apic->irq_dest_mode;
1536                 entry->dest = destination;
1537         }
1538
1539         entry->mask = 0;                                /* enable IRQ */
1540         entry->trigger = trigger;
1541         entry->polarity = polarity;
1542         entry->vector = vector;
1543
1544         /* Mask level triggered irqs.
1545          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1546          */
1547         if (trigger)
1548                 entry->mask = 1;
1549         return 0;
1550 }
1551
1552 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1553                               int trigger, int polarity)
1554 {
1555         struct irq_cfg *cfg;
1556         struct IO_APIC_route_entry entry;
1557         unsigned int dest;
1558
1559         if (!IO_APIC_IRQ(irq))
1560                 return;
1561
1562         cfg = desc->chip_data;
1563
1564         if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1565                 return;
1566
1567         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1568
1569         apic_printk(APIC_VERBOSE,KERN_DEBUG
1570                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1571                     "IRQ %d Mode:%i Active:%i)\n",
1572                     apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1573                     irq, trigger, polarity);
1574
1575
1576         if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1577                                dest, trigger, polarity, cfg->vector)) {
1578                 printk("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
1579                        mp_ioapics[apic_id].apicid, pin);
1580                 __clear_irq_vector(irq, cfg);
1581                 return;
1582         }
1583
1584         ioapic_register_intr(irq, desc, trigger);
1585         if (irq < NR_IRQS_LEGACY)
1586                 disable_8259A_irq(irq);
1587
1588         ioapic_write_entry(apic_id, pin, entry);
1589 }
1590
1591 static void __init setup_IO_APIC_irqs(void)
1592 {
1593         int apic_id, pin, idx, irq;
1594         int notcon = 0;
1595         struct irq_desc *desc;
1596         struct irq_cfg *cfg;
1597         int cpu = boot_cpu_id;
1598
1599         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1600
1601         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1602                 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1603
1604                         idx = find_irq_entry(apic_id, pin, mp_INT);
1605                         if (idx == -1) {
1606                                 if (!notcon) {
1607                                         notcon = 1;
1608                                         apic_printk(APIC_VERBOSE,
1609                                                 KERN_DEBUG " %d-%d",
1610                                                 mp_ioapics[apic_id].apicid, pin);
1611                                 } else
1612                                         apic_printk(APIC_VERBOSE, " %d-%d",
1613                                                 mp_ioapics[apic_id].apicid, pin);
1614                                 continue;
1615                         }
1616                         if (notcon) {
1617                                 apic_printk(APIC_VERBOSE,
1618                                         " (apicid-pin) not connected\n");
1619                                 notcon = 0;
1620                         }
1621
1622                         irq = pin_2_irq(idx, apic_id, pin);
1623
1624                         /*
1625                          * Skip the timer IRQ if there's a quirk handler
1626                          * installed and if it returns 1:
1627                          */
1628                         if (apic->multi_timer_check &&
1629                                         apic->multi_timer_check(apic_id, irq))
1630                                 continue;
1631
1632                         desc = irq_to_desc_alloc_cpu(irq, cpu);
1633                         if (!desc) {
1634                                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1635                                 continue;
1636                         }
1637                         cfg = desc->chip_data;
1638                         add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1639
1640                         setup_IO_APIC_irq(apic_id, pin, irq, desc,
1641                                         irq_trigger(idx), irq_polarity(idx));
1642                 }
1643         }
1644
1645         if (notcon)
1646                 apic_printk(APIC_VERBOSE,
1647                         " (apicid-pin) not connected\n");
1648 }
1649
1650 /*
1651  * Set up the timer pin, possibly with the 8259A-master behind.
1652  */
1653 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1654                                         int vector)
1655 {
1656         struct IO_APIC_route_entry entry;
1657
1658 #ifdef CONFIG_INTR_REMAP
1659         if (intr_remapping_enabled)
1660                 return;
1661 #endif
1662
1663         memset(&entry, 0, sizeof(entry));
1664
1665         /*
1666          * We use logical delivery to get the timer IRQ
1667          * to the first CPU.
1668          */
1669         entry.dest_mode = apic->irq_dest_mode;
1670         entry.mask = 1;                                 /* mask IRQ now */
1671         entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1672         entry.delivery_mode = apic->irq_delivery_mode;
1673         entry.polarity = 0;
1674         entry.trigger = 0;
1675         entry.vector = vector;
1676
1677         /*
1678          * The timer IRQ doesn't have to know that behind the
1679          * scene we may have a 8259A-master in AEOI mode ...
1680          */
1681         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1682
1683         /*
1684          * Add it to the IO-APIC irq-routing table:
1685          */
1686         ioapic_write_entry(apic_id, pin, entry);
1687 }
1688
1689
1690 __apicdebuginit(void) print_IO_APIC(void)
1691 {
1692         int apic, i;
1693         union IO_APIC_reg_00 reg_00;
1694         union IO_APIC_reg_01 reg_01;
1695         union IO_APIC_reg_02 reg_02;
1696         union IO_APIC_reg_03 reg_03;
1697         unsigned long flags;
1698         struct irq_cfg *cfg;
1699         struct irq_desc *desc;
1700         unsigned int irq;
1701
1702         if (apic_verbosity == APIC_QUIET)
1703                 return;
1704
1705         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1706         for (i = 0; i < nr_ioapics; i++)
1707                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1708                        mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1709
1710         /*
1711          * We are a bit conservative about what we expect.  We have to
1712          * know about every hardware change ASAP.
1713          */
1714         printk(KERN_INFO "testing the IO APIC.......................\n");
1715
1716         for (apic = 0; apic < nr_ioapics; apic++) {
1717
1718         spin_lock_irqsave(&ioapic_lock, flags);
1719         reg_00.raw = io_apic_read(apic, 0);
1720         reg_01.raw = io_apic_read(apic, 1);
1721         if (reg_01.bits.version >= 0x10)
1722                 reg_02.raw = io_apic_read(apic, 2);
1723         if (reg_01.bits.version >= 0x20)
1724                 reg_03.raw = io_apic_read(apic, 3);
1725         spin_unlock_irqrestore(&ioapic_lock, flags);
1726
1727         printk("\n");
1728         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1729         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1730         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1731         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1732         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1733
1734         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1735         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1736
1737         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1738         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1739
1740         /*
1741          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1742          * but the value of reg_02 is read as the previous read register
1743          * value, so ignore it if reg_02 == reg_01.
1744          */
1745         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1746                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1747                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1748         }
1749
1750         /*
1751          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1752          * or reg_03, but the value of reg_0[23] is read as the previous read
1753          * register value, so ignore it if reg_03 == reg_0[12].
1754          */
1755         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1756             reg_03.raw != reg_01.raw) {
1757                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1758                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1759         }
1760
1761         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1762
1763         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1764                           " Stat Dmod Deli Vect:   \n");
1765
1766         for (i = 0; i <= reg_01.bits.entries; i++) {
1767                 struct IO_APIC_route_entry entry;
1768
1769                 entry = ioapic_read_entry(apic, i);
1770
1771                 printk(KERN_DEBUG " %02x %03X ",
1772                         i,
1773                         entry.dest
1774                 );
1775
1776                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1777                         entry.mask,
1778                         entry.trigger,
1779                         entry.irr,
1780                         entry.polarity,
1781                         entry.delivery_status,
1782                         entry.dest_mode,
1783                         entry.delivery_mode,
1784                         entry.vector
1785                 );
1786         }
1787         }
1788         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1789         for_each_irq_desc(irq, desc) {
1790                 struct irq_pin_list *entry;
1791
1792                 cfg = desc->chip_data;
1793                 entry = cfg->irq_2_pin;
1794                 if (!entry)
1795                         continue;
1796                 printk(KERN_DEBUG "IRQ%d ", irq);
1797                 for (;;) {
1798                         printk("-> %d:%d", entry->apic, entry->pin);
1799                         if (!entry->next)
1800                                 break;
1801                         entry = entry->next;
1802                 }
1803                 printk("\n");
1804         }
1805
1806         printk(KERN_INFO ".................................... done.\n");
1807
1808         return;
1809 }
1810
1811 __apicdebuginit(void) print_APIC_bitfield(int base)
1812 {
1813         unsigned int v;
1814         int i, j;
1815
1816         if (apic_verbosity == APIC_QUIET)
1817                 return;
1818
1819         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1820         for (i = 0; i < 8; i++) {
1821                 v = apic_read(base + i*0x10);
1822                 for (j = 0; j < 32; j++) {
1823                         if (v & (1<<j))
1824                                 printk("1");
1825                         else
1826                                 printk("0");
1827                 }
1828                 printk("\n");
1829         }
1830 }
1831
1832 __apicdebuginit(void) print_local_APIC(void *dummy)
1833 {
1834         unsigned int v, ver, maxlvt;
1835         u64 icr;
1836
1837         if (apic_verbosity == APIC_QUIET)
1838                 return;
1839
1840         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1841                 smp_processor_id(), hard_smp_processor_id());
1842         v = apic_read(APIC_ID);
1843         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, read_apic_id());
1844         v = apic_read(APIC_LVR);
1845         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1846         ver = GET_APIC_VERSION(v);
1847         maxlvt = lapic_get_maxlvt();
1848
1849         v = apic_read(APIC_TASKPRI);
1850         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1851
1852         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1853                 if (!APIC_XAPIC(ver)) {
1854                         v = apic_read(APIC_ARBPRI);
1855                         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1856                                v & APIC_ARBPRI_MASK);
1857                 }
1858                 v = apic_read(APIC_PROCPRI);
1859                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1860         }
1861
1862         /*
1863          * Remote read supported only in the 82489DX and local APIC for
1864          * Pentium processors.
1865          */
1866         if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1867                 v = apic_read(APIC_RRR);
1868                 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1869         }
1870
1871         v = apic_read(APIC_LDR);
1872         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1873         if (!x2apic_enabled()) {
1874                 v = apic_read(APIC_DFR);
1875                 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1876         }
1877         v = apic_read(APIC_SPIV);
1878         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1879
1880         printk(KERN_DEBUG "... APIC ISR field:\n");
1881         print_APIC_bitfield(APIC_ISR);
1882         printk(KERN_DEBUG "... APIC TMR field:\n");
1883         print_APIC_bitfield(APIC_TMR);
1884         printk(KERN_DEBUG "... APIC IRR field:\n");
1885         print_APIC_bitfield(APIC_IRR);
1886
1887         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1888                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1889                         apic_write(APIC_ESR, 0);
1890
1891                 v = apic_read(APIC_ESR);
1892                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1893         }
1894
1895         icr = apic_icr_read();
1896         printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1897         printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1898
1899         v = apic_read(APIC_LVTT);
1900         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1901
1902         if (maxlvt > 3) {                       /* PC is LVT#4. */
1903                 v = apic_read(APIC_LVTPC);
1904                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1905         }
1906         v = apic_read(APIC_LVT0);
1907         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1908         v = apic_read(APIC_LVT1);
1909         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1910
1911         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1912                 v = apic_read(APIC_LVTERR);
1913                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1914         }
1915
1916         v = apic_read(APIC_TMICT);
1917         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1918         v = apic_read(APIC_TMCCT);
1919         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1920         v = apic_read(APIC_TDCR);
1921         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1922         printk("\n");
1923 }
1924
1925 __apicdebuginit(void) print_all_local_APICs(void)
1926 {
1927         int cpu;
1928
1929         preempt_disable();
1930         for_each_online_cpu(cpu)
1931                 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1932         preempt_enable();
1933 }
1934
1935 __apicdebuginit(void) print_PIC(void)
1936 {
1937         unsigned int v;
1938         unsigned long flags;
1939
1940         if (apic_verbosity == APIC_QUIET)
1941                 return;
1942
1943         printk(KERN_DEBUG "\nprinting PIC contents\n");
1944
1945         spin_lock_irqsave(&i8259A_lock, flags);
1946
1947         v = inb(0xa1) << 8 | inb(0x21);
1948         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1949
1950         v = inb(0xa0) << 8 | inb(0x20);
1951         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1952
1953         outb(0x0b,0xa0);
1954         outb(0x0b,0x20);
1955         v = inb(0xa0) << 8 | inb(0x20);
1956         outb(0x0a,0xa0);
1957         outb(0x0a,0x20);
1958
1959         spin_unlock_irqrestore(&i8259A_lock, flags);
1960
1961         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1962
1963         v = inb(0x4d1) << 8 | inb(0x4d0);
1964         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1965 }
1966
1967 __apicdebuginit(int) print_all_ICs(void)
1968 {
1969         print_PIC();
1970         print_all_local_APICs();
1971         print_IO_APIC();
1972
1973         return 0;
1974 }
1975
1976 fs_initcall(print_all_ICs);
1977
1978
1979 /* Where if anywhere is the i8259 connect in external int mode */
1980 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1981
1982 void __init enable_IO_APIC(void)
1983 {
1984         union IO_APIC_reg_01 reg_01;
1985         int i8259_apic, i8259_pin;
1986         int apic;
1987         unsigned long flags;
1988
1989 #ifdef CONFIG_X86_32
1990         int i;
1991         if (!pirqs_enabled)
1992                 for (i = 0; i < MAX_PIRQS; i++)
1993                         pirq_entries[i] = -1;
1994 #endif
1995
1996         /*
1997          * The number of IO-APIC IRQ registers (== #pins):
1998          */
1999         for (apic = 0; apic < nr_ioapics; apic++) {
2000                 spin_lock_irqsave(&ioapic_lock, flags);
2001                 reg_01.raw = io_apic_read(apic, 1);
2002                 spin_unlock_irqrestore(&ioapic_lock, flags);
2003                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
2004         }
2005         for(apic = 0; apic < nr_ioapics; apic++) {
2006                 int pin;
2007                 /* See if any of the pins is in ExtINT mode */
2008                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
2009                         struct IO_APIC_route_entry entry;
2010                         entry = ioapic_read_entry(apic, pin);
2011
2012                         /* If the interrupt line is enabled and in ExtInt mode
2013                          * I have found the pin where the i8259 is connected.
2014                          */
2015                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2016                                 ioapic_i8259.apic = apic;
2017                                 ioapic_i8259.pin  = pin;
2018                                 goto found_i8259;
2019                         }
2020                 }
2021         }
2022  found_i8259:
2023         /* Look to see what if the MP table has reported the ExtINT */
2024         /* If we could not find the appropriate pin by looking at the ioapic
2025          * the i8259 probably is not connected the ioapic but give the
2026          * mptable a chance anyway.
2027          */
2028         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
2029         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2030         /* Trust the MP table if nothing is setup in the hardware */
2031         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2032                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2033                 ioapic_i8259.pin  = i8259_pin;
2034                 ioapic_i8259.apic = i8259_apic;
2035         }
2036         /* Complain if the MP table and the hardware disagree */
2037         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2038                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2039         {
2040                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2041         }
2042
2043         /*
2044          * Do not trust the IO-APIC being empty at bootup
2045          */
2046         clear_IO_APIC();
2047 }
2048
2049 /*
2050  * Not an __init, needed by the reboot code
2051  */
2052 void disable_IO_APIC(void)
2053 {
2054         /*
2055          * Clear the IO-APIC before rebooting:
2056          */
2057         clear_IO_APIC();
2058
2059         /*
2060          * If the i8259 is routed through an IOAPIC
2061          * Put that IOAPIC in virtual wire mode
2062          * so legacy interrupts can be delivered.
2063          */
2064         if (ioapic_i8259.pin != -1) {
2065                 struct IO_APIC_route_entry entry;
2066
2067                 memset(&entry, 0, sizeof(entry));
2068                 entry.mask            = 0; /* Enabled */
2069                 entry.trigger         = 0; /* Edge */
2070                 entry.irr             = 0;
2071                 entry.polarity        = 0; /* High */
2072                 entry.delivery_status = 0;
2073                 entry.dest_mode       = 0; /* Physical */
2074                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
2075                 entry.vector          = 0;
2076                 entry.dest            = read_apic_id();
2077
2078                 /*
2079                  * Add it to the IO-APIC irq-routing table:
2080                  */
2081                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2082         }
2083
2084         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
2085 }
2086
2087 #ifdef CONFIG_X86_32
2088 /*
2089  * function to set the IO-APIC physical IDs based on the
2090  * values stored in the MPC table.
2091  *
2092  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
2093  */
2094
2095 static void __init setup_ioapic_ids_from_mpc(void)
2096 {
2097         union IO_APIC_reg_00 reg_00;
2098         physid_mask_t phys_id_present_map;
2099         int apic_id;
2100         int i;
2101         unsigned char old_id;
2102         unsigned long flags;
2103
2104         if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2105                 return;
2106
2107         /*
2108          * Don't check I/O APIC IDs for xAPIC systems.  They have
2109          * no meaning without the serial APIC bus.
2110          */
2111         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2112                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2113                 return;
2114         /*
2115          * This is broken; anything with a real cpu count has to
2116          * circumvent this idiocy regardless.
2117          */
2118         phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2119
2120         /*
2121          * Set the IOAPIC ID to the value stored in the MPC table.
2122          */
2123         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2124
2125                 /* Read the register 0 value */
2126                 spin_lock_irqsave(&ioapic_lock, flags);
2127                 reg_00.raw = io_apic_read(apic_id, 0);
2128                 spin_unlock_irqrestore(&ioapic_lock, flags);
2129
2130                 old_id = mp_ioapics[apic_id].apicid;
2131
2132                 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2133                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2134                                 apic_id, mp_ioapics[apic_id].apicid);
2135                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2136                                 reg_00.bits.ID);
2137                         mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2138                 }
2139
2140                 /*
2141                  * Sanity check, is the ID really free? Every APIC in a
2142                  * system must have a unique ID or we get lots of nice
2143                  * 'stuck on smp_invalidate_needed IPI wait' messages.
2144                  */
2145                 if (apic->check_apicid_used(phys_id_present_map,
2146                                         mp_ioapics[apic_id].apicid)) {
2147                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2148                                 apic_id, mp_ioapics[apic_id].apicid);
2149                         for (i = 0; i < get_physical_broadcast(); i++)
2150                                 if (!physid_isset(i, phys_id_present_map))
2151                                         break;
2152                         if (i >= get_physical_broadcast())
2153                                 panic("Max APIC ID exceeded!\n");
2154                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2155                                 i);
2156                         physid_set(i, phys_id_present_map);
2157                         mp_ioapics[apic_id].apicid = i;
2158                 } else {
2159                         physid_mask_t tmp;
2160                         tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2161                         apic_printk(APIC_VERBOSE, "Setting %d in the "
2162                                         "phys_id_present_map\n",
2163                                         mp_ioapics[apic_id].apicid);
2164                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
2165                 }
2166
2167
2168                 /*
2169                  * We need to adjust the IRQ routing table
2170                  * if the ID changed.
2171                  */
2172                 if (old_id != mp_ioapics[apic_id].apicid)
2173                         for (i = 0; i < mp_irq_entries; i++)
2174                                 if (mp_irqs[i].dstapic == old_id)
2175                                         mp_irqs[i].dstapic
2176                                                 = mp_ioapics[apic_id].apicid;
2177
2178                 /*
2179                  * Read the right value from the MPC table and
2180                  * write it into the ID register.
2181                  */
2182                 apic_printk(APIC_VERBOSE, KERN_INFO
2183                         "...changing IO-APIC physical APIC ID to %d ...",
2184                         mp_ioapics[apic_id].apicid);
2185
2186                 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2187                 spin_lock_irqsave(&ioapic_lock, flags);
2188                 io_apic_write(apic_id, 0, reg_00.raw);
2189                 spin_unlock_irqrestore(&ioapic_lock, flags);
2190
2191                 /*
2192                  * Sanity check
2193                  */
2194                 spin_lock_irqsave(&ioapic_lock, flags);
2195                 reg_00.raw = io_apic_read(apic_id, 0);
2196                 spin_unlock_irqrestore(&ioapic_lock, flags);
2197                 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2198                         printk("could not set ID!\n");
2199                 else
2200                         apic_printk(APIC_VERBOSE, " ok.\n");
2201         }
2202 }
2203 #endif
2204
2205 int no_timer_check __initdata;
2206
2207 static int __init notimercheck(char *s)
2208 {
2209         no_timer_check = 1;
2210         return 1;
2211 }
2212 __setup("no_timer_check", notimercheck);
2213
2214 /*
2215  * There is a nasty bug in some older SMP boards, their mptable lies
2216  * about the timer IRQ. We do the following to work around the situation:
2217  *
2218  *      - timer IRQ defaults to IO-APIC IRQ
2219  *      - if this function detects that timer IRQs are defunct, then we fall
2220  *        back to ISA timer IRQs
2221  */
2222 static int __init timer_irq_works(void)
2223 {
2224         unsigned long t1 = jiffies;
2225         unsigned long flags;
2226
2227         if (no_timer_check)
2228                 return 1;
2229
2230         local_save_flags(flags);
2231         local_irq_enable();
2232         /* Let ten ticks pass... */
2233         mdelay((10 * 1000) / HZ);
2234         local_irq_restore(flags);
2235
2236         /*
2237          * Expect a few ticks at least, to be sure some possible
2238          * glue logic does not lock up after one or two first
2239          * ticks in a non-ExtINT mode.  Also the local APIC
2240          * might have cached one ExtINT interrupt.  Finally, at
2241          * least one tick may be lost due to delays.
2242          */
2243
2244         /* jiffies wrap? */
2245         if (time_after(jiffies, t1 + 4))
2246                 return 1;
2247         return 0;
2248 }
2249
2250 /*
2251  * In the SMP+IOAPIC case it might happen that there are an unspecified
2252  * number of pending IRQ events unhandled. These cases are very rare,
2253  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2254  * better to do it this way as thus we do not have to be aware of
2255  * 'pending' interrupts in the IRQ path, except at this point.
2256  */
2257 /*
2258  * Edge triggered needs to resend any interrupt
2259  * that was delayed but this is now handled in the device
2260  * independent code.
2261  */
2262
2263 /*
2264  * Starting up a edge-triggered IO-APIC interrupt is
2265  * nasty - we need to make sure that we get the edge.
2266  * If it is already asserted for some reason, we need
2267  * return 1 to indicate that is was pending.
2268  *
2269  * This is not complete - we should be able to fake
2270  * an edge even if it isn't on the 8259A...
2271  */
2272
2273 static unsigned int startup_ioapic_irq(unsigned int irq)
2274 {
2275         int was_pending = 0;
2276         unsigned long flags;
2277         struct irq_cfg *cfg;
2278
2279         spin_lock_irqsave(&ioapic_lock, flags);
2280         if (irq < NR_IRQS_LEGACY) {
2281                 disable_8259A_irq(irq);
2282                 if (i8259A_irq_pending(irq))
2283                         was_pending = 1;
2284         }
2285         cfg = irq_cfg(irq);
2286         __unmask_IO_APIC_irq(cfg);
2287         spin_unlock_irqrestore(&ioapic_lock, flags);
2288
2289         return was_pending;
2290 }
2291
2292 #ifdef CONFIG_X86_64
2293 static int ioapic_retrigger_irq(unsigned int irq)
2294 {
2295
2296         struct irq_cfg *cfg = irq_cfg(irq);
2297         unsigned long flags;
2298
2299         spin_lock_irqsave(&vector_lock, flags);
2300         apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2301         spin_unlock_irqrestore(&vector_lock, flags);
2302
2303         return 1;
2304 }
2305 #else
2306 static int ioapic_retrigger_irq(unsigned int irq)
2307 {
2308         apic->send_IPI_self(irq_cfg(irq)->vector);
2309
2310         return 1;
2311 }
2312 #endif
2313
2314 /*
2315  * Level and edge triggered IO-APIC interrupts need different handling,
2316  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2317  * handled with the level-triggered descriptor, but that one has slightly
2318  * more overhead. Level-triggered interrupts cannot be handled with the
2319  * edge-triggered handler, without risking IRQ storms and other ugly
2320  * races.
2321  */
2322
2323 #ifdef CONFIG_SMP
2324
2325 #ifdef CONFIG_INTR_REMAP
2326 static void ir_irq_migration(struct work_struct *work);
2327
2328 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2329
2330 /*
2331  * Migrate the IO-APIC irq in the presence of intr-remapping.
2332  *
2333  * For edge triggered, irq migration is a simple atomic update(of vector
2334  * and cpu destination) of IRTE and flush the hardware cache.
2335  *
2336  * For level triggered, we need to modify the io-apic RTE aswell with the update
2337  * vector information, along with modifying IRTE with vector and destination.
2338  * So irq migration for level triggered is little  bit more complex compared to
2339  * edge triggered migration. But the good news is, we use the same algorithm
2340  * for level triggered migration as we have today, only difference being,
2341  * we now initiate the irq migration from process context instead of the
2342  * interrupt context.
2343  *
2344  * In future, when we do a directed EOI (combined with cpu EOI broadcast
2345  * suppression) to the IO-APIC, level triggered irq migration will also be
2346  * as simple as edge triggered migration and we can do the irq migration
2347  * with a simple atomic update to IO-APIC RTE.
2348  */
2349 static void
2350 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2351 {
2352         struct irq_cfg *cfg;
2353         struct irte irte;
2354         int modify_ioapic_rte;
2355         unsigned int dest;
2356         unsigned long flags;
2357         unsigned int irq;
2358
2359         if (!cpumask_intersects(mask, cpu_online_mask))
2360                 return;
2361
2362         irq = desc->irq;
2363         if (get_irte(irq, &irte))
2364                 return;
2365
2366         cfg = desc->chip_data;
2367         if (assign_irq_vector(irq, cfg, mask))
2368                 return;
2369
2370         set_extra_move_desc(desc, mask);
2371
2372         dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2373
2374         modify_ioapic_rte = desc->status & IRQ_LEVEL;
2375         if (modify_ioapic_rte) {
2376                 spin_lock_irqsave(&ioapic_lock, flags);
2377                 __target_IO_APIC_irq(irq, dest, cfg);
2378                 spin_unlock_irqrestore(&ioapic_lock, flags);
2379         }
2380
2381         irte.vector = cfg->vector;
2382         irte.dest_id = IRTE_DEST(dest);
2383
2384         /*
2385          * Modified the IRTE and flushes the Interrupt entry cache.
2386          */
2387         modify_irte(irq, &irte);
2388
2389         if (cfg->move_in_progress)
2390                 send_cleanup_vector(cfg);
2391
2392         cpumask_copy(desc->affinity, mask);
2393 }
2394
2395 static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
2396 {
2397         int ret = -1;
2398         struct irq_cfg *cfg = desc->chip_data;
2399
2400         mask_IO_APIC_irq_desc(desc);
2401
2402         if (io_apic_level_ack_pending(cfg)) {
2403                 /*
2404                  * Interrupt in progress. Migrating irq now will change the
2405                  * vector information in the IO-APIC RTE and that will confuse
2406                  * the EOI broadcast performed by cpu.
2407                  * So, delay the irq migration to the next instance.
2408                  */
2409                 schedule_delayed_work(&ir_migration_work, 1);
2410                 goto unmask;
2411         }
2412
2413         /* everthing is clear. we have right of way */
2414         migrate_ioapic_irq_desc(desc, desc->pending_mask);
2415
2416         ret = 0;
2417         desc->status &= ~IRQ_MOVE_PENDING;
2418         cpumask_clear(desc->pending_mask);
2419
2420 unmask:
2421         unmask_IO_APIC_irq_desc(desc);
2422
2423         return ret;
2424 }
2425
2426 static void ir_irq_migration(struct work_struct *work)
2427 {
2428         unsigned int irq;
2429         struct irq_desc *desc;
2430
2431         for_each_irq_desc(irq, desc) {
2432                 if (desc->status & IRQ_MOVE_PENDING) {
2433                         unsigned long flags;
2434
2435                         spin_lock_irqsave(&desc->lock, flags);
2436                         if (!desc->chip->set_affinity ||
2437                             !(desc->status & IRQ_MOVE_PENDING)) {
2438                                 desc->status &= ~IRQ_MOVE_PENDING;
2439                                 spin_unlock_irqrestore(&desc->lock, flags);
2440                                 continue;
2441                         }
2442
2443                         desc->chip->set_affinity(irq, desc->pending_mask);
2444                         spin_unlock_irqrestore(&desc->lock, flags);
2445                 }
2446         }
2447 }
2448
2449 /*
2450  * Migrates the IRQ destination in the process context.
2451  */
2452 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2453                                             const struct cpumask *mask)
2454 {
2455         if (desc->status & IRQ_LEVEL) {
2456                 desc->status |= IRQ_MOVE_PENDING;
2457                 cpumask_copy(desc->pending_mask, mask);
2458                 migrate_irq_remapped_level_desc(desc);
2459                 return;
2460         }
2461
2462         migrate_ioapic_irq_desc(desc, mask);
2463 }
2464 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2465                                        const struct cpumask *mask)
2466 {
2467         struct irq_desc *desc = irq_to_desc(irq);
2468
2469         set_ir_ioapic_affinity_irq_desc(desc, mask);
2470 }
2471 #endif
2472
2473 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2474 {
2475         unsigned vector, me;
2476
2477         ack_APIC_irq();
2478         exit_idle();
2479         irq_enter();
2480
2481         me = smp_processor_id();
2482         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2483                 unsigned int irq;
2484                 struct irq_desc *desc;
2485                 struct irq_cfg *cfg;
2486                 irq = __get_cpu_var(vector_irq)[vector];
2487
2488                 if (irq == -1)
2489                         continue;
2490
2491                 desc = irq_to_desc(irq);
2492                 if (!desc)
2493                         continue;
2494
2495                 cfg = irq_cfg(irq);
2496                 spin_lock(&desc->lock);
2497                 if (!cfg->move_cleanup_count)
2498                         goto unlock;
2499
2500                 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2501                         goto unlock;
2502
2503                 __get_cpu_var(vector_irq)[vector] = -1;
2504                 cfg->move_cleanup_count--;
2505 unlock:
2506                 spin_unlock(&desc->lock);
2507         }
2508
2509         irq_exit();
2510 }
2511
2512 static void irq_complete_move(struct irq_desc **descp)
2513 {
2514         struct irq_desc *desc = *descp;
2515         struct irq_cfg *cfg = desc->chip_data;
2516         unsigned vector, me;
2517
2518         if (likely(!cfg->move_in_progress)) {
2519 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2520                 if (likely(!cfg->move_desc_pending))
2521                         return;
2522
2523                 /* domain has not changed, but affinity did */
2524                 me = smp_processor_id();
2525                 if (cpumask_test_cpu(me, desc->affinity)) {
2526                         *descp = desc = move_irq_desc(desc, me);
2527                         /* get the new one */
2528                         cfg = desc->chip_data;
2529                         cfg->move_desc_pending = 0;
2530                 }
2531 #endif
2532                 return;
2533         }
2534
2535         vector = ~get_irq_regs()->orig_ax;
2536         me = smp_processor_id();
2537 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2538                 *descp = desc = move_irq_desc(desc, me);
2539                 /* get the new one */
2540                 cfg = desc->chip_data;
2541 #endif
2542
2543         if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2544                 send_cleanup_vector(cfg);
2545 }
2546 #else
2547 static inline void irq_complete_move(struct irq_desc **descp) {}
2548 #endif
2549
2550 #ifdef CONFIG_INTR_REMAP
2551 static void ack_x2apic_level(unsigned int irq)
2552 {
2553         ack_x2APIC_irq();
2554 }
2555
2556 static void ack_x2apic_edge(unsigned int irq)
2557 {
2558         ack_x2APIC_irq();
2559 }
2560
2561 #endif
2562
2563 static void ack_apic_edge(unsigned int irq)
2564 {
2565         struct irq_desc *desc = irq_to_desc(irq);
2566
2567         irq_complete_move(&desc);
2568         move_native_irq(irq);
2569         ack_APIC_irq();
2570 }
2571
2572 atomic_t irq_mis_count;
2573
2574 static void ack_apic_level(unsigned int irq)
2575 {
2576         struct irq_desc *desc = irq_to_desc(irq);
2577
2578 #ifdef CONFIG_X86_32
2579         unsigned long v;
2580         int i;
2581 #endif
2582         struct irq_cfg *cfg;
2583         int do_unmask_irq = 0;
2584
2585         irq_complete_move(&desc);
2586 #ifdef CONFIG_GENERIC_PENDING_IRQ
2587         /* If we are moving the irq we need to mask it */
2588         if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2589                 do_unmask_irq = 1;
2590                 mask_IO_APIC_irq_desc(desc);
2591         }
2592 #endif
2593
2594 #ifdef CONFIG_X86_32
2595         /*
2596         * It appears there is an erratum which affects at least version 0x11
2597         * of I/O APIC (that's the 82093AA and cores integrated into various
2598         * chipsets).  Under certain conditions a level-triggered interrupt is
2599         * erroneously delivered as edge-triggered one but the respective IRR
2600         * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2601         * message but it will never arrive and further interrupts are blocked
2602         * from the source.  The exact reason is so far unknown, but the
2603         * phenomenon was observed when two consecutive interrupt requests
2604         * from a given source get delivered to the same CPU and the source is
2605         * temporarily disabled in between.
2606         *
2607         * A workaround is to simulate an EOI message manually.  We achieve it
2608         * by setting the trigger mode to edge and then to level when the edge
2609         * trigger mode gets detected in the TMR of a local APIC for a
2610         * level-triggered interrupt.  We mask the source for the time of the
2611         * operation to prevent an edge-triggered interrupt escaping meanwhile.
2612         * The idea is from Manfred Spraul.  --macro
2613         */
2614         cfg = desc->chip_data;
2615         i = cfg->vector;
2616
2617         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2618 #endif
2619
2620         /*
2621          * We must acknowledge the irq before we move it or the acknowledge will
2622          * not propagate properly.
2623          */
2624         ack_APIC_irq();
2625
2626         /* Now we can move and renable the irq */
2627         if (unlikely(do_unmask_irq)) {
2628                 /* Only migrate the irq if the ack has been received.
2629                  *
2630                  * On rare occasions the broadcast level triggered ack gets
2631                  * delayed going to ioapics, and if we reprogram the
2632                  * vector while Remote IRR is still set the irq will never
2633                  * fire again.
2634                  *
2635                  * To prevent this scenario we read the Remote IRR bit
2636                  * of the ioapic.  This has two effects.
2637                  * - On any sane system the read of the ioapic will
2638                  *   flush writes (and acks) going to the ioapic from
2639                  *   this cpu.
2640                  * - We get to see if the ACK has actually been delivered.
2641                  *
2642                  * Based on failed experiments of reprogramming the
2643                  * ioapic entry from outside of irq context starting
2644                  * with masking the ioapic entry and then polling until
2645                  * Remote IRR was clear before reprogramming the
2646                  * ioapic I don't trust the Remote IRR bit to be
2647                  * completey accurate.
2648                  *
2649                  * However there appears to be no other way to plug
2650                  * this race, so if the Remote IRR bit is not
2651                  * accurate and is causing problems then it is a hardware bug
2652                  * and you can go talk to the chipset vendor about it.
2653                  */
2654                 cfg = desc->chip_data;
2655                 if (!io_apic_level_ack_pending(cfg))
2656                         move_masked_irq(irq);
2657                 unmask_IO_APIC_irq_desc(desc);
2658         }
2659
2660 #ifdef CONFIG_X86_32
2661         if (!(v & (1 << (i & 0x1f)))) {
2662                 atomic_inc(&irq_mis_count);
2663                 spin_lock(&ioapic_lock);
2664                 __mask_and_edge_IO_APIC_irq(cfg);
2665                 __unmask_and_level_IO_APIC_irq(cfg);
2666                 spin_unlock(&ioapic_lock);
2667         }
2668 #endif
2669 }
2670
2671 static struct irq_chip ioapic_chip __read_mostly = {
2672         .name           = "IO-APIC",
2673         .startup        = startup_ioapic_irq,
2674         .mask           = mask_IO_APIC_irq,
2675         .unmask         = unmask_IO_APIC_irq,
2676         .ack            = ack_apic_edge,
2677         .eoi            = ack_apic_level,
2678 #ifdef CONFIG_SMP
2679         .set_affinity   = set_ioapic_affinity_irq,
2680 #endif
2681         .retrigger      = ioapic_retrigger_irq,
2682 };
2683
2684 #ifdef CONFIG_INTR_REMAP
2685 static struct irq_chip ir_ioapic_chip __read_mostly = {
2686         .name           = "IR-IO-APIC",
2687         .startup        = startup_ioapic_irq,
2688         .mask           = mask_IO_APIC_irq,
2689         .unmask         = unmask_IO_APIC_irq,
2690         .ack            = ack_x2apic_edge,
2691         .eoi            = ack_x2apic_level,
2692 #ifdef CONFIG_SMP
2693         .set_affinity   = set_ir_ioapic_affinity_irq,
2694 #endif
2695         .retrigger      = ioapic_retrigger_irq,
2696 };
2697 #endif
2698
2699 static inline void init_IO_APIC_traps(void)
2700 {
2701         int irq;
2702         struct irq_desc *desc;
2703         struct irq_cfg *cfg;
2704
2705         /*
2706          * NOTE! The local APIC isn't very good at handling
2707          * multiple interrupts at the same interrupt level.
2708          * As the interrupt level is determined by taking the
2709          * vector number and shifting that right by 4, we
2710          * want to spread these out a bit so that they don't
2711          * all fall in the same interrupt level.
2712          *
2713          * Also, we've got to be careful not to trash gate
2714          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2715          */
2716         for_each_irq_desc(irq, desc) {
2717                 cfg = desc->chip_data;
2718                 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2719                         /*
2720                          * Hmm.. We don't have an entry for this,
2721                          * so default to an old-fashioned 8259
2722                          * interrupt if we can..
2723                          */
2724                         if (irq < NR_IRQS_LEGACY)
2725                                 make_8259A_irq(irq);
2726                         else
2727                                 /* Strange. Oh, well.. */
2728                                 desc->chip = &no_irq_chip;
2729                 }
2730         }
2731 }
2732
2733 /*
2734  * The local APIC irq-chip implementation:
2735  */
2736
2737 static void mask_lapic_irq(unsigned int irq)
2738 {
2739         unsigned long v;
2740
2741         v = apic_read(APIC_LVT0);
2742         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2743 }
2744
2745 static void unmask_lapic_irq(unsigned int irq)
2746 {
2747         unsigned long v;
2748
2749         v = apic_read(APIC_LVT0);
2750         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2751 }
2752
2753 static void ack_lapic_irq(unsigned int irq)
2754 {
2755         ack_APIC_irq();
2756 }
2757
2758 static struct irq_chip lapic_chip __read_mostly = {
2759         .name           = "local-APIC",
2760         .mask           = mask_lapic_irq,
2761         .unmask         = unmask_lapic_irq,
2762         .ack            = ack_lapic_irq,
2763 };
2764
2765 static void lapic_register_intr(int irq, struct irq_desc *desc)
2766 {
2767         desc->status &= ~IRQ_LEVEL;
2768         set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2769                                       "edge");
2770 }
2771
2772 static void __init setup_nmi(void)
2773 {
2774         /*
2775          * Dirty trick to enable the NMI watchdog ...
2776          * We put the 8259A master into AEOI mode and
2777          * unmask on all local APICs LVT0 as NMI.
2778          *
2779          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2780          * is from Maciej W. Rozycki - so we do not have to EOI from
2781          * the NMI handler or the timer interrupt.
2782          */
2783         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2784
2785         enable_NMI_through_LVT0();
2786
2787         apic_printk(APIC_VERBOSE, " done.\n");
2788 }
2789
2790 /*
2791  * This looks a bit hackish but it's about the only one way of sending
2792  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2793  * not support the ExtINT mode, unfortunately.  We need to send these
2794  * cycles as some i82489DX-based boards have glue logic that keeps the
2795  * 8259A interrupt line asserted until INTA.  --macro
2796  */
2797 static inline void __init unlock_ExtINT_logic(void)
2798 {
2799         int apic, pin, i;
2800         struct IO_APIC_route_entry entry0, entry1;
2801         unsigned char save_control, save_freq_select;
2802
2803         pin  = find_isa_irq_pin(8, mp_INT);
2804         if (pin == -1) {
2805                 WARN_ON_ONCE(1);
2806                 return;
2807         }
2808         apic = find_isa_irq_apic(8, mp_INT);
2809         if (apic == -1) {
2810                 WARN_ON_ONCE(1);
2811                 return;
2812         }
2813
2814         entry0 = ioapic_read_entry(apic, pin);
2815         clear_IO_APIC_pin(apic, pin);
2816
2817         memset(&entry1, 0, sizeof(entry1));
2818
2819         entry1.dest_mode = 0;                   /* physical delivery */
2820         entry1.mask = 0;                        /* unmask IRQ now */
2821         entry1.dest = hard_smp_processor_id();
2822         entry1.delivery_mode = dest_ExtINT;
2823         entry1.polarity = entry0.polarity;
2824         entry1.trigger = 0;
2825         entry1.vector = 0;
2826
2827         ioapic_write_entry(apic, pin, entry1);
2828
2829         save_control = CMOS_READ(RTC_CONTROL);
2830         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2831         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2832                    RTC_FREQ_SELECT);
2833         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2834
2835         i = 100;
2836         while (i-- > 0) {
2837                 mdelay(10);
2838                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2839                         i -= 10;
2840         }
2841
2842         CMOS_WRITE(save_control, RTC_CONTROL);
2843         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2844         clear_IO_APIC_pin(apic, pin);
2845
2846         ioapic_write_entry(apic, pin, entry0);
2847 }
2848
2849 static int disable_timer_pin_1 __initdata;
2850 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2851 static int __init disable_timer_pin_setup(char *arg)
2852 {
2853         disable_timer_pin_1 = 1;
2854         return 0;
2855 }
2856 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2857
2858 int timer_through_8259 __initdata;
2859
2860 /*
2861  * This code may look a bit paranoid, but it's supposed to cooperate with
2862  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2863  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2864  * fanatically on his truly buggy board.
2865  *
2866  * FIXME: really need to revamp this for all platforms.
2867  */
2868 static inline void __init check_timer(void)
2869 {
2870         struct irq_desc *desc = irq_to_desc(0);
2871         struct irq_cfg *cfg = desc->chip_data;
2872         int cpu = boot_cpu_id;
2873         int apic1, pin1, apic2, pin2;
2874         unsigned long flags;
2875         unsigned int ver;
2876         int no_pin1 = 0;
2877
2878         local_irq_save(flags);
2879
2880         ver = apic_read(APIC_LVR);
2881         ver = GET_APIC_VERSION(ver);
2882
2883         /*
2884          * get/set the timer IRQ vector:
2885          */
2886         disable_8259A_irq(0);
2887         assign_irq_vector(0, cfg, apic->target_cpus());
2888
2889         /*
2890          * As IRQ0 is to be enabled in the 8259A, the virtual
2891          * wire has to be disabled in the local APIC.  Also
2892          * timer interrupts need to be acknowledged manually in
2893          * the 8259A for the i82489DX when using the NMI
2894          * watchdog as that APIC treats NMIs as level-triggered.
2895          * The AEOI mode will finish them in the 8259A
2896          * automatically.
2897          */
2898         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2899         init_8259A(1);
2900 #ifdef CONFIG_X86_32
2901         timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2902 #endif
2903
2904         pin1  = find_isa_irq_pin(0, mp_INT);
2905         apic1 = find_isa_irq_apic(0, mp_INT);
2906         pin2  = ioapic_i8259.pin;
2907         apic2 = ioapic_i8259.apic;
2908
2909         apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2910                     "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2911                     cfg->vector, apic1, pin1, apic2, pin2);
2912
2913         /*
2914          * Some BIOS writers are clueless and report the ExtINTA
2915          * I/O APIC input from the cascaded 8259A as the timer
2916          * interrupt input.  So just in case, if only one pin
2917          * was found above, try it both directly and through the
2918          * 8259A.
2919          */
2920         if (pin1 == -1) {
2921 #ifdef CONFIG_INTR_REMAP
2922                 if (intr_remapping_enabled)
2923                         panic("BIOS bug: timer not connected to IO-APIC");
2924 #endif
2925                 pin1 = pin2;
2926                 apic1 = apic2;
2927                 no_pin1 = 1;
2928         } else if (pin2 == -1) {
2929                 pin2 = pin1;
2930                 apic2 = apic1;
2931         }
2932
2933         if (pin1 != -1) {
2934                 /*
2935                  * Ok, does IRQ0 through the IOAPIC work?
2936                  */
2937                 if (no_pin1) {
2938                         add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2939                         setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2940                 }
2941                 unmask_IO_APIC_irq_desc(desc);
2942                 if (timer_irq_works()) {
2943                         if (nmi_watchdog == NMI_IO_APIC) {
2944                                 setup_nmi();
2945                                 enable_8259A_irq(0);
2946                         }
2947                         if (disable_timer_pin_1 > 0)
2948                                 clear_IO_APIC_pin(0, pin1);
2949                         goto out;
2950                 }
2951 #ifdef CONFIG_INTR_REMAP
2952                 if (intr_remapping_enabled)
2953                         panic("timer doesn't work through Interrupt-remapped IO-APIC");
2954 #endif
2955                 clear_IO_APIC_pin(apic1, pin1);
2956                 if (!no_pin1)
2957                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2958                                     "8254 timer not connected to IO-APIC\n");
2959
2960                 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2961                             "(IRQ0) through the 8259A ...\n");
2962                 apic_printk(APIC_QUIET, KERN_INFO
2963                             "..... (found apic %d pin %d) ...\n", apic2, pin2);
2964                 /*
2965                  * legacy devices should be connected to IO APIC #0
2966                  */
2967                 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2968                 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2969                 unmask_IO_APIC_irq_desc(desc);
2970                 enable_8259A_irq(0);
2971                 if (timer_irq_works()) {
2972                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2973                         timer_through_8259 = 1;
2974                         if (nmi_watchdog == NMI_IO_APIC) {
2975                                 disable_8259A_irq(0);
2976                                 setup_nmi();
2977                                 enable_8259A_irq(0);
2978                         }
2979                         goto out;
2980                 }
2981                 /*
2982                  * Cleanup, just in case ...
2983                  */
2984                 disable_8259A_irq(0);
2985                 clear_IO_APIC_pin(apic2, pin2);
2986                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2987         }
2988
2989         if (nmi_watchdog == NMI_IO_APIC) {
2990                 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2991                             "through the IO-APIC - disabling NMI Watchdog!\n");
2992                 nmi_watchdog = NMI_NONE;
2993         }
2994 #ifdef CONFIG_X86_32
2995         timer_ack = 0;
2996 #endif
2997
2998         apic_printk(APIC_QUIET, KERN_INFO
2999                     "...trying to set up timer as Virtual Wire IRQ...\n");
3000
3001         lapic_register_intr(0, desc);
3002         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
3003         enable_8259A_irq(0);
3004
3005         if (timer_irq_works()) {
3006                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3007                 goto out;
3008         }
3009         disable_8259A_irq(0);
3010         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3011         apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3012
3013         apic_printk(APIC_QUIET, KERN_INFO
3014                     "...trying to set up timer as ExtINT IRQ...\n");
3015
3016         init_8259A(0);
3017         make_8259A_irq(0);
3018         apic_write(APIC_LVT0, APIC_DM_EXTINT);
3019
3020         unlock_ExtINT_logic();
3021
3022         if (timer_irq_works()) {
3023                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3024                 goto out;
3025         }
3026         apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3027         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
3028                 "report.  Then try booting with the 'noapic' option.\n");
3029 out:
3030         local_irq_restore(flags);
3031 }
3032
3033 /*
3034  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3035  * to devices.  However there may be an I/O APIC pin available for
3036  * this interrupt regardless.  The pin may be left unconnected, but
3037  * typically it will be reused as an ExtINT cascade interrupt for
3038  * the master 8259A.  In the MPS case such a pin will normally be
3039  * reported as an ExtINT interrupt in the MP table.  With ACPI
3040  * there is no provision for ExtINT interrupts, and in the absence
3041  * of an override it would be treated as an ordinary ISA I/O APIC
3042  * interrupt, that is edge-triggered and unmasked by default.  We
3043  * used to do this, but it caused problems on some systems because
3044  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3045  * the same ExtINT cascade interrupt to drive the local APIC of the
3046  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
3047  * the I/O APIC in all cases now.  No actual device should request
3048  * it anyway.  --macro
3049  */
3050 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
3051
3052 void __init setup_IO_APIC(void)
3053 {
3054
3055 #ifdef CONFIG_X86_32
3056         enable_IO_APIC();
3057 #else
3058         /*
3059          * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3060          */
3061 #endif
3062
3063         io_apic_irqs = ~PIC_IRQS;
3064
3065         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3066         /*
3067          * Set up IO-APIC IRQ routing.
3068          */
3069 #ifdef CONFIG_X86_32
3070         if (!acpi_ioapic)
3071                 setup_ioapic_ids_from_mpc();
3072 #endif
3073         sync_Arb_IDs();
3074         setup_IO_APIC_irqs();
3075         init_IO_APIC_traps();
3076         check_timer();
3077 }
3078
3079 /*
3080  *      Called after all the initialization is done. If we didnt find any
3081  *      APIC bugs then we can allow the modify fast path
3082  */
3083
3084 static int __init io_apic_bug_finalize(void)
3085 {
3086         if (sis_apic_bug == -1)
3087                 sis_apic_bug = 0;
3088         return 0;
3089 }
3090
3091 late_initcall(io_apic_bug_finalize);
3092
3093 struct sysfs_ioapic_data {
3094         struct sys_device dev;
3095         struct IO_APIC_route_entry entry[0];
3096 };
3097 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3098
3099 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3100 {
3101         struct IO_APIC_route_entry *entry;
3102         struct sysfs_ioapic_data *data;
3103         int i;
3104
3105         data = container_of(dev, struct sysfs_ioapic_data, dev);
3106         entry = data->entry;
3107         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3108                 *entry = ioapic_read_entry(dev->id, i);
3109
3110         return 0;
3111 }
3112
3113 static int ioapic_resume(struct sys_device *dev)
3114 {
3115         struct IO_APIC_route_entry *entry;
3116         struct sysfs_ioapic_data *data;
3117         unsigned long flags;
3118         union IO_APIC_reg_00 reg_00;
3119         int i;
3120
3121         data = container_of(dev, struct sysfs_ioapic_data, dev);
3122         entry = data->entry;
3123
3124         spin_lock_irqsave(&ioapic_lock, flags);
3125         reg_00.raw = io_apic_read(dev->id, 0);
3126         if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3127                 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3128                 io_apic_write(dev->id, 0, reg_00.raw);
3129         }
3130         spin_unlock_irqrestore(&ioapic_lock, flags);
3131         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3132                 ioapic_write_entry(dev->id, i, entry[i]);
3133
3134         return 0;
3135 }
3136
3137 static struct sysdev_class ioapic_sysdev_class = {
3138         .name = "ioapic",
3139         .suspend = ioapic_suspend,
3140         .resume = ioapic_resume,
3141 };
3142
3143 static int __init ioapic_init_sysfs(void)
3144 {
3145         struct sys_device * dev;
3146         int i, size, error;
3147
3148         error = sysdev_class_register(&ioapic_sysdev_class);
3149         if (error)
3150                 return error;
3151
3152         for (i = 0; i < nr_ioapics; i++ ) {
3153                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3154                         * sizeof(struct IO_APIC_route_entry);
3155                 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3156                 if (!mp_ioapic_data[i]) {
3157                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3158                         continue;
3159                 }
3160                 dev = &mp_ioapic_data[i]->dev;
3161                 dev->id = i;
3162                 dev->cls = &ioapic_sysdev_class;
3163                 error = sysdev_register(dev);
3164                 if (error) {
3165                         kfree(mp_ioapic_data[i]);
3166                         mp_ioapic_data[i] = NULL;
3167                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3168                         continue;
3169                 }
3170         }
3171
3172         return 0;
3173 }
3174
3175 device_initcall(ioapic_init_sysfs);
3176
3177 /*
3178  * Dynamic irq allocate and deallocation
3179  */
3180 unsigned int create_irq_nr(unsigned int irq_want)
3181 {
3182         /* Allocate an unused irq */
3183         unsigned int irq;
3184         unsigned int new;
3185         unsigned long flags;
3186         struct irq_cfg *cfg_new = NULL;
3187         int cpu = boot_cpu_id;
3188         struct irq_desc *desc_new = NULL;
3189
3190         irq = 0;
3191         spin_lock_irqsave(&vector_lock, flags);
3192         for (new = irq_want; new < nr_irqs; new++) {
3193                 if (platform_legacy_irq(new))
3194                         continue;
3195
3196                 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3197                 if (!desc_new) {
3198                         printk(KERN_INFO "can not get irq_desc for %d\n", new);
3199                         continue;
3200                 }
3201                 cfg_new = desc_new->chip_data;
3202
3203                 if (cfg_new->vector != 0)
3204                         continue;
3205                 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3206                         irq = new;
3207                 break;
3208         }
3209         spin_unlock_irqrestore(&vector_lock, flags);
3210
3211         if (irq > 0) {
3212                 dynamic_irq_init(irq);
3213                 /* restore it, in case dynamic_irq_init clear it */
3214                 if (desc_new)
3215                         desc_new->chip_data = cfg_new;
3216         }
3217         return irq;
3218 }
3219
3220 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3221 int create_irq(void)
3222 {
3223         unsigned int irq_want;
3224         int irq;
3225
3226         irq_want = nr_irqs_gsi;
3227         irq = create_irq_nr(irq_want);
3228
3229         if (irq == 0)
3230                 irq = -1;
3231
3232         return irq;
3233 }
3234
3235 void destroy_irq(unsigned int irq)
3236 {
3237         unsigned long flags;
3238         struct irq_cfg *cfg;
3239         struct irq_desc *desc;
3240
3241         /* store it, in case dynamic_irq_cleanup clear it */
3242         desc = irq_to_desc(irq);
3243         cfg = desc->chip_data;
3244         dynamic_irq_cleanup(irq);
3245         /* connect back irq_cfg */
3246         if (desc)
3247                 desc->chip_data = cfg;
3248
3249 #ifdef CONFIG_INTR_REMAP
3250         free_irte(irq);
3251 #endif
3252         spin_lock_irqsave(&vector_lock, flags);
3253         __clear_irq_vector(irq, cfg);
3254         spin_unlock_irqrestore(&vector_lock, flags);
3255 }
3256
3257 /*
3258  * MSI message composition
3259  */
3260 #ifdef CONFIG_PCI_MSI
3261 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3262 {
3263         struct irq_cfg *cfg;
3264         int err;
3265         unsigned dest;
3266
3267         if (disable_apic)
3268                 return -ENXIO;
3269
3270         cfg = irq_cfg(irq);
3271         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3272         if (err)
3273                 return err;
3274
3275         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3276
3277 #ifdef CONFIG_INTR_REMAP
3278         if (irq_remapped(irq)) {
3279                 struct irte irte;
3280                 int ir_index;
3281                 u16 sub_handle;
3282
3283                 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3284                 BUG_ON(ir_index == -1);
3285
3286                 memset (&irte, 0, sizeof(irte));
3287
3288                 irte.present = 1;
3289                 irte.dst_mode = apic->irq_dest_mode;
3290                 irte.trigger_mode = 0; /* edge */
3291                 irte.dlvry_mode = apic->irq_delivery_mode;
3292                 irte.vector = cfg->vector;
3293                 irte.dest_id = IRTE_DEST(dest);
3294
3295                 modify_irte(irq, &irte);
3296
3297                 msg->address_hi = MSI_ADDR_BASE_HI;
3298                 msg->data = sub_handle;
3299                 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3300                                   MSI_ADDR_IR_SHV |
3301                                   MSI_ADDR_IR_INDEX1(ir_index) |
3302                                   MSI_ADDR_IR_INDEX2(ir_index);
3303         } else
3304 #endif
3305         {
3306                 msg->address_hi = MSI_ADDR_BASE_HI;
3307                 msg->address_lo =
3308                         MSI_ADDR_BASE_LO |
3309                         ((apic->irq_dest_mode == 0) ?
3310                                 MSI_ADDR_DEST_MODE_PHYSICAL:
3311                                 MSI_ADDR_DEST_MODE_LOGICAL) |
3312                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3313                                 MSI_ADDR_REDIRECTION_CPU:
3314                                 MSI_ADDR_REDIRECTION_LOWPRI) |
3315                         MSI_ADDR_DEST_ID(dest);
3316
3317                 msg->data =
3318                         MSI_DATA_TRIGGER_EDGE |
3319                         MSI_DATA_LEVEL_ASSERT |
3320                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3321                                 MSI_DATA_DELIVERY_FIXED:
3322                                 MSI_DATA_DELIVERY_LOWPRI) |
3323                         MSI_DATA_VECTOR(cfg->vector);
3324         }
3325         return err;
3326 }
3327
3328 #ifdef CONFIG_SMP
3329 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3330 {
3331         struct irq_desc *desc = irq_to_desc(irq);
3332         struct irq_cfg *cfg;
3333         struct msi_msg msg;
3334         unsigned int dest;
3335
3336         dest = set_desc_affinity(desc, mask);
3337         if (dest == BAD_APICID)
3338                 return;
3339
3340         cfg = desc->chip_data;
3341
3342         read_msi_msg_desc(desc, &msg);
3343
3344         msg.data &= ~MSI_DATA_VECTOR_MASK;
3345         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3346         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3347         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3348
3349         write_msi_msg_desc(desc, &msg);
3350 }
3351 #ifdef CONFIG_INTR_REMAP
3352 /*
3353  * Migrate the MSI irq to another cpumask. This migration is
3354  * done in the process context using interrupt-remapping hardware.
3355  */
3356 static void
3357 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3358 {
3359         struct irq_desc *desc = irq_to_desc(irq);
3360         struct irq_cfg *cfg = desc->chip_data;
3361         unsigned int dest;
3362         struct irte irte;
3363
3364         if (get_irte(irq, &irte))
3365                 return;
3366
3367         dest = set_desc_affinity(desc, mask);
3368         if (dest == BAD_APICID)
3369                 return;
3370
3371         irte.vector = cfg->vector;
3372         irte.dest_id = IRTE_DEST(dest);
3373
3374         /*
3375          * atomically update the IRTE with the new destination and vector.
3376          */
3377         modify_irte(irq, &irte);
3378
3379         /*
3380          * After this point, all the interrupts will start arriving
3381          * at the new destination. So, time to cleanup the previous
3382          * vector allocation.
3383          */
3384         if (cfg->move_in_progress)
3385                 send_cleanup_vector(cfg);
3386 }
3387
3388 #endif
3389 #endif /* CONFIG_SMP */
3390
3391 /*
3392  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3393  * which implement the MSI or MSI-X Capability Structure.
3394  */
3395 static struct irq_chip msi_chip = {
3396         .name           = "PCI-MSI",
3397         .unmask         = unmask_msi_irq,
3398         .mask           = mask_msi_irq,
3399         .ack            = ack_apic_edge,
3400 #ifdef CONFIG_SMP
3401         .set_affinity   = set_msi_irq_affinity,
3402 #endif
3403         .retrigger      = ioapic_retrigger_irq,
3404 };
3405
3406 #ifdef CONFIG_INTR_REMAP
3407 static struct irq_chip msi_ir_chip = {
3408         .name           = "IR-PCI-MSI",
3409         .unmask         = unmask_msi_irq,
3410         .mask           = mask_msi_irq,
3411         .ack            = ack_x2apic_edge,
3412 #ifdef CONFIG_SMP
3413         .set_affinity   = ir_set_msi_irq_affinity,
3414 #endif
3415         .retrigger      = ioapic_retrigger_irq,
3416 };
3417
3418 /*
3419  * Map the PCI dev to the corresponding remapping hardware unit
3420  * and allocate 'nvec' consecutive interrupt-remapping table entries
3421  * in it.
3422  */
3423 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3424 {
3425         struct intel_iommu *iommu;
3426         int index;
3427
3428         iommu = map_dev_to_ir(dev);
3429         if (!iommu) {
3430                 printk(KERN_ERR
3431                        "Unable to map PCI %s to iommu\n", pci_name(dev));
3432                 return -ENOENT;
3433         }
3434
3435         index = alloc_irte(iommu, irq, nvec);
3436         if (index < 0) {
3437                 printk(KERN_ERR
3438                        "Unable to allocate %d IRTE for PCI %s\n", nvec,
3439                        pci_name(dev));
3440                 return -ENOSPC;
3441         }
3442         return index;
3443 }
3444 #endif
3445
3446 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3447 {
3448         int ret;
3449         struct msi_msg msg;
3450
3451         ret = msi_compose_msg(dev, irq, &msg);
3452         if (ret < 0)
3453                 return ret;
3454
3455         set_irq_msi(irq, msidesc);
3456         write_msi_msg(irq, &msg);
3457
3458 #ifdef CONFIG_INTR_REMAP
3459         if (irq_remapped(irq)) {
3460                 struct irq_desc *desc = irq_to_desc(irq);
3461                 /*
3462                  * irq migration in process context
3463                  */
3464                 desc->status |= IRQ_MOVE_PCNTXT;
3465                 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3466         } else
3467 #endif
3468                 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3469
3470         dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3471
3472         return 0;
3473 }
3474
3475 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3476 {
3477         unsigned int irq;
3478         int ret, sub_handle;
3479         struct msi_desc *msidesc;
3480         unsigned int irq_want;
3481
3482 #ifdef CONFIG_INTR_REMAP
3483         struct intel_iommu *iommu = 0;
3484         int index = 0;
3485 #endif
3486
3487         irq_want = nr_irqs_gsi;
3488         sub_handle = 0;
3489         list_for_each_entry(msidesc, &dev->msi_list, list) {
3490                 irq = create_irq_nr(irq_want);
3491                 irq_want++;
3492                 if (irq == 0)
3493                         return -1;
3494 #ifdef CONFIG_INTR_REMAP
3495                 if (!intr_remapping_enabled)
3496                         goto no_ir;
3497
3498                 if (!sub_handle) {
3499                         /*
3500                          * allocate the consecutive block of IRTE's
3501                          * for 'nvec'
3502                          */
3503                         index = msi_alloc_irte(dev, irq, nvec);
3504                         if (index < 0) {
3505                                 ret = index;
3506                                 goto error;
3507                         }
3508                 } else {
3509                         iommu = map_dev_to_ir(dev);
3510                         if (!iommu) {
3511                                 ret = -ENOENT;
3512                                 goto error;
3513                         }
3514                         /*
3515                          * setup the mapping between the irq and the IRTE
3516                          * base index, the sub_handle pointing to the
3517                          * appropriate interrupt remap table entry.
3518                          */
3519                         set_irte_irq(irq, iommu, index, sub_handle);
3520                 }
3521 no_ir:
3522 #endif
3523                 ret = setup_msi_irq(dev, msidesc, irq);
3524                 if (ret < 0)
3525                         goto error;
3526                 sub_handle++;
3527         }
3528         return 0;
3529
3530 error:
3531         destroy_irq(irq);
3532         return ret;
3533 }
3534
3535 void arch_teardown_msi_irq(unsigned int irq)
3536 {
3537         destroy_irq(irq);
3538 }
3539
3540 #ifdef CONFIG_DMAR
3541 #ifdef CONFIG_SMP
3542 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3543 {
3544         struct irq_desc *desc = irq_to_desc(irq);
3545         struct irq_cfg *cfg;
3546         struct msi_msg msg;
3547         unsigned int dest;
3548
3549         dest = set_desc_affinity(desc, mask);
3550         if (dest == BAD_APICID)
3551                 return;
3552
3553         cfg = desc->chip_data;
3554
3555         dmar_msi_read(irq, &msg);
3556
3557         msg.data &= ~MSI_DATA_VECTOR_MASK;
3558         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3559         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3560         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3561
3562         dmar_msi_write(irq, &msg);
3563 }
3564
3565 #endif /* CONFIG_SMP */
3566
3567 struct irq_chip dmar_msi_type = {
3568         .name = "DMAR_MSI",
3569         .unmask = dmar_msi_unmask,
3570         .mask = dmar_msi_mask,
3571         .ack = ack_apic_edge,
3572 #ifdef CONFIG_SMP
3573         .set_affinity = dmar_msi_set_affinity,
3574 #endif
3575         .retrigger = ioapic_retrigger_irq,
3576 };
3577
3578 int arch_setup_dmar_msi(unsigned int irq)
3579 {
3580         int ret;
3581         struct msi_msg msg;
3582
3583         ret = msi_compose_msg(NULL, irq, &msg);
3584         if (ret < 0)
3585                 return ret;
3586         dmar_msi_write(irq, &msg);
3587         set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3588                 "edge");
3589         return 0;
3590 }
3591 #endif
3592
3593 #ifdef CONFIG_HPET_TIMER
3594
3595 #ifdef CONFIG_SMP
3596 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3597 {
3598         struct irq_desc *desc = irq_to_desc(irq);
3599         struct irq_cfg *cfg;
3600         struct msi_msg msg;
3601         unsigned int dest;
3602
3603         dest = set_desc_affinity(desc, mask);
3604         if (dest == BAD_APICID)
3605                 return;
3606
3607         cfg = desc->chip_data;
3608
3609         hpet_msi_read(irq, &msg);
3610
3611         msg.data &= ~MSI_DATA_VECTOR_MASK;
3612         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3613         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3614         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3615
3616         hpet_msi_write(irq, &msg);
3617 }
3618
3619 #endif /* CONFIG_SMP */
3620
3621 struct irq_chip hpet_msi_type = {
3622         .name = "HPET_MSI",
3623         .unmask = hpet_msi_unmask,
3624         .mask = hpet_msi_mask,
3625         .ack = ack_apic_edge,
3626 #ifdef CONFIG_SMP
3627         .set_affinity = hpet_msi_set_affinity,
3628 #endif
3629         .retrigger = ioapic_retrigger_irq,
3630 };
3631
3632 int arch_setup_hpet_msi(unsigned int irq)
3633 {
3634         int ret;
3635         struct msi_msg msg;
3636
3637         ret = msi_compose_msg(NULL, irq, &msg);
3638         if (ret < 0)
3639                 return ret;
3640
3641         hpet_msi_write(irq, &msg);
3642         set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3643                 "edge");
3644
3645         return 0;
3646 }
3647 #endif
3648
3649 #endif /* CONFIG_PCI_MSI */
3650 /*
3651  * Hypertransport interrupt support
3652  */
3653 #ifdef CONFIG_HT_IRQ
3654
3655 #ifdef CONFIG_SMP
3656
3657 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3658 {
3659         struct ht_irq_msg msg;
3660         fetch_ht_irq_msg(irq, &msg);
3661
3662         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3663         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3664
3665         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3666         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3667
3668         write_ht_irq_msg(irq, &msg);
3669 }
3670
3671 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3672 {
3673         struct irq_desc *desc = irq_to_desc(irq);
3674         struct irq_cfg *cfg;
3675         unsigned int dest;
3676
3677         dest = set_desc_affinity(desc, mask);
3678         if (dest == BAD_APICID)
3679                 return;
3680
3681         cfg = desc->chip_data;
3682
3683         target_ht_irq(irq, dest, cfg->vector);
3684 }
3685
3686 #endif
3687
3688 static struct irq_chip ht_irq_chip = {
3689         .name           = "PCI-HT",
3690         .mask           = mask_ht_irq,
3691         .unmask         = unmask_ht_irq,
3692         .ack            = ack_apic_edge,
3693 #ifdef CONFIG_SMP
3694         .set_affinity   = set_ht_irq_affinity,
3695 #endif
3696         .retrigger      = ioapic_retrigger_irq,
3697 };
3698
3699 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3700 {
3701         struct irq_cfg *cfg;
3702         int err;
3703
3704         if (disable_apic)
3705                 return -ENXIO;
3706
3707         cfg = irq_cfg(irq);
3708         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3709         if (!err) {
3710                 struct ht_irq_msg msg;
3711                 unsigned dest;
3712
3713                 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3714                                                     apic->target_cpus());
3715
3716                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3717
3718                 msg.address_lo =
3719                         HT_IRQ_LOW_BASE |
3720                         HT_IRQ_LOW_DEST_ID(dest) |
3721                         HT_IRQ_LOW_VECTOR(cfg->vector) |
3722                         ((apic->irq_dest_mode == 0) ?
3723                                 HT_IRQ_LOW_DM_PHYSICAL :
3724                                 HT_IRQ_LOW_DM_LOGICAL) |
3725                         HT_IRQ_LOW_RQEOI_EDGE |
3726                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3727                                 HT_IRQ_LOW_MT_FIXED :
3728                                 HT_IRQ_LOW_MT_ARBITRATED) |
3729                         HT_IRQ_LOW_IRQ_MASKED;
3730
3731                 write_ht_irq_msg(irq, &msg);
3732
3733                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3734                                               handle_edge_irq, "edge");
3735
3736                 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3737         }
3738         return err;
3739 }
3740 #endif /* CONFIG_HT_IRQ */
3741
3742 #ifdef CONFIG_X86_UV
3743 /*
3744  * Re-target the irq to the specified CPU and enable the specified MMR located
3745  * on the specified blade to allow the sending of MSIs to the specified CPU.
3746  */
3747 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3748                        unsigned long mmr_offset)
3749 {
3750         const struct cpumask *eligible_cpu = cpumask_of(cpu);
3751         struct irq_cfg *cfg;
3752         int mmr_pnode;
3753         unsigned long mmr_value;
3754         struct uv_IO_APIC_route_entry *entry;
3755         unsigned long flags;
3756         int err;
3757
3758         cfg = irq_cfg(irq);
3759
3760         err = assign_irq_vector(irq, cfg, eligible_cpu);
3761         if (err != 0)
3762                 return err;
3763
3764         spin_lock_irqsave(&vector_lock, flags);
3765         set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3766                                       irq_name);
3767         spin_unlock_irqrestore(&vector_lock, flags);
3768
3769         mmr_value = 0;
3770         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3771         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3772
3773         entry->vector = cfg->vector;
3774         entry->delivery_mode = apic->irq_delivery_mode;
3775         entry->dest_mode = apic->irq_dest_mode;
3776         entry->polarity = 0;
3777         entry->trigger = 0;
3778         entry->mask = 0;
3779         entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3780
3781         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3782         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3783
3784         return irq;
3785 }
3786
3787 /*
3788  * Disable the specified MMR located on the specified blade so that MSIs are
3789  * longer allowed to be sent.
3790  */
3791 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3792 {
3793         unsigned long mmr_value;
3794         struct uv_IO_APIC_route_entry *entry;
3795         int mmr_pnode;
3796
3797         mmr_value = 0;
3798         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3799         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3800
3801         entry->mask = 1;
3802
3803         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3804         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3805 }
3806 #endif /* CONFIG_X86_64 */
3807
3808 int __init io_apic_get_redir_entries (int ioapic)
3809 {
3810         union IO_APIC_reg_01    reg_01;
3811         unsigned long flags;
3812
3813         spin_lock_irqsave(&ioapic_lock, flags);
3814         reg_01.raw = io_apic_read(ioapic, 1);
3815         spin_unlock_irqrestore(&ioapic_lock, flags);
3816
3817         return reg_01.bits.entries;
3818 }
3819
3820 void __init probe_nr_irqs_gsi(void)
3821 {
3822         int idx;
3823         int nr = 0;
3824
3825         for (idx = 0; idx < nr_ioapics; idx++)
3826                 nr += io_apic_get_redir_entries(idx) + 1;
3827
3828         if (nr > nr_irqs_gsi)
3829                 nr_irqs_gsi = nr;
3830 }
3831
3832 #ifdef CONFIG_SPARSE_IRQ
3833 int __init arch_probe_nr_irqs(void)
3834 {
3835         int nr;
3836
3837         nr = ((8 * nr_cpu_ids) > (32 * nr_ioapics) ?
3838                 (NR_VECTORS + (8 * nr_cpu_ids)) :
3839                 (NR_VECTORS + (32 * nr_ioapics)));
3840
3841         if (nr < nr_irqs && nr > nr_irqs_gsi)
3842                 nr_irqs = nr;
3843
3844         return 0;
3845 }
3846 #endif
3847
3848 /* --------------------------------------------------------------------------
3849                           ACPI-based IOAPIC Configuration
3850    -------------------------------------------------------------------------- */
3851
3852 #ifdef CONFIG_ACPI
3853
3854 #ifdef CONFIG_X86_32
3855 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3856 {
3857         union IO_APIC_reg_00 reg_00;
3858         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3859         physid_mask_t tmp;
3860         unsigned long flags;
3861         int i = 0;
3862
3863         /*
3864          * The P4 platform supports up to 256 APIC IDs on two separate APIC
3865          * buses (one for LAPICs, one for IOAPICs), where predecessors only
3866          * supports up to 16 on one shared APIC bus.
3867          *
3868          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3869          *      advantage of new APIC bus architecture.
3870          */
3871
3872         if (physids_empty(apic_id_map))
3873                 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3874
3875         spin_lock_irqsave(&ioapic_lock, flags);
3876         reg_00.raw = io_apic_read(ioapic, 0);
3877         spin_unlock_irqrestore(&ioapic_lock, flags);
3878
3879         if (apic_id >= get_physical_broadcast()) {
3880                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3881                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
3882                 apic_id = reg_00.bits.ID;
3883         }
3884
3885         /*
3886          * Every APIC in a system must have a unique ID or we get lots of nice
3887          * 'stuck on smp_invalidate_needed IPI wait' messages.
3888          */
3889         if (apic->check_apicid_used(apic_id_map, apic_id)) {
3890
3891                 for (i = 0; i < get_physical_broadcast(); i++) {
3892                         if (!apic->check_apicid_used(apic_id_map, i))
3893                                 break;
3894                 }
3895
3896                 if (i == get_physical_broadcast())
3897                         panic("Max apic_id exceeded!\n");
3898
3899                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3900                         "trying %d\n", ioapic, apic_id, i);
3901
3902                 apic_id = i;
3903         }
3904
3905         tmp = apic->apicid_to_cpu_present(apic_id);
3906         physids_or(apic_id_map, apic_id_map, tmp);
3907
3908         if (reg_00.bits.ID != apic_id) {
3909                 reg_00.bits.ID = apic_id;
3910
3911                 spin_lock_irqsave(&ioapic_lock, flags);
3912                 io_apic_write(ioapic, 0, reg_00.raw);
3913                 reg_00.raw = io_apic_read(ioapic, 0);
3914                 spin_unlock_irqrestore(&ioapic_lock, flags);
3915
3916                 /* Sanity check */
3917                 if (reg_00.bits.ID != apic_id) {
3918                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3919                         return -1;
3920                 }
3921         }
3922
3923         apic_printk(APIC_VERBOSE, KERN_INFO
3924                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3925
3926         return apic_id;
3927 }
3928
3929 int __init io_apic_get_version(int ioapic)
3930 {
3931         union IO_APIC_reg_01    reg_01;
3932         unsigned long flags;
3933
3934         spin_lock_irqsave(&ioapic_lock, flags);
3935         reg_01.raw = io_apic_read(ioapic, 1);
3936         spin_unlock_irqrestore(&ioapic_lock, flags);
3937
3938         return reg_01.bits.version;
3939 }
3940 #endif
3941
3942 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3943 {
3944         struct irq_desc *desc;
3945         struct irq_cfg *cfg;
3946         int cpu = boot_cpu_id;
3947
3948         if (!IO_APIC_IRQ(irq)) {
3949                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3950                         ioapic);
3951                 return -EINVAL;
3952         }
3953
3954         desc = irq_to_desc_alloc_cpu(irq, cpu);
3955         if (!desc) {
3956                 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3957                 return 0;
3958         }
3959
3960         /*
3961          * IRQs < 16 are already in the irq_2_pin[] map
3962          */
3963         if (irq >= NR_IRQS_LEGACY) {
3964                 cfg = desc->chip_data;
3965                 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3966         }
3967
3968         setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3969
3970         return 0;
3971 }
3972
3973
3974 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3975 {
3976         int i;
3977
3978         if (skip_ioapic_setup)
3979                 return -1;
3980
3981         for (i = 0; i < mp_irq_entries; i++)
3982                 if (mp_irqs[i].irqtype == mp_INT &&
3983                     mp_irqs[i].srcbusirq == bus_irq)
3984                         break;
3985         if (i >= mp_irq_entries)
3986                 return -1;
3987
3988         *trigger = irq_trigger(i);
3989         *polarity = irq_polarity(i);
3990         return 0;
3991 }
3992
3993 #endif /* CONFIG_ACPI */
3994
3995 /*
3996  * This function currently is only a helper for the i386 smp boot process where
3997  * we need to reprogram the ioredtbls to cater for the cpus which have come online
3998  * so mask in all cases should simply be apic->target_cpus()
3999  */
4000 #ifdef CONFIG_SMP
4001 void __init setup_ioapic_dest(void)
4002 {
4003         int pin, ioapic, irq, irq_entry;
4004         struct irq_desc *desc;
4005         struct irq_cfg *cfg;
4006         const struct cpumask *mask;
4007
4008         if (skip_ioapic_setup == 1)
4009                 return;
4010
4011         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4012                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4013                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4014                         if (irq_entry == -1)
4015                                 continue;
4016                         irq = pin_2_irq(irq_entry, ioapic, pin);
4017
4018                         /* setup_IO_APIC_irqs could fail to get vector for some device
4019                          * when you have too many devices, because at that time only boot
4020                          * cpu is online.
4021                          */
4022                         desc = irq_to_desc(irq);
4023                         cfg = desc->chip_data;
4024                         if (!cfg->vector) {
4025                                 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4026                                                   irq_trigger(irq_entry),
4027                                                   irq_polarity(irq_entry));
4028                                 continue;
4029
4030                         }
4031
4032                         /*
4033                          * Honour affinities which have been set in early boot
4034                          */
4035                         if (desc->status &
4036                             (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4037                                 mask = desc->affinity;
4038                         else
4039                                 mask = apic->target_cpus();
4040
4041 #ifdef CONFIG_INTR_REMAP
4042                         if (intr_remapping_enabled)
4043                                 set_ir_ioapic_affinity_irq_desc(desc, mask);
4044                         else
4045 #endif
4046                                 set_ioapic_affinity_irq_desc(desc, mask);
4047                 }
4048
4049         }
4050 }
4051 #endif
4052
4053 #define IOAPIC_RESOURCE_NAME_SIZE 11
4054
4055 static struct resource *ioapic_resources;
4056
4057 static struct resource * __init ioapic_setup_resources(void)
4058 {
4059         unsigned long n;
4060         struct resource *res;
4061         char *mem;
4062         int i;
4063
4064         if (nr_ioapics <= 0)
4065                 return NULL;
4066
4067         n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4068         n *= nr_ioapics;
4069
4070         mem = alloc_bootmem(n);
4071         res = (void *)mem;
4072
4073         if (mem != NULL) {
4074                 mem += sizeof(struct resource) * nr_ioapics;
4075
4076                 for (i = 0; i < nr_ioapics; i++) {
4077                         res[i].name = mem;
4078                         res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4079                         sprintf(mem,  "IOAPIC %u", i);
4080                         mem += IOAPIC_RESOURCE_NAME_SIZE;
4081                 }
4082         }
4083
4084         ioapic_resources = res;
4085
4086         return res;
4087 }
4088
4089 void __init ioapic_init_mappings(void)
4090 {
4091         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4092         struct resource *ioapic_res;
4093         int i;
4094
4095         ioapic_res = ioapic_setup_resources();
4096         for (i = 0; i < nr_ioapics; i++) {
4097                 if (smp_found_config) {
4098                         ioapic_phys = mp_ioapics[i].apicaddr;
4099 #ifdef CONFIG_X86_32
4100                         if (!ioapic_phys) {
4101                                 printk(KERN_ERR
4102                                        "WARNING: bogus zero IO-APIC "
4103                                        "address found in MPTABLE, "
4104                                        "disabling IO/APIC support!\n");
4105                                 smp_found_config = 0;
4106                                 skip_ioapic_setup = 1;
4107                                 goto fake_ioapic_page;
4108                         }
4109 #endif
4110                 } else {
4111 #ifdef CONFIG_X86_32
4112 fake_ioapic_page:
4113 #endif
4114                         ioapic_phys = (unsigned long)
4115                                 alloc_bootmem_pages(PAGE_SIZE);
4116                         ioapic_phys = __pa(ioapic_phys);
4117                 }
4118                 set_fixmap_nocache(idx, ioapic_phys);
4119                 apic_printk(APIC_VERBOSE,
4120                             "mapped IOAPIC to %08lx (%08lx)\n",
4121                             __fix_to_virt(idx), ioapic_phys);
4122                 idx++;
4123
4124                 if (ioapic_res != NULL) {
4125                         ioapic_res->start = ioapic_phys;
4126                         ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4127                         ioapic_res++;
4128                 }
4129         }
4130 }
4131
4132 static int __init ioapic_insert_resources(void)
4133 {
4134         int i;
4135         struct resource *r = ioapic_resources;
4136
4137         if (!r) {
4138                 printk(KERN_ERR
4139                        "IO APIC resources could be not be allocated.\n");
4140                 return -1;
4141         }
4142
4143         for (i = 0; i < nr_ioapics; i++) {
4144                 insert_resource(&iomem_resource, r);
4145                 r++;
4146         }
4147
4148         return 0;
4149 }
4150
4151 /* Insert the IO APIC resources after PCI initialization has occured to handle
4152  * IO APICS that are mapped in on a BAR in PCI space. */
4153 late_initcall(ioapic_insert_resources);