1 #include <linux/linkage.h>
2 #include <linux/errno.h>
3 #include <linux/signal.h>
4 #include <linux/sched.h>
5 #include <linux/ioport.h>
6 #include <linux/interrupt.h>
7 #include <linux/timex.h>
8 #include <linux/slab.h>
9 #include <linux/random.h>
10 #include <linux/init.h>
11 #include <linux/kernel_stat.h>
12 #include <linux/sysdev.h>
13 #include <linux/bitops.h>
14 #include <linux/acpi.h>
16 #include <linux/delay.h>
18 #include <asm/atomic.h>
19 #include <asm/system.h>
20 #include <asm/timer.h>
21 #include <asm/hw_irq.h>
22 #include <asm/pgtable.h>
25 #include <asm/i8259.h>
28 * This is the 'legacy' 8259A Programmable Interrupt Controller,
29 * present in the majority of PC/AT boxes.
30 * plus some generic x86 specific things if generic specifics makes
34 static int i8259A_auto_eoi;
35 DEFINE_RAW_SPINLOCK(i8259A_lock);
36 static void mask_and_ack_8259A(unsigned int);
37 static void mask_8259A(void);
38 static void unmask_8259A(void);
39 static void disable_8259A_irq(unsigned int irq);
40 static void enable_8259A_irq(unsigned int irq);
41 static void init_8259A(int auto_eoi);
42 static int i8259A_irq_pending(unsigned int irq);
44 struct irq_chip i8259A_chip = {
46 .mask = disable_8259A_irq,
47 .disable = disable_8259A_irq,
48 .unmask = enable_8259A_irq,
49 .mask_ack = mask_and_ack_8259A,
53 * 8259A PIC functions to handle ISA devices:
57 * This contains the irq mask for both 8259A irq controllers,
59 unsigned int cached_irq_mask = 0xffff;
62 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
63 * boards the timer interrupt is not really connected to any IO-APIC pin,
64 * it's fed to the master 8259A's IR0 line only.
66 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
67 * this 'mixed mode' IRQ handling costs nothing because it's only used
70 unsigned long io_apic_irqs;
72 static void disable_8259A_irq(unsigned int irq)
74 unsigned int mask = 1 << irq;
77 raw_spin_lock_irqsave(&i8259A_lock, flags);
78 cached_irq_mask |= mask;
80 outb(cached_slave_mask, PIC_SLAVE_IMR);
82 outb(cached_master_mask, PIC_MASTER_IMR);
83 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
86 static void enable_8259A_irq(unsigned int irq)
88 unsigned int mask = ~(1 << irq);
91 raw_spin_lock_irqsave(&i8259A_lock, flags);
92 cached_irq_mask &= mask;
94 outb(cached_slave_mask, PIC_SLAVE_IMR);
96 outb(cached_master_mask, PIC_MASTER_IMR);
97 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
100 static int i8259A_irq_pending(unsigned int irq)
102 unsigned int mask = 1<<irq;
106 raw_spin_lock_irqsave(&i8259A_lock, flags);
108 ret = inb(PIC_MASTER_CMD) & mask;
110 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
111 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
116 static void make_8259A_irq(unsigned int irq)
118 disable_irq_nosync(irq);
119 io_apic_irqs &= ~(1<<irq);
120 set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
126 * This function assumes to be called rarely. Switching between
127 * 8259A registers is slow.
128 * This has to be protected by the irq controller spinlock
129 * before being called.
131 static inline int i8259A_irq_real(unsigned int irq)
134 int irqmask = 1<<irq;
137 outb(0x0B, PIC_MASTER_CMD); /* ISR register */
138 value = inb(PIC_MASTER_CMD) & irqmask;
139 outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
142 outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
143 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
144 outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
149 * Careful! The 8259A is a fragile beast, it pretty
150 * much _has_ to be done exactly like this (mask it
151 * first, _then_ send the EOI, and the order of EOI
152 * to the two 8259s is important!
154 static void mask_and_ack_8259A(unsigned int irq)
156 unsigned int irqmask = 1 << irq;
159 raw_spin_lock_irqsave(&i8259A_lock, flags);
161 * Lightweight spurious IRQ detection. We do not want
162 * to overdo spurious IRQ handling - it's usually a sign
163 * of hardware problems, so we only do the checks we can
164 * do without slowing down good hardware unnecessarily.
166 * Note that IRQ7 and IRQ15 (the two spurious IRQs
167 * usually resulting from the 8259A-1|2 PICs) occur
168 * even if the IRQ is masked in the 8259A. Thus we
169 * can check spurious 8259A IRQs without doing the
170 * quite slow i8259A_irq_real() call for every IRQ.
171 * This does not cover 100% of spurious interrupts,
172 * but should be enough to warn the user that there
173 * is something bad going on ...
175 if (cached_irq_mask & irqmask)
176 goto spurious_8259A_irq;
177 cached_irq_mask |= irqmask;
181 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
182 outb(cached_slave_mask, PIC_SLAVE_IMR);
183 /* 'Specific EOI' to slave */
184 outb(0x60+(irq&7), PIC_SLAVE_CMD);
185 /* 'Specific EOI' to master-IRQ2 */
186 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
188 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
189 outb(cached_master_mask, PIC_MASTER_IMR);
190 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
192 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
197 * this is the slow path - should happen rarely.
199 if (i8259A_irq_real(irq))
201 * oops, the IRQ _is_ in service according to the
202 * 8259A - not spurious, go handle it.
204 goto handle_real_irq;
207 static int spurious_irq_mask;
209 * At this point we can be sure the IRQ is spurious,
210 * lets ACK and report it. [once per IRQ]
212 if (!(spurious_irq_mask & irqmask)) {
214 "spurious 8259A interrupt: IRQ%d.\n", irq);
215 spurious_irq_mask |= irqmask;
217 atomic_inc(&irq_err_count);
219 * Theoretically we do not have to handle this IRQ,
220 * but in Linux this does not cause problems and is
223 goto handle_real_irq;
227 static char irq_trigger[2];
229 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
231 static void restore_ELCR(char *trigger)
233 outb(trigger[0], 0x4d0);
234 outb(trigger[1], 0x4d1);
237 static void save_ELCR(char *trigger)
239 /* IRQ 0,1,2,8,13 are marked as reserved */
240 trigger[0] = inb(0x4d0) & 0xF8;
241 trigger[1] = inb(0x4d1) & 0xDE;
244 static int i8259A_resume(struct sys_device *dev)
246 init_8259A(i8259A_auto_eoi);
247 restore_ELCR(irq_trigger);
251 static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
253 save_ELCR(irq_trigger);
257 static int i8259A_shutdown(struct sys_device *dev)
259 /* Put the i8259A into a quiescent state that
260 * the kernel initialization code can get it
263 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
264 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
268 static struct sysdev_class i8259_sysdev_class = {
270 .suspend = i8259A_suspend,
271 .resume = i8259A_resume,
272 .shutdown = i8259A_shutdown,
275 static struct sys_device device_i8259A = {
277 .cls = &i8259_sysdev_class,
280 static int __init i8259A_init_sysfs(void)
282 int error = sysdev_class_register(&i8259_sysdev_class);
284 error = sysdev_register(&device_i8259A);
288 device_initcall(i8259A_init_sysfs);
290 static void mask_8259A(void)
294 raw_spin_lock_irqsave(&i8259A_lock, flags);
296 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
297 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
299 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
302 static void unmask_8259A(void)
306 raw_spin_lock_irqsave(&i8259A_lock, flags);
308 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
309 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
311 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
314 static void init_8259A(int auto_eoi)
318 i8259A_auto_eoi = auto_eoi;
320 raw_spin_lock_irqsave(&i8259A_lock, flags);
322 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
323 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
326 * outb_pic - this has to work on a wide range of PC hardware.
328 outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
330 /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 on x86-64,
331 to 0x20-0x27 on i386 */
332 outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
334 /* 8259A-1 (the master) has a slave on IR2 */
335 outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);
337 if (auto_eoi) /* master does Auto EOI */
338 outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
339 else /* master expects normal EOI */
340 outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
342 outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
344 /* ICW2: 8259A-2 IR0-7 mapped to IRQ8_VECTOR */
345 outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
346 /* 8259A-2 is a slave on master's IR2 */
347 outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
348 /* (slave's support for AEOI in flat mode is to be investigated) */
349 outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
353 * In AEOI mode we just have to mask the interrupt
356 i8259A_chip.mask_ack = disable_8259A_irq;
358 i8259A_chip.mask_ack = mask_and_ack_8259A;
360 udelay(100); /* wait for 8259A to initialize */
362 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
363 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
365 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
369 * make i8259 a driver so that we can select pic functions at run time. the goal
370 * is to make x86 binary compatible among pc compatible and non-pc compatible
371 * platforms, such as x86 MID.
374 static void legacy_pic_noop(void) { };
375 static void legacy_pic_uint_noop(unsigned int unused) { };
376 static void legacy_pic_int_noop(int unused) { };
378 static struct irq_chip dummy_pic_chip = {
380 .mask = legacy_pic_uint_noop,
381 .unmask = legacy_pic_uint_noop,
382 .disable = legacy_pic_uint_noop,
383 .mask_ack = legacy_pic_uint_noop,
385 static int legacy_pic_irq_pending_noop(unsigned int irq)
390 struct legacy_pic null_legacy_pic = {
392 .chip = &dummy_pic_chip,
393 .mask_all = legacy_pic_noop,
394 .restore_mask = legacy_pic_noop,
395 .init = legacy_pic_int_noop,
396 .irq_pending = legacy_pic_irq_pending_noop,
397 .make_irq = legacy_pic_uint_noop,
400 struct legacy_pic default_legacy_pic = {
401 .nr_legacy_irqs = NR_IRQS_LEGACY,
402 .chip = &i8259A_chip,
403 .mask_all = mask_8259A,
404 .restore_mask = unmask_8259A,
406 .irq_pending = i8259A_irq_pending,
407 .make_irq = make_8259A_irq,
410 struct legacy_pic *legacy_pic = &default_legacy_pic;