2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16 * Copyright (C) 2007 Alan Stern
17 * Copyright (C) 2009 IBM Corporation
18 * Copyright (C) 2009 Frederic Weisbecker <fweisbec@gmail.com>
22 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
23 * using the CPU's debug registers.
26 #include <linux/perf_event.h>
27 #include <linux/hw_breakpoint.h>
28 #include <linux/irqflags.h>
29 #include <linux/notifier.h>
30 #include <linux/kallsyms.h>
31 #include <linux/kprobes.h>
32 #include <linux/percpu.h>
33 #include <linux/kdebug.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/sched.h>
37 #include <linux/init.h>
38 #include <linux/smp.h>
40 #include <asm/hw_breakpoint.h>
41 #include <asm/processor.h>
42 #include <asm/debugreg.h>
44 /* Per cpu debug control register value */
45 DEFINE_PER_CPU(unsigned long, dr7);
47 /* Per cpu debug address registers values */
48 static DEFINE_PER_CPU(unsigned long, cpu_debugreg[HBP_NUM]);
51 * Stores the breakpoints currently in use on each breakpoint address
52 * register for each cpus
54 static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM]);
58 * Encode the length, type, Exact, and Enable bits for a particular breakpoint
59 * as stored in debug register 7.
61 unsigned long encode_dr7(int drnum, unsigned int len, unsigned int type)
63 unsigned long bp_info;
65 bp_info = (len | type) & 0xf;
66 bp_info <<= (DR_CONTROL_SHIFT + drnum * DR_CONTROL_SIZE);
67 bp_info |= (DR_GLOBAL_ENABLE << (drnum * DR_ENABLE_SIZE)) |
73 * Decode the length and type bits for a particular breakpoint as
74 * stored in debug register 7. Return the "enabled" status.
76 int decode_dr7(unsigned long dr7, int bpnum, unsigned *len, unsigned *type)
78 int bp_info = dr7 >> (DR_CONTROL_SHIFT + bpnum * DR_CONTROL_SIZE);
80 *len = (bp_info & 0xc) | 0x40;
81 *type = (bp_info & 0x3) | 0x80;
83 return (dr7 >> (bpnum * DR_ENABLE_SIZE)) & 0x3;
87 * Install a perf counter breakpoint.
89 * We seek a free debug address register and use it for this
90 * breakpoint. Eventually we enable it in the debug control register.
92 * Atomic: we hold the counter->ctx->lock and we only handle variables
93 * and registers local to this cpu.
95 int arch_install_hw_breakpoint(struct perf_event *bp)
97 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
101 for (i = 0; i < HBP_NUM; i++) {
102 struct perf_event **slot = &__get_cpu_var(bp_per_reg[i]);
110 if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
113 set_debugreg(info->address, i);
114 __get_cpu_var(cpu_debugreg[i]) = info->address;
116 dr7 = &__get_cpu_var(dr7);
117 *dr7 |= encode_dr7(i, info->len, info->type);
119 set_debugreg(*dr7, 7);
125 * Uninstall the breakpoint contained in the given counter.
127 * First we search the debug address register it uses and then we disable
130 * Atomic: we hold the counter->ctx->lock and we only handle variables
131 * and registers local to this cpu.
133 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
135 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
139 for (i = 0; i < HBP_NUM; i++) {
140 struct perf_event **slot = &__get_cpu_var(bp_per_reg[i]);
148 if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
151 dr7 = &__get_cpu_var(dr7);
152 *dr7 &= ~encode_dr7(i, info->len, info->type);
154 set_debugreg(*dr7, 7);
157 static int get_hbp_len(u8 hbp_len)
159 unsigned int len_in_bytes = 0;
162 case X86_BREAKPOINT_LEN_1:
165 case X86_BREAKPOINT_LEN_2:
168 case X86_BREAKPOINT_LEN_4:
172 case X86_BREAKPOINT_LEN_8:
181 * Check for virtual address in user space.
183 int arch_check_va_in_userspace(unsigned long va, u8 hbp_len)
187 len = get_hbp_len(hbp_len);
189 return (va <= TASK_SIZE - len);
193 * Check for virtual address in kernel space.
195 static int arch_check_va_in_kernelspace(unsigned long va, u8 hbp_len)
199 len = get_hbp_len(hbp_len);
201 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
205 * Store a breakpoint's encoded address, length, and type.
207 static int arch_store_info(struct perf_event *bp)
209 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
211 * For kernel-addresses, either the address or symbol name can be
215 info->address = (unsigned long)
216 kallsyms_lookup_name(info->name);
223 int arch_bp_generic_fields(int x86_len, int x86_type,
224 int *gen_len, int *gen_type)
228 case X86_BREAKPOINT_LEN_1:
229 *gen_len = HW_BREAKPOINT_LEN_1;
231 case X86_BREAKPOINT_LEN_2:
232 *gen_len = HW_BREAKPOINT_LEN_2;
234 case X86_BREAKPOINT_LEN_4:
235 *gen_len = HW_BREAKPOINT_LEN_4;
238 case X86_BREAKPOINT_LEN_8:
239 *gen_len = HW_BREAKPOINT_LEN_8;
248 case X86_BREAKPOINT_EXECUTE:
249 *gen_type = HW_BREAKPOINT_X;
251 case X86_BREAKPOINT_WRITE:
252 *gen_type = HW_BREAKPOINT_W;
254 case X86_BREAKPOINT_RW:
255 *gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R;
265 static int arch_build_bp_info(struct perf_event *bp)
267 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
269 info->address = bp->attr.bp_addr;
272 switch (bp->attr.bp_len) {
273 case HW_BREAKPOINT_LEN_1:
274 info->len = X86_BREAKPOINT_LEN_1;
276 case HW_BREAKPOINT_LEN_2:
277 info->len = X86_BREAKPOINT_LEN_2;
279 case HW_BREAKPOINT_LEN_4:
280 info->len = X86_BREAKPOINT_LEN_4;
283 case HW_BREAKPOINT_LEN_8:
284 info->len = X86_BREAKPOINT_LEN_8;
292 switch (bp->attr.bp_type) {
293 case HW_BREAKPOINT_W:
294 info->type = X86_BREAKPOINT_WRITE;
296 case HW_BREAKPOINT_W | HW_BREAKPOINT_R:
297 info->type = X86_BREAKPOINT_RW;
299 case HW_BREAKPOINT_X:
300 info->type = X86_BREAKPOINT_EXECUTE;
309 * Validate the arch-specific HW Breakpoint register settings
311 int arch_validate_hwbkpt_settings(struct perf_event *bp,
312 struct task_struct *tsk)
314 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
319 ret = arch_build_bp_info(bp);
325 if (info->type == X86_BREAKPOINT_EXECUTE)
327 * Ptrace-refactoring code
328 * For now, we'll allow instruction breakpoint only for user-space
331 if ((!arch_check_va_in_userspace(info->address, info->len)) &&
332 info->len != X86_BREAKPOINT_EXECUTE)
336 case X86_BREAKPOINT_LEN_1:
339 case X86_BREAKPOINT_LEN_2:
342 case X86_BREAKPOINT_LEN_4:
346 case X86_BREAKPOINT_LEN_8:
355 ret = arch_store_info(bp);
360 * Check that the low-order bits of the address are appropriate
361 * for the alignment implied by len.
363 if (info->address & align)
366 /* Check that the virtual address is in the proper range */
368 if (!arch_check_va_in_userspace(info->address, info->len))
371 if (!arch_check_va_in_kernelspace(info->address, info->len))
379 * Release the user breakpoints used by ptrace
381 void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
384 struct thread_struct *t = &tsk->thread;
386 for (i = 0; i < HBP_NUM; i++) {
387 unregister_hw_breakpoint(t->ptrace_bps[i]);
388 t->ptrace_bps[i] = NULL;
393 void hw_breakpoint_restore(void)
395 set_debugreg(__get_cpu_var(cpu_debugreg[0]), 0);
396 set_debugreg(__get_cpu_var(cpu_debugreg[1]), 1);
397 set_debugreg(__get_cpu_var(cpu_debugreg[2]), 2);
398 set_debugreg(__get_cpu_var(cpu_debugreg[3]), 3);
399 set_debugreg(current->thread.debugreg6, 6);
400 set_debugreg(__get_cpu_var(dr7), 7);
402 EXPORT_SYMBOL_GPL(hw_breakpoint_restore);
406 * Handle debug exception notifications.
408 * Return value is either NOTIFY_STOP or NOTIFY_DONE as explained below.
410 * NOTIFY_DONE returned if one of the following conditions is true.
411 * i) When the causative address is from user-space and the exception
412 * is a valid one, i.e. not triggered as a result of lazy debug register
414 * ii) When there are more bits than trap<n> set in DR6 register (such
415 * as BD, BS or BT) indicating that more than one debug condition is
416 * met and requires some more action in do_debug().
418 * NOTIFY_STOP returned for all other cases
421 static int __kprobes hw_breakpoint_handler(struct die_args *args)
423 int i, cpu, rc = NOTIFY_STOP;
424 struct perf_event *bp;
425 unsigned long dr7, dr6;
426 unsigned long *dr6_p;
428 /* The DR6 value is pointed by args->err */
429 dr6_p = (unsigned long *)ERR_PTR(args->err);
432 /* Do an early return if no trap bits are set in DR6 */
433 if ((dr6 & DR_TRAP_BITS) == 0)
436 get_debugreg(dr7, 7);
437 /* Disable breakpoints during exception handling */
438 set_debugreg(0UL, 7);
440 * Assert that local interrupts are disabled
441 * Reset the DRn bits in the virtualized register value.
442 * The ptrace trigger routine will add in whatever is needed.
444 current->thread.debugreg6 &= ~DR_TRAP_BITS;
447 /* Handle all the breakpoints that were triggered */
448 for (i = 0; i < HBP_NUM; ++i) {
449 if (likely(!(dr6 & (DR_TRAP0 << i))))
453 * The counter may be concurrently released but that can only
454 * occur from a call_rcu() path. We can then safely fetch
455 * the breakpoint, use its callback, touch its counter
456 * while we are in an rcu_read_lock() path.
460 bp = per_cpu(bp_per_reg[i], cpu);
464 * Reset the 'i'th TRAP bit in dr6 to denote completion of
467 (*dr6_p) &= ~(DR_TRAP0 << i);
469 * bp can be NULL due to lazy debug register switching
470 * or due to concurrent perf counter removing.
477 (bp->callback)(bp, args->regs);
481 if (dr6 & (~DR_TRAP_BITS))
484 set_debugreg(dr7, 7);
491 * Handle debug exception notifications.
493 int __kprobes hw_breakpoint_exceptions_notify(
494 struct notifier_block *unused, unsigned long val, void *data)
496 if (val != DIE_DEBUG)
499 return hw_breakpoint_handler(data);
502 void hw_breakpoint_pmu_read(struct perf_event *bp)
507 void hw_breakpoint_pmu_unthrottle(struct perf_event *bp)