arch/x86/kernel/hpet.c

   1 #include <linux/clocksource.h>
   2 #include <linux/clockchips.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/export.h>
   5 #include <linux/delay.h>
   6 #include <linux/errno.h>
   7 #include <linux/i8253.h>
   8 #include <linux/slab.h>
   9 #include <linux/hpet.h>
  10 #include <linux/init.h>
  11 #include <linux/cpu.h>
  12 #include <linux/pm.h>
  13 #include <linux/io.h>
  14
  15 #include <asm/irqdomain.h>
  16 #include <asm/fixmap.h>
  17 #include <asm/hpet.h>
  18 #include <asm/time.h>
  19
  20 #define HPET_MASK                       CLOCKSOURCE_MASK(32)
  21
  22 /* FSEC = 10^-15
  23    NSEC = 10^-9 */
  24 #define FSEC_PER_NSEC                   1000000L
  25
  26 #define HPET_DEV_USED_BIT               2
  27 #define HPET_DEV_USED                   (1 << HPET_DEV_USED_BIT)
  28 #define HPET_DEV_VALID                  0x8
  29 #define HPET_DEV_FSB_CAP                0x1000
  30 #define HPET_DEV_PERI_CAP               0x2000
  31
  32 #define HPET_MIN_CYCLES                 128
  33 #define HPET_MIN_PROG_DELTA             (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
  34
  35 /*
  36  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  37  */
  38 unsigned long                           hpet_address;
  39 u8                                      hpet_blockid; /* OS timer block num */
  40 u8                                      hpet_msi_disable;
  41
  42 #ifdef CONFIG_PCI_MSI
  43 static unsigned long                    hpet_num_timers;
  44 #endif
  45 static void __iomem                     *hpet_virt_address;
  46
  47 struct hpet_dev {
  48         struct clock_event_device       evt;
  49         unsigned int                    num;
  50         int                             cpu;
  51         unsigned int                    irq;
  52         unsigned int                    flags;
  53         char                            name[10];
  54 };
  55
  56 inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
  57 {
  58         return container_of(evtdev, struct hpet_dev, evt);
  59 }
  60
  61 inline unsigned int hpet_readl(unsigned int a)
  62 {
  63         return readl(hpet_virt_address + a);
  64 }
  65
  66 static inline void hpet_writel(unsigned int d, unsigned int a)
  67 {
  68         writel(d, hpet_virt_address + a);
  69 }
  70
  71 #ifdef CONFIG_X86_64
  72 #include <asm/pgtable.h>
  73 #endif
  74
  75 static inline void hpet_set_mapping(void)
  76 {
  77         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
  78 }
  79
  80 static inline void hpet_clear_mapping(void)
  81 {
  82         iounmap(hpet_virt_address);
  83         hpet_virt_address = NULL;
  84 }
  85
  86 /*
  87  * HPET command line enable / disable
  88  */
  89 int boot_hpet_disable;
  90 int hpet_force_user;
  91 static int hpet_verbose;
  92
  93 static int __init hpet_setup(char *str)
  94 {
  95         while (str) {
  96                 char *next = strchr(str, ',');
  97
  98                 if (next)
  99                         *next++ = 0;
 100                 if (!strncmp("disable", str, 7))
 101                         boot_hpet_disable = 1;
 102                 if (!strncmp("force", str, 5))
 103                         hpet_force_user = 1;
 104                 if (!strncmp("verbose", str, 7))
 105                         hpet_verbose = 1;
 106                 str = next;
 107         }
 108         return 1;
 109 }
 110 __setup("hpet=", hpet_setup);
 111
 112 static int __init disable_hpet(char *str)
 113 {
 114         boot_hpet_disable = 1;
 115         return 1;
 116 }
 117 __setup("nohpet", disable_hpet);
 118
 119 static inline int is_hpet_capable(void)
 120 {
 121         return !boot_hpet_disable && hpet_address;
 122 }
 123
 124 /*
 125  * HPET timer interrupt enable / disable
 126  */
 127 static int hpet_legacy_int_enabled;
 128
 129 /**
 130  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 131  */
 132 int is_hpet_enabled(void)
 133 {
 134         return is_hpet_capable() && hpet_legacy_int_enabled;
 135 }
 136 EXPORT_SYMBOL_GPL(is_hpet_enabled);
 137
 138 static void _hpet_print_config(const char *function, int line)
 139 {
 140         u32 i, timers, l, h;
 141         printk(KERN_INFO "hpet: %s(%d):\n", function, line);
 142         l = hpet_readl(HPET_ID);
 143         h = hpet_readl(HPET_PERIOD);
 144         timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 145         printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
 146         l = hpet_readl(HPET_CFG);
 147         h = hpet_readl(HPET_STATUS);
 148         printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
 149         l = hpet_readl(HPET_COUNTER);
 150         h = hpet_readl(HPET_COUNTER+4);
 151         printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
 152
 153         for (i = 0; i < timers; i++) {
 154                 l = hpet_readl(HPET_Tn_CFG(i));
 155                 h = hpet_readl(HPET_Tn_CFG(i)+4);
 156                 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
 157                        i, l, h);
 158                 l = hpet_readl(HPET_Tn_CMP(i));
 159                 h = hpet_readl(HPET_Tn_CMP(i)+4);
 160                 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
 161                        i, l, h);
 162                 l = hpet_readl(HPET_Tn_ROUTE(i));
 163                 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
 164                 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
 165                        i, l, h);
 166         }
 167 }
 168
 169 #define hpet_print_config()                                     \
 170 do {                                                            \
 171         if (hpet_verbose)                                       \
 172                 _hpet_print_config(__func__, __LINE__); \
 173 } while (0)
 174
 175 /*
 176  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 177  * timer 0 and timer 1 in case of RTC emulation.
 178  */
 179 #ifdef CONFIG_HPET
 180
 181 static void hpet_reserve_msi_timers(struct hpet_data *hd);
 182
 183 static void hpet_reserve_platform_timers(unsigned int id)
 184 {
 185         struct hpet __iomem *hpet = hpet_virt_address;
 186         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
 187         unsigned int nrtimers, i;
 188         struct hpet_data hd;
 189
 190         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 191
 192         memset(&hd, 0, sizeof(hd));
 193         hd.hd_phys_address      = hpet_address;
 194         hd.hd_address           = hpet;
 195         hd.hd_nirqs             = nrtimers;
 196         hpet_reserve_timer(&hd, 0);
 197
 198 #ifdef CONFIG_HPET_EMULATE_RTC
 199         hpet_reserve_timer(&hd, 1);
 200 #endif
 201
 202         /*
 203          * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
 204          * is wrong for i8259!) not the output IRQ.  Many BIOS writers
 205          * don't bother configuring *any* comparator interrupts.
 206          */
 207         hd.hd_irq[0] = HPET_LEGACY_8254;
 208         hd.hd_irq[1] = HPET_LEGACY_RTC;
 209
 210         for (i = 2; i < nrtimers; timer++, i++) {
 211                 hd.hd_irq[i] = (readl(&timer->hpet_config) &
 212                         Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
 213         }
 214
 215         hpet_reserve_msi_timers(&hd);
 216
 217         hpet_alloc(&hd);
 218
 219 }
 220 #else
 221 static void hpet_reserve_platform_timers(unsigned int id) { }
 222 #endif
 223
 224 /*
 225  * Common hpet info
 226  */
 227 static unsigned long hpet_freq;
 228
 229 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 230                           struct clock_event_device *evt);
 231 static int hpet_legacy_next_event(unsigned long delta,
 232                            struct clock_event_device *evt);
 233
 234 /*
 235  * The hpet clock event device
 236  */
 237 static struct clock_event_device hpet_clockevent = {
 238         .name           = "hpet",
 239         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 240         .set_mode       = hpet_legacy_set_mode,
 241         .set_next_event = hpet_legacy_next_event,
 242         .irq            = 0,
 243         .rating         = 50,
 244 };
 245
 246 static void hpet_stop_counter(void)
 247 {
 248         unsigned long cfg = hpet_readl(HPET_CFG);
 249         cfg &= ~HPET_CFG_ENABLE;
 250         hpet_writel(cfg, HPET_CFG);
 251 }
 252
 253 static void hpet_reset_counter(void)
 254 {
 255         hpet_writel(0, HPET_COUNTER);
 256         hpet_writel(0, HPET_COUNTER + 4);
 257 }
 258
 259 static void hpet_start_counter(void)
 260 {
 261         unsigned int cfg = hpet_readl(HPET_CFG);
 262         cfg |= HPET_CFG_ENABLE;
 263         hpet_writel(cfg, HPET_CFG);
 264 }
 265
 266 static void hpet_restart_counter(void)
 267 {
 268         hpet_stop_counter();
 269         hpet_reset_counter();
 270         hpet_start_counter();
 271 }
 272
 273 static void hpet_resume_device(void)
 274 {
 275         force_hpet_resume();
 276 }
 277
 278 static void hpet_resume_counter(struct clocksource *cs)
 279 {
 280         hpet_resume_device();
 281         hpet_restart_counter();
 282 }
 283
 284 static void hpet_enable_legacy_int(void)
 285 {
 286         unsigned int cfg = hpet_readl(HPET_CFG);
 287
 288         cfg |= HPET_CFG_LEGACY;
 289         hpet_writel(cfg, HPET_CFG);
 290         hpet_legacy_int_enabled = 1;
 291 }
 292
 293 static void hpet_legacy_clockevent_register(void)
 294 {
 295         /* Start HPET legacy interrupts */
 296         hpet_enable_legacy_int();
 297
 298         /*
 299          * Start hpet with the boot cpu mask and make it
 300          * global after the IO_APIC has been initialized.
 301          */
 302         hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
 303         clockevents_config_and_register(&hpet_clockevent, hpet_freq,
 304                                         HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
 305         global_clock_event = &hpet_clockevent;
 306         printk(KERN_DEBUG "hpet clockevent registered\n");
 307 }
 308
 309 static void hpet_set_mode(enum clock_event_mode mode,
 310                           struct clock_event_device *evt, int timer)
 311 {
 312         unsigned int cfg, cmp, now;
 313         uint64_t delta;
 314
 315         switch (mode) {
 316         case CLOCK_EVT_MODE_PERIODIC:
 317                 hpet_stop_counter();
 318                 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
 319                 delta >>= evt->shift;
 320                 now = hpet_readl(HPET_COUNTER);
 321                 cmp = now + (unsigned int) delta;
 322                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 323                 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
 324                        HPET_TN_SETVAL | HPET_TN_32BIT;
 325                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 326                 hpet_writel(cmp, HPET_Tn_CMP(timer));
 327                 udelay(1);
 328                 /*
 329                  * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
 330                  * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
 331                  * bit is automatically cleared after the first write.
 332                  * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
 333                  * Publication # 24674)
 334                  */
 335                 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
 336                 hpet_start_counter();
 337                 hpet_print_config();
 338                 break;
 339
 340         case CLOCK_EVT_MODE_ONESHOT:
 341                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 342                 cfg &= ~HPET_TN_PERIODIC;
 343                 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 344                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 345                 break;
 346
 347         case CLOCK_EVT_MODE_UNUSED:
 348         case CLOCK_EVT_MODE_SHUTDOWN:
 349                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 350                 cfg &= ~HPET_TN_ENABLE;
 351                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 352                 break;
 353
 354         case CLOCK_EVT_MODE_RESUME:
 355                 if (timer == 0) {
 356                         hpet_enable_legacy_int();
 357                 } else {
 358                         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 359                         irq_domain_activate_irq(irq_get_irq_data(hdev->irq));
 360                         disable_irq(hdev->irq);
 361                         irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
 362                         enable_irq(hdev->irq);
 363                 }
 364                 hpet_print_config();
 365                 break;
 366         }
 367 }
 368
 369 static int hpet_next_event(unsigned long delta,
 370                            struct clock_event_device *evt, int timer)
 371 {
 372         u32 cnt;
 373         s32 res;
 374
 375         cnt = hpet_readl(HPET_COUNTER);
 376         cnt += (u32) delta;
 377         hpet_writel(cnt, HPET_Tn_CMP(timer));
 378
 379         /*
 380          * HPETs are a complete disaster. The compare register is
 381          * based on a equal comparison and neither provides a less
 382          * than or equal functionality (which would require to take
 383          * the wraparound into account) nor a simple count down event
 384          * mode. Further the write to the comparator register is
 385          * delayed internally up to two HPET clock cycles in certain
 386          * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
 387          * longer delays. We worked around that by reading back the
 388          * compare register, but that required another workaround for
 389          * ICH9,10 chips where the first readout after write can
 390          * return the old stale value. We already had a minimum
 391          * programming delta of 5us enforced, but a NMI or SMI hitting
 392          * between the counter readout and the comparator write can
 393          * move us behind that point easily. Now instead of reading
 394          * the compare register back several times, we make the ETIME
 395          * decision based on the following: Return ETIME if the
 396          * counter value after the write is less than HPET_MIN_CYCLES
 397          * away from the event or if the counter is already ahead of
 398          * the event. The minimum programming delta for the generic
 399          * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
 400          */
 401         res = (s32)(cnt - hpet_readl(HPET_COUNTER));
 402
 403         return res < HPET_MIN_CYCLES ? -ETIME : 0;
 404 }
 405
 406 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 407                         struct clock_event_device *evt)
 408 {
 409         hpet_set_mode(mode, evt, 0);
 410 }
 411
 412 static int hpet_legacy_next_event(unsigned long delta,
 413                         struct clock_event_device *evt)
 414 {
 415         return hpet_next_event(delta, evt, 0);
 416 }
 417
 418 /*
 419  * HPET MSI Support
 420  */
 421 #ifdef CONFIG_PCI_MSI
 422
 423 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
 424 static struct hpet_dev  *hpet_devs;
 425 static struct irq_domain *hpet_domain;
 426
 427 void hpet_msi_unmask(struct irq_data *data)
 428 {
 429         struct hpet_dev *hdev = data->handler_data;
 430         unsigned int cfg;
 431
 432         /* unmask it */
 433         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 434         cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
 435         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 436 }
 437
 438 void hpet_msi_mask(struct irq_data *data)
 439 {
 440         struct hpet_dev *hdev = data->handler_data;
 441         unsigned int cfg;
 442
 443         /* mask it */
 444         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 445         cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
 446         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 447 }
 448
 449 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
 450 {
 451         hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
 452         hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
 453 }
 454
 455 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
 456 {
 457         msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
 458         msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
 459         msg->address_hi = 0;
 460 }
 461
 462 static void hpet_msi_set_mode(enum clock_event_mode mode,
 463                                 struct clock_event_device *evt)
 464 {
 465         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 466         hpet_set_mode(mode, evt, hdev->num);
 467 }
 468
 469 static int hpet_msi_next_event(unsigned long delta,
 470                                 struct clock_event_device *evt)
 471 {
 472         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 473         return hpet_next_event(delta, evt, hdev->num);
 474 }
 475
 476 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
 477 {
 478         struct hpet_dev *dev = (struct hpet_dev *)data;
 479         struct clock_event_device *hevt = &dev->evt;
 480
 481         if (!hevt->event_handler) {
 482                 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
 483                                 dev->num);
 484                 return IRQ_HANDLED;
 485         }
 486
 487         hevt->event_handler(hevt);
 488         return IRQ_HANDLED;
 489 }
 490
 491 static int hpet_setup_irq(struct hpet_dev *dev)
 492 {
 493
 494         if (request_irq(dev->irq, hpet_interrupt_handler,
 495                         IRQF_TIMER | IRQF_NOBALANCING,
 496                         dev->name, dev))
 497                 return -1;
 498
 499         disable_irq(dev->irq);
 500         irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
 501         enable_irq(dev->irq);
 502
 503         printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
 504                          dev->name, dev->irq);
 505
 506         return 0;
 507 }
 508
 509 /* This should be called in specific @cpu */
 510 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
 511 {
 512         struct clock_event_device *evt = &hdev->evt;
 513
 514         WARN_ON(cpu != smp_processor_id());
 515         if (!(hdev->flags & HPET_DEV_VALID))
 516                 return;
 517
 518         hdev->cpu = cpu;
 519         per_cpu(cpu_hpet_dev, cpu) = hdev;
 520         evt->name = hdev->name;
 521         hpet_setup_irq(hdev);
 522         evt->irq = hdev->irq;
 523
 524         evt->rating = 110;
 525         evt->features = CLOCK_EVT_FEAT_ONESHOT;
 526         if (hdev->flags & HPET_DEV_PERI_CAP)
 527                 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
 528
 529         evt->set_mode = hpet_msi_set_mode;
 530         evt->set_next_event = hpet_msi_next_event;
 531         evt->cpumask = cpumask_of(hdev->cpu);
 532
 533         clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
 534                                         0x7FFFFFFF);
 535 }
 536
 537 #ifdef CONFIG_HPET
 538 /* Reserve at least one timer for userspace (/dev/hpet) */
 539 #define RESERVE_TIMERS 1
 540 #else
 541 #define RESERVE_TIMERS 0
 542 #endif
 543
 544 static void hpet_msi_capability_lookup(unsigned int start_timer)
 545 {
 546         unsigned int id;
 547         unsigned int num_timers;
 548         unsigned int num_timers_used = 0;
 549         int i, irq;
 550
 551         if (hpet_msi_disable)
 552                 return;
 553
 554         if (boot_cpu_has(X86_FEATURE_ARAT))
 555                 return;
 556         id = hpet_readl(HPET_ID);
 557
 558         num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
 559         num_timers++; /* Value read out starts from 0 */
 560         hpet_print_config();
 561
 562         hpet_domain = hpet_create_irq_domain(hpet_blockid);
 563         if (!hpet_domain)
 564                 return;
 565
 566         hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
 567         if (!hpet_devs)
 568                 return;
 569
 570         hpet_num_timers = num_timers;
 571
 572         for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
 573                 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
 574                 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
 575
 576                 /* Only consider HPET timer with MSI support */
 577                 if (!(cfg & HPET_TN_FSB_CAP))
 578                         continue;
 579
 580                 irq = hpet_assign_irq(hpet_domain, hdev, hdev->num);
 581                 if (irq < 0)
 582                         continue;
 583
 584                 sprintf(hdev->name, "hpet%d", i);
 585                 hdev->num = i;
 586                 hdev->irq = irq;
 587                 hdev->flags = 0;
 588                 if (cfg & HPET_TN_PERIODIC_CAP)
 589                         hdev->flags |= HPET_DEV_PERI_CAP;
 590                 hdev->flags |= HPET_DEV_FSB_CAP;
 591                 hdev->flags |= HPET_DEV_VALID;
 592                 num_timers_used++;
 593                 if (num_timers_used == num_possible_cpus())
 594                         break;
 595         }
 596
 597         printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
 598                 num_timers, num_timers_used);
 599 }
 600
 601 #ifdef CONFIG_HPET
 602 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 603 {
 604         int i;
 605
 606         if (!hpet_devs)
 607                 return;
 608
 609         for (i = 0; i < hpet_num_timers; i++) {
 610                 struct hpet_dev *hdev = &hpet_devs[i];
 611
 612                 if (!(hdev->flags & HPET_DEV_VALID))
 613                         continue;
 614
 615                 hd->hd_irq[hdev->num] = hdev->irq;
 616                 hpet_reserve_timer(hd, hdev->num);
 617         }
 618 }
 619 #endif
 620
 621 static struct hpet_dev *hpet_get_unused_timer(void)
 622 {
 623         int i;
 624
 625         if (!hpet_devs)
 626                 return NULL;
 627
 628         for (i = 0; i < hpet_num_timers; i++) {
 629                 struct hpet_dev *hdev = &hpet_devs[i];
 630
 631                 if (!(hdev->flags & HPET_DEV_VALID))
 632                         continue;
 633                 if (test_and_set_bit(HPET_DEV_USED_BIT,
 634                         (unsigned long *)&hdev->flags))
 635                         continue;
 636                 return hdev;
 637         }
 638         return NULL;
 639 }
 640
 641 struct hpet_work_struct {
 642         struct delayed_work work;
 643         struct completion complete;
 644 };
 645
 646 static void hpet_work(struct work_struct *w)
 647 {
 648         struct hpet_dev *hdev;
 649         int cpu = smp_processor_id();
 650         struct hpet_work_struct *hpet_work;
 651
 652         hpet_work = container_of(w, struct hpet_work_struct, work.work);
 653
 654         hdev = hpet_get_unused_timer();
 655         if (hdev)
 656                 init_one_hpet_msi_clockevent(hdev, cpu);
 657
 658         complete(&hpet_work->complete);
 659 }
 660
 661 static int hpet_cpuhp_notify(struct notifier_block *n,
 662                 unsigned long action, void *hcpu)
 663 {
 664         unsigned long cpu = (unsigned long)hcpu;
 665         struct hpet_work_struct work;
 666         struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
 667
 668         switch (action & 0xf) {
 669         case CPU_ONLINE:
 670                 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
 671                 init_completion(&work.complete);
 672                 /* FIXME: add schedule_work_on() */
 673                 schedule_delayed_work_on(cpu, &work.work, 0);
 674                 wait_for_completion(&work.complete);
 675                 destroy_delayed_work_on_stack(&work.work);
 676                 break;
 677         case CPU_DEAD:
 678                 if (hdev) {
 679                         free_irq(hdev->irq, hdev);
 680                         hdev->flags &= ~HPET_DEV_USED;
 681                         per_cpu(cpu_hpet_dev, cpu) = NULL;
 682                 }
 683                 break;
 684         }
 685         return NOTIFY_OK;
 686 }
 687 #else
 688
 689 static void hpet_msi_capability_lookup(unsigned int start_timer)
 690 {
 691         return;
 692 }
 693
 694 #ifdef CONFIG_HPET
 695 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 696 {
 697         return;
 698 }
 699 #endif
 700
 701 static int hpet_cpuhp_notify(struct notifier_block *n,
 702                 unsigned long action, void *hcpu)
 703 {
 704         return NOTIFY_OK;
 705 }
 706
 707 #endif
 708
 709 /*
 710  * Clock source related code
 711  */
 712 static cycle_t read_hpet(struct clocksource *cs)
 713 {
 714         return (cycle_t)hpet_readl(HPET_COUNTER);
 715 }
 716
 717 static struct clocksource clocksource_hpet = {
 718         .name           = "hpet",
 719         .rating         = 250,
 720         .read           = read_hpet,
 721         .mask           = HPET_MASK,
 722         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 723         .resume         = hpet_resume_counter,
 724         .archdata       = { .vclock_mode = VCLOCK_HPET },
 725 };
 726
 727 static int hpet_clocksource_register(void)
 728 {
 729         u64 start, now;
 730         cycle_t t1;
 731
 732         /* Start the counter */
 733         hpet_restart_counter();
 734
 735         /* Verify whether hpet counter works */
 736         t1 = hpet_readl(HPET_COUNTER);
 737         rdtscll(start);
 738
 739         /*
 740          * We don't know the TSC frequency yet, but waiting for
 741          * 200000 TSC cycles is safe:
 742          * 4 GHz == 50us
 743          * 1 GHz == 200us
 744          */
 745         do {
 746                 rep_nop();
 747                 rdtscll(now);
 748         } while ((now - start) < 200000UL);
 749
 750         if (t1 == hpet_readl(HPET_COUNTER)) {
 751                 printk(KERN_WARNING
 752                        "HPET counter not counting. HPET disabled\n");
 753                 return -ENODEV;
 754         }
 755
 756         clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
 757         return 0;
 758 }
 759
 760 static u32 *hpet_boot_cfg;
 761
 762 /**
 763  * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
 764  */
 765 int __init hpet_enable(void)
 766 {
 767         u32 hpet_period, cfg, id;
 768         u64 freq;
 769         unsigned int i, last;
 770
 771         if (!is_hpet_capable())
 772                 return 0;
 773
 774         hpet_set_mapping();
 775
 776         /*
 777          * Read the period and check for a sane value:
 778          */
 779         hpet_period = hpet_readl(HPET_PERIOD);
 780
 781         /*
 782          * AMD SB700 based systems with spread spectrum enabled use a
 783          * SMM based HPET emulation to provide proper frequency
 784          * setting. The SMM code is initialized with the first HPET
 785          * register access and takes some time to complete. During
 786          * this time the config register reads 0xffffffff. We check
 787          * for max. 1000 loops whether the config register reads a non
 788          * 0xffffffff value to make sure that HPET is up and running
 789          * before we go further. A counting loop is safe, as the HPET
 790          * access takes thousands of CPU cycles. On non SB700 based
 791          * machines this check is only done once and has no side
 792          * effects.
 793          */
 794         for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
 795                 if (i == 1000) {
 796                         printk(KERN_WARNING
 797                                "HPET config register value = 0xFFFFFFFF. "
 798                                "Disabling HPET\n");
 799                         goto out_nohpet;
 800                 }
 801         }
 802
 803         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
 804                 goto out_nohpet;
 805
 806         /*
 807          * The period is a femto seconds value. Convert it to a
 808          * frequency.
 809          */
 810         freq = FSEC_PER_SEC;
 811         do_div(freq, hpet_period);
 812         hpet_freq = freq;
 813
 814         /*
 815          * Read the HPET ID register to retrieve the IRQ routing
 816          * information and the number of channels
 817          */
 818         id = hpet_readl(HPET_ID);
 819         hpet_print_config();
 820
 821         last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
 822
 823 #ifdef CONFIG_HPET_EMULATE_RTC
 824         /*
 825          * The legacy routing mode needs at least two channels, tick timer
 826          * and the rtc emulation channel.
 827          */
 828         if (!last)
 829                 goto out_nohpet;
 830 #endif
 831
 832         cfg = hpet_readl(HPET_CFG);
 833         hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
 834                                 GFP_KERNEL);
 835         if (hpet_boot_cfg)
 836                 *hpet_boot_cfg = cfg;
 837         else
 838                 pr_warn("HPET initial state will not be saved\n");
 839         cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
 840         hpet_writel(cfg, HPET_CFG);
 841         if (cfg)
 842                 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
 843                         cfg);
 844
 845         for (i = 0; i <= last; ++i) {
 846                 cfg = hpet_readl(HPET_Tn_CFG(i));
 847                 if (hpet_boot_cfg)
 848                         hpet_boot_cfg[i + 1] = cfg;
 849                 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
 850                 hpet_writel(cfg, HPET_Tn_CFG(i));
 851                 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
 852                          | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
 853                          | HPET_TN_FSB | HPET_TN_FSB_CAP);
 854                 if (cfg)
 855                         pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
 856                                 cfg, i);
 857         }
 858         hpet_print_config();
 859
 860         if (hpet_clocksource_register())
 861                 goto out_nohpet;
 862
 863         if (id & HPET_ID_LEGSUP) {
 864                 hpet_legacy_clockevent_register();
 865                 return 1;
 866         }
 867         return 0;
 868
 869 out_nohpet:
 870         hpet_clear_mapping();
 871         hpet_address = 0;
 872         return 0;
 873 }
 874
 875 /*
 876  * Needs to be late, as the reserve_timer code calls kalloc !
 877  *
 878  * Not a problem on i386 as hpet_enable is called from late_time_init,
 879  * but on x86_64 it is necessary !
 880  */
 881 static __init int hpet_late_init(void)
 882 {
 883         int cpu;
 884
 885         if (boot_hpet_disable)
 886                 return -ENODEV;
 887
 888         if (!hpet_address) {
 889                 if (!force_hpet_address)
 890                         return -ENODEV;
 891
 892                 hpet_address = force_hpet_address;
 893                 hpet_enable();
 894         }
 895
 896         if (!hpet_virt_address)
 897                 return -ENODEV;
 898
 899         if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
 900                 hpet_msi_capability_lookup(2);
 901         else
 902                 hpet_msi_capability_lookup(0);
 903
 904         hpet_reserve_platform_timers(hpet_readl(HPET_ID));
 905         hpet_print_config();
 906
 907         if (hpet_msi_disable)
 908                 return 0;
 909
 910         if (boot_cpu_has(X86_FEATURE_ARAT))
 911                 return 0;
 912
 913         cpu_notifier_register_begin();
 914         for_each_online_cpu(cpu) {
 915                 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
 916         }
 917
 918         /* This notifier should be called after workqueue is ready */
 919         __hotcpu_notifier(hpet_cpuhp_notify, -20);
 920         cpu_notifier_register_done();
 921
 922         return 0;
 923 }
 924 fs_initcall(hpet_late_init);
 925
 926 void hpet_disable(void)
 927 {
 928         if (is_hpet_capable() && hpet_virt_address) {
 929                 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
 930
 931                 if (hpet_boot_cfg)
 932                         cfg = *hpet_boot_cfg;
 933                 else if (hpet_legacy_int_enabled) {
 934                         cfg &= ~HPET_CFG_LEGACY;
 935                         hpet_legacy_int_enabled = 0;
 936                 }
 937                 cfg &= ~HPET_CFG_ENABLE;
 938                 hpet_writel(cfg, HPET_CFG);
 939
 940                 if (!hpet_boot_cfg)
 941                         return;
 942
 943                 id = hpet_readl(HPET_ID);
 944                 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
 945
 946                 for (id = 0; id <= last; ++id)
 947                         hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
 948
 949                 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
 950                         hpet_writel(*hpet_boot_cfg, HPET_CFG);
 951         }
 952 }
 953
 954 #ifdef CONFIG_HPET_EMULATE_RTC
 955
 956 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 957  * is enabled, we support RTC interrupt functionality in software.
 958  * RTC has 3 kinds of interrupts:
 959  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 960  *    is updated
 961  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 962  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 963  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 964  * (1) and (2) above are implemented using polling at a frequency of
 965  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 966  * overhead. (DEFAULT_RTC_INT_FREQ)
 967  * For (3), we use interrupts at 64Hz or user specified periodic
 968  * frequency, whichever is higher.
 969  */
 970 #include <linux/mc146818rtc.h>
 971 #include <linux/rtc.h>
 972 #include <asm/rtc.h>
 973
 974 #define DEFAULT_RTC_INT_FREQ    64
 975 #define DEFAULT_RTC_SHIFT       6
 976 #define RTC_NUM_INTS            1
 977
 978 static unsigned long hpet_rtc_flags;
 979 static int hpet_prev_update_sec;
 980 static struct rtc_time hpet_alarm_time;
 981 static unsigned long hpet_pie_count;
 982 static u32 hpet_t1_cmp;
 983 static u32 hpet_default_delta;
 984 static u32 hpet_pie_delta;
 985 static unsigned long hpet_pie_limit;
 986
 987 static rtc_irq_handler irq_handler;
 988
 989 /*
 990  * Check that the hpet counter c1 is ahead of the c2
 991  */
 992 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
 993 {
 994         return (s32)(c2 - c1) < 0;
 995 }
 996
 997 /*
 998  * Registers a IRQ handler.
 999  */
1000 int hpet_register_irq_handler(rtc_irq_handler handler)
1001 {
1002         if (!is_hpet_enabled())
1003                 return -ENODEV;
1004         if (irq_handler)
1005                 return -EBUSY;
1006
1007         irq_handler = handler;
1008
1009         return 0;
1010 }
1011 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1012
1013 /*
1014  * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1015  * and does cleanup.
1016  */
1017 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1018 {
1019         if (!is_hpet_enabled())
1020                 return;
1021
1022         irq_handler = NULL;
1023         hpet_rtc_flags = 0;
1024 }
1025 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1026
1027 /*
1028  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1029  * is not supported by all HPET implementations for timer 1.
1030  *
1031  * hpet_rtc_timer_init() is called when the rtc is initialized.
1032  */
1033 int hpet_rtc_timer_init(void)
1034 {
1035         unsigned int cfg, cnt, delta;
1036         unsigned long flags;
1037
1038         if (!is_hpet_enabled())
1039                 return 0;
1040
1041         if (!hpet_default_delta) {
1042                 uint64_t clc;
1043
1044                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1045                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1046                 hpet_default_delta = clc;
1047         }
1048
1049         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1050                 delta = hpet_default_delta;
1051         else
1052                 delta = hpet_pie_delta;
1053
1054         local_irq_save(flags);
1055
1056         cnt = delta + hpet_readl(HPET_COUNTER);
1057         hpet_writel(cnt, HPET_T1_CMP);
1058         hpet_t1_cmp = cnt;
1059
1060         cfg = hpet_readl(HPET_T1_CFG);
1061         cfg &= ~HPET_TN_PERIODIC;
1062         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1063         hpet_writel(cfg, HPET_T1_CFG);
1064
1065         local_irq_restore(flags);
1066
1067         return 1;
1068 }
1069 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1070
1071 static void hpet_disable_rtc_channel(void)
1072 {
1073         unsigned long cfg;
1074         cfg = hpet_readl(HPET_T1_CFG);
1075         cfg &= ~HPET_TN_ENABLE;
1076         hpet_writel(cfg, HPET_T1_CFG);
1077 }
1078
1079 /*
1080  * The functions below are called from rtc driver.
1081  * Return 0 if HPET is not being used.
1082  * Otherwise do the necessary changes and return 1.
1083  */
1084 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1085 {
1086         if (!is_hpet_enabled())
1087                 return 0;
1088
1089         hpet_rtc_flags &= ~bit_mask;
1090         if (unlikely(!hpet_rtc_flags))
1091                 hpet_disable_rtc_channel();
1092
1093         return 1;
1094 }
1095 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1096
1097 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1098 {
1099         unsigned long oldbits = hpet_rtc_flags;
1100
1101         if (!is_hpet_enabled())
1102                 return 0;
1103
1104         hpet_rtc_flags |= bit_mask;
1105
1106         if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1107                 hpet_prev_update_sec = -1;
1108
1109         if (!oldbits)
1110                 hpet_rtc_timer_init();
1111
1112         return 1;
1113 }
1114 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1115
1116 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1117                         unsigned char sec)
1118 {
1119         if (!is_hpet_enabled())
1120                 return 0;
1121
1122         hpet_alarm_time.tm_hour = hrs;
1123         hpet_alarm_time.tm_min = min;
1124         hpet_alarm_time.tm_sec = sec;
1125
1126         return 1;
1127 }
1128 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1129
1130 int hpet_set_periodic_freq(unsigned long freq)
1131 {
1132         uint64_t clc;
1133
1134         if (!is_hpet_enabled())
1135                 return 0;
1136
1137         if (freq <= DEFAULT_RTC_INT_FREQ)
1138                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1139         else {
1140                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1141                 do_div(clc, freq);
1142                 clc >>= hpet_clockevent.shift;
1143                 hpet_pie_delta = clc;
1144                 hpet_pie_limit = 0;
1145         }
1146         return 1;
1147 }
1148 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1149
1150 int hpet_rtc_dropped_irq(void)
1151 {
1152         return is_hpet_enabled();
1153 }
1154 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1155
1156 static void hpet_rtc_timer_reinit(void)
1157 {
1158         unsigned int delta;
1159         int lost_ints = -1;
1160
1161         if (unlikely(!hpet_rtc_flags))
1162                 hpet_disable_rtc_channel();
1163
1164         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1165                 delta = hpet_default_delta;
1166         else
1167                 delta = hpet_pie_delta;
1168
1169         /*
1170          * Increment the comparator value until we are ahead of the
1171          * current count.
1172          */
1173         do {
1174                 hpet_t1_cmp += delta;
1175                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1176                 lost_ints++;
1177         } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1178
1179         if (lost_ints) {
1180                 if (hpet_rtc_flags & RTC_PIE)
1181                         hpet_pie_count += lost_ints;
1182                 if (printk_ratelimit())
1183                         printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1184                                 lost_ints);
1185         }
1186 }
1187
1188 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1189 {
1190         struct rtc_time curr_time;
1191         unsigned long rtc_int_flag = 0;
1192
1193         hpet_rtc_timer_reinit();
1194         memset(&curr_time, 0, sizeof(struct rtc_time));
1195
1196         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1197                 get_rtc_time(&curr_time);
1198
1199         if (hpet_rtc_flags & RTC_UIE &&
1200             curr_time.tm_sec != hpet_prev_update_sec) {
1201                 if (hpet_prev_update_sec >= 0)
1202                         rtc_int_flag = RTC_UF;
1203                 hpet_prev_update_sec = curr_time.tm_sec;
1204         }
1205
1206         if (hpet_rtc_flags & RTC_PIE &&
1207             ++hpet_pie_count >= hpet_pie_limit) {
1208                 rtc_int_flag |= RTC_PF;
1209                 hpet_pie_count = 0;
1210         }
1211
1212         if (hpet_rtc_flags & RTC_AIE &&
1213             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1214             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1215             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1216                         rtc_int_flag |= RTC_AF;
1217
1218         if (rtc_int_flag) {
1219                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1220                 if (irq_handler)
1221                         irq_handler(rtc_int_flag, dev_id);
1222         }
1223         return IRQ_HANDLED;
1224 }
1225 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1226 #endif