2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
11 #include <linux/kernel.h>
12 #include <linux/threads.h>
13 #include <linux/cpu.h>
14 #include <linux/cpumask.h>
15 #include <linux/string.h>
16 #include <linux/ctype.h>
17 #include <linux/init.h>
18 #include <linux/sched.h>
19 #include <linux/module.h>
20 #include <linux/hardirq.h>
21 #include <linux/timer.h>
22 #include <linux/proc_fs.h>
23 #include <asm/current.h>
26 #include <asm/genapic.h>
27 #include <asm/pgtable.h>
28 #include <asm/uv/uv.h>
29 #include <asm/uv/uv_mmrs.h>
30 #include <asm/uv/uv_hub.h>
31 #include <asm/uv/bios.h>
33 DEFINE_PER_CPU(int, x2apic_extra_bits);
35 static enum uv_system_type uv_system_type;
37 static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
39 if (!strcmp(oem_id, "SGI")) {
40 if (!strcmp(oem_table_id, "UVL"))
41 uv_system_type = UV_LEGACY_APIC;
42 else if (!strcmp(oem_table_id, "UVX"))
43 uv_system_type = UV_X2APIC;
44 else if (!strcmp(oem_table_id, "UVH")) {
45 uv_system_type = UV_NON_UNIQUE_APIC;
52 enum uv_system_type get_uv_system_type(void)
54 return uv_system_type;
57 int is_uv_system(void)
59 return uv_system_type != UV_NONE;
61 EXPORT_SYMBOL_GPL(is_uv_system);
63 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
64 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
66 struct uv_blade_info *uv_blade_info;
67 EXPORT_SYMBOL_GPL(uv_blade_info);
69 short *uv_node_to_blade;
70 EXPORT_SYMBOL_GPL(uv_node_to_blade);
72 short *uv_cpu_to_blade;
73 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
75 short uv_possible_blades;
76 EXPORT_SYMBOL_GPL(uv_possible_blades);
78 unsigned long sn_rtc_cycles_per_second;
79 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
81 /* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
83 static const struct cpumask *uv_target_cpus(void)
88 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
90 cpumask_clear(retmask);
91 cpumask_set_cpu(cpu, retmask);
94 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
99 pnode = uv_apicid_to_pnode(phys_apicid);
100 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
101 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
102 (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
104 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
107 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
108 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
109 (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
111 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
115 static void uv_send_IPI_one(int cpu, int vector)
117 unsigned long val, apicid, lapicid;
120 apicid = per_cpu(x86_cpu_to_apicid, cpu);
121 lapicid = apicid & 0x3f; /* ZZZ macro needed */
122 pnode = uv_apicid_to_pnode(apicid);
124 (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
125 UVH_IPI_INT_APIC_ID_SHFT) |
126 (vector << UVH_IPI_INT_VECTOR_SHFT);
127 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
130 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
134 for_each_cpu(cpu, mask)
135 uv_send_IPI_one(cpu, vector);
138 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
141 unsigned int this_cpu = smp_processor_id();
143 for_each_cpu(cpu, mask)
145 uv_send_IPI_one(cpu, vector);
148 static void uv_send_IPI_allbutself(int vector)
151 unsigned int this_cpu = smp_processor_id();
153 for_each_online_cpu(cpu)
155 uv_send_IPI_one(cpu, vector);
158 static void uv_send_IPI_all(int vector)
160 uv_send_IPI_mask(cpu_online_mask, vector);
163 static int uv_apic_id_registered(void)
168 static void uv_init_apic_ldr(void)
172 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
177 * We're using fixed IRQ delivery, can only return one phys APIC ID.
178 * May as well be the first.
180 cpu = cpumask_first(cpumask);
181 if ((unsigned)cpu < nr_cpu_ids)
182 return per_cpu(x86_cpu_to_apicid, cpu);
187 static unsigned int uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
188 const struct cpumask *andmask)
193 * We're using fixed IRQ delivery, can only return one phys APIC ID.
194 * May as well be the first.
196 for_each_cpu_and(cpu, cpumask, andmask)
197 if (cpumask_test_cpu(cpu, cpu_online_mask))
199 if (cpu < nr_cpu_ids)
200 return per_cpu(x86_cpu_to_apicid, cpu);
204 static unsigned int get_apic_id(unsigned long x)
208 WARN_ON(preemptible() && num_online_cpus() > 1);
209 id = x | __get_cpu_var(x2apic_extra_bits);
214 static unsigned long set_apic_id(unsigned int id)
218 /* maskout x2apic_extra_bits ? */
223 static unsigned int uv_read_apic_id(void)
226 return get_apic_id(apic_read(APIC_ID));
229 static unsigned int phys_pkg_id(int index_msb)
231 return uv_read_apic_id() >> index_msb;
234 static void uv_send_IPI_self(int vector)
236 apic_write(APIC_SELF_IPI, vector);
239 struct genapic apic_x2apic_uv_x = {
241 .name = "UV large system",
243 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
244 .apic_id_registered = uv_apic_id_registered,
246 .irq_delivery_mode = dest_Fixed,
247 .irq_dest_mode = 1, /* logical */
249 .target_cpus = uv_target_cpus,
251 .apic_destination_logical = APIC_DEST_LOGICAL,
252 .check_apicid_used = NULL,
253 .check_apicid_present = NULL,
256 .no_ioapic_check = 0,
258 .vector_allocation_domain = uv_vector_allocation_domain,
259 .init_apic_ldr = uv_init_apic_ldr,
261 .ioapic_phys_id_map = NULL,
262 .setup_apic_routing = NULL,
263 .multi_timer_check = NULL,
264 .apicid_to_node = NULL,
265 .cpu_to_logical_apicid = NULL,
266 .cpu_present_to_apicid = NULL,
267 .apicid_to_cpu_present = NULL,
268 .setup_portio_remap = NULL,
269 .check_phys_apicid_present = NULL,
270 .enable_apic_mode = NULL,
271 .phys_pkg_id = phys_pkg_id,
272 .mps_oem_check = NULL,
274 .get_apic_id = get_apic_id,
275 .set_apic_id = set_apic_id,
276 .apic_id_mask = 0xFFFFFFFFu,
278 .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
279 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
281 .send_IPI_mask = uv_send_IPI_mask,
282 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
283 .send_IPI_allbutself = uv_send_IPI_allbutself,
284 .send_IPI_all = uv_send_IPI_all,
285 .send_IPI_self = uv_send_IPI_self,
288 .trampoline_phys_low = 0,
289 .trampoline_phys_high = 0,
290 .wait_for_init_deassert = NULL,
291 .smp_callin_clear_local_apic = NULL,
292 .store_NMI_vector = NULL,
293 .restore_NMI_vector = NULL,
294 .inquire_remote_apic = NULL,
297 static __cpuinit void set_x2apic_extra_bits(int pnode)
299 __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
303 * Called on boot cpu.
305 static __init int boot_pnode_to_blade(int pnode)
309 for (blade = 0; blade < uv_num_possible_blades(); blade++)
310 if (pnode == uv_blade_info[blade].pnode)
316 unsigned long redirect;
320 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
322 static __initdata struct redir_addr redir_addrs[] = {
323 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
324 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
325 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
328 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
330 union uvh_si_alias0_overlay_config_u alias;
331 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
334 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
335 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
336 if (alias.s.base == 0) {
337 *size = (1UL << alias.s.m_alias);
338 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
339 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
346 static __init void map_low_mmrs(void)
348 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
349 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
352 enum map_type {map_wb, map_uc};
354 static __init void map_high(char *id, unsigned long base, int shift,
355 int max_pnode, enum map_type map_type)
357 unsigned long bytes, paddr;
359 paddr = base << shift;
360 bytes = (1UL << shift) * (max_pnode + 1);
361 printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
363 if (map_type == map_uc)
364 init_extra_mapping_uc(paddr, bytes);
366 init_extra_mapping_wb(paddr, bytes);
369 static __init void map_gru_high(int max_pnode)
371 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
372 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
374 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
376 map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
379 static __init void map_config_high(int max_pnode)
381 union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
382 int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
384 cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
386 map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
389 static __init void map_mmr_high(int max_pnode)
391 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
392 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
394 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
396 map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
399 static __init void map_mmioh_high(int max_pnode)
401 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
402 int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
404 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
406 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
409 static __init void uv_rtc_init(void)
414 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
416 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
418 "unable to determine platform RTC clock frequency, "
420 /* BIOS gives wrong value for clock freq. so guess */
421 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
423 sn_rtc_cycles_per_second = ticks_per_sec;
427 * percpu heartbeat timer
429 static void uv_heartbeat(unsigned long ignored)
431 struct timer_list *timer = &uv_hub_info->scir.timer;
432 unsigned char bits = uv_hub_info->scir.state;
434 /* flip heartbeat bit */
435 bits ^= SCIR_CPU_HEARTBEAT;
437 /* is this cpu idle? */
438 if (idle_cpu(raw_smp_processor_id()))
439 bits &= ~SCIR_CPU_ACTIVITY;
441 bits |= SCIR_CPU_ACTIVITY;
443 /* update system controller interface reg */
444 uv_set_scir_bits(bits);
446 /* enable next timer period */
447 mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
450 static void __cpuinit uv_heartbeat_enable(int cpu)
452 if (!uv_cpu_hub_info(cpu)->scir.enabled) {
453 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
455 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
456 setup_timer(timer, uv_heartbeat, cpu);
457 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
458 add_timer_on(timer, cpu);
459 uv_cpu_hub_info(cpu)->scir.enabled = 1;
463 if (!uv_cpu_hub_info(0)->scir.enabled)
464 uv_heartbeat_enable(0);
467 #ifdef CONFIG_HOTPLUG_CPU
468 static void __cpuinit uv_heartbeat_disable(int cpu)
470 if (uv_cpu_hub_info(cpu)->scir.enabled) {
471 uv_cpu_hub_info(cpu)->scir.enabled = 0;
472 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
474 uv_set_cpu_scir_bits(cpu, 0xff);
478 * cpu hotplug notifier
480 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
481 unsigned long action, void *hcpu)
483 long cpu = (long)hcpu;
487 uv_heartbeat_enable(cpu);
489 case CPU_DOWN_PREPARE:
490 uv_heartbeat_disable(cpu);
498 static __init void uv_scir_register_cpu_notifier(void)
500 hotcpu_notifier(uv_scir_cpu_notify, 0);
503 #else /* !CONFIG_HOTPLUG_CPU */
505 static __init void uv_scir_register_cpu_notifier(void)
509 static __init int uv_init_heartbeat(void)
514 for_each_online_cpu(cpu)
515 uv_heartbeat_enable(cpu);
519 late_initcall(uv_init_heartbeat);
521 #endif /* !CONFIG_HOTPLUG_CPU */
524 * Called on each cpu to initialize the per_cpu UV data area.
525 * ZZZ hotplug not supported yet
527 void __cpuinit uv_cpu_init(void)
529 /* CPU 0 initilization will be done via uv_system_init. */
533 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
535 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
536 set_x2apic_extra_bits(uv_hub_info->pnode);
540 void __init uv_system_init(void)
542 union uvh_si_addr_map_config_u m_n_config;
543 union uvh_node_id_u node_id;
544 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
545 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
547 unsigned long mmr_base, present;
551 m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
552 m_val = m_n_config.s.m_skt;
553 n_val = m_n_config.s.n_skt;
555 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
557 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
559 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
560 uv_possible_blades +=
561 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
562 printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
564 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
565 uv_blade_info = kmalloc(bytes, GFP_KERNEL);
567 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
569 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
570 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
571 memset(uv_node_to_blade, 255, bytes);
573 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
574 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
575 memset(uv_cpu_to_blade, 255, bytes);
578 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
579 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
580 for (j = 0; j < 64; j++) {
581 if (!test_bit(j, &present))
583 uv_blade_info[blade].pnode = (i * 64 + j);
584 uv_blade_info[blade].nr_possible_cpus = 0;
585 uv_blade_info[blade].nr_online_cpus = 0;
590 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
591 gnode_upper = (((unsigned long)node_id.s.node_id) &
592 ~((1 << n_val) - 1)) << m_val;
595 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
596 &sn_coherency_id, &sn_region_size);
599 for_each_present_cpu(cpu) {
600 nid = cpu_to_node(cpu);
601 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
602 blade = boot_pnode_to_blade(pnode);
603 lcpu = uv_blade_info[blade].nr_possible_cpus;
604 uv_blade_info[blade].nr_possible_cpus++;
606 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
607 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
608 uv_cpu_hub_info(cpu)->m_val = m_val;
609 uv_cpu_hub_info(cpu)->n_val = m_val;
610 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
611 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
612 uv_cpu_hub_info(cpu)->pnode = pnode;
613 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
614 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
615 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
616 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
617 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
618 uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu;
619 uv_node_to_blade[nid] = blade;
620 uv_cpu_to_blade[cpu] = blade;
621 max_pnode = max(pnode, max_pnode);
623 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
624 "lcpu %d, blade %d\n",
625 cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
629 map_gru_high(max_pnode);
630 map_mmr_high(max_pnode);
631 map_config_high(max_pnode);
632 map_mmioh_high(max_pnode);
635 uv_scir_register_cpu_notifier();
636 proc_mkdir("sgi_uv", NULL);