1 // SPDX-License-Identifier: GPL-2.0
3 * FPU register's regset abstraction, for ptrace, core dumps, etc.
5 #include <asm/fpu/internal.h>
6 #include <asm/fpu/signal.h>
7 #include <asm/fpu/regset.h>
8 #include <asm/fpu/xstate.h>
9 #include <linux/sched/task_stack.h>
12 * The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
13 * as the "regset->n" for the xstate regset will be updated based on the feature
14 * capabilities supported by the xsave.
16 int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
21 int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
23 if (boot_cpu_has(X86_FEATURE_FXSR))
29 int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
30 unsigned int pos, unsigned int count,
31 void *kbuf, void __user *ubuf)
33 struct fpu *fpu = &target->thread.fpu;
35 if (!boot_cpu_has(X86_FEATURE_FXSR))
38 fpu__prepare_read(fpu);
39 fpstate_sanitize_xstate(fpu);
41 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
42 &fpu->state.fxsave, 0, -1);
45 int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
46 unsigned int pos, unsigned int count,
47 const void *kbuf, const void __user *ubuf)
49 struct fpu *fpu = &target->thread.fpu;
52 if (!boot_cpu_has(X86_FEATURE_FXSR))
55 fpu__prepare_write(fpu);
56 fpstate_sanitize_xstate(fpu);
58 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
59 &fpu->state.fxsave, 0, -1);
62 * mxcsr reserved bits must be masked to zero for security reasons.
64 fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;
67 * update the header bits in the xsave header, indicating the
68 * presence of FP and SSE state.
70 if (boot_cpu_has(X86_FEATURE_XSAVE))
71 fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;
76 int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
77 unsigned int pos, unsigned int count,
78 void *kbuf, void __user *ubuf)
80 struct fpu *fpu = &target->thread.fpu;
81 struct xregs_state *xsave;
84 if (!boot_cpu_has(X86_FEATURE_XSAVE))
87 xsave = &fpu->state.xsave;
89 fpu__prepare_read(fpu);
91 if (using_compacted_format()) {
93 ret = copy_xstate_to_kernel(kbuf, xsave, pos, count);
95 ret = copy_xstate_to_user(ubuf, xsave, pos, count);
97 fpstate_sanitize_xstate(fpu);
99 * Copy the 48 bytes defined by the software into the xsave
100 * area in the thread struct, so that we can copy the whole
101 * area to user using one user_regset_copyout().
103 memcpy(&xsave->i387.sw_reserved, xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes));
106 * Copy the xstate memory layout.
108 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
113 int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
114 unsigned int pos, unsigned int count,
115 const void *kbuf, const void __user *ubuf)
117 struct fpu *fpu = &target->thread.fpu;
118 struct xregs_state *xsave;
121 if (!boot_cpu_has(X86_FEATURE_XSAVE))
125 * A whole standard-format XSAVE buffer is needed:
127 if ((pos != 0) || (count < fpu_user_xstate_size))
130 xsave = &fpu->state.xsave;
132 fpu__prepare_write(fpu);
134 if (using_compacted_format()) {
136 ret = copy_kernel_to_xstate(xsave, kbuf);
138 ret = copy_user_to_xstate(xsave, ubuf);
140 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
142 ret = validate_xstate_header(&xsave->header);
146 * mxcsr reserved bits must be masked to zero for security reasons.
148 xsave->i387.mxcsr &= mxcsr_feature_mask;
151 * In case of failure, mark all states as init:
154 fpstate_init(&fpu->state);
159 #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
162 * FPU tag word conversions.
165 static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
167 unsigned int tmp; /* to avoid 16 bit prefixes in the code */
169 /* Transform each pair of bits into 01 (valid) or 00 (empty) */
171 tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
172 /* and move the valid bits to the lower byte. */
173 tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
174 tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
175 tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
180 #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16)
181 #define FP_EXP_TAG_VALID 0
182 #define FP_EXP_TAG_ZERO 1
183 #define FP_EXP_TAG_SPECIAL 2
184 #define FP_EXP_TAG_EMPTY 3
186 static inline u32 twd_fxsr_to_i387(struct fxregs_state *fxsave)
189 u32 tos = (fxsave->swd >> 11) & 7;
190 u32 twd = (unsigned long) fxsave->twd;
192 u32 ret = 0xffff0000u;
195 for (i = 0; i < 8; i++, twd >>= 1) {
197 st = FPREG_ADDR(fxsave, (i - tos) & 7);
199 switch (st->exponent & 0x7fff) {
201 tag = FP_EXP_TAG_SPECIAL;
204 if (!st->significand[0] &&
205 !st->significand[1] &&
206 !st->significand[2] &&
208 tag = FP_EXP_TAG_ZERO;
210 tag = FP_EXP_TAG_SPECIAL;
213 if (st->significand[3] & 0x8000)
214 tag = FP_EXP_TAG_VALID;
216 tag = FP_EXP_TAG_SPECIAL;
220 tag = FP_EXP_TAG_EMPTY;
222 ret |= tag << (2 * i);
228 * FXSR floating point environment conversions.
232 convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
234 struct fxregs_state *fxsave = &tsk->thread.fpu.state.fxsave;
235 struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
236 struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
239 env->cwd = fxsave->cwd | 0xffff0000u;
240 env->swd = fxsave->swd | 0xffff0000u;
241 env->twd = twd_fxsr_to_i387(fxsave);
244 env->fip = fxsave->rip;
245 env->foo = fxsave->rdp;
247 * should be actually ds/cs at fpu exception time, but
248 * that information is not available in 64bit mode.
250 env->fcs = task_pt_regs(tsk)->cs;
251 if (tsk == current) {
252 savesegment(ds, env->fos);
254 env->fos = tsk->thread.ds;
256 env->fos |= 0xffff0000;
258 env->fip = fxsave->fip;
259 env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
260 env->foo = fxsave->foo;
261 env->fos = fxsave->fos;
264 for (i = 0; i < 8; ++i)
265 memcpy(&to[i], &from[i], sizeof(to[0]));
268 void convert_to_fxsr(struct fxregs_state *fxsave,
269 const struct user_i387_ia32_struct *env)
272 struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
273 struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
276 fxsave->cwd = env->cwd;
277 fxsave->swd = env->swd;
278 fxsave->twd = twd_i387_to_fxsr(env->twd);
279 fxsave->fop = (u16) ((u32) env->fcs >> 16);
281 fxsave->rip = env->fip;
282 fxsave->rdp = env->foo;
283 /* cs and ds ignored */
285 fxsave->fip = env->fip;
286 fxsave->fcs = (env->fcs & 0xffff);
287 fxsave->foo = env->foo;
288 fxsave->fos = env->fos;
291 for (i = 0; i < 8; ++i)
292 memcpy(&to[i], &from[i], sizeof(from[0]));
295 int fpregs_get(struct task_struct *target, const struct user_regset *regset,
296 unsigned int pos, unsigned int count,
297 void *kbuf, void __user *ubuf)
299 struct fpu *fpu = &target->thread.fpu;
300 struct user_i387_ia32_struct env;
302 fpu__prepare_read(fpu);
304 if (!boot_cpu_has(X86_FEATURE_FPU))
305 return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);
307 if (!boot_cpu_has(X86_FEATURE_FXSR))
308 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
309 &fpu->state.fsave, 0,
312 fpstate_sanitize_xstate(fpu);
314 if (kbuf && pos == 0 && count == sizeof(env)) {
315 convert_from_fxsr(kbuf, target);
319 convert_from_fxsr(&env, target);
321 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
324 int fpregs_set(struct task_struct *target, const struct user_regset *regset,
325 unsigned int pos, unsigned int count,
326 const void *kbuf, const void __user *ubuf)
328 struct fpu *fpu = &target->thread.fpu;
329 struct user_i387_ia32_struct env;
332 fpu__prepare_write(fpu);
333 fpstate_sanitize_xstate(fpu);
335 if (!boot_cpu_has(X86_FEATURE_FPU))
336 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
338 if (!boot_cpu_has(X86_FEATURE_FXSR))
339 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
340 &fpu->state.fsave, 0,
343 if (pos > 0 || count < sizeof(env))
344 convert_from_fxsr(&env, target);
346 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
348 convert_to_fxsr(&target->thread.fpu.state.fxsave, &env);
351 * update the header bit in the xsave header, indicating the
354 if (boot_cpu_has(X86_FEATURE_XSAVE))
355 fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FP;
360 * FPU state for core dumps.
361 * This is only used for a.out dumps now.
362 * It is declared generically using elf_fpregset_t (which is
363 * struct user_i387_struct) but is in fact only used for 32-bit
364 * dumps, so on 64-bit it is really struct user_i387_ia32_struct.
366 int dump_fpu(struct pt_regs *regs, struct user_i387_struct *ufpu)
368 struct task_struct *tsk = current;
370 return !fpregs_get(tsk, NULL, 0, sizeof(struct user_i387_ia32_struct),
373 EXPORT_SYMBOL(dump_fpu);
375 #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */