1 /* Various workarounds for chipset bugs.
2 This code runs very early and can't use the regular PCI subsystem
3 The entries are keyed to PCI bridges which usually identify chipsets
5 This is only for whole classes of chipsets with specific problems which
6 need early invasive action (e.g. before the timers are initialized).
7 Most PCI device specific workarounds can be done later and should be
9 Mainboard specific bugs should be handled by DMI entries.
10 CPU specific bugs in setup.c */
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/delay.h>
15 #include <linux/dmi.h>
16 #include <linux/pci_ids.h>
17 #include <linux/bcma/bcma.h>
18 #include <linux/bcma/bcma_regs.h>
19 #include <drm/i915_drm.h>
20 #include <asm/pci-direct.h>
22 #include <asm/io_apic.h>
25 #include <asm/iommu.h>
27 #include <asm/irq_remapping.h>
28 #include <asm/early_ioremap.h>
30 #define dev_err(msg) pr_err("pci 0000:%02x:%02x.%d: %s", bus, slot, func, msg)
32 static void __init fix_hypertransport_config(int num, int slot, int func)
36 * we found a hypertransport bus
37 * make sure that we are broadcasting
38 * interrupts to all cpus on the ht bus
39 * if we're using extended apic ids
41 htcfg = read_pci_config(num, slot, func, 0x68);
42 if (htcfg & (1 << 18)) {
43 printk(KERN_INFO "Detected use of extended apic ids "
44 "on hypertransport bus\n");
45 if ((htcfg & (1 << 17)) == 0) {
46 printk(KERN_INFO "Enabling hypertransport extended "
47 "apic interrupt broadcast\n");
48 printk(KERN_INFO "Note this is a bios bug, "
49 "please contact your hw vendor\n");
51 write_pci_config(num, slot, func, 0x68, htcfg);
58 static void __init via_bugs(int num, int slot, int func)
60 #ifdef CONFIG_GART_IOMMU
61 if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
62 !gart_iommu_aperture_allowed) {
64 "Looks like a VIA chipset. Disabling IOMMU."
65 " Override with iommu=allowed\n");
66 gart_iommu_aperture_disabled = 1;
72 #ifdef CONFIG_X86_IO_APIC
74 static int __init nvidia_hpet_check(struct acpi_table_header *header)
78 #endif /* CONFIG_X86_IO_APIC */
79 #endif /* CONFIG_ACPI */
81 static void __init nvidia_bugs(int num, int slot, int func)
84 #ifdef CONFIG_X86_IO_APIC
86 * Only applies to Nvidia root ports (bus 0) and not to
87 * Nvidia graphics cards with PCI ports on secondary buses.
93 * All timer overrides on Nvidia are
94 * wrong unless HPET is enabled.
95 * Unfortunately that's not true on many Asus boards.
96 * We don't know yet how to detect this automatically, but
97 * at least allow a command line override.
99 if (acpi_use_timer_override)
102 if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
103 acpi_skip_timer_override = 1;
104 printk(KERN_INFO "Nvidia board "
105 "detected. Ignoring ACPI "
106 "timer override.\n");
107 printk(KERN_INFO "If you got timer trouble "
108 "try acpi_use_timer_override\n");
112 /* RED-PEN skip them on mptables too? */
116 #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
117 static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
122 b = read_pci_config_byte(num, slot, func, 0xac);
124 write_pci_config_byte(num, slot, func, 0xac, b);
126 d = read_pci_config(num, slot, func, 0x70);
128 write_pci_config(num, slot, func, 0x70, d);
130 d = read_pci_config(num, slot, func, 0x8);
135 static void __init ati_bugs(int num, int slot, int func)
140 if (acpi_use_timer_override)
143 d = ati_ixp4x0_rev(num, slot, func);
145 acpi_skip_timer_override = 1;
147 /* check for IRQ0 interrupt swap */
148 outb(0x72, 0xcd6); b = inb(0xcd7);
150 acpi_skip_timer_override = 1;
153 if (acpi_skip_timer_override) {
154 printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
155 printk(KERN_INFO "Ignoring ACPI timer override.\n");
156 printk(KERN_INFO "If you got timer trouble "
157 "try acpi_use_timer_override\n");
161 static u32 __init ati_sbx00_rev(int num, int slot, int func)
165 d = read_pci_config(num, slot, func, 0x8);
171 static void __init ati_bugs_contd(int num, int slot, int func)
175 rev = ati_sbx00_rev(num, slot, func);
177 acpi_fix_pin2_polarity = 1;
180 * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
181 * SB700: revisions 0x39, 0x3a, ...
182 * SB800: revisions 0x40, 0x41, ...
187 if (acpi_use_timer_override)
190 /* check for IRQ0 interrupt swap */
191 d = read_pci_config(num, slot, func, 0x64);
193 acpi_skip_timer_override = 1;
195 if (acpi_skip_timer_override) {
196 printk(KERN_INFO "SB600 revision 0x%x\n", rev);
197 printk(KERN_INFO "Ignoring ACPI timer override.\n");
198 printk(KERN_INFO "If you got timer trouble "
199 "try acpi_use_timer_override\n");
203 static void __init ati_bugs(int num, int slot, int func)
207 static void __init ati_bugs_contd(int num, int slot, int func)
212 static void __init intel_remapping_check(int num, int slot, int func)
217 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
218 revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
221 * Revision <= 13 of all triggering devices id in this quirk
222 * have a problem draining interrupts when irq remapping is
223 * enabled, and should be flagged as broken. Additionally
224 * revision 0x22 of device id 0x3405 has this problem.
226 if (revision <= 0x13)
227 set_irq_remapping_broken();
228 else if (device == 0x3405 && revision == 0x22)
229 set_irq_remapping_broken();
233 * Systems with Intel graphics controllers set aside memory exclusively
234 * for gfx driver use. This memory is not marked in the E820 as reserved
235 * or as RAM, and so is subject to overlap from E820 manipulation later
236 * in the boot process. On some systems, MMIO space is allocated on top,
237 * despite the efforts of the "RAM buffer" approach, which simply rounds
238 * memory boundaries up to 64M to try to catch space that may decode
239 * as RAM and so is not suitable for MMIO.
241 * And yes, so far on current devices the base addr is always under 4G.
243 static u32 __init intel_stolen_base(int num, int slot, int func, size_t stolen_size)
248 * For the PCI IDs in this quirk, the stolen base is always
249 * in 0x5c, aka the BDSM register (yes that's really what
252 base = read_pci_config(num, slot, func, 0x5c);
253 base &= ~((1<<20) - 1);
258 #define KB(x) ((x) * 1024UL)
259 #define MB(x) (KB (KB (x)))
260 #define GB(x) (MB (KB (x)))
262 static size_t __init i830_tseg_size(void)
264 u8 tmp = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
266 if (!(tmp & TSEG_ENABLE))
269 if (tmp & I830_TSEG_SIZE_1M)
275 static size_t __init i845_tseg_size(void)
277 u8 tmp = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
279 if (!(tmp & TSEG_ENABLE))
282 switch (tmp & I845_TSEG_SIZE_MASK) {
283 case I845_TSEG_SIZE_512K:
285 case I845_TSEG_SIZE_1M:
293 static size_t __init i85x_tseg_size(void)
295 u8 tmp = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
297 if (!(tmp & TSEG_ENABLE))
303 static size_t __init i830_mem_size(void)
305 return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
308 static size_t __init i85x_mem_size(void)
310 return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
314 * On 830/845/85x the stolen memory base isn't available in any
315 * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
317 static u32 __init i830_stolen_base(int num, int slot, int func, size_t stolen_size)
319 return i830_mem_size() - i830_tseg_size() - stolen_size;
322 static u32 __init i845_stolen_base(int num, int slot, int func, size_t stolen_size)
324 return i830_mem_size() - i845_tseg_size() - stolen_size;
327 static u32 __init i85x_stolen_base(int num, int slot, int func, size_t stolen_size)
329 return i85x_mem_size() - i85x_tseg_size() - stolen_size;
332 static u32 __init i865_stolen_base(int num, int slot, int func, size_t stolen_size)
335 * FIXME is the graphics stolen memory region
336 * always at TOUD? Ie. is it always the last
337 * one to be allocated by the BIOS?
339 return read_pci_config_16(0, 0, 0, I865_TOUD) << 16;
342 static size_t __init i830_stolen_size(int num, int slot, int func)
347 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
349 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
350 case I830_GMCH_GMS_STOLEN_512:
351 stolen_size = KB(512);
353 case I830_GMCH_GMS_STOLEN_1024:
356 case I830_GMCH_GMS_STOLEN_8192:
359 case I830_GMCH_GMS_LOCAL:
360 /* local memory isn't part of the normal address space */
370 static size_t __init gen3_stolen_size(int num, int slot, int func)
375 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
377 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
378 case I855_GMCH_GMS_STOLEN_1M:
381 case I855_GMCH_GMS_STOLEN_4M:
384 case I855_GMCH_GMS_STOLEN_8M:
387 case I855_GMCH_GMS_STOLEN_16M:
388 stolen_size = MB(16);
390 case I855_GMCH_GMS_STOLEN_32M:
391 stolen_size = MB(32);
393 case I915_GMCH_GMS_STOLEN_48M:
394 stolen_size = MB(48);
396 case I915_GMCH_GMS_STOLEN_64M:
397 stolen_size = MB(64);
399 case G33_GMCH_GMS_STOLEN_128M:
400 stolen_size = MB(128);
402 case G33_GMCH_GMS_STOLEN_256M:
403 stolen_size = MB(256);
405 case INTEL_GMCH_GMS_STOLEN_96M:
406 stolen_size = MB(96);
408 case INTEL_GMCH_GMS_STOLEN_160M:
409 stolen_size = MB(160);
411 case INTEL_GMCH_GMS_STOLEN_224M:
412 stolen_size = MB(224);
414 case INTEL_GMCH_GMS_STOLEN_352M:
415 stolen_size = MB(352);
425 static size_t __init gen6_stolen_size(int num, int slot, int func)
429 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
430 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
431 gmch_ctrl &= SNB_GMCH_GMS_MASK;
433 return gmch_ctrl << 25; /* 32 MB units */
436 static size_t __init gen8_stolen_size(int num, int slot, int func)
440 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
441 gmch_ctrl >>= BDW_GMCH_GMS_SHIFT;
442 gmch_ctrl &= BDW_GMCH_GMS_MASK;
443 return gmch_ctrl << 25; /* 32 MB units */
446 static size_t __init chv_stolen_size(int num, int slot, int func)
450 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
451 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
452 gmch_ctrl &= SNB_GMCH_GMS_MASK;
455 * 0x0 to 0x10: 32MB increments starting at 0MB
456 * 0x11 to 0x16: 4MB increments starting at 8MB
457 * 0x17 to 0x1d: 4MB increments start at 36MB
459 if (gmch_ctrl < 0x11)
460 return gmch_ctrl << 25;
461 else if (gmch_ctrl < 0x17)
462 return (gmch_ctrl - 0x11 + 2) << 22;
464 return (gmch_ctrl - 0x17 + 9) << 22;
467 struct intel_stolen_funcs {
468 size_t (*size)(int num, int slot, int func);
469 u32 (*base)(int num, int slot, int func, size_t size);
472 static size_t __init gen9_stolen_size(int num, int slot, int func)
476 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
477 gmch_ctrl >>= BDW_GMCH_GMS_SHIFT;
478 gmch_ctrl &= BDW_GMCH_GMS_MASK;
480 if (gmch_ctrl < 0xf0)
481 return gmch_ctrl << 25; /* 32 MB units */
483 /* 4MB increments starting at 0xf0 for 4MB */
484 return (gmch_ctrl - 0xf0 + 1) << 22;
487 typedef size_t (*stolen_size_fn)(int num, int slot, int func);
489 static const struct intel_stolen_funcs i830_stolen_funcs __initconst = {
490 .base = i830_stolen_base,
491 .size = i830_stolen_size,
494 static const struct intel_stolen_funcs i845_stolen_funcs __initconst = {
495 .base = i845_stolen_base,
496 .size = i830_stolen_size,
499 static const struct intel_stolen_funcs i85x_stolen_funcs __initconst = {
500 .base = i85x_stolen_base,
501 .size = gen3_stolen_size,
504 static const struct intel_stolen_funcs i865_stolen_funcs __initconst = {
505 .base = i865_stolen_base,
506 .size = gen3_stolen_size,
509 static const struct intel_stolen_funcs gen3_stolen_funcs __initconst = {
510 .base = intel_stolen_base,
511 .size = gen3_stolen_size,
514 static const struct intel_stolen_funcs gen6_stolen_funcs __initconst = {
515 .base = intel_stolen_base,
516 .size = gen6_stolen_size,
519 static const struct intel_stolen_funcs gen8_stolen_funcs __initconst = {
520 .base = intel_stolen_base,
521 .size = gen8_stolen_size,
524 static const struct intel_stolen_funcs gen9_stolen_funcs __initconst = {
525 .base = intel_stolen_base,
526 .size = gen9_stolen_size,
529 static const struct intel_stolen_funcs chv_stolen_funcs __initconst = {
530 .base = intel_stolen_base,
531 .size = chv_stolen_size,
534 static const struct pci_device_id intel_stolen_ids[] __initconst = {
535 INTEL_I830_IDS(&i830_stolen_funcs),
536 INTEL_I845G_IDS(&i845_stolen_funcs),
537 INTEL_I85X_IDS(&i85x_stolen_funcs),
538 INTEL_I865G_IDS(&i865_stolen_funcs),
539 INTEL_I915G_IDS(&gen3_stolen_funcs),
540 INTEL_I915GM_IDS(&gen3_stolen_funcs),
541 INTEL_I945G_IDS(&gen3_stolen_funcs),
542 INTEL_I945GM_IDS(&gen3_stolen_funcs),
543 INTEL_VLV_M_IDS(&gen6_stolen_funcs),
544 INTEL_VLV_D_IDS(&gen6_stolen_funcs),
545 INTEL_PINEVIEW_IDS(&gen3_stolen_funcs),
546 INTEL_I965G_IDS(&gen3_stolen_funcs),
547 INTEL_G33_IDS(&gen3_stolen_funcs),
548 INTEL_I965GM_IDS(&gen3_stolen_funcs),
549 INTEL_GM45_IDS(&gen3_stolen_funcs),
550 INTEL_G45_IDS(&gen3_stolen_funcs),
551 INTEL_IRONLAKE_D_IDS(&gen3_stolen_funcs),
552 INTEL_IRONLAKE_M_IDS(&gen3_stolen_funcs),
553 INTEL_SNB_D_IDS(&gen6_stolen_funcs),
554 INTEL_SNB_M_IDS(&gen6_stolen_funcs),
555 INTEL_IVB_M_IDS(&gen6_stolen_funcs),
556 INTEL_IVB_D_IDS(&gen6_stolen_funcs),
557 INTEL_HSW_D_IDS(&gen6_stolen_funcs),
558 INTEL_HSW_M_IDS(&gen6_stolen_funcs),
559 INTEL_BDW_M_IDS(&gen8_stolen_funcs),
560 INTEL_BDW_D_IDS(&gen8_stolen_funcs),
561 INTEL_CHV_IDS(&chv_stolen_funcs),
562 INTEL_SKL_IDS(&gen9_stolen_funcs),
563 INTEL_BXT_IDS(&gen9_stolen_funcs),
564 INTEL_KBL_IDS(&gen9_stolen_funcs),
567 static void __init intel_graphics_stolen(int num, int slot, int func)
572 u16 device, subvendor, subdevice;
574 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
575 subvendor = read_pci_config_16(num, slot, func,
576 PCI_SUBSYSTEM_VENDOR_ID);
577 subdevice = read_pci_config_16(num, slot, func, PCI_SUBSYSTEM_ID);
579 for (i = 0; i < ARRAY_SIZE(intel_stolen_ids); i++) {
580 if (intel_stolen_ids[i].device == device) {
581 const struct intel_stolen_funcs *stolen_funcs =
582 (const struct intel_stolen_funcs *)intel_stolen_ids[i].driver_data;
583 size = stolen_funcs->size(num, slot, func);
584 start = stolen_funcs->base(num, slot, func, size);
586 printk(KERN_INFO "Reserving Intel graphics stolen memory at 0x%x-0x%x\n",
587 start, start + (u32)size - 1);
588 /* Mark this space as reserved */
589 e820_add_region(start, size, E820_RESERVED);
590 sanitize_e820_map(e820.map,
591 ARRAY_SIZE(e820.map),
599 static void __init force_disable_hpet(int num, int slot, int func)
601 #ifdef CONFIG_HPET_TIMER
602 boot_hpet_disable = true;
603 pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n");
607 #define BCM4331_MMIO_SIZE 16384
608 #define BCM4331_PM_CAP 0x40
609 #define bcma_aread32(reg) ioread32(mmio + 1 * BCMA_CORE_SIZE + reg)
610 #define bcma_awrite32(reg, val) iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg)
612 static void __init apple_airport_reset(int bus, int slot, int func)
619 if (!dmi_match(DMI_SYS_VENDOR, "Apple Inc."))
622 /* Card may have been put into PCI_D3hot by grub quirk */
623 pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
625 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
626 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
627 write_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL, pmcsr);
630 pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
631 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
632 dev_err("Cannot power up Apple AirPort card\n");
637 addr = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
638 addr |= (u64)read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_1) << 32;
639 addr &= PCI_BASE_ADDRESS_MEM_MASK;
641 mmio = early_ioremap(addr, BCM4331_MMIO_SIZE);
643 dev_err("Cannot iomap Apple AirPort card\n");
647 pr_info("Resetting Apple AirPort card (left enabled by EFI)\n");
649 for (i = 0; bcma_aread32(BCMA_RESET_ST) && i < 30; i++)
652 bcma_awrite32(BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
653 bcma_aread32(BCMA_RESET_CTL);
656 bcma_awrite32(BCMA_RESET_CTL, 0);
657 bcma_aread32(BCMA_RESET_CTL);
660 early_iounmap(mmio, BCM4331_MMIO_SIZE);
663 #define QFLAG_APPLY_ONCE 0x1
664 #define QFLAG_APPLIED 0x2
665 #define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
672 void (*f)(int num, int slot, int func);
675 static struct chipset early_qrk[] __initdata = {
676 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
677 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
678 { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
679 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
680 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
681 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
682 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
683 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
684 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
685 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
686 { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
687 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
688 { PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST,
689 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
690 { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
691 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
692 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
693 QFLAG_APPLY_ONCE, intel_graphics_stolen },
695 * HPET on the current version of the Baytrail platform has accuracy
696 * problems: it will halt in deep idle state - so we disable it.
698 * More details can be found in section 18.10.1.3 of the datasheet:
700 * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-1.pdf
702 { PCI_VENDOR_ID_INTEL, 0x0f00,
703 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
704 { PCI_VENDOR_ID_BROADCOM, 0x4331,
705 PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset},
709 static void __init early_pci_scan_bus(int bus);
712 * check_dev_quirk - apply early quirks to a given PCI device
715 * @func: PCI function
717 * Check the vendor & device ID against the early quirks table.
719 * If the device is single function, let early_pci_scan_bus() know so we don't
720 * poke at this device again.
722 static int __init check_dev_quirk(int num, int slot, int func)
731 class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
734 return -1; /* no class, treat as single function */
736 vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
738 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
740 for (i = 0; early_qrk[i].f != NULL; i++) {
741 if (((early_qrk[i].vendor == PCI_ANY_ID) ||
742 (early_qrk[i].vendor == vendor)) &&
743 ((early_qrk[i].device == PCI_ANY_ID) ||
744 (early_qrk[i].device == device)) &&
745 (!((early_qrk[i].class ^ class) &
746 early_qrk[i].class_mask))) {
747 if ((early_qrk[i].flags &
748 QFLAG_DONE) != QFLAG_DONE)
749 early_qrk[i].f(num, slot, func);
750 early_qrk[i].flags |= QFLAG_APPLIED;
754 type = read_pci_config_byte(num, slot, func,
757 if ((type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
758 sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS);
760 early_pci_scan_bus(sec);
769 static void __init early_pci_scan_bus(int bus)
773 /* Poor man's PCI discovery */
774 for (slot = 0; slot < 32; slot++)
775 for (func = 0; func < 8; func++) {
776 /* Only probe function 0 on single fn devices */
777 if (check_dev_quirk(bus, slot, func))
782 void __init early_quirks(void)
784 if (!early_pci_allowed())
787 early_pci_scan_bus(0);