1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/sched.h>
3 #include <linux/sched/clock.h>
5 #include <asm/cpufeature.h>
9 #define MSR_ZHAOXIN_FCR57 0x00001257
11 #define ACE_PRESENT (1 << 6)
12 #define ACE_ENABLED (1 << 7)
13 #define ACE_FCR (1 << 7) /* MSR_ZHAOXIN_FCR */
15 #define RNG_PRESENT (1 << 2)
16 #define RNG_ENABLED (1 << 3)
17 #define RNG_ENABLE (1 << 8) /* MSR_ZHAOXIN_RNG */
19 static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
23 /* Test for Extended Feature Flags presence */
24 if (cpuid_eax(0xC0000000) >= 0xC0000001) {
25 u32 tmp = cpuid_edx(0xC0000001);
27 /* Enable ACE unit, if present and disabled */
28 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
29 rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
32 wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
33 pr_info("CPU: Enabled ACE h/w crypto\n");
36 /* Enable RNG unit, if present and disabled */
37 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
38 rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
41 wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
42 pr_info("CPU: Enabled h/w RNG\n");
46 * Store Extended Feature Flags as word 5 of the CPU
47 * capability bit array
49 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
53 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
56 static void early_init_zhaoxin(struct cpuinfo_x86 *c)
59 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
61 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
63 if (c->x86_power & (1 << 8)) {
64 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
65 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
68 if (c->cpuid_level >= 0x00000001) {
69 u32 eax, ebx, ecx, edx;
71 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
73 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
74 * apicids which are reserved per package. Store the resulting
75 * shift value for the package management code.
78 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
83 static void init_zhaoxin(struct cpuinfo_x86 *c)
85 early_init_zhaoxin(c);
86 init_intel_cacheinfo(c);
87 detect_num_cpu_cores(c);
92 if (c->cpuid_level > 9) {
93 unsigned int eax = cpuid_eax(10);
96 * Check for version and the number of counters
97 * Version(eax[7:0]) can't be 0;
98 * Counters(eax[15:8]) should be greater than 1;
100 if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
101 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
107 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
110 init_ia32_feat_ctl(c);
115 zhaoxin_size_cache(struct cpuinfo_x86 *c, unsigned int size)
121 static const struct cpu_dev zhaoxin_cpu_dev = {
122 .c_vendor = "zhaoxin",
123 .c_ident = { " Shanghai " },
124 .c_early_init = early_init_zhaoxin,
125 .c_init = init_zhaoxin,
127 .legacy_cache_size = zhaoxin_size_cache,
129 .c_x86_vendor = X86_VENDOR_ZHAOXIN,
132 cpu_dev_register(zhaoxin_cpu_dev);