2 * perf_event_intel_rapl.c: support Intel RAPL energy consumption counters
3 * Copyright (C) 2013 Google, Inc., Stephane Eranian
5 * Intel RAPL interface is specified in the IA-32 Manual Vol3b
6 * section 14.7.1 (September 2013)
8 * RAPL provides more controls than just reporting energy consumption
9 * however here we only expose the 3 energy consumption free running
10 * counters (pp0, pkg, dram).
12 * Each of those counters increments in a power unit defined by the
13 * RAPL_POWER_UNIT MSR. On SandyBridge, this unit is 1/(2^16) Joules
16 * Counter to rapl events mappings:
18 * pp0 counter: consumption of all physical cores (power plane 0)
19 * event: rapl_energy_cores
22 * pkg counter: consumption of the whole processor package
23 * event: rapl_energy_pkg
26 * dram counter: consumption of the dram domain (servers only)
27 * event: rapl_energy_dram
30 * dram counter: consumption of the builtin-gpu domain (client only)
31 * event: rapl_energy_gpu
34 * We manage those counters as free running (read-only). They may be
35 * use simultaneously by other tools, such as turbostat.
37 * The events only support system-wide mode counting. There is no
38 * sampling support because it does not make sense and is not
39 * supported by the RAPL hardware.
41 * Because we want to avoid floating-point operations in the kernel,
42 * the events are all reported in fixed point arithmetic (32.32).
43 * Tools must adjust the counts to convert them to Watts using
44 * the duration of the measurement. Tools may use a function such as
45 * ldexp(raw_count, -32);
47 #include <linux/module.h>
48 #include <linux/slab.h>
49 #include <linux/perf_event.h>
50 #include <asm/cpu_device_id.h>
51 #include "perf_event.h"
54 * RAPL energy status counters
56 #define RAPL_IDX_PP0_NRG_STAT 0 /* all cores */
57 #define INTEL_RAPL_PP0 0x1 /* pseudo-encoding */
58 #define RAPL_IDX_PKG_NRG_STAT 1 /* entire package */
59 #define INTEL_RAPL_PKG 0x2 /* pseudo-encoding */
60 #define RAPL_IDX_RAM_NRG_STAT 2 /* DRAM */
61 #define INTEL_RAPL_RAM 0x3 /* pseudo-encoding */
62 #define RAPL_IDX_PP1_NRG_STAT 3 /* gpu */
63 #define INTEL_RAPL_PP1 0x4 /* pseudo-encoding */
65 /* Clients have PP0, PKG */
66 #define RAPL_IDX_CLN (1<<RAPL_IDX_PP0_NRG_STAT|\
67 1<<RAPL_IDX_PKG_NRG_STAT|\
68 1<<RAPL_IDX_PP1_NRG_STAT)
70 /* Servers have PP0, PKG, RAM */
71 #define RAPL_IDX_SRV (1<<RAPL_IDX_PP0_NRG_STAT|\
72 1<<RAPL_IDX_PKG_NRG_STAT|\
73 1<<RAPL_IDX_RAM_NRG_STAT)
75 /* Servers have PP0, PKG, RAM, PP1 */
76 #define RAPL_IDX_HSW (1<<RAPL_IDX_PP0_NRG_STAT|\
77 1<<RAPL_IDX_PKG_NRG_STAT|\
78 1<<RAPL_IDX_RAM_NRG_STAT|\
79 1<<RAPL_IDX_PP1_NRG_STAT)
82 * event code: LSB 8 bits, passed in attr->config
83 * any other bit is reserved
85 #define RAPL_EVENT_MASK 0xFFULL
87 #define DEFINE_RAPL_FORMAT_ATTR(_var, _name, _format) \
88 static ssize_t __rapl_##_var##_show(struct kobject *kobj, \
89 struct kobj_attribute *attr, \
92 BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
93 return sprintf(page, _format "\n"); \
95 static struct kobj_attribute format_attr_##_var = \
96 __ATTR(_name, 0444, __rapl_##_var##_show, NULL)
98 #define RAPL_EVENT_DESC(_name, _config) \
100 .attr = __ATTR(_name, 0444, rapl_event_show, NULL), \
104 #define RAPL_CNTR_WIDTH 32 /* 32-bit rapl counters */
108 int hw_unit; /* 1/2^hw_unit Joule */
109 int n_active; /* number of active events */
110 struct list_head active_list;
111 struct pmu *pmu; /* pointer to rapl_pmu_class */
112 ktime_t timer_interval; /* in ktime_t unit */
113 struct hrtimer hrtimer;
116 static struct pmu rapl_pmu_class;
117 static cpumask_t rapl_cpu_mask;
118 static int rapl_cntr_mask;
120 static DEFINE_PER_CPU(struct rapl_pmu *, rapl_pmu);
121 static DEFINE_PER_CPU(struct rapl_pmu *, rapl_pmu_to_free);
123 static inline u64 rapl_read_counter(struct perf_event *event)
126 rdmsrl(event->hw.event_base, raw);
130 static inline u64 rapl_scale(u64 v)
133 * scale delta to smallest unit (1/2^32)
134 * users must then scale back: count * 1/(1e9*2^32) to get Joules
135 * or use ldexp(count, -32).
136 * Watts = Joules/Time delta
138 return v << (32 - __this_cpu_read(rapl_pmu->hw_unit));
141 static u64 rapl_event_update(struct perf_event *event)
143 struct hw_perf_event *hwc = &event->hw;
144 u64 prev_raw_count, new_raw_count;
146 int shift = RAPL_CNTR_WIDTH;
149 prev_raw_count = local64_read(&hwc->prev_count);
150 rdmsrl(event->hw.event_base, new_raw_count);
152 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
153 new_raw_count) != prev_raw_count) {
159 * Now we have the new raw value and have updated the prev
160 * timestamp already. We can now calculate the elapsed delta
161 * (event-)time and add that to the generic event.
163 * Careful, not all hw sign-extends above the physical width
166 delta = (new_raw_count << shift) - (prev_raw_count << shift);
169 sdelta = rapl_scale(delta);
171 local64_add(sdelta, &event->count);
173 return new_raw_count;
176 static void rapl_start_hrtimer(struct rapl_pmu *pmu)
178 __hrtimer_start_range_ns(&pmu->hrtimer,
179 pmu->timer_interval, 0,
180 HRTIMER_MODE_REL_PINNED, 0);
183 static void rapl_stop_hrtimer(struct rapl_pmu *pmu)
185 hrtimer_cancel(&pmu->hrtimer);
188 static enum hrtimer_restart rapl_hrtimer_handle(struct hrtimer *hrtimer)
190 struct rapl_pmu *pmu = __this_cpu_read(rapl_pmu);
191 struct perf_event *event;
195 return HRTIMER_NORESTART;
197 spin_lock_irqsave(&pmu->lock, flags);
199 list_for_each_entry(event, &pmu->active_list, active_entry) {
200 rapl_event_update(event);
203 spin_unlock_irqrestore(&pmu->lock, flags);
205 hrtimer_forward_now(hrtimer, pmu->timer_interval);
207 return HRTIMER_RESTART;
210 static void rapl_hrtimer_init(struct rapl_pmu *pmu)
212 struct hrtimer *hr = &pmu->hrtimer;
214 hrtimer_init(hr, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
215 hr->function = rapl_hrtimer_handle;
218 static void __rapl_pmu_event_start(struct rapl_pmu *pmu,
219 struct perf_event *event)
221 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
226 list_add_tail(&event->active_entry, &pmu->active_list);
228 local64_set(&event->hw.prev_count, rapl_read_counter(event));
231 if (pmu->n_active == 1)
232 rapl_start_hrtimer(pmu);
235 static void rapl_pmu_event_start(struct perf_event *event, int mode)
237 struct rapl_pmu *pmu = __this_cpu_read(rapl_pmu);
240 spin_lock_irqsave(&pmu->lock, flags);
241 __rapl_pmu_event_start(pmu, event);
242 spin_unlock_irqrestore(&pmu->lock, flags);
245 static void rapl_pmu_event_stop(struct perf_event *event, int mode)
247 struct rapl_pmu *pmu = __this_cpu_read(rapl_pmu);
248 struct hw_perf_event *hwc = &event->hw;
251 spin_lock_irqsave(&pmu->lock, flags);
253 /* mark event as deactivated and stopped */
254 if (!(hwc->state & PERF_HES_STOPPED)) {
255 WARN_ON_ONCE(pmu->n_active <= 0);
257 if (pmu->n_active == 0)
258 rapl_stop_hrtimer(pmu);
260 list_del(&event->active_entry);
262 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
263 hwc->state |= PERF_HES_STOPPED;
266 /* check if update of sw counter is necessary */
267 if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
269 * Drain the remaining delta count out of a event
270 * that we are disabling:
272 rapl_event_update(event);
273 hwc->state |= PERF_HES_UPTODATE;
276 spin_unlock_irqrestore(&pmu->lock, flags);
279 static int rapl_pmu_event_add(struct perf_event *event, int mode)
281 struct rapl_pmu *pmu = __this_cpu_read(rapl_pmu);
282 struct hw_perf_event *hwc = &event->hw;
285 spin_lock_irqsave(&pmu->lock, flags);
287 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
289 if (mode & PERF_EF_START)
290 __rapl_pmu_event_start(pmu, event);
292 spin_unlock_irqrestore(&pmu->lock, flags);
297 static void rapl_pmu_event_del(struct perf_event *event, int flags)
299 rapl_pmu_event_stop(event, PERF_EF_UPDATE);
302 static int rapl_pmu_event_init(struct perf_event *event)
304 u64 cfg = event->attr.config & RAPL_EVENT_MASK;
305 int bit, msr, ret = 0;
307 /* only look at RAPL events */
308 if (event->attr.type != rapl_pmu_class.type)
311 /* check only supported bits are set */
312 if (event->attr.config & ~RAPL_EVENT_MASK)
316 * check event is known (determines counter)
320 bit = RAPL_IDX_PP0_NRG_STAT;
321 msr = MSR_PP0_ENERGY_STATUS;
324 bit = RAPL_IDX_PKG_NRG_STAT;
325 msr = MSR_PKG_ENERGY_STATUS;
328 bit = RAPL_IDX_RAM_NRG_STAT;
329 msr = MSR_DRAM_ENERGY_STATUS;
332 bit = RAPL_IDX_PP1_NRG_STAT;
333 msr = MSR_PP1_ENERGY_STATUS;
338 /* check event supported */
339 if (!(rapl_cntr_mask & (1 << bit)))
342 /* unsupported modes and filters */
343 if (event->attr.exclude_user ||
344 event->attr.exclude_kernel ||
345 event->attr.exclude_hv ||
346 event->attr.exclude_idle ||
347 event->attr.exclude_host ||
348 event->attr.exclude_guest ||
349 event->attr.sample_period) /* no sampling */
352 /* must be done before validate_group */
353 event->hw.event_base = msr;
354 event->hw.config = cfg;
360 static void rapl_pmu_event_read(struct perf_event *event)
362 rapl_event_update(event);
365 static ssize_t rapl_get_attr_cpumask(struct device *dev,
366 struct device_attribute *attr, char *buf)
368 return cpumap_print_to_pagebuf(true, buf, &rapl_cpu_mask);
371 static DEVICE_ATTR(cpumask, S_IRUGO, rapl_get_attr_cpumask, NULL);
373 static struct attribute *rapl_pmu_attrs[] = {
374 &dev_attr_cpumask.attr,
378 static struct attribute_group rapl_pmu_attr_group = {
379 .attrs = rapl_pmu_attrs,
382 EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01");
383 EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event=0x02");
384 EVENT_ATTR_STR(energy-ram , rapl_ram, "event=0x03");
385 EVENT_ATTR_STR(energy-gpu , rapl_gpu, "event=0x04");
387 EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules");
388 EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules");
389 EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules");
390 EVENT_ATTR_STR(energy-gpu.unit , rapl_gpu_unit, "Joules");
393 * we compute in 0.23 nJ increments regardless of MSR
395 EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10");
396 EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scale, "2.3283064365386962890625e-10");
397 EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890625e-10");
398 EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10");
400 static struct attribute *rapl_events_srv_attr[] = {
401 EVENT_PTR(rapl_cores),
405 EVENT_PTR(rapl_cores_unit),
406 EVENT_PTR(rapl_pkg_unit),
407 EVENT_PTR(rapl_ram_unit),
409 EVENT_PTR(rapl_cores_scale),
410 EVENT_PTR(rapl_pkg_scale),
411 EVENT_PTR(rapl_ram_scale),
415 static struct attribute *rapl_events_cln_attr[] = {
416 EVENT_PTR(rapl_cores),
420 EVENT_PTR(rapl_cores_unit),
421 EVENT_PTR(rapl_pkg_unit),
422 EVENT_PTR(rapl_gpu_unit),
424 EVENT_PTR(rapl_cores_scale),
425 EVENT_PTR(rapl_pkg_scale),
426 EVENT_PTR(rapl_gpu_scale),
430 static struct attribute *rapl_events_hsw_attr[] = {
431 EVENT_PTR(rapl_cores),
436 EVENT_PTR(rapl_cores_unit),
437 EVENT_PTR(rapl_pkg_unit),
438 EVENT_PTR(rapl_gpu_unit),
439 EVENT_PTR(rapl_ram_unit),
441 EVENT_PTR(rapl_cores_scale),
442 EVENT_PTR(rapl_pkg_scale),
443 EVENT_PTR(rapl_gpu_scale),
444 EVENT_PTR(rapl_ram_scale),
448 static struct attribute_group rapl_pmu_events_group = {
450 .attrs = NULL, /* patched at runtime */
453 DEFINE_RAPL_FORMAT_ATTR(event, event, "config:0-7");
454 static struct attribute *rapl_formats_attr[] = {
455 &format_attr_event.attr,
459 static struct attribute_group rapl_pmu_format_group = {
461 .attrs = rapl_formats_attr,
464 const struct attribute_group *rapl_attr_groups[] = {
465 &rapl_pmu_attr_group,
466 &rapl_pmu_format_group,
467 &rapl_pmu_events_group,
471 static struct pmu rapl_pmu_class = {
472 .attr_groups = rapl_attr_groups,
473 .task_ctx_nr = perf_invalid_context, /* system-wide only */
474 .event_init = rapl_pmu_event_init,
475 .add = rapl_pmu_event_add, /* must have */
476 .del = rapl_pmu_event_del, /* must have */
477 .start = rapl_pmu_event_start,
478 .stop = rapl_pmu_event_stop,
479 .read = rapl_pmu_event_read,
482 static void rapl_cpu_exit(int cpu)
484 struct rapl_pmu *pmu = per_cpu(rapl_pmu, cpu);
485 int i, phys_id = topology_physical_package_id(cpu);
488 /* find a new cpu on same package */
489 for_each_online_cpu(i) {
492 if (phys_id == topology_physical_package_id(i)) {
498 * clear cpu from cpumask
499 * if was set in cpumask and still some cpu on package,
500 * then move to new cpu
502 if (cpumask_test_and_clear_cpu(cpu, &rapl_cpu_mask) && target >= 0)
503 cpumask_set_cpu(target, &rapl_cpu_mask);
505 WARN_ON(cpumask_empty(&rapl_cpu_mask));
507 * migrate events and context to new cpu
510 perf_pmu_migrate_context(pmu->pmu, cpu, target);
512 /* cancel overflow polling timer for CPU */
513 rapl_stop_hrtimer(pmu);
516 static void rapl_cpu_init(int cpu)
518 int i, phys_id = topology_physical_package_id(cpu);
520 /* check if phys_is is already covered */
521 for_each_cpu(i, &rapl_cpu_mask) {
522 if (phys_id == topology_physical_package_id(i))
525 /* was not found, so add it */
526 cpumask_set_cpu(cpu, &rapl_cpu_mask);
529 static int rapl_cpu_prepare(int cpu)
531 struct rapl_pmu *pmu = per_cpu(rapl_pmu, cpu);
532 int phys_id = topology_physical_package_id(cpu);
534 u64 msr_rapl_power_unit_bits;
542 /* protect rdmsrl() to handle virtualization */
543 if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &msr_rapl_power_unit_bits))
546 pmu = kzalloc_node(sizeof(*pmu), GFP_KERNEL, cpu_to_node(cpu));
550 spin_lock_init(&pmu->lock);
552 INIT_LIST_HEAD(&pmu->active_list);
555 * grab power unit as: 1/2^unit Joules
557 * we cache in local PMU instance
559 pmu->hw_unit = (msr_rapl_power_unit_bits >> 8) & 0x1FULL;
560 pmu->pmu = &rapl_pmu_class;
563 * use reference of 200W for scaling the timeout
564 * to avoid missing counter overflows.
565 * 200W = 200 Joules/sec
566 * divide interval by 2 to avoid lockstep (2 * 100)
567 * if hw unit is 32, then we use 2 ms 1/200/2
569 if (pmu->hw_unit < 32)
570 ms = (1000 / (2 * 100)) * (1ULL << (32 - pmu->hw_unit - 1));
574 pmu->timer_interval = ms_to_ktime(ms);
576 rapl_hrtimer_init(pmu);
578 /* set RAPL pmu for this cpu for now */
579 per_cpu(rapl_pmu, cpu) = pmu;
580 per_cpu(rapl_pmu_to_free, cpu) = NULL;
585 static void rapl_cpu_kfree(int cpu)
587 struct rapl_pmu *pmu = per_cpu(rapl_pmu_to_free, cpu);
591 per_cpu(rapl_pmu_to_free, cpu) = NULL;
594 static int rapl_cpu_dying(int cpu)
596 struct rapl_pmu *pmu = per_cpu(rapl_pmu, cpu);
601 per_cpu(rapl_pmu, cpu) = NULL;
603 per_cpu(rapl_pmu_to_free, cpu) = pmu;
608 static int rapl_cpu_notifier(struct notifier_block *self,
609 unsigned long action, void *hcpu)
611 unsigned int cpu = (long)hcpu;
613 switch (action & ~CPU_TASKS_FROZEN) {
615 rapl_cpu_prepare(cpu);
620 case CPU_UP_CANCELED:
628 case CPU_DOWN_PREPARE:
638 static const struct x86_cpu_id rapl_cpu_match[] = {
639 [0] = { .vendor = X86_VENDOR_INTEL, .family = 6 },
643 static int __init rapl_pmu_init(void)
645 struct rapl_pmu *pmu;
649 * check for Intel processor family 6
651 if (!x86_match_cpu(rapl_cpu_match))
654 /* check supported CPU */
655 switch (boot_cpu_data.x86_model) {
656 case 42: /* Sandy Bridge */
657 case 58: /* Ivy Bridge */
658 rapl_cntr_mask = RAPL_IDX_CLN;
659 rapl_pmu_events_group.attrs = rapl_events_cln_attr;
661 case 60: /* Haswell */
662 case 69: /* Haswell-Celeron */
663 rapl_cntr_mask = RAPL_IDX_HSW;
664 rapl_pmu_events_group.attrs = rapl_events_hsw_attr;
666 case 45: /* Sandy Bridge-EP */
667 case 62: /* IvyTown */
668 rapl_cntr_mask = RAPL_IDX_SRV;
669 rapl_pmu_events_group.attrs = rapl_events_srv_attr;
677 cpu_notifier_register_begin();
679 for_each_online_cpu(cpu) {
680 ret = rapl_cpu_prepare(cpu);
686 __perf_cpu_notifier(rapl_cpu_notifier);
688 ret = perf_pmu_register(&rapl_pmu_class, "power", -1);
690 pr_info("RAPL PMU detected, registration failed (%d), RAPL PMU disabled\n", ret);
691 cpu_notifier_register_done();
695 pmu = __this_cpu_read(rapl_pmu);
697 pr_info("RAPL PMU detected, hw unit 2^-%d Joules,"
698 " API unit is 2^-32 Joules,"
700 " %llu ms ovfl timer\n",
702 hweight32(rapl_cntr_mask),
703 ktime_to_ms(pmu->timer_interval));
706 cpu_notifier_register_done();
710 device_initcall(rapl_pmu_init);