2 * perf_event_intel_rapl.c: support Intel RAPL energy consumption counters
3 * Copyright (C) 2013 Google, Inc., Stephane Eranian
5 * Intel RAPL interface is specified in the IA-32 Manual Vol3b
6 * section 14.7.1 (September 2013)
8 * RAPL provides more controls than just reporting energy consumption
9 * however here we only expose the 3 energy consumption free running
10 * counters (pp0, pkg, dram).
12 * Each of those counters increments in a power unit defined by the
13 * RAPL_POWER_UNIT MSR. On SandyBridge, this unit is 1/(2^16) Joules
16 * Counter to rapl events mappings:
18 * pp0 counter: consumption of all physical cores (power plane 0)
19 * event: rapl_energy_cores
22 * pkg counter: consumption of the whole processor package
23 * event: rapl_energy_pkg
26 * dram counter: consumption of the dram domain (servers only)
27 * event: rapl_energy_dram
30 * dram counter: consumption of the builtin-gpu domain (client only)
31 * event: rapl_energy_gpu
34 * We manage those counters as free running (read-only). They may be
35 * use simultaneously by other tools, such as turbostat.
37 * The events only support system-wide mode counting. There is no
38 * sampling support because it does not make sense and is not
39 * supported by the RAPL hardware.
41 * Because we want to avoid floating-point operations in the kernel,
42 * the events are all reported in fixed point arithmetic (32.32).
43 * Tools must adjust the counts to convert them to Watts using
44 * the duration of the measurement. Tools may use a function such as
45 * ldexp(raw_count, -32);
47 #include <linux/module.h>
48 #include <linux/slab.h>
49 #include <linux/perf_event.h>
50 #include <asm/cpu_device_id.h>
51 #include "perf_event.h"
54 * RAPL energy status counters
56 #define RAPL_IDX_PP0_NRG_STAT 0 /* all cores */
57 #define INTEL_RAPL_PP0 0x1 /* pseudo-encoding */
58 #define RAPL_IDX_PKG_NRG_STAT 1 /* entire package */
59 #define INTEL_RAPL_PKG 0x2 /* pseudo-encoding */
60 #define RAPL_IDX_RAM_NRG_STAT 2 /* DRAM */
61 #define INTEL_RAPL_RAM 0x3 /* pseudo-encoding */
62 #define RAPL_IDX_PP1_NRG_STAT 3 /* gpu */
63 #define INTEL_RAPL_PP1 0x4 /* pseudo-encoding */
65 /* Clients have PP0, PKG */
66 #define RAPL_IDX_CLN (1<<RAPL_IDX_PP0_NRG_STAT|\
67 1<<RAPL_IDX_PKG_NRG_STAT|\
68 1<<RAPL_IDX_PP1_NRG_STAT)
70 /* Servers have PP0, PKG, RAM */
71 #define RAPL_IDX_SRV (1<<RAPL_IDX_PP0_NRG_STAT|\
72 1<<RAPL_IDX_PKG_NRG_STAT|\
73 1<<RAPL_IDX_RAM_NRG_STAT)
75 /* Servers have PP0, PKG, RAM, PP1 */
76 #define RAPL_IDX_HSW (1<<RAPL_IDX_PP0_NRG_STAT|\
77 1<<RAPL_IDX_PKG_NRG_STAT|\
78 1<<RAPL_IDX_RAM_NRG_STAT|\
79 1<<RAPL_IDX_PP1_NRG_STAT)
82 * event code: LSB 8 bits, passed in attr->config
83 * any other bit is reserved
85 #define RAPL_EVENT_MASK 0xFFULL
87 #define DEFINE_RAPL_FORMAT_ATTR(_var, _name, _format) \
88 static ssize_t __rapl_##_var##_show(struct kobject *kobj, \
89 struct kobj_attribute *attr, \
92 BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
93 return sprintf(page, _format "\n"); \
95 static struct kobj_attribute format_attr_##_var = \
96 __ATTR(_name, 0444, __rapl_##_var##_show, NULL)
98 #define RAPL_EVENT_DESC(_name, _config) \
100 .attr = __ATTR(_name, 0444, rapl_event_show, NULL), \
104 #define RAPL_CNTR_WIDTH 32 /* 32-bit rapl counters */
106 #define RAPL_EVENT_ATTR_STR(_name, v, str) \
107 static struct perf_pmu_events_attr event_attr_##v = { \
108 .attr = __ATTR(_name, 0444, rapl_sysfs_show, NULL), \
115 int hw_unit; /* 1/2^hw_unit Joule */
116 int n_active; /* number of active events */
117 struct list_head active_list;
118 struct pmu *pmu; /* pointer to rapl_pmu_class */
119 ktime_t timer_interval; /* in ktime_t unit */
120 struct hrtimer hrtimer;
123 static struct pmu rapl_pmu_class;
124 static cpumask_t rapl_cpu_mask;
125 static int rapl_cntr_mask;
127 static DEFINE_PER_CPU(struct rapl_pmu *, rapl_pmu);
128 static DEFINE_PER_CPU(struct rapl_pmu *, rapl_pmu_to_free);
130 static inline u64 rapl_read_counter(struct perf_event *event)
133 rdmsrl(event->hw.event_base, raw);
137 static inline u64 rapl_scale(u64 v)
140 * scale delta to smallest unit (1/2^32)
141 * users must then scale back: count * 1/(1e9*2^32) to get Joules
142 * or use ldexp(count, -32).
143 * Watts = Joules/Time delta
145 return v << (32 - __this_cpu_read(rapl_pmu)->hw_unit);
148 static u64 rapl_event_update(struct perf_event *event)
150 struct hw_perf_event *hwc = &event->hw;
151 u64 prev_raw_count, new_raw_count;
153 int shift = RAPL_CNTR_WIDTH;
156 prev_raw_count = local64_read(&hwc->prev_count);
157 rdmsrl(event->hw.event_base, new_raw_count);
159 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
160 new_raw_count) != prev_raw_count) {
166 * Now we have the new raw value and have updated the prev
167 * timestamp already. We can now calculate the elapsed delta
168 * (event-)time and add that to the generic event.
170 * Careful, not all hw sign-extends above the physical width
173 delta = (new_raw_count << shift) - (prev_raw_count << shift);
176 sdelta = rapl_scale(delta);
178 local64_add(sdelta, &event->count);
180 return new_raw_count;
183 static void rapl_start_hrtimer(struct rapl_pmu *pmu)
185 __hrtimer_start_range_ns(&pmu->hrtimer,
186 pmu->timer_interval, 0,
187 HRTIMER_MODE_REL_PINNED, 0);
190 static void rapl_stop_hrtimer(struct rapl_pmu *pmu)
192 hrtimer_cancel(&pmu->hrtimer);
195 static enum hrtimer_restart rapl_hrtimer_handle(struct hrtimer *hrtimer)
197 struct rapl_pmu *pmu = __this_cpu_read(rapl_pmu);
198 struct perf_event *event;
202 return HRTIMER_NORESTART;
204 spin_lock_irqsave(&pmu->lock, flags);
206 list_for_each_entry(event, &pmu->active_list, active_entry) {
207 rapl_event_update(event);
210 spin_unlock_irqrestore(&pmu->lock, flags);
212 hrtimer_forward_now(hrtimer, pmu->timer_interval);
214 return HRTIMER_RESTART;
217 static void rapl_hrtimer_init(struct rapl_pmu *pmu)
219 struct hrtimer *hr = &pmu->hrtimer;
221 hrtimer_init(hr, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
222 hr->function = rapl_hrtimer_handle;
225 static void __rapl_pmu_event_start(struct rapl_pmu *pmu,
226 struct perf_event *event)
228 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
233 list_add_tail(&event->active_entry, &pmu->active_list);
235 local64_set(&event->hw.prev_count, rapl_read_counter(event));
238 if (pmu->n_active == 1)
239 rapl_start_hrtimer(pmu);
242 static void rapl_pmu_event_start(struct perf_event *event, int mode)
244 struct rapl_pmu *pmu = __this_cpu_read(rapl_pmu);
247 spin_lock_irqsave(&pmu->lock, flags);
248 __rapl_pmu_event_start(pmu, event);
249 spin_unlock_irqrestore(&pmu->lock, flags);
252 static void rapl_pmu_event_stop(struct perf_event *event, int mode)
254 struct rapl_pmu *pmu = __this_cpu_read(rapl_pmu);
255 struct hw_perf_event *hwc = &event->hw;
258 spin_lock_irqsave(&pmu->lock, flags);
260 /* mark event as deactivated and stopped */
261 if (!(hwc->state & PERF_HES_STOPPED)) {
262 WARN_ON_ONCE(pmu->n_active <= 0);
264 if (pmu->n_active == 0)
265 rapl_stop_hrtimer(pmu);
267 list_del(&event->active_entry);
269 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
270 hwc->state |= PERF_HES_STOPPED;
273 /* check if update of sw counter is necessary */
274 if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
276 * Drain the remaining delta count out of a event
277 * that we are disabling:
279 rapl_event_update(event);
280 hwc->state |= PERF_HES_UPTODATE;
283 spin_unlock_irqrestore(&pmu->lock, flags);
286 static int rapl_pmu_event_add(struct perf_event *event, int mode)
288 struct rapl_pmu *pmu = __this_cpu_read(rapl_pmu);
289 struct hw_perf_event *hwc = &event->hw;
292 spin_lock_irqsave(&pmu->lock, flags);
294 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
296 if (mode & PERF_EF_START)
297 __rapl_pmu_event_start(pmu, event);
299 spin_unlock_irqrestore(&pmu->lock, flags);
304 static void rapl_pmu_event_del(struct perf_event *event, int flags)
306 rapl_pmu_event_stop(event, PERF_EF_UPDATE);
309 static int rapl_pmu_event_init(struct perf_event *event)
311 u64 cfg = event->attr.config & RAPL_EVENT_MASK;
312 int bit, msr, ret = 0;
314 /* only look at RAPL events */
315 if (event->attr.type != rapl_pmu_class.type)
318 /* check only supported bits are set */
319 if (event->attr.config & ~RAPL_EVENT_MASK)
323 * check event is known (determines counter)
327 bit = RAPL_IDX_PP0_NRG_STAT;
328 msr = MSR_PP0_ENERGY_STATUS;
331 bit = RAPL_IDX_PKG_NRG_STAT;
332 msr = MSR_PKG_ENERGY_STATUS;
335 bit = RAPL_IDX_RAM_NRG_STAT;
336 msr = MSR_DRAM_ENERGY_STATUS;
339 bit = RAPL_IDX_PP1_NRG_STAT;
340 msr = MSR_PP1_ENERGY_STATUS;
345 /* check event supported */
346 if (!(rapl_cntr_mask & (1 << bit)))
349 /* unsupported modes and filters */
350 if (event->attr.exclude_user ||
351 event->attr.exclude_kernel ||
352 event->attr.exclude_hv ||
353 event->attr.exclude_idle ||
354 event->attr.exclude_host ||
355 event->attr.exclude_guest ||
356 event->attr.sample_period) /* no sampling */
359 /* must be done before validate_group */
360 event->hw.event_base = msr;
361 event->hw.config = cfg;
367 static void rapl_pmu_event_read(struct perf_event *event)
369 rapl_event_update(event);
372 static ssize_t rapl_get_attr_cpumask(struct device *dev,
373 struct device_attribute *attr, char *buf)
375 return cpumap_print_to_pagebuf(true, buf, &rapl_cpu_mask);
378 static DEVICE_ATTR(cpumask, S_IRUGO, rapl_get_attr_cpumask, NULL);
380 static struct attribute *rapl_pmu_attrs[] = {
381 &dev_attr_cpumask.attr,
385 static struct attribute_group rapl_pmu_attr_group = {
386 .attrs = rapl_pmu_attrs,
389 static ssize_t rapl_sysfs_show(struct device *dev,
390 struct device_attribute *attr,
393 struct perf_pmu_events_attr *pmu_attr = \
394 container_of(attr, struct perf_pmu_events_attr, attr);
396 if (pmu_attr->event_str)
397 return sprintf(page, "%s", pmu_attr->event_str);
402 RAPL_EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01");
403 RAPL_EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event=0x02");
404 RAPL_EVENT_ATTR_STR(energy-ram , rapl_ram, "event=0x03");
405 RAPL_EVENT_ATTR_STR(energy-gpu , rapl_gpu, "event=0x04");
407 RAPL_EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules");
408 RAPL_EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules");
409 RAPL_EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules");
410 RAPL_EVENT_ATTR_STR(energy-gpu.unit , rapl_gpu_unit, "Joules");
413 * we compute in 0.23 nJ increments regardless of MSR
415 RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10");
416 RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scale, "2.3283064365386962890625e-10");
417 RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890625e-10");
418 RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10");
420 static struct attribute *rapl_events_srv_attr[] = {
421 EVENT_PTR(rapl_cores),
425 EVENT_PTR(rapl_cores_unit),
426 EVENT_PTR(rapl_pkg_unit),
427 EVENT_PTR(rapl_ram_unit),
429 EVENT_PTR(rapl_cores_scale),
430 EVENT_PTR(rapl_pkg_scale),
431 EVENT_PTR(rapl_ram_scale),
435 static struct attribute *rapl_events_cln_attr[] = {
436 EVENT_PTR(rapl_cores),
440 EVENT_PTR(rapl_cores_unit),
441 EVENT_PTR(rapl_pkg_unit),
442 EVENT_PTR(rapl_gpu_unit),
444 EVENT_PTR(rapl_cores_scale),
445 EVENT_PTR(rapl_pkg_scale),
446 EVENT_PTR(rapl_gpu_scale),
450 static struct attribute *rapl_events_hsw_attr[] = {
451 EVENT_PTR(rapl_cores),
456 EVENT_PTR(rapl_cores_unit),
457 EVENT_PTR(rapl_pkg_unit),
458 EVENT_PTR(rapl_gpu_unit),
459 EVENT_PTR(rapl_ram_unit),
461 EVENT_PTR(rapl_cores_scale),
462 EVENT_PTR(rapl_pkg_scale),
463 EVENT_PTR(rapl_gpu_scale),
464 EVENT_PTR(rapl_ram_scale),
468 static struct attribute_group rapl_pmu_events_group = {
470 .attrs = NULL, /* patched at runtime */
473 DEFINE_RAPL_FORMAT_ATTR(event, event, "config:0-7");
474 static struct attribute *rapl_formats_attr[] = {
475 &format_attr_event.attr,
479 static struct attribute_group rapl_pmu_format_group = {
481 .attrs = rapl_formats_attr,
484 const struct attribute_group *rapl_attr_groups[] = {
485 &rapl_pmu_attr_group,
486 &rapl_pmu_format_group,
487 &rapl_pmu_events_group,
491 static struct pmu rapl_pmu_class = {
492 .attr_groups = rapl_attr_groups,
493 .task_ctx_nr = perf_invalid_context, /* system-wide only */
494 .event_init = rapl_pmu_event_init,
495 .add = rapl_pmu_event_add, /* must have */
496 .del = rapl_pmu_event_del, /* must have */
497 .start = rapl_pmu_event_start,
498 .stop = rapl_pmu_event_stop,
499 .read = rapl_pmu_event_read,
502 static void rapl_cpu_exit(int cpu)
504 struct rapl_pmu *pmu = per_cpu(rapl_pmu, cpu);
505 int i, phys_id = topology_physical_package_id(cpu);
508 /* find a new cpu on same package */
509 for_each_online_cpu(i) {
512 if (phys_id == topology_physical_package_id(i)) {
518 * clear cpu from cpumask
519 * if was set in cpumask and still some cpu on package,
520 * then move to new cpu
522 if (cpumask_test_and_clear_cpu(cpu, &rapl_cpu_mask) && target >= 0)
523 cpumask_set_cpu(target, &rapl_cpu_mask);
525 WARN_ON(cpumask_empty(&rapl_cpu_mask));
527 * migrate events and context to new cpu
530 perf_pmu_migrate_context(pmu->pmu, cpu, target);
532 /* cancel overflow polling timer for CPU */
533 rapl_stop_hrtimer(pmu);
536 static void rapl_cpu_init(int cpu)
538 int i, phys_id = topology_physical_package_id(cpu);
540 /* check if phys_is is already covered */
541 for_each_cpu(i, &rapl_cpu_mask) {
542 if (phys_id == topology_physical_package_id(i))
545 /* was not found, so add it */
546 cpumask_set_cpu(cpu, &rapl_cpu_mask);
549 static int rapl_cpu_prepare(int cpu)
551 struct rapl_pmu *pmu = per_cpu(rapl_pmu, cpu);
552 int phys_id = topology_physical_package_id(cpu);
554 u64 msr_rapl_power_unit_bits;
562 /* protect rdmsrl() to handle virtualization */
563 if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &msr_rapl_power_unit_bits))
566 pmu = kzalloc_node(sizeof(*pmu), GFP_KERNEL, cpu_to_node(cpu));
570 spin_lock_init(&pmu->lock);
572 INIT_LIST_HEAD(&pmu->active_list);
575 * grab power unit as: 1/2^unit Joules
577 * we cache in local PMU instance
579 pmu->hw_unit = (msr_rapl_power_unit_bits >> 8) & 0x1FULL;
580 pmu->pmu = &rapl_pmu_class;
583 * use reference of 200W for scaling the timeout
584 * to avoid missing counter overflows.
585 * 200W = 200 Joules/sec
586 * divide interval by 2 to avoid lockstep (2 * 100)
587 * if hw unit is 32, then we use 2 ms 1/200/2
589 if (pmu->hw_unit < 32)
590 ms = (1000 / (2 * 100)) * (1ULL << (32 - pmu->hw_unit - 1));
594 pmu->timer_interval = ms_to_ktime(ms);
596 rapl_hrtimer_init(pmu);
598 /* set RAPL pmu for this cpu for now */
599 per_cpu(rapl_pmu, cpu) = pmu;
600 per_cpu(rapl_pmu_to_free, cpu) = NULL;
605 static void rapl_cpu_kfree(int cpu)
607 struct rapl_pmu *pmu = per_cpu(rapl_pmu_to_free, cpu);
611 per_cpu(rapl_pmu_to_free, cpu) = NULL;
614 static int rapl_cpu_dying(int cpu)
616 struct rapl_pmu *pmu = per_cpu(rapl_pmu, cpu);
621 per_cpu(rapl_pmu, cpu) = NULL;
623 per_cpu(rapl_pmu_to_free, cpu) = pmu;
628 static int rapl_cpu_notifier(struct notifier_block *self,
629 unsigned long action, void *hcpu)
631 unsigned int cpu = (long)hcpu;
633 switch (action & ~CPU_TASKS_FROZEN) {
635 rapl_cpu_prepare(cpu);
640 case CPU_UP_CANCELED:
648 case CPU_DOWN_PREPARE:
658 static const struct x86_cpu_id rapl_cpu_match[] = {
659 [0] = { .vendor = X86_VENDOR_INTEL, .family = 6 },
663 static int __init rapl_pmu_init(void)
665 struct rapl_pmu *pmu;
669 * check for Intel processor family 6
671 if (!x86_match_cpu(rapl_cpu_match))
674 /* check supported CPU */
675 switch (boot_cpu_data.x86_model) {
676 case 42: /* Sandy Bridge */
677 case 58: /* Ivy Bridge */
678 rapl_cntr_mask = RAPL_IDX_CLN;
679 rapl_pmu_events_group.attrs = rapl_events_cln_attr;
681 case 60: /* Haswell */
682 case 69: /* Haswell-Celeron */
683 rapl_cntr_mask = RAPL_IDX_HSW;
684 rapl_pmu_events_group.attrs = rapl_events_hsw_attr;
686 case 45: /* Sandy Bridge-EP */
687 case 62: /* IvyTown */
688 rapl_cntr_mask = RAPL_IDX_SRV;
689 rapl_pmu_events_group.attrs = rapl_events_srv_attr;
697 cpu_notifier_register_begin();
699 for_each_online_cpu(cpu) {
700 ret = rapl_cpu_prepare(cpu);
706 __perf_cpu_notifier(rapl_cpu_notifier);
708 ret = perf_pmu_register(&rapl_pmu_class, "power", -1);
710 pr_info("RAPL PMU detected, registration failed (%d), RAPL PMU disabled\n", ret);
711 cpu_notifier_register_done();
715 pmu = __this_cpu_read(rapl_pmu);
717 pr_info("RAPL PMU detected, hw unit 2^-%d Joules,"
718 " API unit is 2^-32 Joules,"
720 " %llu ms ovfl timer\n",
722 hweight32(rapl_cntr_mask),
723 ktime_to_ms(pmu->timer_interval));
726 cpu_notifier_register_done();
730 device_initcall(rapl_pmu_init);