arch/x86/kernel/cpu/perf_event_intel.c

   1 /*
   2  * Per core/cpu state
   3  *
   4  * Used to coordinate shared registers between HT threads or
   5  * among events on a single PMU.
   6  */
   7
   8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   9
  10 #include <linux/stddef.h>
  11 #include <linux/types.h>
  12 #include <linux/init.h>
  13 #include <linux/slab.h>
  14 #include <linux/export.h>
  15
  16 #include <asm/cpufeature.h>
  17 #include <asm/hardirq.h>
  18 #include <asm/apic.h>
  19
  20 #include "perf_event.h"
  21
  22 /*
  23  * Intel PerfMon, used on Core and later.
  24  */
  25 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
  26 {
  27         [PERF_COUNT_HW_CPU_CYCLES]              = 0x003c,
  28         [PERF_COUNT_HW_INSTRUCTIONS]            = 0x00c0,
  29         [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x4f2e,
  30         [PERF_COUNT_HW_CACHE_MISSES]            = 0x412e,
  31         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x00c4,
  32         [PERF_COUNT_HW_BRANCH_MISSES]           = 0x00c5,
  33         [PERF_COUNT_HW_BUS_CYCLES]              = 0x013c,
  34         [PERF_COUNT_HW_REF_CPU_CYCLES]          = 0x0300, /* pseudo-encoding */
  35 };
  36
  37 static struct event_constraint intel_core_event_constraints[] __read_mostly =
  38 {
  39         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  40         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  41         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  42         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  43         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  44         INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
  45         EVENT_CONSTRAINT_END
  46 };
  47
  48 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
  49 {
  50         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  51         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  52         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  53         INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
  54         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  55         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  56         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  57         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  58         INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
  59         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  60         INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
  61         INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
  62         INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
  63         EVENT_CONSTRAINT_END
  64 };
  65
  66 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
  67 {
  68         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  69         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  70         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  71         INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
  72         INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
  73         INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
  74         INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
  75         INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
  76         INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
  77         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  78         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  79         EVENT_CONSTRAINT_END
  80 };
  81
  82 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
  83 {
  84         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
  85         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
  86         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
  87         EVENT_EXTRA_END
  88 };
  89
  90 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
  91 {
  92         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  93         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  94         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  95         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  96         INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
  97         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  98         INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
  99         EVENT_CONSTRAINT_END
 100 };
 101
 102 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 103 {
 104         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 105         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 106         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 107         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 108         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 109         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 110         INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 111         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
 112         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 113         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 114         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 115         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 116         EVENT_CONSTRAINT_END
 117 };
 118
 119 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
 120 {
 121         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 122         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 123         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 124         INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
 125         INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
 126         INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
 127         INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
 128         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 129         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 130         INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
 131         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 132         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 133         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 134         /*
 135          * Errata BV98 -- MEM_*_RETIRED events can leak between counters of SMT
 136          * siblings; disable these events because they can corrupt unrelated
 137          * counters.
 138          */
 139         INTEL_EVENT_CONSTRAINT(0xd0, 0x0), /* MEM_UOPS_RETIRED.* */
 140         INTEL_EVENT_CONSTRAINT(0xd1, 0x0), /* MEM_LOAD_UOPS_RETIRED.* */
 141         INTEL_EVENT_CONSTRAINT(0xd2, 0x0), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 142         INTEL_EVENT_CONSTRAINT(0xd3, 0x0), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 143         EVENT_CONSTRAINT_END
 144 };
 145
 146 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
 147 {
 148         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 149         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
 150         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
 151         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
 152         EVENT_EXTRA_END
 153 };
 154
 155 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
 156 {
 157         EVENT_CONSTRAINT_END
 158 };
 159
 160 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
 161 {
 162         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 163         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 164         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 165         EVENT_CONSTRAINT_END
 166 };
 167
 168 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
 169 {
 170         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 171         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 172         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
 173         EVENT_CONSTRAINT_END
 174 };
 175
 176 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
 177         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 178         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
 179         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
 180         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 181         EVENT_EXTRA_END
 182 };
 183
 184 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
 185         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 186         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 187         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 188         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 189         EVENT_EXTRA_END
 190 };
 191
 192 EVENT_ATTR_STR(mem-loads,       mem_ld_nhm,     "event=0x0b,umask=0x10,ldlat=3");
 193 EVENT_ATTR_STR(mem-loads,       mem_ld_snb,     "event=0xcd,umask=0x1,ldlat=3");
 194 EVENT_ATTR_STR(mem-stores,      mem_st_snb,     "event=0xcd,umask=0x2");
 195
 196 struct attribute *nhm_events_attrs[] = {
 197         EVENT_PTR(mem_ld_nhm),
 198         NULL,
 199 };
 200
 201 struct attribute *snb_events_attrs[] = {
 202         EVENT_PTR(mem_ld_snb),
 203         EVENT_PTR(mem_st_snb),
 204         NULL,
 205 };
 206
 207 static struct event_constraint intel_hsw_event_constraints[] = {
 208         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 209         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 210         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 211         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
 212         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 213         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 214         /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 215         INTEL_EVENT_CONSTRAINT(0x08a3, 0x4),
 216         /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 217         INTEL_EVENT_CONSTRAINT(0x0ca3, 0x4),
 218         /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 219         INTEL_EVENT_CONSTRAINT(0x04a3, 0xf),
 220         EVENT_CONSTRAINT_END
 221 };
 222
 223 struct event_constraint intel_bdw_event_constraints[] = {
 224         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 225         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 226         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 227         INTEL_UEVENT_CONSTRAINT(0x148, 0x4),    /* L1D_PEND_MISS.PENDING */
 228         INTEL_EVENT_CONSTRAINT(0xa3, 0x4),      /* CYCLE_ACTIVITY.* */
 229         EVENT_CONSTRAINT_END
 230 };
 231
 232 static u64 intel_pmu_event_map(int hw_event)
 233 {
 234         return intel_perfmon_event_map[hw_event];
 235 }
 236
 237 #define SNB_DMND_DATA_RD        (1ULL << 0)
 238 #define SNB_DMND_RFO            (1ULL << 1)
 239 #define SNB_DMND_IFETCH         (1ULL << 2)
 240 #define SNB_DMND_WB             (1ULL << 3)
 241 #define SNB_PF_DATA_RD          (1ULL << 4)
 242 #define SNB_PF_RFO              (1ULL << 5)
 243 #define SNB_PF_IFETCH           (1ULL << 6)
 244 #define SNB_LLC_DATA_RD         (1ULL << 7)
 245 #define SNB_LLC_RFO             (1ULL << 8)
 246 #define SNB_LLC_IFETCH          (1ULL << 9)
 247 #define SNB_BUS_LOCKS           (1ULL << 10)
 248 #define SNB_STRM_ST             (1ULL << 11)
 249 #define SNB_OTHER               (1ULL << 15)
 250 #define SNB_RESP_ANY            (1ULL << 16)
 251 #define SNB_NO_SUPP             (1ULL << 17)
 252 #define SNB_LLC_HITM            (1ULL << 18)
 253 #define SNB_LLC_HITE            (1ULL << 19)
 254 #define SNB_LLC_HITS            (1ULL << 20)
 255 #define SNB_LLC_HITF            (1ULL << 21)
 256 #define SNB_LOCAL               (1ULL << 22)
 257 #define SNB_REMOTE              (0xffULL << 23)
 258 #define SNB_SNP_NONE            (1ULL << 31)
 259 #define SNB_SNP_NOT_NEEDED      (1ULL << 32)
 260 #define SNB_SNP_MISS            (1ULL << 33)
 261 #define SNB_NO_FWD              (1ULL << 34)
 262 #define SNB_SNP_FWD             (1ULL << 35)
 263 #define SNB_HITM                (1ULL << 36)
 264 #define SNB_NON_DRAM            (1ULL << 37)
 265
 266 #define SNB_DMND_READ           (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
 267 #define SNB_DMND_WRITE          (SNB_DMND_RFO|SNB_LLC_RFO)
 268 #define SNB_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
 269
 270 #define SNB_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
 271                                  SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
 272                                  SNB_HITM)
 273
 274 #define SNB_DRAM_ANY            (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
 275 #define SNB_DRAM_REMOTE         (SNB_REMOTE|SNB_SNP_ANY)
 276
 277 #define SNB_L3_ACCESS           SNB_RESP_ANY
 278 #define SNB_L3_MISS             (SNB_DRAM_ANY|SNB_NON_DRAM)
 279
 280 static __initconst const u64 snb_hw_cache_extra_regs
 281                                 [PERF_COUNT_HW_CACHE_MAX]
 282                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 283                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 284 {
 285  [ C(LL  ) ] = {
 286         [ C(OP_READ) ] = {
 287                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
 288                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_L3_MISS,
 289         },
 290         [ C(OP_WRITE) ] = {
 291                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
 292                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_L3_MISS,
 293         },
 294         [ C(OP_PREFETCH) ] = {
 295                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
 296                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
 297         },
 298  },
 299  [ C(NODE) ] = {
 300         [ C(OP_READ) ] = {
 301                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
 302                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
 303         },
 304         [ C(OP_WRITE) ] = {
 305                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
 306                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
 307         },
 308         [ C(OP_PREFETCH) ] = {
 309                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
 310                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
 311         },
 312  },
 313 };
 314
 315 static __initconst const u64 snb_hw_cache_event_ids
 316                                 [PERF_COUNT_HW_CACHE_MAX]
 317                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 318                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 319 {
 320  [ C(L1D) ] = {
 321         [ C(OP_READ) ] = {
 322                 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS        */
 323                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPLACEMENT              */
 324         },
 325         [ C(OP_WRITE) ] = {
 326                 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES       */
 327                 [ C(RESULT_MISS)   ] = 0x0851, /* L1D.ALL_M_REPLACEMENT        */
 328         },
 329         [ C(OP_PREFETCH) ] = {
 330                 [ C(RESULT_ACCESS) ] = 0x0,
 331                 [ C(RESULT_MISS)   ] = 0x024e, /* HW_PRE_REQ.DL1_MISS          */
 332         },
 333  },
 334  [ C(L1I ) ] = {
 335         [ C(OP_READ) ] = {
 336                 [ C(RESULT_ACCESS) ] = 0x0,
 337                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACHE.MISSES */
 338         },
 339         [ C(OP_WRITE) ] = {
 340                 [ C(RESULT_ACCESS) ] = -1,
 341                 [ C(RESULT_MISS)   ] = -1,
 342         },
 343         [ C(OP_PREFETCH) ] = {
 344                 [ C(RESULT_ACCESS) ] = 0x0,
 345                 [ C(RESULT_MISS)   ] = 0x0,
 346         },
 347  },
 348  [ C(LL  ) ] = {
 349         [ C(OP_READ) ] = {
 350                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 351                 [ C(RESULT_ACCESS) ] = 0x01b7,
 352                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 353                 [ C(RESULT_MISS)   ] = 0x01b7,
 354         },
 355         [ C(OP_WRITE) ] = {
 356                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 357                 [ C(RESULT_ACCESS) ] = 0x01b7,
 358                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 359                 [ C(RESULT_MISS)   ] = 0x01b7,
 360         },
 361         [ C(OP_PREFETCH) ] = {
 362                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 363                 [ C(RESULT_ACCESS) ] = 0x01b7,
 364                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 365                 [ C(RESULT_MISS)   ] = 0x01b7,
 366         },
 367  },
 368  [ C(DTLB) ] = {
 369         [ C(OP_READ) ] = {
 370                 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
 371                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
 372         },
 373         [ C(OP_WRITE) ] = {
 374                 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
 375                 [ C(RESULT_MISS)   ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
 376         },
 377         [ C(OP_PREFETCH) ] = {
 378                 [ C(RESULT_ACCESS) ] = 0x0,
 379                 [ C(RESULT_MISS)   ] = 0x0,
 380         },
 381  },
 382  [ C(ITLB) ] = {
 383         [ C(OP_READ) ] = {
 384                 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT         */
 385                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK    */
 386         },
 387         [ C(OP_WRITE) ] = {
 388                 [ C(RESULT_ACCESS) ] = -1,
 389                 [ C(RESULT_MISS)   ] = -1,
 390         },
 391         [ C(OP_PREFETCH) ] = {
 392                 [ C(RESULT_ACCESS) ] = -1,
 393                 [ C(RESULT_MISS)   ] = -1,
 394         },
 395  },
 396  [ C(BPU ) ] = {
 397         [ C(OP_READ) ] = {
 398                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 399                 [ C(RESULT_MISS)   ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
 400         },
 401         [ C(OP_WRITE) ] = {
 402                 [ C(RESULT_ACCESS) ] = -1,
 403                 [ C(RESULT_MISS)   ] = -1,
 404         },
 405         [ C(OP_PREFETCH) ] = {
 406                 [ C(RESULT_ACCESS) ] = -1,
 407                 [ C(RESULT_MISS)   ] = -1,
 408         },
 409  },
 410  [ C(NODE) ] = {
 411         [ C(OP_READ) ] = {
 412                 [ C(RESULT_ACCESS) ] = 0x01b7,
 413                 [ C(RESULT_MISS)   ] = 0x01b7,
 414         },
 415         [ C(OP_WRITE) ] = {
 416                 [ C(RESULT_ACCESS) ] = 0x01b7,
 417                 [ C(RESULT_MISS)   ] = 0x01b7,
 418         },
 419         [ C(OP_PREFETCH) ] = {
 420                 [ C(RESULT_ACCESS) ] = 0x01b7,
 421                 [ C(RESULT_MISS)   ] = 0x01b7,
 422         },
 423  },
 424
 425 };
 426
 427 /*
 428  * Notes on the events:
 429  * - data reads do not include code reads (comparable to earlier tables)
 430  * - data counts include speculative execution (except L1 write, dtlb, bpu)
 431  * - remote node access includes remote memory, remote cache, remote mmio.
 432  * - prefetches are not included in the counts because they are not
 433  *   reliably counted.
 434  */
 435
 436 #define HSW_DEMAND_DATA_RD              BIT_ULL(0)
 437 #define HSW_DEMAND_RFO                  BIT_ULL(1)
 438 #define HSW_ANY_RESPONSE                BIT_ULL(16)
 439 #define HSW_SUPPLIER_NONE               BIT_ULL(17)
 440 #define HSW_L3_MISS_LOCAL_DRAM          BIT_ULL(22)
 441 #define HSW_L3_MISS_REMOTE_HOP0         BIT_ULL(27)
 442 #define HSW_L3_MISS_REMOTE_HOP1         BIT_ULL(28)
 443 #define HSW_L3_MISS_REMOTE_HOP2P        BIT_ULL(29)
 444 #define HSW_L3_MISS                     (HSW_L3_MISS_LOCAL_DRAM| \
 445                                          HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
 446                                          HSW_L3_MISS_REMOTE_HOP2P)
 447 #define HSW_SNOOP_NONE                  BIT_ULL(31)
 448 #define HSW_SNOOP_NOT_NEEDED            BIT_ULL(32)
 449 #define HSW_SNOOP_MISS                  BIT_ULL(33)
 450 #define HSW_SNOOP_HIT_NO_FWD            BIT_ULL(34)
 451 #define HSW_SNOOP_HIT_WITH_FWD          BIT_ULL(35)
 452 #define HSW_SNOOP_HITM                  BIT_ULL(36)
 453 #define HSW_SNOOP_NON_DRAM              BIT_ULL(37)
 454 #define HSW_ANY_SNOOP                   (HSW_SNOOP_NONE| \
 455                                          HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
 456                                          HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
 457                                          HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
 458 #define HSW_SNOOP_DRAM                  (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
 459 #define HSW_DEMAND_READ                 HSW_DEMAND_DATA_RD
 460 #define HSW_DEMAND_WRITE                HSW_DEMAND_RFO
 461 #define HSW_L3_MISS_REMOTE              (HSW_L3_MISS_REMOTE_HOP0|\
 462                                          HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
 463 #define HSW_LLC_ACCESS                  HSW_ANY_RESPONSE
 464
 465 #define BDW_L3_MISS_LOCAL               BIT(26)
 466 #define BDW_L3_MISS                     (BDW_L3_MISS_LOCAL| \
 467                                          HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
 468                                          HSW_L3_MISS_REMOTE_HOP2P)
 469
 470
 471 static __initconst const u64 hsw_hw_cache_event_ids
 472                                 [PERF_COUNT_HW_CACHE_MAX]
 473                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 474                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 475 {
 476  [ C(L1D ) ] = {
 477         [ C(OP_READ) ] = {
 478                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
 479                 [ C(RESULT_MISS)   ] = 0x151,   /* L1D.REPLACEMENT */
 480         },
 481         [ C(OP_WRITE) ] = {
 482                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
 483                 [ C(RESULT_MISS)   ] = 0x0,
 484         },
 485         [ C(OP_PREFETCH) ] = {
 486                 [ C(RESULT_ACCESS) ] = 0x0,
 487                 [ C(RESULT_MISS)   ] = 0x0,
 488         },
 489  },
 490  [ C(L1I ) ] = {
 491         [ C(OP_READ) ] = {
 492                 [ C(RESULT_ACCESS) ] = 0x0,
 493                 [ C(RESULT_MISS)   ] = 0x280,   /* ICACHE.MISSES */
 494         },
 495         [ C(OP_WRITE) ] = {
 496                 [ C(RESULT_ACCESS) ] = -1,
 497                 [ C(RESULT_MISS)   ] = -1,
 498         },
 499         [ C(OP_PREFETCH) ] = {
 500                 [ C(RESULT_ACCESS) ] = 0x0,
 501                 [ C(RESULT_MISS)   ] = 0x0,
 502         },
 503  },
 504  [ C(LL  ) ] = {
 505         [ C(OP_READ) ] = {
 506                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 507                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 508         },
 509         [ C(OP_WRITE) ] = {
 510                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 511                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 512         },
 513         [ C(OP_PREFETCH) ] = {
 514                 [ C(RESULT_ACCESS) ] = 0x0,
 515                 [ C(RESULT_MISS)   ] = 0x0,
 516         },
 517  },
 518  [ C(DTLB) ] = {
 519         [ C(OP_READ) ] = {
 520                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
 521                 [ C(RESULT_MISS)   ] = 0x108,   /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
 522         },
 523         [ C(OP_WRITE) ] = {
 524                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
 525                 [ C(RESULT_MISS)   ] = 0x149,   /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
 526         },
 527         [ C(OP_PREFETCH) ] = {
 528                 [ C(RESULT_ACCESS) ] = 0x0,
 529                 [ C(RESULT_MISS)   ] = 0x0,
 530         },
 531  },
 532  [ C(ITLB) ] = {
 533         [ C(OP_READ) ] = {
 534                 [ C(RESULT_ACCESS) ] = 0x6085,  /* ITLB_MISSES.STLB_HIT */
 535                 [ C(RESULT_MISS)   ] = 0x185,   /* ITLB_MISSES.MISS_CAUSES_A_WALK */
 536         },
 537         [ C(OP_WRITE) ] = {
 538                 [ C(RESULT_ACCESS) ] = -1,
 539                 [ C(RESULT_MISS)   ] = -1,
 540         },
 541         [ C(OP_PREFETCH) ] = {
 542                 [ C(RESULT_ACCESS) ] = -1,
 543                 [ C(RESULT_MISS)   ] = -1,
 544         },
 545  },
 546  [ C(BPU ) ] = {
 547         [ C(OP_READ) ] = {
 548                 [ C(RESULT_ACCESS) ] = 0xc4,    /* BR_INST_RETIRED.ALL_BRANCHES */
 549                 [ C(RESULT_MISS)   ] = 0xc5,    /* BR_MISP_RETIRED.ALL_BRANCHES */
 550         },
 551         [ C(OP_WRITE) ] = {
 552                 [ C(RESULT_ACCESS) ] = -1,
 553                 [ C(RESULT_MISS)   ] = -1,
 554         },
 555         [ C(OP_PREFETCH) ] = {
 556                 [ C(RESULT_ACCESS) ] = -1,
 557                 [ C(RESULT_MISS)   ] = -1,
 558         },
 559  },
 560  [ C(NODE) ] = {
 561         [ C(OP_READ) ] = {
 562                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 563                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 564         },
 565         [ C(OP_WRITE) ] = {
 566                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 567                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 568         },
 569         [ C(OP_PREFETCH) ] = {
 570                 [ C(RESULT_ACCESS) ] = 0x0,
 571                 [ C(RESULT_MISS)   ] = 0x0,
 572         },
 573  },
 574 };
 575
 576 static __initconst const u64 hsw_hw_cache_extra_regs
 577                                 [PERF_COUNT_HW_CACHE_MAX]
 578                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 579                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 580 {
 581  [ C(LL  ) ] = {
 582         [ C(OP_READ) ] = {
 583                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
 584                                        HSW_LLC_ACCESS,
 585                 [ C(RESULT_MISS)   ] = HSW_DEMAND_READ|
 586                                        HSW_L3_MISS|HSW_ANY_SNOOP,
 587         },
 588         [ C(OP_WRITE) ] = {
 589                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
 590                                        HSW_LLC_ACCESS,
 591                 [ C(RESULT_MISS)   ] = HSW_DEMAND_WRITE|
 592                                        HSW_L3_MISS|HSW_ANY_SNOOP,
 593         },
 594         [ C(OP_PREFETCH) ] = {
 595                 [ C(RESULT_ACCESS) ] = 0x0,
 596                 [ C(RESULT_MISS)   ] = 0x0,
 597         },
 598  },
 599  [ C(NODE) ] = {
 600         [ C(OP_READ) ] = {
 601                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
 602                                        HSW_L3_MISS_LOCAL_DRAM|
 603                                        HSW_SNOOP_DRAM,
 604                 [ C(RESULT_MISS)   ] = HSW_DEMAND_READ|
 605                                        HSW_L3_MISS_REMOTE|
 606                                        HSW_SNOOP_DRAM,
 607         },
 608         [ C(OP_WRITE) ] = {
 609                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
 610                                        HSW_L3_MISS_LOCAL_DRAM|
 611                                        HSW_SNOOP_DRAM,
 612                 [ C(RESULT_MISS)   ] = HSW_DEMAND_WRITE|
 613                                        HSW_L3_MISS_REMOTE|
 614                                        HSW_SNOOP_DRAM,
 615         },
 616         [ C(OP_PREFETCH) ] = {
 617                 [ C(RESULT_ACCESS) ] = 0x0,
 618                 [ C(RESULT_MISS)   ] = 0x0,
 619         },
 620  },
 621 };
 622
 623 static __initconst const u64 westmere_hw_cache_event_ids
 624                                 [PERF_COUNT_HW_CACHE_MAX]
 625                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 626                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 627 {
 628  [ C(L1D) ] = {
 629         [ C(OP_READ) ] = {
 630                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 631                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
 632         },
 633         [ C(OP_WRITE) ] = {
 634                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 635                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
 636         },
 637         [ C(OP_PREFETCH) ] = {
 638                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 639                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 640         },
 641  },
 642  [ C(L1I ) ] = {
 643         [ C(OP_READ) ] = {
 644                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 645                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 646         },
 647         [ C(OP_WRITE) ] = {
 648                 [ C(RESULT_ACCESS) ] = -1,
 649                 [ C(RESULT_MISS)   ] = -1,
 650         },
 651         [ C(OP_PREFETCH) ] = {
 652                 [ C(RESULT_ACCESS) ] = 0x0,
 653                 [ C(RESULT_MISS)   ] = 0x0,
 654         },
 655  },
 656  [ C(LL  ) ] = {
 657         [ C(OP_READ) ] = {
 658                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 659                 [ C(RESULT_ACCESS) ] = 0x01b7,
 660                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 661                 [ C(RESULT_MISS)   ] = 0x01b7,
 662         },
 663         /*
 664          * Use RFO, not WRITEBACK, because a write miss would typically occur
 665          * on RFO.
 666          */
 667         [ C(OP_WRITE) ] = {
 668                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 669                 [ C(RESULT_ACCESS) ] = 0x01b7,
 670                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 671                 [ C(RESULT_MISS)   ] = 0x01b7,
 672         },
 673         [ C(OP_PREFETCH) ] = {
 674                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 675                 [ C(RESULT_ACCESS) ] = 0x01b7,
 676                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 677                 [ C(RESULT_MISS)   ] = 0x01b7,
 678         },
 679  },
 680  [ C(DTLB) ] = {
 681         [ C(OP_READ) ] = {
 682                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 683                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 684         },
 685         [ C(OP_WRITE) ] = {
 686                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 687                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 688         },
 689         [ C(OP_PREFETCH) ] = {
 690                 [ C(RESULT_ACCESS) ] = 0x0,
 691                 [ C(RESULT_MISS)   ] = 0x0,
 692         },
 693  },
 694  [ C(ITLB) ] = {
 695         [ C(OP_READ) ] = {
 696                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 697                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.ANY              */
 698         },
 699         [ C(OP_WRITE) ] = {
 700                 [ C(RESULT_ACCESS) ] = -1,
 701                 [ C(RESULT_MISS)   ] = -1,
 702         },
 703         [ C(OP_PREFETCH) ] = {
 704                 [ C(RESULT_ACCESS) ] = -1,
 705                 [ C(RESULT_MISS)   ] = -1,
 706         },
 707  },
 708  [ C(BPU ) ] = {
 709         [ C(OP_READ) ] = {
 710                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 711                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 712         },
 713         [ C(OP_WRITE) ] = {
 714                 [ C(RESULT_ACCESS) ] = -1,
 715                 [ C(RESULT_MISS)   ] = -1,
 716         },
 717         [ C(OP_PREFETCH) ] = {
 718                 [ C(RESULT_ACCESS) ] = -1,
 719                 [ C(RESULT_MISS)   ] = -1,
 720         },
 721  },
 722  [ C(NODE) ] = {
 723         [ C(OP_READ) ] = {
 724                 [ C(RESULT_ACCESS) ] = 0x01b7,
 725                 [ C(RESULT_MISS)   ] = 0x01b7,
 726         },
 727         [ C(OP_WRITE) ] = {
 728                 [ C(RESULT_ACCESS) ] = 0x01b7,
 729                 [ C(RESULT_MISS)   ] = 0x01b7,
 730         },
 731         [ C(OP_PREFETCH) ] = {
 732                 [ C(RESULT_ACCESS) ] = 0x01b7,
 733                 [ C(RESULT_MISS)   ] = 0x01b7,
 734         },
 735  },
 736 };
 737
 738 /*
 739  * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
 740  * See IA32 SDM Vol 3B 30.6.1.3
 741  */
 742
 743 #define NHM_DMND_DATA_RD        (1 << 0)
 744 #define NHM_DMND_RFO            (1 << 1)
 745 #define NHM_DMND_IFETCH         (1 << 2)
 746 #define NHM_DMND_WB             (1 << 3)
 747 #define NHM_PF_DATA_RD          (1 << 4)
 748 #define NHM_PF_DATA_RFO         (1 << 5)
 749 #define NHM_PF_IFETCH           (1 << 6)
 750 #define NHM_OFFCORE_OTHER       (1 << 7)
 751 #define NHM_UNCORE_HIT          (1 << 8)
 752 #define NHM_OTHER_CORE_HIT_SNP  (1 << 9)
 753 #define NHM_OTHER_CORE_HITM     (1 << 10)
 754                                 /* reserved */
 755 #define NHM_REMOTE_CACHE_FWD    (1 << 12)
 756 #define NHM_REMOTE_DRAM         (1 << 13)
 757 #define NHM_LOCAL_DRAM          (1 << 14)
 758 #define NHM_NON_DRAM            (1 << 15)
 759
 760 #define NHM_LOCAL               (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
 761 #define NHM_REMOTE              (NHM_REMOTE_DRAM)
 762
 763 #define NHM_DMND_READ           (NHM_DMND_DATA_RD)
 764 #define NHM_DMND_WRITE          (NHM_DMND_RFO|NHM_DMND_WB)
 765 #define NHM_DMND_PREFETCH       (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
 766
 767 #define NHM_L3_HIT      (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
 768 #define NHM_L3_MISS     (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
 769 #define NHM_L3_ACCESS   (NHM_L3_HIT|NHM_L3_MISS)
 770
 771 static __initconst const u64 nehalem_hw_cache_extra_regs
 772                                 [PERF_COUNT_HW_CACHE_MAX]
 773                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 774                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 775 {
 776  [ C(LL  ) ] = {
 777         [ C(OP_READ) ] = {
 778                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
 779                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_L3_MISS,
 780         },
 781         [ C(OP_WRITE) ] = {
 782                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
 783                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_L3_MISS,
 784         },
 785         [ C(OP_PREFETCH) ] = {
 786                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
 787                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
 788         },
 789  },
 790  [ C(NODE) ] = {
 791         [ C(OP_READ) ] = {
 792                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
 793                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_REMOTE,
 794         },
 795         [ C(OP_WRITE) ] = {
 796                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
 797                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_REMOTE,
 798         },
 799         [ C(OP_PREFETCH) ] = {
 800                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
 801                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_REMOTE,
 802         },
 803  },
 804 };
 805
 806 static __initconst const u64 nehalem_hw_cache_event_ids
 807                                 [PERF_COUNT_HW_CACHE_MAX]
 808                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 809                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 810 {
 811  [ C(L1D) ] = {
 812         [ C(OP_READ) ] = {
 813                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 814                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
 815         },
 816         [ C(OP_WRITE) ] = {
 817                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 818                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
 819         },
 820         [ C(OP_PREFETCH) ] = {
 821                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 822                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 823         },
 824  },
 825  [ C(L1I ) ] = {
 826         [ C(OP_READ) ] = {
 827                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 828                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 829         },
 830         [ C(OP_WRITE) ] = {
 831                 [ C(RESULT_ACCESS) ] = -1,
 832                 [ C(RESULT_MISS)   ] = -1,
 833         },
 834         [ C(OP_PREFETCH) ] = {
 835                 [ C(RESULT_ACCESS) ] = 0x0,
 836                 [ C(RESULT_MISS)   ] = 0x0,
 837         },
 838  },
 839  [ C(LL  ) ] = {
 840         [ C(OP_READ) ] = {
 841                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 842                 [ C(RESULT_ACCESS) ] = 0x01b7,
 843                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 844                 [ C(RESULT_MISS)   ] = 0x01b7,
 845         },
 846         /*
 847          * Use RFO, not WRITEBACK, because a write miss would typically occur
 848          * on RFO.
 849          */
 850         [ C(OP_WRITE) ] = {
 851                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 852                 [ C(RESULT_ACCESS) ] = 0x01b7,
 853                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 854                 [ C(RESULT_MISS)   ] = 0x01b7,
 855         },
 856         [ C(OP_PREFETCH) ] = {
 857                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 858                 [ C(RESULT_ACCESS) ] = 0x01b7,
 859                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 860                 [ C(RESULT_MISS)   ] = 0x01b7,
 861         },
 862  },
 863  [ C(DTLB) ] = {
 864         [ C(OP_READ) ] = {
 865                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
 866                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 867         },
 868         [ C(OP_WRITE) ] = {
 869                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
 870                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 871         },
 872         [ C(OP_PREFETCH) ] = {
 873                 [ C(RESULT_ACCESS) ] = 0x0,
 874                 [ C(RESULT_MISS)   ] = 0x0,
 875         },
 876  },
 877  [ C(ITLB) ] = {
 878         [ C(OP_READ) ] = {
 879                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 880                 [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
 881         },
 882         [ C(OP_WRITE) ] = {
 883                 [ C(RESULT_ACCESS) ] = -1,
 884                 [ C(RESULT_MISS)   ] = -1,
 885         },
 886         [ C(OP_PREFETCH) ] = {
 887                 [ C(RESULT_ACCESS) ] = -1,
 888                 [ C(RESULT_MISS)   ] = -1,
 889         },
 890  },
 891  [ C(BPU ) ] = {
 892         [ C(OP_READ) ] = {
 893                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 894                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 895         },
 896         [ C(OP_WRITE) ] = {
 897                 [ C(RESULT_ACCESS) ] = -1,
 898                 [ C(RESULT_MISS)   ] = -1,
 899         },
 900         [ C(OP_PREFETCH) ] = {
 901                 [ C(RESULT_ACCESS) ] = -1,
 902                 [ C(RESULT_MISS)   ] = -1,
 903         },
 904  },
 905  [ C(NODE) ] = {
 906         [ C(OP_READ) ] = {
 907                 [ C(RESULT_ACCESS) ] = 0x01b7,
 908                 [ C(RESULT_MISS)   ] = 0x01b7,
 909         },
 910         [ C(OP_WRITE) ] = {
 911                 [ C(RESULT_ACCESS) ] = 0x01b7,
 912                 [ C(RESULT_MISS)   ] = 0x01b7,
 913         },
 914         [ C(OP_PREFETCH) ] = {
 915                 [ C(RESULT_ACCESS) ] = 0x01b7,
 916                 [ C(RESULT_MISS)   ] = 0x01b7,
 917         },
 918  },
 919 };
 920
 921 static __initconst const u64 core2_hw_cache_event_ids
 922                                 [PERF_COUNT_HW_CACHE_MAX]
 923                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 924                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 925 {
 926  [ C(L1D) ] = {
 927         [ C(OP_READ) ] = {
 928                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
 929                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
 930         },
 931         [ C(OP_WRITE) ] = {
 932                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
 933                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
 934         },
 935         [ C(OP_PREFETCH) ] = {
 936                 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
 937                 [ C(RESULT_MISS)   ] = 0,
 938         },
 939  },
 940  [ C(L1I ) ] = {
 941         [ C(OP_READ) ] = {
 942                 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
 943                 [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
 944         },
 945         [ C(OP_WRITE) ] = {
 946                 [ C(RESULT_ACCESS) ] = -1,
 947                 [ C(RESULT_MISS)   ] = -1,
 948         },
 949         [ C(OP_PREFETCH) ] = {
 950                 [ C(RESULT_ACCESS) ] = 0,
 951                 [ C(RESULT_MISS)   ] = 0,
 952         },
 953  },
 954  [ C(LL  ) ] = {
 955         [ C(OP_READ) ] = {
 956                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
 957                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
 958         },
 959         [ C(OP_WRITE) ] = {
 960                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
 961                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
 962         },
 963         [ C(OP_PREFETCH) ] = {
 964                 [ C(RESULT_ACCESS) ] = 0,
 965                 [ C(RESULT_MISS)   ] = 0,
 966         },
 967  },
 968  [ C(DTLB) ] = {
 969         [ C(OP_READ) ] = {
 970                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
 971                 [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
 972         },
 973         [ C(OP_WRITE) ] = {
 974                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
 975                 [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
 976         },
 977         [ C(OP_PREFETCH) ] = {
 978                 [ C(RESULT_ACCESS) ] = 0,
 979                 [ C(RESULT_MISS)   ] = 0,
 980         },
 981  },
 982  [ C(ITLB) ] = {
 983         [ C(OP_READ) ] = {
 984                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
 985                 [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
 986         },
 987         [ C(OP_WRITE) ] = {
 988                 [ C(RESULT_ACCESS) ] = -1,
 989                 [ C(RESULT_MISS)   ] = -1,
 990         },
 991         [ C(OP_PREFETCH) ] = {
 992                 [ C(RESULT_ACCESS) ] = -1,
 993                 [ C(RESULT_MISS)   ] = -1,
 994         },
 995  },
 996  [ C(BPU ) ] = {
 997         [ C(OP_READ) ] = {
 998                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
 999                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
1000         },
1001         [ C(OP_WRITE) ] = {
1002                 [ C(RESULT_ACCESS) ] = -1,
1003                 [ C(RESULT_MISS)   ] = -1,
1004         },
1005         [ C(OP_PREFETCH) ] = {
1006                 [ C(RESULT_ACCESS) ] = -1,
1007                 [ C(RESULT_MISS)   ] = -1,
1008         },
1009  },
1010 };
1011
1012 static __initconst const u64 atom_hw_cache_event_ids
1013                                 [PERF_COUNT_HW_CACHE_MAX]
1014                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1015                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1016 {
1017  [ C(L1D) ] = {
1018         [ C(OP_READ) ] = {
1019                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
1020                 [ C(RESULT_MISS)   ] = 0,
1021         },
1022         [ C(OP_WRITE) ] = {
1023                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
1024                 [ C(RESULT_MISS)   ] = 0,
1025         },
1026         [ C(OP_PREFETCH) ] = {
1027                 [ C(RESULT_ACCESS) ] = 0x0,
1028                 [ C(RESULT_MISS)   ] = 0,
1029         },
1030  },
1031  [ C(L1I ) ] = {
1032         [ C(OP_READ) ] = {
1033                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
1034                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
1035         },
1036         [ C(OP_WRITE) ] = {
1037                 [ C(RESULT_ACCESS) ] = -1,
1038                 [ C(RESULT_MISS)   ] = -1,
1039         },
1040         [ C(OP_PREFETCH) ] = {
1041                 [ C(RESULT_ACCESS) ] = 0,
1042                 [ C(RESULT_MISS)   ] = 0,
1043         },
1044  },
1045  [ C(LL  ) ] = {
1046         [ C(OP_READ) ] = {
1047                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
1048                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
1049         },
1050         [ C(OP_WRITE) ] = {
1051                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
1052                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
1053         },
1054         [ C(OP_PREFETCH) ] = {
1055                 [ C(RESULT_ACCESS) ] = 0,
1056                 [ C(RESULT_MISS)   ] = 0,
1057         },
1058  },
1059  [ C(DTLB) ] = {
1060         [ C(OP_READ) ] = {
1061                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
1062                 [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
1063         },
1064         [ C(OP_WRITE) ] = {
1065                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
1066                 [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
1067         },
1068         [ C(OP_PREFETCH) ] = {
1069                 [ C(RESULT_ACCESS) ] = 0,
1070                 [ C(RESULT_MISS)   ] = 0,
1071         },
1072  },
1073  [ C(ITLB) ] = {
1074         [ C(OP_READ) ] = {
1075                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
1076                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
1077         },
1078         [ C(OP_WRITE) ] = {
1079                 [ C(RESULT_ACCESS) ] = -1,
1080                 [ C(RESULT_MISS)   ] = -1,
1081         },
1082         [ C(OP_PREFETCH) ] = {
1083                 [ C(RESULT_ACCESS) ] = -1,
1084                 [ C(RESULT_MISS)   ] = -1,
1085         },
1086  },
1087  [ C(BPU ) ] = {
1088         [ C(OP_READ) ] = {
1089                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
1090                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
1091         },
1092         [ C(OP_WRITE) ] = {
1093                 [ C(RESULT_ACCESS) ] = -1,
1094                 [ C(RESULT_MISS)   ] = -1,
1095         },
1096         [ C(OP_PREFETCH) ] = {
1097                 [ C(RESULT_ACCESS) ] = -1,
1098                 [ C(RESULT_MISS)   ] = -1,
1099         },
1100  },
1101 };
1102
1103 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1104 {
1105         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1106         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1107         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x768005ffffull, RSP_1),
1108         EVENT_EXTRA_END
1109 };
1110
1111 #define SLM_DMND_READ           SNB_DMND_DATA_RD
1112 #define SLM_DMND_WRITE          SNB_DMND_RFO
1113 #define SLM_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
1114
1115 #define SLM_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1116 #define SLM_LLC_ACCESS          SNB_RESP_ANY
1117 #define SLM_LLC_MISS            (SLM_SNP_ANY|SNB_NON_DRAM)
1118
1119 static __initconst const u64 slm_hw_cache_extra_regs
1120                                 [PERF_COUNT_HW_CACHE_MAX]
1121                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1122                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1123 {
1124  [ C(LL  ) ] = {
1125         [ C(OP_READ) ] = {
1126                 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1127                 [ C(RESULT_MISS)   ] = SLM_DMND_READ|SLM_LLC_MISS,
1128         },
1129         [ C(OP_WRITE) ] = {
1130                 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1131                 [ C(RESULT_MISS)   ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1132         },
1133         [ C(OP_PREFETCH) ] = {
1134                 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1135                 [ C(RESULT_MISS)   ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1136         },
1137  },
1138 };
1139
1140 static __initconst const u64 slm_hw_cache_event_ids
1141                                 [PERF_COUNT_HW_CACHE_MAX]
1142                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1143                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1144 {
1145  [ C(L1D) ] = {
1146         [ C(OP_READ) ] = {
1147                 [ C(RESULT_ACCESS) ] = 0,
1148                 [ C(RESULT_MISS)   ] = 0x0104, /* LD_DCU_MISS */
1149         },
1150         [ C(OP_WRITE) ] = {
1151                 [ C(RESULT_ACCESS) ] = 0,
1152                 [ C(RESULT_MISS)   ] = 0,
1153         },
1154         [ C(OP_PREFETCH) ] = {
1155                 [ C(RESULT_ACCESS) ] = 0,
1156                 [ C(RESULT_MISS)   ] = 0,
1157         },
1158  },
1159  [ C(L1I ) ] = {
1160         [ C(OP_READ) ] = {
1161                 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1162                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACGE.MISSES */
1163         },
1164         [ C(OP_WRITE) ] = {
1165                 [ C(RESULT_ACCESS) ] = -1,
1166                 [ C(RESULT_MISS)   ] = -1,
1167         },
1168         [ C(OP_PREFETCH) ] = {
1169                 [ C(RESULT_ACCESS) ] = 0,
1170                 [ C(RESULT_MISS)   ] = 0,
1171         },
1172  },
1173  [ C(LL  ) ] = {
1174         [ C(OP_READ) ] = {
1175                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1176                 [ C(RESULT_ACCESS) ] = 0x01b7,
1177                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1178                 [ C(RESULT_MISS)   ] = 0x01b7,
1179         },
1180         [ C(OP_WRITE) ] = {
1181                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1182                 [ C(RESULT_ACCESS) ] = 0x01b7,
1183                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1184                 [ C(RESULT_MISS)   ] = 0x01b7,
1185         },
1186         [ C(OP_PREFETCH) ] = {
1187                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1188                 [ C(RESULT_ACCESS) ] = 0x01b7,
1189                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1190                 [ C(RESULT_MISS)   ] = 0x01b7,
1191         },
1192  },
1193  [ C(DTLB) ] = {
1194         [ C(OP_READ) ] = {
1195                 [ C(RESULT_ACCESS) ] = 0,
1196                 [ C(RESULT_MISS)   ] = 0x0804, /* LD_DTLB_MISS */
1197         },
1198         [ C(OP_WRITE) ] = {
1199                 [ C(RESULT_ACCESS) ] = 0,
1200                 [ C(RESULT_MISS)   ] = 0,
1201         },
1202         [ C(OP_PREFETCH) ] = {
1203                 [ C(RESULT_ACCESS) ] = 0,
1204                 [ C(RESULT_MISS)   ] = 0,
1205         },
1206  },
1207  [ C(ITLB) ] = {
1208         [ C(OP_READ) ] = {
1209                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1210                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES */
1211         },
1212         [ C(OP_WRITE) ] = {
1213                 [ C(RESULT_ACCESS) ] = -1,
1214                 [ C(RESULT_MISS)   ] = -1,
1215         },
1216         [ C(OP_PREFETCH) ] = {
1217                 [ C(RESULT_ACCESS) ] = -1,
1218                 [ C(RESULT_MISS)   ] = -1,
1219         },
1220  },
1221  [ C(BPU ) ] = {
1222         [ C(OP_READ) ] = {
1223                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1224                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1225         },
1226         [ C(OP_WRITE) ] = {
1227                 [ C(RESULT_ACCESS) ] = -1,
1228                 [ C(RESULT_MISS)   ] = -1,
1229         },
1230         [ C(OP_PREFETCH) ] = {
1231                 [ C(RESULT_ACCESS) ] = -1,
1232                 [ C(RESULT_MISS)   ] = -1,
1233         },
1234  },
1235 };
1236
1237 static void intel_pmu_disable_all(void)
1238 {
1239         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1240
1241         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1242
1243         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1244                 intel_pmu_disable_bts();
1245
1246         intel_pmu_pebs_disable_all();
1247         intel_pmu_lbr_disable_all();
1248 }
1249
1250 static void intel_pmu_enable_all(int added)
1251 {
1252         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1253
1254         intel_pmu_pebs_enable_all();
1255         intel_pmu_lbr_enable_all();
1256         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1257                         x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1258
1259         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1260                 struct perf_event *event =
1261                         cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1262
1263                 if (WARN_ON_ONCE(!event))
1264                         return;
1265
1266                 intel_pmu_enable_bts(event->hw.config);
1267         }
1268 }
1269
1270 /*
1271  * Workaround for:
1272  *   Intel Errata AAK100 (model 26)
1273  *   Intel Errata AAP53  (model 30)
1274  *   Intel Errata BD53   (model 44)
1275  *
1276  * The official story:
1277  *   These chips need to be 'reset' when adding counters by programming the
1278  *   magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1279  *   in sequence on the same PMC or on different PMCs.
1280  *
1281  * In practise it appears some of these events do in fact count, and
1282  * we need to programm all 4 events.
1283  */
1284 static void intel_pmu_nhm_workaround(void)
1285 {
1286         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1287         static const unsigned long nhm_magic[4] = {
1288                 0x4300B5,
1289                 0x4300D2,
1290                 0x4300B1,
1291                 0x4300B1
1292         };
1293         struct perf_event *event;
1294         int i;
1295
1296         /*
1297          * The Errata requires below steps:
1298          * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1299          * 2) Configure 4 PERFEVTSELx with the magic events and clear
1300          *    the corresponding PMCx;
1301          * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1302          * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1303          * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1304          */
1305
1306         /*
1307          * The real steps we choose are a little different from above.
1308          * A) To reduce MSR operations, we don't run step 1) as they
1309          *    are already cleared before this function is called;
1310          * B) Call x86_perf_event_update to save PMCx before configuring
1311          *    PERFEVTSELx with magic number;
1312          * C) With step 5), we do clear only when the PERFEVTSELx is
1313          *    not used currently.
1314          * D) Call x86_perf_event_set_period to restore PMCx;
1315          */
1316
1317         /* We always operate 4 pairs of PERF Counters */
1318         for (i = 0; i < 4; i++) {
1319                 event = cpuc->events[i];
1320                 if (event)
1321                         x86_perf_event_update(event);
1322         }
1323
1324         for (i = 0; i < 4; i++) {
1325                 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1326                 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1327         }
1328
1329         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1330         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
1331
1332         for (i = 0; i < 4; i++) {
1333                 event = cpuc->events[i];
1334
1335                 if (event) {
1336                         x86_perf_event_set_period(event);
1337                         __x86_pmu_enable_event(&event->hw,
1338                                         ARCH_PERFMON_EVENTSEL_ENABLE);
1339                 } else
1340                         wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
1341         }
1342 }
1343
1344 static void intel_pmu_nhm_enable_all(int added)
1345 {
1346         if (added)
1347                 intel_pmu_nhm_workaround();
1348         intel_pmu_enable_all(added);
1349 }
1350
1351 static inline u64 intel_pmu_get_status(void)
1352 {
1353         u64 status;
1354
1355         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1356
1357         return status;
1358 }
1359
1360 static inline void intel_pmu_ack_status(u64 ack)
1361 {
1362         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1363 }
1364
1365 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
1366 {
1367         int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1368         u64 ctrl_val, mask;
1369
1370         mask = 0xfULL << (idx * 4);
1371
1372         rdmsrl(hwc->config_base, ctrl_val);
1373         ctrl_val &= ~mask;
1374         wrmsrl(hwc->config_base, ctrl_val);
1375 }
1376
1377 static inline bool event_is_checkpointed(struct perf_event *event)
1378 {
1379         return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1380 }
1381
1382 static void intel_pmu_disable_event(struct perf_event *event)
1383 {
1384         struct hw_perf_event *hwc = &event->hw;
1385         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1386
1387         if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1388                 intel_pmu_disable_bts();
1389                 intel_pmu_drain_bts_buffer();
1390                 return;
1391         }
1392
1393         cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1394         cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1395         cpuc->intel_cp_status &= ~(1ull << hwc->idx);
1396
1397         /*
1398          * must disable before any actual event
1399          * because any event may be combined with LBR
1400          */
1401         if (needs_branch_stack(event))
1402                 intel_pmu_lbr_disable(event);
1403
1404         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1405                 intel_pmu_disable_fixed(hwc);
1406                 return;
1407         }
1408
1409         x86_pmu_disable_event(event);
1410
1411         if (unlikely(event->attr.precise_ip))
1412                 intel_pmu_pebs_disable(event);
1413 }
1414
1415 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
1416 {
1417         int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1418         u64 ctrl_val, bits, mask;
1419
1420         /*
1421          * Enable IRQ generation (0x8),
1422          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1423          * if requested:
1424          */
1425         bits = 0x8ULL;
1426         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1427                 bits |= 0x2;
1428         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1429                 bits |= 0x1;
1430
1431         /*
1432          * ANY bit is supported in v3 and up
1433          */
1434         if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1435                 bits |= 0x4;
1436
1437         bits <<= (idx * 4);
1438         mask = 0xfULL << (idx * 4);
1439
1440         rdmsrl(hwc->config_base, ctrl_val);
1441         ctrl_val &= ~mask;
1442         ctrl_val |= bits;
1443         wrmsrl(hwc->config_base, ctrl_val);
1444 }
1445
1446 static void intel_pmu_enable_event(struct perf_event *event)
1447 {
1448         struct hw_perf_event *hwc = &event->hw;
1449         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1450
1451         if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1452                 if (!__this_cpu_read(cpu_hw_events.enabled))
1453                         return;
1454
1455                 intel_pmu_enable_bts(hwc->config);
1456                 return;
1457         }
1458         /*
1459          * must enabled before any actual event
1460          * because any event may be combined with LBR
1461          */
1462         if (needs_branch_stack(event))
1463                 intel_pmu_lbr_enable(event);
1464
1465         if (event->attr.exclude_host)
1466                 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1467         if (event->attr.exclude_guest)
1468                 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1469
1470         if (unlikely(event_is_checkpointed(event)))
1471                 cpuc->intel_cp_status |= (1ull << hwc->idx);
1472
1473         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1474                 intel_pmu_enable_fixed(hwc);
1475                 return;
1476         }
1477
1478         if (unlikely(event->attr.precise_ip))
1479                 intel_pmu_pebs_enable(event);
1480
1481         __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1482 }
1483
1484 /*
1485  * Save and restart an expired event. Called by NMI contexts,
1486  * so it has to be careful about preempting normal event ops:
1487  */
1488 int intel_pmu_save_and_restart(struct perf_event *event)
1489 {
1490         x86_perf_event_update(event);
1491         /*
1492          * For a checkpointed counter always reset back to 0.  This
1493          * avoids a situation where the counter overflows, aborts the
1494          * transaction and is then set back to shortly before the
1495          * overflow, and overflows and aborts again.
1496          */
1497         if (unlikely(event_is_checkpointed(event))) {
1498                 /* No race with NMIs because the counter should not be armed */
1499                 wrmsrl(event->hw.event_base, 0);
1500                 local64_set(&event->hw.prev_count, 0);
1501         }
1502         return x86_perf_event_set_period(event);
1503 }
1504
1505 static void intel_pmu_reset(void)
1506 {
1507         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1508         unsigned long flags;
1509         int idx;
1510
1511         if (!x86_pmu.num_counters)
1512                 return;
1513
1514         local_irq_save(flags);
1515
1516         pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
1517
1518         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1519                 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1520                 wrmsrl_safe(x86_pmu_event_addr(idx),  0ull);
1521         }
1522         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
1523                 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1524
1525         if (ds)
1526                 ds->bts_index = ds->bts_buffer_base;
1527
1528         local_irq_restore(flags);
1529 }
1530
1531 /*
1532  * This handler is triggered by the local APIC, so the APIC IRQ handling
1533  * rules apply:
1534  */
1535 static int intel_pmu_handle_irq(struct pt_regs *regs)
1536 {
1537         struct perf_sample_data data;
1538         struct cpu_hw_events *cpuc;
1539         int bit, loops;
1540         u64 status;
1541         int handled;
1542
1543         cpuc = this_cpu_ptr(&cpu_hw_events);
1544
1545         /*
1546          * No known reason to not always do late ACK,
1547          * but just in case do it opt-in.
1548          */
1549         if (!x86_pmu.late_ack)
1550                 apic_write(APIC_LVTPC, APIC_DM_NMI);
1551         intel_pmu_disable_all();
1552         handled = intel_pmu_drain_bts_buffer();
1553         status = intel_pmu_get_status();
1554         if (!status)
1555                 goto done;
1556
1557         loops = 0;
1558 again:
1559         intel_pmu_ack_status(status);
1560         if (++loops > 100) {
1561                 static bool warned = false;
1562                 if (!warned) {
1563                         WARN(1, "perfevents: irq loop stuck!\n");
1564                         perf_event_print_debug();
1565                         warned = true;
1566                 }
1567                 intel_pmu_reset();
1568                 goto done;
1569         }
1570
1571         inc_irq_stat(apic_perf_irqs);
1572
1573         intel_pmu_lbr_read();
1574
1575         /*
1576          * CondChgd bit 63 doesn't mean any overflow status. Ignore
1577          * and clear the bit.
1578          */
1579         if (__test_and_clear_bit(63, (unsigned long *)&status)) {
1580                 if (!status)
1581                         goto done;
1582         }
1583
1584         /*
1585          * PEBS overflow sets bit 62 in the global status register
1586          */
1587         if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1588                 handled++;
1589                 x86_pmu.drain_pebs(regs);
1590         }
1591
1592         /*
1593          * Checkpointed counters can lead to 'spurious' PMIs because the
1594          * rollback caused by the PMI will have cleared the overflow status
1595          * bit. Therefore always force probe these counters.
1596          */
1597         status |= cpuc->intel_cp_status;
1598
1599         for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1600                 struct perf_event *event = cpuc->events[bit];
1601
1602                 handled++;
1603
1604                 if (!test_bit(bit, cpuc->active_mask))
1605                         continue;
1606
1607                 if (!intel_pmu_save_and_restart(event))
1608                         continue;
1609
1610                 perf_sample_data_init(&data, 0, event->hw.last_period);
1611
1612                 if (has_branch_stack(event))
1613                         data.br_stack = &cpuc->lbr_stack;
1614
1615                 if (perf_event_overflow(event, &data, regs))
1616                         x86_pmu_stop(event, 0);
1617         }
1618
1619         /*
1620          * Repeat if there is more work to be done:
1621          */
1622         status = intel_pmu_get_status();
1623         if (status)
1624                 goto again;
1625
1626 done:
1627         intel_pmu_enable_all(0);
1628         /*
1629          * Only unmask the NMI after the overflow counters
1630          * have been reset. This avoids spurious NMIs on
1631          * Haswell CPUs.
1632          */
1633         if (x86_pmu.late_ack)
1634                 apic_write(APIC_LVTPC, APIC_DM_NMI);
1635         return handled;
1636 }
1637
1638 static struct event_constraint *
1639 intel_bts_constraints(struct perf_event *event)
1640 {
1641         struct hw_perf_event *hwc = &event->hw;
1642         unsigned int hw_event, bts_event;
1643
1644         if (event->attr.freq)
1645                 return NULL;
1646
1647         hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1648         bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1649
1650         if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
1651                 return &bts_constraint;
1652
1653         return NULL;
1654 }
1655
1656 static int intel_alt_er(int idx)
1657 {
1658         if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
1659                 return idx;
1660
1661         if (idx == EXTRA_REG_RSP_0)
1662                 return EXTRA_REG_RSP_1;
1663
1664         if (idx == EXTRA_REG_RSP_1)
1665                 return EXTRA_REG_RSP_0;
1666
1667         return idx;
1668 }
1669
1670 static void intel_fixup_er(struct perf_event *event, int idx)
1671 {
1672         event->hw.extra_reg.idx = idx;
1673
1674         if (idx == EXTRA_REG_RSP_0) {
1675                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1676                 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
1677                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1678         } else if (idx == EXTRA_REG_RSP_1) {
1679                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1680                 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
1681                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1682         }
1683 }
1684
1685 /*
1686  * manage allocation of shared extra msr for certain events
1687  *
1688  * sharing can be:
1689  * per-cpu: to be shared between the various events on a single PMU
1690  * per-core: per-cpu + shared by HT threads
1691  */
1692 static struct event_constraint *
1693 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
1694                                    struct perf_event *event,
1695                                    struct hw_perf_event_extra *reg)
1696 {
1697         struct event_constraint *c = &emptyconstraint;
1698         struct er_account *era;
1699         unsigned long flags;
1700         int idx = reg->idx;
1701
1702         /*
1703          * reg->alloc can be set due to existing state, so for fake cpuc we
1704          * need to ignore this, otherwise we might fail to allocate proper fake
1705          * state for this extra reg constraint. Also see the comment below.
1706          */
1707         if (reg->alloc && !cpuc->is_fake)
1708                 return NULL; /* call x86_get_event_constraint() */
1709
1710 again:
1711         era = &cpuc->shared_regs->regs[idx];
1712         /*
1713          * we use spin_lock_irqsave() to avoid lockdep issues when
1714          * passing a fake cpuc
1715          */
1716         raw_spin_lock_irqsave(&era->lock, flags);
1717
1718         if (!atomic_read(&era->ref) || era->config == reg->config) {
1719
1720                 /*
1721                  * If its a fake cpuc -- as per validate_{group,event}() we
1722                  * shouldn't touch event state and we can avoid doing so
1723                  * since both will only call get_event_constraints() once
1724                  * on each event, this avoids the need for reg->alloc.
1725                  *
1726                  * Not doing the ER fixup will only result in era->reg being
1727                  * wrong, but since we won't actually try and program hardware
1728                  * this isn't a problem either.
1729                  */
1730                 if (!cpuc->is_fake) {
1731                         if (idx != reg->idx)
1732                                 intel_fixup_er(event, idx);
1733
1734                         /*
1735                          * x86_schedule_events() can call get_event_constraints()
1736                          * multiple times on events in the case of incremental
1737                          * scheduling(). reg->alloc ensures we only do the ER
1738                          * allocation once.
1739                          */
1740                         reg->alloc = 1;
1741                 }
1742
1743                 /* lock in msr value */
1744                 era->config = reg->config;
1745                 era->reg = reg->reg;
1746
1747                 /* one more user */
1748                 atomic_inc(&era->ref);
1749
1750                 /*
1751                  * need to call x86_get_event_constraint()
1752                  * to check if associated event has constraints
1753                  */
1754                 c = NULL;
1755         } else {
1756                 idx = intel_alt_er(idx);
1757                 if (idx != reg->idx) {
1758                         raw_spin_unlock_irqrestore(&era->lock, flags);
1759                         goto again;
1760                 }
1761         }
1762         raw_spin_unlock_irqrestore(&era->lock, flags);
1763
1764         return c;
1765 }
1766
1767 static void
1768 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1769                                    struct hw_perf_event_extra *reg)
1770 {
1771         struct er_account *era;
1772
1773         /*
1774          * Only put constraint if extra reg was actually allocated. Also takes
1775          * care of event which do not use an extra shared reg.
1776          *
1777          * Also, if this is a fake cpuc we shouldn't touch any event state
1778          * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1779          * either since it'll be thrown out.
1780          */
1781         if (!reg->alloc || cpuc->is_fake)
1782                 return;
1783
1784         era = &cpuc->shared_regs->regs[reg->idx];
1785
1786         /* one fewer user */
1787         atomic_dec(&era->ref);
1788
1789         /* allocate again next time */
1790         reg->alloc = 0;
1791 }
1792
1793 static struct event_constraint *
1794 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1795                               struct perf_event *event)
1796 {
1797         struct event_constraint *c = NULL, *d;
1798         struct hw_perf_event_extra *xreg, *breg;
1799
1800         xreg = &event->hw.extra_reg;
1801         if (xreg->idx != EXTRA_REG_NONE) {
1802                 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1803                 if (c == &emptyconstraint)
1804                         return c;
1805         }
1806         breg = &event->hw.branch_reg;
1807         if (breg->idx != EXTRA_REG_NONE) {
1808                 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1809                 if (d == &emptyconstraint) {
1810                         __intel_shared_reg_put_constraints(cpuc, xreg);
1811                         c = d;
1812                 }
1813         }
1814         return c;
1815 }
1816
1817 struct event_constraint *
1818 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1819 {
1820         struct event_constraint *c;
1821
1822         if (x86_pmu.event_constraints) {
1823                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1824                         if ((event->hw.config & c->cmask) == c->code) {
1825                                 event->hw.flags |= c->flags;
1826                                 return c;
1827                         }
1828                 }
1829         }
1830
1831         return &unconstrained;
1832 }
1833
1834 static struct event_constraint *
1835 intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1836 {
1837         struct event_constraint *c;
1838
1839         c = intel_bts_constraints(event);
1840         if (c)
1841                 return c;
1842
1843         c = intel_pebs_constraints(event);
1844         if (c)
1845                 return c;
1846
1847         c = intel_shared_regs_constraints(cpuc, event);
1848         if (c)
1849                 return c;
1850
1851         return x86_get_event_constraints(cpuc, event);
1852 }
1853
1854 static void
1855 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
1856                                         struct perf_event *event)
1857 {
1858         struct hw_perf_event_extra *reg;
1859
1860         reg = &event->hw.extra_reg;
1861         if (reg->idx != EXTRA_REG_NONE)
1862                 __intel_shared_reg_put_constraints(cpuc, reg);
1863
1864         reg = &event->hw.branch_reg;
1865         if (reg->idx != EXTRA_REG_NONE)
1866                 __intel_shared_reg_put_constraints(cpuc, reg);
1867 }
1868
1869 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1870                                         struct perf_event *event)
1871 {
1872         intel_put_shared_regs_event_constraints(cpuc, event);
1873 }
1874
1875 static void intel_pebs_aliases_core2(struct perf_event *event)
1876 {
1877         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1878                 /*
1879                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1880                  * (0x003c) so that we can use it with PEBS.
1881                  *
1882                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1883                  * PEBS capable. However we can use INST_RETIRED.ANY_P
1884                  * (0x00c0), which is a PEBS capable event, to get the same
1885                  * count.
1886                  *
1887                  * INST_RETIRED.ANY_P counts the number of cycles that retires
1888                  * CNTMASK instructions. By setting CNTMASK to a value (16)
1889                  * larger than the maximum number of instructions that can be
1890                  * retired per cycle (4) and then inverting the condition, we
1891                  * count all cycles that retire 16 or less instructions, which
1892                  * is every cycle.
1893                  *
1894                  * Thereby we gain a PEBS capable cycle counter.
1895                  */
1896                 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
1897
1898                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1899                 event->hw.config = alt_config;
1900         }
1901 }
1902
1903 static void intel_pebs_aliases_snb(struct perf_event *event)
1904 {
1905         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1906                 /*
1907                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1908                  * (0x003c) so that we can use it with PEBS.
1909                  *
1910                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1911                  * PEBS capable. However we can use UOPS_RETIRED.ALL
1912                  * (0x01c2), which is a PEBS capable event, to get the same
1913                  * count.
1914                  *
1915                  * UOPS_RETIRED.ALL counts the number of cycles that retires
1916                  * CNTMASK micro-ops. By setting CNTMASK to a value (16)
1917                  * larger than the maximum number of micro-ops that can be
1918                  * retired per cycle (4) and then inverting the condition, we
1919                  * count all cycles that retire 16 or less micro-ops, which
1920                  * is every cycle.
1921                  *
1922                  * Thereby we gain a PEBS capable cycle counter.
1923                  */
1924                 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
1925
1926                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1927                 event->hw.config = alt_config;
1928         }
1929 }
1930
1931 static int intel_pmu_hw_config(struct perf_event *event)
1932 {
1933         int ret = x86_pmu_hw_config(event);
1934
1935         if (ret)
1936                 return ret;
1937
1938         if (event->attr.precise_ip && x86_pmu.pebs_aliases)
1939                 x86_pmu.pebs_aliases(event);
1940
1941         if (needs_branch_stack(event)) {
1942                 ret = intel_pmu_setup_lbr_filter(event);
1943                 if (ret)
1944                         return ret;
1945
1946                 /*
1947                  * BTS is set up earlier in this path, so don't account twice
1948                  */
1949                 if (!intel_pmu_has_bts(event)) {
1950                         /* disallow lbr if conflicting events are present */
1951                         if (x86_add_exclusive(x86_lbr_exclusive_lbr))
1952                                 return -EBUSY;
1953
1954                         event->destroy = hw_perf_lbr_event_destroy;
1955                 }
1956         }
1957
1958         if (event->attr.type != PERF_TYPE_RAW)
1959                 return 0;
1960
1961         if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1962                 return 0;
1963
1964         if (x86_pmu.version < 3)
1965                 return -EINVAL;
1966
1967         if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1968                 return -EACCES;
1969
1970         event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1971
1972         return 0;
1973 }
1974
1975 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1976 {
1977         if (x86_pmu.guest_get_msrs)
1978                 return x86_pmu.guest_get_msrs(nr);
1979         *nr = 0;
1980         return NULL;
1981 }
1982 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1983
1984 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1985 {
1986         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1987         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1988
1989         arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1990         arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1991         arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
1992         /*
1993          * If PMU counter has PEBS enabled it is not enough to disable counter
1994          * on a guest entry since PEBS memory write can overshoot guest entry
1995          * and corrupt guest memory. Disabling PEBS solves the problem.
1996          */
1997         arr[1].msr = MSR_IA32_PEBS_ENABLE;
1998         arr[1].host = cpuc->pebs_enabled;
1999         arr[1].guest = 0;
2000
2001         *nr = 2;
2002         return arr;
2003 }
2004
2005 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
2006 {
2007         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2008         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2009         int idx;
2010
2011         for (idx = 0; idx < x86_pmu.num_counters; idx++)  {
2012                 struct perf_event *event = cpuc->events[idx];
2013
2014                 arr[idx].msr = x86_pmu_config_addr(idx);
2015                 arr[idx].host = arr[idx].guest = 0;
2016
2017                 if (!test_bit(idx, cpuc->active_mask))
2018                         continue;
2019
2020                 arr[idx].host = arr[idx].guest =
2021                         event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
2022
2023                 if (event->attr.exclude_host)
2024                         arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2025                 else if (event->attr.exclude_guest)
2026                         arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2027         }
2028
2029         *nr = x86_pmu.num_counters;
2030         return arr;
2031 }
2032
2033 static void core_pmu_enable_event(struct perf_event *event)
2034 {
2035         if (!event->attr.exclude_host)
2036                 x86_pmu_enable_event(event);
2037 }
2038
2039 static void core_pmu_enable_all(int added)
2040 {
2041         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2042         int idx;
2043
2044         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2045                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
2046
2047                 if (!test_bit(idx, cpuc->active_mask) ||
2048                                 cpuc->events[idx]->attr.exclude_host)
2049                         continue;
2050
2051                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2052         }
2053 }
2054
2055 static int hsw_hw_config(struct perf_event *event)
2056 {
2057         int ret = intel_pmu_hw_config(event);
2058
2059         if (ret)
2060                 return ret;
2061         if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
2062                 return 0;
2063         event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
2064
2065         /*
2066          * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2067          * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2068          * this combination.
2069          */
2070         if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
2071              ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
2072               event->attr.precise_ip > 0))
2073                 return -EOPNOTSUPP;
2074
2075         if (event_is_checkpointed(event)) {
2076                 /*
2077                  * Sampling of checkpointed events can cause situations where
2078                  * the CPU constantly aborts because of a overflow, which is
2079                  * then checkpointed back and ignored. Forbid checkpointing
2080                  * for sampling.
2081                  *
2082                  * But still allow a long sampling period, so that perf stat
2083                  * from KVM works.
2084                  */
2085                 if (event->attr.sample_period > 0 &&
2086                     event->attr.sample_period < 0x7fffffff)
2087                         return -EOPNOTSUPP;
2088         }
2089         return 0;
2090 }
2091
2092 static struct event_constraint counter2_constraint =
2093                         EVENT_CONSTRAINT(0, 0x4, 0);
2094
2095 static struct event_constraint *
2096 hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
2097 {
2098         struct event_constraint *c = intel_get_event_constraints(cpuc, event);
2099
2100         /* Handle special quirk on in_tx_checkpointed only in counter 2 */
2101         if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
2102                 if (c->idxmsk64 & (1U << 2))
2103                         return &counter2_constraint;
2104                 return &emptyconstraint;
2105         }
2106
2107         return c;
2108 }
2109
2110 /*
2111  * Broadwell:
2112  *
2113  * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
2114  * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
2115  * the two to enforce a minimum period of 128 (the smallest value that has bits
2116  * 0-5 cleared and >= 100).
2117  *
2118  * Because of how the code in x86_perf_event_set_period() works, the truncation
2119  * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
2120  * to make up for the 'lost' events due to carrying the 'error' in period_left.
2121  *
2122  * Therefore the effective (average) period matches the requested period,
2123  * despite coarser hardware granularity.
2124  */
2125 static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
2126 {
2127         if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
2128                         X86_CONFIG(.event=0xc0, .umask=0x01)) {
2129                 if (left < 128)
2130                         left = 128;
2131                 left &= ~0x3fu;
2132         }
2133         return left;
2134 }
2135
2136 PMU_FORMAT_ATTR(event,  "config:0-7"    );
2137 PMU_FORMAT_ATTR(umask,  "config:8-15"   );
2138 PMU_FORMAT_ATTR(edge,   "config:18"     );
2139 PMU_FORMAT_ATTR(pc,     "config:19"     );
2140 PMU_FORMAT_ATTR(any,    "config:21"     ); /* v3 + */
2141 PMU_FORMAT_ATTR(inv,    "config:23"     );
2142 PMU_FORMAT_ATTR(cmask,  "config:24-31"  );
2143 PMU_FORMAT_ATTR(in_tx,  "config:32");
2144 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
2145
2146 static struct attribute *intel_arch_formats_attr[] = {
2147         &format_attr_event.attr,
2148         &format_attr_umask.attr,
2149         &format_attr_edge.attr,
2150         &format_attr_pc.attr,
2151         &format_attr_inv.attr,
2152         &format_attr_cmask.attr,
2153         NULL,
2154 };
2155
2156 ssize_t intel_event_sysfs_show(char *page, u64 config)
2157 {
2158         u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
2159
2160         return x86_event_sysfs_show(page, config, event);
2161 }
2162
2163 static __initconst const struct x86_pmu core_pmu = {
2164         .name                   = "core",
2165         .handle_irq             = x86_pmu_handle_irq,
2166         .disable_all            = x86_pmu_disable_all,
2167         .enable_all             = core_pmu_enable_all,
2168         .enable                 = core_pmu_enable_event,
2169         .disable                = x86_pmu_disable_event,
2170         .hw_config              = x86_pmu_hw_config,
2171         .schedule_events        = x86_schedule_events,
2172         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
2173         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
2174         .event_map              = intel_pmu_event_map,
2175         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
2176         .apic                   = 1,
2177         /*
2178          * Intel PMCs cannot be accessed sanely above 32 bit width,
2179          * so we install an artificial 1<<31 period regardless of
2180          * the generic event period:
2181          */
2182         .max_period             = (1ULL << 31) - 1,
2183         .get_event_constraints  = intel_get_event_constraints,
2184         .put_event_constraints  = intel_put_event_constraints,
2185         .event_constraints      = intel_core_event_constraints,
2186         .guest_get_msrs         = core_guest_get_msrs,
2187         .format_attrs           = intel_arch_formats_attr,
2188         .events_sysfs_show      = intel_event_sysfs_show,
2189 };
2190
2191 struct intel_shared_regs *allocate_shared_regs(int cpu)
2192 {
2193         struct intel_shared_regs *regs;
2194         int i;
2195
2196         regs = kzalloc_node(sizeof(struct intel_shared_regs),
2197                             GFP_KERNEL, cpu_to_node(cpu));
2198         if (regs) {
2199                 /*
2200                  * initialize the locks to keep lockdep happy
2201                  */
2202                 for (i = 0; i < EXTRA_REG_MAX; i++)
2203                         raw_spin_lock_init(&regs->regs[i].lock);
2204
2205                 regs->core_id = -1;
2206         }
2207         return regs;
2208 }
2209
2210 static int intel_pmu_cpu_prepare(int cpu)
2211 {
2212         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2213
2214         if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
2215                 return NOTIFY_OK;
2216
2217         cpuc->shared_regs = allocate_shared_regs(cpu);
2218         if (!cpuc->shared_regs)
2219                 return NOTIFY_BAD;
2220
2221         return NOTIFY_OK;
2222 }
2223
2224 static void intel_pmu_cpu_starting(int cpu)
2225 {
2226         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2227         int core_id = topology_core_id(cpu);
2228         int i;
2229
2230         init_debug_store_on_cpu(cpu);
2231         /*
2232          * Deal with CPUs that don't clear their LBRs on power-up.
2233          */
2234         intel_pmu_lbr_reset();
2235
2236         cpuc->lbr_sel = NULL;
2237
2238         if (!cpuc->shared_regs)
2239                 return;
2240
2241         if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
2242                 for_each_cpu(i, topology_thread_cpumask(cpu)) {
2243                         struct intel_shared_regs *pc;
2244
2245                         pc = per_cpu(cpu_hw_events, i).shared_regs;
2246                         if (pc && pc->core_id == core_id) {
2247                                 cpuc->kfree_on_online = cpuc->shared_regs;
2248                                 cpuc->shared_regs = pc;
2249                                 break;
2250                         }
2251                 }
2252                 cpuc->shared_regs->core_id = core_id;
2253                 cpuc->shared_regs->refcnt++;
2254         }
2255
2256         if (x86_pmu.lbr_sel_map)
2257                 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
2258 }
2259
2260 static void intel_pmu_cpu_dying(int cpu)
2261 {
2262         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2263         struct intel_shared_regs *pc;
2264
2265         pc = cpuc->shared_regs;
2266         if (pc) {
2267                 if (pc->core_id == -1 || --pc->refcnt == 0)
2268                         kfree(pc);
2269                 cpuc->shared_regs = NULL;
2270         }
2271
2272         fini_debug_store_on_cpu(cpu);
2273 }
2274
2275 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
2276
2277 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
2278
2279 static struct attribute *intel_arch3_formats_attr[] = {
2280         &format_attr_event.attr,
2281         &format_attr_umask.attr,
2282         &format_attr_edge.attr,
2283         &format_attr_pc.attr,
2284         &format_attr_any.attr,
2285         &format_attr_inv.attr,
2286         &format_attr_cmask.attr,
2287         &format_attr_in_tx.attr,
2288         &format_attr_in_tx_cp.attr,
2289
2290         &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
2291         &format_attr_ldlat.attr, /* PEBS load latency */
2292         NULL,
2293 };
2294
2295 static __initconst const struct x86_pmu intel_pmu = {
2296         .name                   = "Intel",
2297         .handle_irq             = intel_pmu_handle_irq,
2298         .disable_all            = intel_pmu_disable_all,
2299         .enable_all             = intel_pmu_enable_all,
2300         .enable                 = intel_pmu_enable_event,
2301         .disable                = intel_pmu_disable_event,
2302         .hw_config              = intel_pmu_hw_config,
2303         .schedule_events        = x86_schedule_events,
2304         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
2305         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
2306         .event_map              = intel_pmu_event_map,
2307         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
2308         .apic                   = 1,
2309         /*
2310          * Intel PMCs cannot be accessed sanely above 32 bit width,
2311          * so we install an artificial 1<<31 period regardless of
2312          * the generic event period:
2313          */
2314         .max_period             = (1ULL << 31) - 1,
2315         .get_event_constraints  = intel_get_event_constraints,
2316         .put_event_constraints  = intel_put_event_constraints,
2317         .pebs_aliases           = intel_pebs_aliases_core2,
2318
2319         .format_attrs           = intel_arch3_formats_attr,
2320         .events_sysfs_show      = intel_event_sysfs_show,
2321
2322         .cpu_prepare            = intel_pmu_cpu_prepare,
2323         .cpu_starting           = intel_pmu_cpu_starting,
2324         .cpu_dying              = intel_pmu_cpu_dying,
2325         .guest_get_msrs         = intel_guest_get_msrs,
2326         .sched_task             = intel_pmu_lbr_sched_task,
2327 };
2328
2329 static __init void intel_clovertown_quirk(void)
2330 {
2331         /*
2332          * PEBS is unreliable due to:
2333          *
2334          *   AJ67  - PEBS may experience CPL leaks
2335          *   AJ68  - PEBS PMI may be delayed by one event
2336          *   AJ69  - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
2337          *   AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
2338          *
2339          * AJ67 could be worked around by restricting the OS/USR flags.
2340          * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
2341          *
2342          * AJ106 could possibly be worked around by not allowing LBR
2343          *       usage from PEBS, including the fixup.
2344          * AJ68  could possibly be worked around by always programming
2345          *       a pebs_event_reset[0] value and coping with the lost events.
2346          *
2347          * But taken together it might just make sense to not enable PEBS on
2348          * these chips.
2349          */
2350         pr_warn("PEBS disabled due to CPU errata\n");
2351         x86_pmu.pebs = 0;
2352         x86_pmu.pebs_constraints = NULL;
2353 }
2354
2355 static int intel_snb_pebs_broken(int cpu)
2356 {
2357         u32 rev = UINT_MAX; /* default to broken for unknown models */
2358
2359         switch (cpu_data(cpu).x86_model) {
2360         case 42: /* SNB */
2361                 rev = 0x28;
2362                 break;
2363
2364         case 45: /* SNB-EP */
2365                 switch (cpu_data(cpu).x86_mask) {
2366                 case 6: rev = 0x618; break;
2367                 case 7: rev = 0x70c; break;
2368                 }
2369         }
2370
2371         return (cpu_data(cpu).microcode < rev);
2372 }
2373
2374 static void intel_snb_check_microcode(void)
2375 {
2376         int pebs_broken = 0;
2377         int cpu;
2378
2379         get_online_cpus();
2380         for_each_online_cpu(cpu) {
2381                 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
2382                         break;
2383         }
2384         put_online_cpus();
2385
2386         if (pebs_broken == x86_pmu.pebs_broken)
2387                 return;
2388
2389         /*
2390          * Serialized by the microcode lock..
2391          */
2392         if (x86_pmu.pebs_broken) {
2393                 pr_info("PEBS enabled due to microcode update\n");
2394                 x86_pmu.pebs_broken = 0;
2395         } else {
2396                 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
2397                 x86_pmu.pebs_broken = 1;
2398         }
2399 }
2400
2401 /*
2402  * Under certain circumstances, access certain MSR may cause #GP.
2403  * The function tests if the input MSR can be safely accessed.
2404  */
2405 static bool check_msr(unsigned long msr, u64 mask)
2406 {
2407         u64 val_old, val_new, val_tmp;
2408
2409         /*
2410          * Read the current value, change it and read it back to see if it
2411          * matches, this is needed to detect certain hardware emulators
2412          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
2413          */
2414         if (rdmsrl_safe(msr, &val_old))
2415                 return false;
2416
2417         /*
2418          * Only change the bits which can be updated by wrmsrl.
2419          */
2420         val_tmp = val_old ^ mask;
2421         if (wrmsrl_safe(msr, val_tmp) ||
2422             rdmsrl_safe(msr, &val_new))
2423                 return false;
2424
2425         if (val_new != val_tmp)
2426                 return false;
2427
2428         /* Here it's sure that the MSR can be safely accessed.
2429          * Restore the old value and return.
2430          */
2431         wrmsrl(msr, val_old);
2432
2433         return true;
2434 }
2435
2436 static __init void intel_sandybridge_quirk(void)
2437 {
2438         x86_pmu.check_microcode = intel_snb_check_microcode;
2439         intel_snb_check_microcode();
2440 }
2441
2442 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
2443         { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
2444         { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
2445         { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
2446         { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
2447         { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
2448         { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
2449         { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
2450 };
2451
2452 static __init void intel_arch_events_quirk(void)
2453 {
2454         int bit;
2455
2456         /* disable event that reported as not presend by cpuid */
2457         for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
2458                 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
2459                 pr_warn("CPUID marked event: \'%s\' unavailable\n",
2460                         intel_arch_events_map[bit].name);
2461         }
2462 }
2463
2464 static __init void intel_nehalem_quirk(void)
2465 {
2466         union cpuid10_ebx ebx;
2467
2468         ebx.full = x86_pmu.events_maskl;
2469         if (ebx.split.no_branch_misses_retired) {
2470                 /*
2471                  * Erratum AAJ80 detected, we work it around by using
2472                  * the BR_MISP_EXEC.ANY event. This will over-count
2473                  * branch-misses, but it's still much better than the
2474                  * architectural event which is often completely bogus:
2475                  */
2476                 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
2477                 ebx.split.no_branch_misses_retired = 0;
2478                 x86_pmu.events_maskl = ebx.full;
2479                 pr_info("CPU erratum AAJ80 worked around\n");
2480         }
2481 }
2482
2483 EVENT_ATTR_STR(mem-loads,       mem_ld_hsw,     "event=0xcd,umask=0x1,ldlat=3");
2484 EVENT_ATTR_STR(mem-stores,      mem_st_hsw,     "event=0xd0,umask=0x82")
2485
2486 /* Haswell special events */
2487 EVENT_ATTR_STR(tx-start,        tx_start,       "event=0xc9,umask=0x1");
2488 EVENT_ATTR_STR(tx-commit,       tx_commit,      "event=0xc9,umask=0x2");
2489 EVENT_ATTR_STR(tx-abort,        tx_abort,       "event=0xc9,umask=0x4");
2490 EVENT_ATTR_STR(tx-capacity,     tx_capacity,    "event=0x54,umask=0x2");
2491 EVENT_ATTR_STR(tx-conflict,     tx_conflict,    "event=0x54,umask=0x1");
2492 EVENT_ATTR_STR(el-start,        el_start,       "event=0xc8,umask=0x1");
2493 EVENT_ATTR_STR(el-commit,       el_commit,      "event=0xc8,umask=0x2");
2494 EVENT_ATTR_STR(el-abort,        el_abort,       "event=0xc8,umask=0x4");
2495 EVENT_ATTR_STR(el-capacity,     el_capacity,    "event=0x54,umask=0x2");
2496 EVENT_ATTR_STR(el-conflict,     el_conflict,    "event=0x54,umask=0x1");
2497 EVENT_ATTR_STR(cycles-t,        cycles_t,       "event=0x3c,in_tx=1");
2498 EVENT_ATTR_STR(cycles-ct,       cycles_ct,      "event=0x3c,in_tx=1,in_tx_cp=1");
2499
2500 static struct attribute *hsw_events_attrs[] = {
2501         EVENT_PTR(tx_start),
2502         EVENT_PTR(tx_commit),
2503         EVENT_PTR(tx_abort),
2504         EVENT_PTR(tx_capacity),
2505         EVENT_PTR(tx_conflict),
2506         EVENT_PTR(el_start),
2507         EVENT_PTR(el_commit),
2508         EVENT_PTR(el_abort),
2509         EVENT_PTR(el_capacity),
2510         EVENT_PTR(el_conflict),
2511         EVENT_PTR(cycles_t),
2512         EVENT_PTR(cycles_ct),
2513         EVENT_PTR(mem_ld_hsw),
2514         EVENT_PTR(mem_st_hsw),
2515         NULL
2516 };
2517
2518 __init int intel_pmu_init(void)
2519 {
2520         union cpuid10_edx edx;
2521         union cpuid10_eax eax;
2522         union cpuid10_ebx ebx;
2523         struct event_constraint *c;
2524         unsigned int unused;
2525         struct extra_reg *er;
2526         int version, i;
2527
2528         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
2529                 switch (boot_cpu_data.x86) {
2530                 case 0x6:
2531                         return p6_pmu_init();
2532                 case 0xb:
2533                         return knc_pmu_init();
2534                 case 0xf:
2535                         return p4_pmu_init();
2536                 }
2537                 return -ENODEV;
2538         }
2539
2540         /*
2541          * Check whether the Architectural PerfMon supports
2542          * Branch Misses Retired hw_event or not.
2543          */
2544         cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
2545         if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
2546                 return -ENODEV;
2547
2548         version = eax.split.version_id;
2549         if (version < 2)
2550                 x86_pmu = core_pmu;
2551         else
2552                 x86_pmu = intel_pmu;
2553
2554         x86_pmu.version                 = version;
2555         x86_pmu.num_counters            = eax.split.num_counters;
2556         x86_pmu.cntval_bits             = eax.split.bit_width;
2557         x86_pmu.cntval_mask             = (1ULL << eax.split.bit_width) - 1;
2558
2559         x86_pmu.events_maskl            = ebx.full;
2560         x86_pmu.events_mask_len         = eax.split.mask_length;
2561
2562         x86_pmu.max_pebs_events         = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
2563
2564         /*
2565          * Quirk: v2 perfmon does not report fixed-purpose events, so
2566          * assume at least 3 events:
2567          */
2568         if (version > 1)
2569                 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
2570
2571         if (boot_cpu_has(X86_FEATURE_PDCM)) {
2572                 u64 capabilities;
2573
2574                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
2575                 x86_pmu.intel_cap.capabilities = capabilities;
2576         }
2577
2578         intel_ds_init();
2579
2580         x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
2581
2582         /*
2583          * Install the hw-cache-events table:
2584          */
2585         switch (boot_cpu_data.x86_model) {
2586         case 14: /* 65nm Core "Yonah" */
2587                 pr_cont("Core events, ");
2588                 break;
2589
2590         case 15: /* 65nm Core2 "Merom"          */
2591                 x86_add_quirk(intel_clovertown_quirk);
2592         case 22: /* 65nm Core2 "Merom-L"        */
2593         case 23: /* 45nm Core2 "Penryn"         */
2594         case 29: /* 45nm Core2 "Dunnington (MP) */
2595                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2596                        sizeof(hw_cache_event_ids));
2597
2598                 intel_pmu_lbr_init_core();
2599
2600                 x86_pmu.event_constraints = intel_core2_event_constraints;
2601                 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
2602                 pr_cont("Core2 events, ");
2603                 break;
2604
2605         case 30: /* 45nm Nehalem    */
2606         case 26: /* 45nm Nehalem-EP */
2607         case 46: /* 45nm Nehalem-EX */
2608                 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2609                        sizeof(hw_cache_event_ids));
2610                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2611                        sizeof(hw_cache_extra_regs));
2612
2613                 intel_pmu_lbr_init_nhm();
2614
2615                 x86_pmu.event_constraints = intel_nehalem_event_constraints;
2616                 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
2617                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
2618                 x86_pmu.extra_regs = intel_nehalem_extra_regs;
2619
2620                 x86_pmu.cpu_events = nhm_events_attrs;
2621
2622                 /* UOPS_ISSUED.STALLED_CYCLES */
2623                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2624                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2625                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
2626                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2627                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
2628
2629                 x86_add_quirk(intel_nehalem_quirk);
2630
2631                 pr_cont("Nehalem events, ");
2632                 break;
2633
2634         case 28: /* 45nm Atom "Pineview"   */
2635         case 38: /* 45nm Atom "Lincroft"   */
2636         case 39: /* 32nm Atom "Penwell"    */
2637         case 53: /* 32nm Atom "Cloverview" */
2638         case 54: /* 32nm Atom "Cedarview"  */
2639                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2640                        sizeof(hw_cache_event_ids));
2641
2642                 intel_pmu_lbr_init_atom();
2643
2644                 x86_pmu.event_constraints = intel_gen_event_constraints;
2645                 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
2646                 pr_cont("Atom events, ");
2647                 break;
2648
2649         case 55: /* 22nm Atom "Silvermont"                */
2650         case 76: /* 14nm Atom "Airmont"                   */
2651         case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
2652                 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
2653                         sizeof(hw_cache_event_ids));
2654                 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
2655                        sizeof(hw_cache_extra_regs));
2656
2657                 intel_pmu_lbr_init_atom();
2658
2659                 x86_pmu.event_constraints = intel_slm_event_constraints;
2660                 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
2661                 x86_pmu.extra_regs = intel_slm_extra_regs;
2662                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2663                 pr_cont("Silvermont events, ");
2664                 break;
2665
2666         case 37: /* 32nm Westmere    */
2667         case 44: /* 32nm Westmere-EP */
2668         case 47: /* 32nm Westmere-EX */
2669                 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
2670                        sizeof(hw_cache_event_ids));
2671                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2672                        sizeof(hw_cache_extra_regs));
2673
2674                 intel_pmu_lbr_init_nhm();
2675
2676                 x86_pmu.event_constraints = intel_westmere_event_constraints;
2677                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
2678                 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
2679                 x86_pmu.extra_regs = intel_westmere_extra_regs;
2680                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2681
2682                 x86_pmu.cpu_events = nhm_events_attrs;
2683
2684                 /* UOPS_ISSUED.STALLED_CYCLES */
2685                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2686                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2687                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
2688                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2689                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
2690
2691                 pr_cont("Westmere events, ");
2692                 break;
2693
2694         case 42: /* 32nm SandyBridge         */
2695         case 45: /* 32nm SandyBridge-E/EN/EP */
2696                 x86_add_quirk(intel_sandybridge_quirk);
2697                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2698                        sizeof(hw_cache_event_ids));
2699                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2700                        sizeof(hw_cache_extra_regs));
2701
2702                 intel_pmu_lbr_init_snb();
2703
2704                 x86_pmu.event_constraints = intel_snb_event_constraints;
2705                 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
2706                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2707                 if (boot_cpu_data.x86_model == 45)
2708                         x86_pmu.extra_regs = intel_snbep_extra_regs;
2709                 else
2710                         x86_pmu.extra_regs = intel_snb_extra_regs;
2711                 /* all extra regs are per-cpu when HT is on */
2712                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2713                 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2714
2715                 x86_pmu.cpu_events = snb_events_attrs;
2716
2717                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2718                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2719                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2720                 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
2721                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2722                         X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
2723
2724                 pr_cont("SandyBridge events, ");
2725                 break;
2726
2727         case 58: /* 22nm IvyBridge       */
2728         case 62: /* 22nm IvyBridge-EP/EX */
2729                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2730                        sizeof(hw_cache_event_ids));
2731                 /* dTLB-load-misses on IVB is different than SNB */
2732                 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
2733
2734                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2735                        sizeof(hw_cache_extra_regs));
2736
2737                 intel_pmu_lbr_init_snb();
2738
2739                 x86_pmu.event_constraints = intel_ivb_event_constraints;
2740                 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
2741                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2742                 if (boot_cpu_data.x86_model == 62)
2743                         x86_pmu.extra_regs = intel_snbep_extra_regs;
2744                 else
2745                         x86_pmu.extra_regs = intel_snb_extra_regs;
2746                 /* all extra regs are per-cpu when HT is on */
2747                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2748                 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2749
2750                 x86_pmu.cpu_events = snb_events_attrs;
2751
2752                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2753                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2754                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2755
2756                 pr_cont("IvyBridge events, ");
2757                 break;
2758
2759
2760         case 60: /* 22nm Haswell Core */
2761         case 63: /* 22nm Haswell Server */
2762         case 69: /* 22nm Haswell ULT */
2763         case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
2764                 x86_pmu.late_ack = true;
2765                 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
2766                 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
2767
2768                 intel_pmu_lbr_init_hsw();
2769
2770                 x86_pmu.event_constraints = intel_hsw_event_constraints;
2771                 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
2772                 x86_pmu.extra_regs = intel_snbep_extra_regs;
2773                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2774                 /* all extra regs are per-cpu when HT is on */
2775                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2776                 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2777
2778                 x86_pmu.hw_config = hsw_hw_config;
2779                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
2780                 x86_pmu.cpu_events = hsw_events_attrs;
2781                 x86_pmu.lbr_double_abort = true;
2782                 pr_cont("Haswell events, ");
2783                 break;
2784
2785         case 61: /* 14nm Broadwell Core-M */
2786         case 86: /* 14nm Broadwell Xeon D */
2787                 x86_pmu.late_ack = true;
2788                 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
2789                 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
2790
2791                 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
2792                 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
2793                                                                          BDW_L3_MISS|HSW_SNOOP_DRAM;
2794                 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
2795                                                                           HSW_SNOOP_DRAM;
2796                 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
2797                                                                              BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
2798                 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
2799                                                                               BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
2800
2801                 intel_pmu_lbr_init_snb();
2802
2803                 x86_pmu.event_constraints = intel_bdw_event_constraints;
2804                 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
2805                 x86_pmu.extra_regs = intel_snbep_extra_regs;
2806                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2807                 /* all extra regs are per-cpu when HT is on */
2808                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2809                 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2810
2811                 x86_pmu.hw_config = hsw_hw_config;
2812                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
2813                 x86_pmu.cpu_events = hsw_events_attrs;
2814                 x86_pmu.limit_period = bdw_limit_period;
2815                 pr_cont("Broadwell events, ");
2816                 break;
2817
2818         default:
2819                 switch (x86_pmu.version) {
2820                 case 1:
2821                         x86_pmu.event_constraints = intel_v1_event_constraints;
2822                         pr_cont("generic architected perfmon v1, ");
2823                         break;
2824                 default:
2825                         /*
2826                          * default constraints for v2 and up
2827                          */
2828                         x86_pmu.event_constraints = intel_gen_event_constraints;
2829                         pr_cont("generic architected perfmon, ");
2830                         break;
2831                 }
2832         }
2833
2834         if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
2835                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2836                      x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
2837                 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
2838         }
2839         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2840
2841         if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
2842                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2843                      x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
2844                 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
2845         }
2846
2847         x86_pmu.intel_ctrl |=
2848                 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
2849
2850         if (x86_pmu.event_constraints) {
2851                 /*
2852                  * event on fixed counter2 (REF_CYCLES) only works on this
2853                  * counter, so do not extend mask to generic counters
2854                  */
2855                 for_each_event_constraint(c, x86_pmu.event_constraints) {
2856                         if (c->cmask != FIXED_EVENT_FLAGS
2857                             || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
2858                                 continue;
2859                         }
2860
2861                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
2862                         c->weight += x86_pmu.num_counters;
2863                 }
2864         }
2865
2866         /*
2867          * Access LBR MSR may cause #GP under certain circumstances.
2868          * E.g. KVM doesn't support LBR MSR
2869          * Check all LBT MSR here.
2870          * Disable LBR access if any LBR MSRs can not be accessed.
2871          */
2872         if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
2873                 x86_pmu.lbr_nr = 0;
2874         for (i = 0; i < x86_pmu.lbr_nr; i++) {
2875                 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
2876                       check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
2877                         x86_pmu.lbr_nr = 0;
2878         }
2879
2880         /*
2881          * Access extra MSR may cause #GP under certain circumstances.
2882          * E.g. KVM doesn't support offcore event
2883          * Check all extra_regs here.
2884          */
2885         if (x86_pmu.extra_regs) {
2886                 for (er = x86_pmu.extra_regs; er->msr; er++) {
2887                         er->extra_msr_access = check_msr(er->msr, 0x1ffUL);
2888                         /* Disable LBR select mapping */
2889                         if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
2890                                 x86_pmu.lbr_sel_map = NULL;
2891                 }
2892         }
2893
2894         /* Support full width counters using alternative MSR range */
2895         if (x86_pmu.intel_cap.full_width_write) {
2896                 x86_pmu.max_period = x86_pmu.cntval_mask;
2897                 x86_pmu.perfctr = MSR_IA32_PMC0;
2898                 pr_cont("full-width counters, ");
2899         }
2900
2901         return 0;
2902 }