arch/x86/kernel/cpu/perf_counter.c

   1 /*
   2  * Performance counter x86 architecture code
   3  *
   4  *  Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright(C) 2008 Red Hat, Inc., Ingo Molnar
   6  *  Copyright(C) 2009 Jaswinder Singh Rajput
   7  *  Copyright(C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *
   9  *  For licencing details see kernel-base/COPYING
  10  */
  11
  12 #include <linux/perf_counter.h>
  13 #include <linux/capability.h>
  14 #include <linux/notifier.h>
  15 #include <linux/hardirq.h>
  16 #include <linux/kprobes.h>
  17 #include <linux/module.h>
  18 #include <linux/kdebug.h>
  19 #include <linux/sched.h>
  20 #include <linux/uaccess.h>
  21
  22 #include <asm/apic.h>
  23 #include <asm/stacktrace.h>
  24 #include <asm/nmi.h>
  25
  26 static u64 perf_counter_mask __read_mostly;
  27
  28 struct cpu_hw_counters {
  29         struct perf_counter     *counters[X86_PMC_IDX_MAX];
  30         unsigned long           used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  31         unsigned long           active[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  32         unsigned long           interrupts;
  33         u64                     throttle_ctrl;
  34         int                     enabled;
  35 };
  36
  37 /*
  38  * struct x86_pmu - generic x86 pmu
  39  */
  40 struct x86_pmu {
  41         const char      *name;
  42         int             version;
  43         int             (*handle_irq)(struct pt_regs *, int);
  44         u64             (*save_disable_all)(void);
  45         void            (*restore_all)(u64);
  46         void            (*enable)(struct hw_perf_counter *, int);
  47         void            (*disable)(struct hw_perf_counter *, int);
  48         unsigned        eventsel;
  49         unsigned        perfctr;
  50         u64             (*event_map)(int);
  51         u64             (*raw_event)(u64);
  52         int             max_events;
  53         int             num_counters;
  54         int             num_counters_fixed;
  55         int             counter_bits;
  56         u64             counter_mask;
  57 };
  58
  59 static struct x86_pmu x86_pmu __read_mostly;
  60
  61 static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
  62         .enabled = 1,
  63 };
  64
  65 /*
  66  * Intel PerfMon v3. Used on Core2 and later.
  67  */
  68 static const u64 intel_perfmon_event_map[] =
  69 {
  70   [PERF_COUNT_CPU_CYCLES]               = 0x003c,
  71   [PERF_COUNT_INSTRUCTIONS]             = 0x00c0,
  72   [PERF_COUNT_CACHE_REFERENCES]         = 0x4f2e,
  73   [PERF_COUNT_CACHE_MISSES]             = 0x412e,
  74   [PERF_COUNT_BRANCH_INSTRUCTIONS]      = 0x00c4,
  75   [PERF_COUNT_BRANCH_MISSES]            = 0x00c5,
  76   [PERF_COUNT_BUS_CYCLES]               = 0x013c,
  77 };
  78
  79 static u64 intel_pmu_event_map(int event)
  80 {
  81         return intel_perfmon_event_map[event];
  82 }
  83
  84 static u64 intel_pmu_raw_event(u64 event)
  85 {
  86 #define CORE_EVNTSEL_EVENT_MASK         0x000000FFULL
  87 #define CORE_EVNTSEL_UNIT_MASK          0x0000FF00ULL
  88 #define CORE_EVNTSEL_COUNTER_MASK       0xFF000000ULL
  89
  90 #define CORE_EVNTSEL_MASK               \
  91         (CORE_EVNTSEL_EVENT_MASK |      \
  92          CORE_EVNTSEL_UNIT_MASK  |      \
  93          CORE_EVNTSEL_COUNTER_MASK)
  94
  95         return event & CORE_EVNTSEL_MASK;
  96 }
  97
  98 /*
  99  * AMD Performance Monitor K7 and later.
 100  */
 101 static const u64 amd_perfmon_event_map[] =
 102 {
 103   [PERF_COUNT_CPU_CYCLES]               = 0x0076,
 104   [PERF_COUNT_INSTRUCTIONS]             = 0x00c0,
 105   [PERF_COUNT_CACHE_REFERENCES]         = 0x0080,
 106   [PERF_COUNT_CACHE_MISSES]             = 0x0081,
 107   [PERF_COUNT_BRANCH_INSTRUCTIONS]      = 0x00c4,
 108   [PERF_COUNT_BRANCH_MISSES]            = 0x00c5,
 109 };
 110
 111 static u64 amd_pmu_event_map(int event)
 112 {
 113         return amd_perfmon_event_map[event];
 114 }
 115
 116 static u64 amd_pmu_raw_event(u64 event)
 117 {
 118 #define K7_EVNTSEL_EVENT_MASK   0x7000000FFULL
 119 #define K7_EVNTSEL_UNIT_MASK    0x00000FF00ULL
 120 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
 121
 122 #define K7_EVNTSEL_MASK                 \
 123         (K7_EVNTSEL_EVENT_MASK |        \
 124          K7_EVNTSEL_UNIT_MASK  |        \
 125          K7_EVNTSEL_COUNTER_MASK)
 126
 127         return event & K7_EVNTSEL_MASK;
 128 }
 129
 130 /*
 131  * Propagate counter elapsed time into the generic counter.
 132  * Can only be executed on the CPU where the counter is active.
 133  * Returns the delta events processed.
 134  */
 135 static u64
 136 x86_perf_counter_update(struct perf_counter *counter,
 137                         struct hw_perf_counter *hwc, int idx)
 138 {
 139         u64 prev_raw_count, new_raw_count, delta;
 140
 141         /*
 142          * Careful: an NMI might modify the previous counter value.
 143          *
 144          * Our tactic to handle this is to first atomically read and
 145          * exchange a new raw count - then add that new-prev delta
 146          * count to the generic counter atomically:
 147          */
 148 again:
 149         prev_raw_count = atomic64_read(&hwc->prev_count);
 150         rdmsrl(hwc->counter_base + idx, new_raw_count);
 151
 152         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
 153                                         new_raw_count) != prev_raw_count)
 154                 goto again;
 155
 156         /*
 157          * Now we have the new raw value and have updated the prev
 158          * timestamp already. We can now calculate the elapsed delta
 159          * (counter-)time and add that to the generic counter.
 160          *
 161          * Careful, not all hw sign-extends above the physical width
 162          * of the count, so we do that by clipping the delta to 32 bits:
 163          */
 164         delta = (u64)(u32)((s32)new_raw_count - (s32)prev_raw_count);
 165
 166         atomic64_add(delta, &counter->count);
 167         atomic64_sub(delta, &hwc->period_left);
 168
 169         return new_raw_count;
 170 }
 171
 172 static atomic_t num_counters;
 173 static DEFINE_MUTEX(pmc_reserve_mutex);
 174
 175 static bool reserve_pmc_hardware(void)
 176 {
 177         int i;
 178
 179         if (nmi_watchdog == NMI_LOCAL_APIC)
 180                 disable_lapic_nmi_watchdog();
 181
 182         for (i = 0; i < x86_pmu.num_counters; i++) {
 183                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 184                         goto perfctr_fail;
 185         }
 186
 187         for (i = 0; i < x86_pmu.num_counters; i++) {
 188                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 189                         goto eventsel_fail;
 190         }
 191
 192         return true;
 193
 194 eventsel_fail:
 195         for (i--; i >= 0; i--)
 196                 release_evntsel_nmi(x86_pmu.eventsel + i);
 197
 198         i = x86_pmu.num_counters;
 199
 200 perfctr_fail:
 201         for (i--; i >= 0; i--)
 202                 release_perfctr_nmi(x86_pmu.perfctr + i);
 203
 204         if (nmi_watchdog == NMI_LOCAL_APIC)
 205                 enable_lapic_nmi_watchdog();
 206
 207         return false;
 208 }
 209
 210 static void release_pmc_hardware(void)
 211 {
 212         int i;
 213
 214         for (i = 0; i < x86_pmu.num_counters; i++) {
 215                 release_perfctr_nmi(x86_pmu.perfctr + i);
 216                 release_evntsel_nmi(x86_pmu.eventsel + i);
 217         }
 218
 219         if (nmi_watchdog == NMI_LOCAL_APIC)
 220                 enable_lapic_nmi_watchdog();
 221 }
 222
 223 static void hw_perf_counter_destroy(struct perf_counter *counter)
 224 {
 225         if (atomic_dec_and_mutex_lock(&num_counters, &pmc_reserve_mutex)) {
 226                 release_pmc_hardware();
 227                 mutex_unlock(&pmc_reserve_mutex);
 228         }
 229 }
 230
 231 static inline int x86_pmu_initialized(void)
 232 {
 233         return x86_pmu.handle_irq != NULL;
 234 }
 235
 236 /*
 237  * Setup the hardware configuration for a given hw_event_type
 238  */
 239 static int __hw_perf_counter_init(struct perf_counter *counter)
 240 {
 241         struct perf_counter_hw_event *hw_event = &counter->hw_event;
 242         struct hw_perf_counter *hwc = &counter->hw;
 243         int err;
 244
 245         if (!x86_pmu_initialized())
 246                 return -ENODEV;
 247
 248         err = 0;
 249         if (atomic_inc_not_zero(&num_counters)) {
 250                 mutex_lock(&pmc_reserve_mutex);
 251                 if (atomic_read(&num_counters) == 0 && !reserve_pmc_hardware())
 252                         err = -EBUSY;
 253                 else
 254                         atomic_inc(&num_counters);
 255                 mutex_unlock(&pmc_reserve_mutex);
 256         }
 257         if (err)
 258                 return err;
 259
 260         /*
 261          * Generate PMC IRQs:
 262          * (keep 'enabled' bit clear for now)
 263          */
 264         hwc->config = ARCH_PERFMON_EVENTSEL_INT;
 265
 266         /*
 267          * Count user and OS events unless requested not to.
 268          */
 269         if (!hw_event->exclude_user)
 270                 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
 271         if (!hw_event->exclude_kernel)
 272                 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
 273
 274         /*
 275          * If privileged enough, allow NMI events:
 276          */
 277         hwc->nmi = 0;
 278         if (capable(CAP_SYS_ADMIN) && hw_event->nmi)
 279                 hwc->nmi = 1;
 280
 281         hwc->irq_period         = hw_event->irq_period;
 282         /*
 283          * Intel PMCs cannot be accessed sanely above 32 bit width,
 284          * so we install an artificial 1<<31 period regardless of
 285          * the generic counter period:
 286          */
 287         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
 288                 if ((s64)hwc->irq_period <= 0 || hwc->irq_period > 0x7FFFFFFF)
 289                         hwc->irq_period = 0x7FFFFFFF;
 290
 291         atomic64_set(&hwc->period_left, hwc->irq_period);
 292
 293         /*
 294          * Raw event type provide the config in the event structure
 295          */
 296         if (perf_event_raw(hw_event)) {
 297                 hwc->config |= x86_pmu.raw_event(perf_event_config(hw_event));
 298         } else {
 299                 if (perf_event_id(hw_event) >= x86_pmu.max_events)
 300                         return -EINVAL;
 301                 /*
 302                  * The generic map:
 303                  */
 304                 hwc->config |= x86_pmu.event_map(perf_event_id(hw_event));
 305         }
 306
 307         counter->destroy = hw_perf_counter_destroy;
 308
 309         return 0;
 310 }
 311
 312 static u64 intel_pmu_save_disable_all(void)
 313 {
 314         u64 ctrl;
 315
 316         rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
 317         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
 318
 319         return ctrl;
 320 }
 321
 322 static u64 amd_pmu_save_disable_all(void)
 323 {
 324         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 325         int enabled, idx;
 326
 327         enabled = cpuc->enabled;
 328         cpuc->enabled = 0;
 329         /*
 330          * ensure we write the disable before we start disabling the
 331          * counters proper, so that amd_pmu_enable_counter() does the
 332          * right thing.
 333          */
 334         barrier();
 335
 336         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 337                 u64 val;
 338
 339                 if (!test_bit(idx, cpuc->active))
 340                         continue;
 341                 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
 342                 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
 343                         continue;
 344                 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
 345                 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
 346         }
 347
 348         return enabled;
 349 }
 350
 351 u64 hw_perf_save_disable(void)
 352 {
 353         if (!x86_pmu_initialized())
 354                 return 0;
 355         return x86_pmu.save_disable_all();
 356 }
 357 /*
 358  * Exported because of ACPI idle
 359  */
 360 EXPORT_SYMBOL_GPL(hw_perf_save_disable);
 361
 362 static void intel_pmu_restore_all(u64 ctrl)
 363 {
 364         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
 365 }
 366
 367 static void amd_pmu_restore_all(u64 ctrl)
 368 {
 369         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 370         int idx;
 371
 372         cpuc->enabled = ctrl;
 373         barrier();
 374         if (!ctrl)
 375                 return;
 376
 377         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 378                 u64 val;
 379
 380                 if (!test_bit(idx, cpuc->active))
 381                         continue;
 382                 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
 383                 if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
 384                         continue;
 385                 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 386                 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
 387         }
 388 }
 389
 390 void hw_perf_restore(u64 ctrl)
 391 {
 392         if (!x86_pmu_initialized())
 393                 return;
 394         x86_pmu.restore_all(ctrl);
 395 }
 396 /*
 397  * Exported because of ACPI idle
 398  */
 399 EXPORT_SYMBOL_GPL(hw_perf_restore);
 400
 401 static inline u64 intel_pmu_get_status(u64 mask)
 402 {
 403         u64 status;
 404
 405         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
 406
 407         return status;
 408 }
 409
 410 static inline void intel_pmu_ack_status(u64 ack)
 411 {
 412         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
 413 }
 414
 415 static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
 416 {
 417         int err;
 418         err = checking_wrmsrl(hwc->config_base + idx,
 419                               hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
 420 }
 421
 422 static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
 423 {
 424         int err;
 425         err = checking_wrmsrl(hwc->config_base + idx,
 426                               hwc->config);
 427 }
 428
 429 static inline void
 430 intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx)
 431 {
 432         int idx = __idx - X86_PMC_IDX_FIXED;
 433         u64 ctrl_val, mask;
 434         int err;
 435
 436         mask = 0xfULL << (idx * 4);
 437
 438         rdmsrl(hwc->config_base, ctrl_val);
 439         ctrl_val &= ~mask;
 440         err = checking_wrmsrl(hwc->config_base, ctrl_val);
 441 }
 442
 443 static inline void
 444 intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
 445 {
 446         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
 447                 intel_pmu_disable_fixed(hwc, idx);
 448                 return;
 449         }
 450
 451         x86_pmu_disable_counter(hwc, idx);
 452 }
 453
 454 static inline void
 455 amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
 456 {
 457         x86_pmu_disable_counter(hwc, idx);
 458 }
 459
 460 static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]);
 461
 462 /*
 463  * Set the next IRQ period, based on the hwc->period_left value.
 464  * To be called with the counter disabled in hw:
 465  */
 466 static void
 467 x86_perf_counter_set_period(struct perf_counter *counter,
 468                              struct hw_perf_counter *hwc, int idx)
 469 {
 470         s64 left = atomic64_read(&hwc->period_left);
 471         s64 period = hwc->irq_period;
 472         int err;
 473
 474         /*
 475          * If we are way outside a reasoable range then just skip forward:
 476          */
 477         if (unlikely(left <= -period)) {
 478                 left = period;
 479                 atomic64_set(&hwc->period_left, left);
 480         }
 481
 482         if (unlikely(left <= 0)) {
 483                 left += period;
 484                 atomic64_set(&hwc->period_left, left);
 485         }
 486
 487         per_cpu(prev_left[idx], smp_processor_id()) = left;
 488
 489         /*
 490          * The hw counter starts counting from this counter offset,
 491          * mark it to be able to extra future deltas:
 492          */
 493         atomic64_set(&hwc->prev_count, (u64)-left);
 494
 495         err = checking_wrmsrl(hwc->counter_base + idx,
 496                              (u64)(-left) & x86_pmu.counter_mask);
 497 }
 498
 499 static inline void
 500 intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx)
 501 {
 502         int idx = __idx - X86_PMC_IDX_FIXED;
 503         u64 ctrl_val, bits, mask;
 504         int err;
 505
 506         /*
 507          * Enable IRQ generation (0x8),
 508          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
 509          * if requested:
 510          */
 511         bits = 0x8ULL;
 512         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
 513                 bits |= 0x2;
 514         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
 515                 bits |= 0x1;
 516         bits <<= (idx * 4);
 517         mask = 0xfULL << (idx * 4);
 518
 519         rdmsrl(hwc->config_base, ctrl_val);
 520         ctrl_val &= ~mask;
 521         ctrl_val |= bits;
 522         err = checking_wrmsrl(hwc->config_base, ctrl_val);
 523 }
 524
 525 static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
 526 {
 527         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
 528                 intel_pmu_enable_fixed(hwc, idx);
 529                 return;
 530         }
 531
 532         x86_pmu_enable_counter(hwc, idx);
 533 }
 534
 535 static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
 536 {
 537         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 538
 539         if (cpuc->enabled)
 540                 x86_pmu_enable_counter(hwc, idx);
 541         else
 542                 x86_pmu_disable_counter(hwc, idx);
 543 }
 544
 545 static int
 546 fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
 547 {
 548         unsigned int event;
 549
 550         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
 551                 return -1;
 552
 553         if (unlikely(hwc->nmi))
 554                 return -1;
 555
 556         event = hwc->config & ARCH_PERFMON_EVENT_MASK;
 557
 558         if (unlikely(event == x86_pmu.event_map(PERF_COUNT_INSTRUCTIONS)))
 559                 return X86_PMC_IDX_FIXED_INSTRUCTIONS;
 560         if (unlikely(event == x86_pmu.event_map(PERF_COUNT_CPU_CYCLES)))
 561                 return X86_PMC_IDX_FIXED_CPU_CYCLES;
 562         if (unlikely(event == x86_pmu.event_map(PERF_COUNT_BUS_CYCLES)))
 563                 return X86_PMC_IDX_FIXED_BUS_CYCLES;
 564
 565         return -1;
 566 }
 567
 568 /*
 569  * Find a PMC slot for the freshly enabled / scheduled in counter:
 570  */
 571 static int x86_pmu_enable(struct perf_counter *counter)
 572 {
 573         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 574         struct hw_perf_counter *hwc = &counter->hw;
 575         int idx;
 576
 577         idx = fixed_mode_idx(counter, hwc);
 578         if (idx >= 0) {
 579                 /*
 580                  * Try to get the fixed counter, if that is already taken
 581                  * then try to get a generic counter:
 582                  */
 583                 if (test_and_set_bit(idx, cpuc->used))
 584                         goto try_generic;
 585
 586                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 587                 /*
 588                  * We set it so that counter_base + idx in wrmsr/rdmsr maps to
 589                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 590                  */
 591                 hwc->counter_base =
 592                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 593                 hwc->idx = idx;
 594         } else {
 595                 idx = hwc->idx;
 596                 /* Try to get the previous generic counter again */
 597                 if (test_and_set_bit(idx, cpuc->used)) {
 598 try_generic:
 599                         idx = find_first_zero_bit(cpuc->used,
 600                                                   x86_pmu.num_counters);
 601                         if (idx == x86_pmu.num_counters)
 602                                 return -EAGAIN;
 603
 604                         set_bit(idx, cpuc->used);
 605                         hwc->idx = idx;
 606                 }
 607                 hwc->config_base  = x86_pmu.eventsel;
 608                 hwc->counter_base = x86_pmu.perfctr;
 609         }
 610
 611         perf_counters_lapic_init(hwc->nmi);
 612
 613         x86_pmu.disable(hwc, idx);
 614
 615         cpuc->counters[idx] = counter;
 616         set_bit(idx, cpuc->active);
 617
 618         x86_perf_counter_set_period(counter, hwc, idx);
 619         x86_pmu.enable(hwc, idx);
 620
 621         return 0;
 622 }
 623
 624 void perf_counter_print_debug(void)
 625 {
 626         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
 627         struct cpu_hw_counters *cpuc;
 628         int cpu, idx;
 629
 630         if (!x86_pmu.num_counters)
 631                 return;
 632
 633         local_irq_disable();
 634
 635         cpu = smp_processor_id();
 636         cpuc = &per_cpu(cpu_hw_counters, cpu);
 637
 638         if (x86_pmu.version >= 2) {
 639                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
 640                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
 641                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
 642                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
 643
 644                 pr_info("\n");
 645                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
 646                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
 647                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
 648                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
 649         }
 650         pr_info("CPU#%d: used:       %016llx\n", cpu, *(u64 *)cpuc->used);
 651
 652         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 653                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
 654                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
 655
 656                 prev_left = per_cpu(prev_left[idx], cpu);
 657
 658                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
 659                         cpu, idx, pmc_ctrl);
 660                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
 661                         cpu, idx, pmc_count);
 662                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
 663                         cpu, idx, prev_left);
 664         }
 665         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
 666                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
 667
 668                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
 669                         cpu, idx, pmc_count);
 670         }
 671         local_irq_enable();
 672 }
 673
 674 static void x86_pmu_disable(struct perf_counter *counter)
 675 {
 676         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 677         struct hw_perf_counter *hwc = &counter->hw;
 678         int idx = hwc->idx;
 679
 680         /*
 681          * Must be done before we disable, otherwise the nmi handler
 682          * could reenable again:
 683          */
 684         clear_bit(idx, cpuc->active);
 685         x86_pmu.disable(hwc, idx);
 686
 687         /*
 688          * Make sure the cleared pointer becomes visible before we
 689          * (potentially) free the counter:
 690          */
 691         barrier();
 692
 693         /*
 694          * Drain the remaining delta count out of a counter
 695          * that we are disabling:
 696          */
 697         x86_perf_counter_update(counter, hwc, idx);
 698         cpuc->counters[idx] = NULL;
 699         clear_bit(idx, cpuc->used);
 700 }
 701
 702 /*
 703  * Save and restart an expired counter. Called by NMI contexts,
 704  * so it has to be careful about preempting normal counter ops:
 705  */
 706 static void intel_pmu_save_and_restart(struct perf_counter *counter)
 707 {
 708         struct hw_perf_counter *hwc = &counter->hw;
 709         int idx = hwc->idx;
 710
 711         x86_perf_counter_update(counter, hwc, idx);
 712         x86_perf_counter_set_period(counter, hwc, idx);
 713
 714         if (counter->state == PERF_COUNTER_STATE_ACTIVE)
 715                 intel_pmu_enable_counter(hwc, idx);
 716 }
 717
 718 /*
 719  * Maximum interrupt frequency of 100KHz per CPU
 720  */
 721 #define PERFMON_MAX_INTERRUPTS (100000/HZ)
 722
 723 /*
 724  * This handler is triggered by the local APIC, so the APIC IRQ handling
 725  * rules apply:
 726  */
 727 static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi)
 728 {
 729         int bit, cpu = smp_processor_id();
 730         u64 ack, status;
 731         struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu);
 732         int ret = 0;
 733
 734         cpuc->throttle_ctrl = intel_pmu_save_disable_all();
 735
 736         status = intel_pmu_get_status(cpuc->throttle_ctrl);
 737         if (!status)
 738                 goto out;
 739
 740         ret = 1;
 741 again:
 742         inc_irq_stat(apic_perf_irqs);
 743         ack = status;
 744         for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
 745                 struct perf_counter *counter = cpuc->counters[bit];
 746
 747                 clear_bit(bit, (unsigned long *) &status);
 748                 if (!test_bit(bit, cpuc->active))
 749                         continue;
 750
 751                 intel_pmu_save_and_restart(counter);
 752                 if (perf_counter_overflow(counter, nmi, regs, 0))
 753                         intel_pmu_disable_counter(&counter->hw, bit);
 754         }
 755
 756         intel_pmu_ack_status(ack);
 757
 758         /*
 759          * Repeat if there is more work to be done:
 760          */
 761         status = intel_pmu_get_status(cpuc->throttle_ctrl);
 762         if (status)
 763                 goto again;
 764 out:
 765         /*
 766          * Restore - do not reenable when global enable is off or throttled:
 767          */
 768         if (++cpuc->interrupts < PERFMON_MAX_INTERRUPTS)
 769                 intel_pmu_restore_all(cpuc->throttle_ctrl);
 770
 771         return ret;
 772 }
 773
 774 static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi)
 775 {
 776         int cpu = smp_processor_id();
 777         struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu);
 778         u64 val;
 779         int handled = 0;
 780         struct perf_counter *counter;
 781         struct hw_perf_counter *hwc;
 782         int idx;
 783
 784         ++cpuc->interrupts;
 785         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 786                 if (!test_bit(idx, cpuc->active))
 787                         continue;
 788                 counter = cpuc->counters[idx];
 789                 hwc = &counter->hw;
 790                 val = x86_perf_counter_update(counter, hwc, idx);
 791                 if (val & (1ULL << (x86_pmu.counter_bits - 1)))
 792                         continue;
 793                 /* counter overflow */
 794                 x86_perf_counter_set_period(counter, hwc, idx);
 795                 handled = 1;
 796                 inc_irq_stat(apic_perf_irqs);
 797                 if (perf_counter_overflow(counter, nmi, regs, 0))
 798                         amd_pmu_disable_counter(hwc, idx);
 799                 else if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS)
 800                         /*
 801                          * do not reenable when throttled, but reload
 802                          * the register
 803                          */
 804                         amd_pmu_disable_counter(hwc, idx);
 805                 else if (counter->state == PERF_COUNTER_STATE_ACTIVE)
 806                         amd_pmu_enable_counter(hwc, idx);
 807         }
 808         return handled;
 809 }
 810
 811 void perf_counter_unthrottle(void)
 812 {
 813         struct cpu_hw_counters *cpuc;
 814
 815         if (!x86_pmu_initialized())
 816                 return;
 817
 818         cpuc = &__get_cpu_var(cpu_hw_counters);
 819         if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) {
 820                 if (printk_ratelimit())
 821                         printk(KERN_WARNING "PERFMON: max interrupts exceeded!\n");
 822                 hw_perf_restore(cpuc->throttle_ctrl);
 823         }
 824         cpuc->interrupts = 0;
 825 }
 826
 827 void smp_perf_counter_interrupt(struct pt_regs *regs)
 828 {
 829         irq_enter();
 830         apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
 831         ack_APIC_irq();
 832         x86_pmu.handle_irq(regs, 0);
 833         irq_exit();
 834 }
 835
 836 void smp_perf_pending_interrupt(struct pt_regs *regs)
 837 {
 838         irq_enter();
 839         ack_APIC_irq();
 840         inc_irq_stat(apic_pending_irqs);
 841         perf_counter_do_pending();
 842         irq_exit();
 843 }
 844
 845 void set_perf_counter_pending(void)
 846 {
 847         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
 848 }
 849
 850 void perf_counters_lapic_init(int nmi)
 851 {
 852         u32 apic_val;
 853
 854         if (!x86_pmu_initialized())
 855                 return;
 856
 857         /*
 858          * Enable the performance counter vector in the APIC LVT:
 859          */
 860         apic_val = apic_read(APIC_LVTERR);
 861
 862         apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED);
 863         if (nmi)
 864                 apic_write(APIC_LVTPC, APIC_DM_NMI);
 865         else
 866                 apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
 867         apic_write(APIC_LVTERR, apic_val);
 868 }
 869
 870 static int __kprobes
 871 perf_counter_nmi_handler(struct notifier_block *self,
 872                          unsigned long cmd, void *__args)
 873 {
 874         struct die_args *args = __args;
 875         struct pt_regs *regs;
 876         int ret;
 877
 878         switch (cmd) {
 879         case DIE_NMI:
 880         case DIE_NMI_IPI:
 881                 break;
 882
 883         default:
 884                 return NOTIFY_DONE;
 885         }
 886
 887         regs = args->regs;
 888
 889         apic_write(APIC_LVTPC, APIC_DM_NMI);
 890         ret = x86_pmu.handle_irq(regs, 1);
 891
 892         return ret ? NOTIFY_STOP : NOTIFY_OK;
 893 }
 894
 895 static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
 896         .notifier_call          = perf_counter_nmi_handler,
 897         .next                   = NULL,
 898         .priority               = 1
 899 };
 900
 901 static struct x86_pmu intel_pmu = {
 902         .name                   = "Intel",
 903         .handle_irq             = intel_pmu_handle_irq,
 904         .save_disable_all       = intel_pmu_save_disable_all,
 905         .restore_all            = intel_pmu_restore_all,
 906         .enable                 = intel_pmu_enable_counter,
 907         .disable                = intel_pmu_disable_counter,
 908         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
 909         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
 910         .event_map              = intel_pmu_event_map,
 911         .raw_event              = intel_pmu_raw_event,
 912         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
 913 };
 914
 915 static struct x86_pmu amd_pmu = {
 916         .name                   = "AMD",
 917         .handle_irq             = amd_pmu_handle_irq,
 918         .save_disable_all       = amd_pmu_save_disable_all,
 919         .restore_all            = amd_pmu_restore_all,
 920         .enable                 = amd_pmu_enable_counter,
 921         .disable                = amd_pmu_disable_counter,
 922         .eventsel               = MSR_K7_EVNTSEL0,
 923         .perfctr                = MSR_K7_PERFCTR0,
 924         .event_map              = amd_pmu_event_map,
 925         .raw_event              = amd_pmu_raw_event,
 926         .max_events             = ARRAY_SIZE(amd_perfmon_event_map),
 927         .num_counters           = 4,
 928         .counter_bits           = 48,
 929         .counter_mask           = (1ULL << 48) - 1,
 930 };
 931
 932 static int intel_pmu_init(void)
 933 {
 934         union cpuid10_edx edx;
 935         union cpuid10_eax eax;
 936         unsigned int unused;
 937         unsigned int ebx;
 938         int version;
 939
 940         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 941                 return -ENODEV;
 942
 943         /*
 944          * Check whether the Architectural PerfMon supports
 945          * Branch Misses Retired Event or not.
 946          */
 947         cpuid(10, &eax.full, &ebx, &unused, &edx.full);
 948         if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
 949                 return -ENODEV;
 950
 951         version = eax.split.version_id;
 952         if (version < 2)
 953                 return -ENODEV;
 954
 955         x86_pmu = intel_pmu;
 956         x86_pmu.version = version;
 957         x86_pmu.num_counters = eax.split.num_counters;
 958         x86_pmu.num_counters_fixed = edx.split.num_counters_fixed;
 959         x86_pmu.counter_bits = eax.split.bit_width;
 960         x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1;
 961
 962         return 0;
 963 }
 964
 965 static int amd_pmu_init(void)
 966 {
 967         x86_pmu = amd_pmu;
 968         return 0;
 969 }
 970
 971 void __init init_hw_perf_counters(void)
 972 {
 973         int err;
 974
 975         switch (boot_cpu_data.x86_vendor) {
 976         case X86_VENDOR_INTEL:
 977                 err = intel_pmu_init();
 978                 break;
 979         case X86_VENDOR_AMD:
 980                 err = amd_pmu_init();
 981                 break;
 982         default:
 983                 return;
 984         }
 985         if (err != 0)
 986                 return;
 987
 988         pr_info("%s Performance Monitoring support detected.\n", x86_pmu.name);
 989         pr_info("... version:         %d\n", x86_pmu.version);
 990         pr_info("... bit width:       %d\n", x86_pmu.counter_bits);
 991
 992         pr_info("... num counters:    %d\n", x86_pmu.num_counters);
 993         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
 994                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
 995                 WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!",
 996                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
 997         }
 998         perf_counter_mask = (1 << x86_pmu.num_counters) - 1;
 999         perf_max_counters = x86_pmu.num_counters;
1000
1001         pr_info("... value mask:      %016Lx\n", x86_pmu.counter_mask);
1002
1003         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1004                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1005                 WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!",
1006                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1007         }
1008         pr_info("... fixed counters:  %d\n", x86_pmu.num_counters_fixed);
1009
1010         perf_counter_mask |=
1011                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1012
1013         pr_info("... counter mask:    %016Lx\n", perf_counter_mask);
1014
1015         perf_counters_lapic_init(0);
1016         register_die_notifier(&perf_counter_nmi_notifier);
1017 }
1018
1019 static inline void x86_pmu_read(struct perf_counter *counter)
1020 {
1021         x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
1022 }
1023
1024 static const struct pmu pmu = {
1025         .enable         = x86_pmu_enable,
1026         .disable        = x86_pmu_disable,
1027         .read           = x86_pmu_read,
1028 };
1029
1030 const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
1031 {
1032         int err;
1033
1034         err = __hw_perf_counter_init(counter);
1035         if (err)
1036                 return ERR_PTR(err);
1037
1038         return &pmu;
1039 }
1040
1041 /*
1042  * callchain support
1043  */
1044
1045 static inline
1046 void callchain_store(struct perf_callchain_entry *entry, unsigned long ip)
1047 {
1048         if (entry->nr < MAX_STACK_DEPTH)
1049                 entry->ip[entry->nr++] = ip;
1050 }
1051
1052 static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry);
1053 static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry);
1054
1055
1056 static void
1057 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1058 {
1059         /* Ignore warnings */
1060 }
1061
1062 static void backtrace_warning(void *data, char *msg)
1063 {
1064         /* Ignore warnings */
1065 }
1066
1067 static int backtrace_stack(void *data, char *name)
1068 {
1069         /* Don't bother with IRQ stacks for now */
1070         return -1;
1071 }
1072
1073 static void backtrace_address(void *data, unsigned long addr, int reliable)
1074 {
1075         struct perf_callchain_entry *entry = data;
1076
1077         if (reliable)
1078                 callchain_store(entry, addr);
1079 }
1080
1081 static const struct stacktrace_ops backtrace_ops = {
1082         .warning                = backtrace_warning,
1083         .warning_symbol         = backtrace_warning_symbol,
1084         .stack                  = backtrace_stack,
1085         .address                = backtrace_address,
1086 };
1087
1088 static void
1089 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1090 {
1091         unsigned long bp;
1092         char *stack;
1093         int nr = entry->nr;
1094
1095         callchain_store(entry, instruction_pointer(regs));
1096
1097         stack = ((char *)regs + sizeof(struct pt_regs));
1098 #ifdef CONFIG_FRAME_POINTER
1099         bp = frame_pointer(regs);
1100 #else
1101         bp = 0;
1102 #endif
1103
1104         dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry);
1105
1106         entry->kernel = entry->nr - nr;
1107 }
1108
1109
1110 struct stack_frame {
1111         const void __user       *next_fp;
1112         unsigned long           return_address;
1113 };
1114
1115 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1116 {
1117         int ret;
1118
1119         if (!access_ok(VERIFY_READ, fp, sizeof(*frame)))
1120                 return 0;
1121
1122         ret = 1;
1123         pagefault_disable();
1124         if (__copy_from_user_inatomic(frame, fp, sizeof(*frame)))
1125                 ret = 0;
1126         pagefault_enable();
1127
1128         return ret;
1129 }
1130
1131 static void
1132 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1133 {
1134         struct stack_frame frame;
1135         const void __user *fp;
1136         int nr = entry->nr;
1137
1138         regs = (struct pt_regs *)current->thread.sp0 - 1;
1139         fp   = (void __user *)regs->bp;
1140
1141         callchain_store(entry, regs->ip);
1142
1143         while (entry->nr < MAX_STACK_DEPTH) {
1144                 frame.next_fp        = NULL;
1145                 frame.return_address = 0;
1146
1147                 if (!copy_stack_frame(fp, &frame))
1148                         break;
1149
1150                 if ((unsigned long)fp < user_stack_pointer(regs))
1151                         break;
1152
1153                 callchain_store(entry, frame.return_address);
1154                 fp = frame.next_fp;
1155         }
1156
1157         entry->user = entry->nr - nr;
1158 }
1159
1160 static void
1161 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1162 {
1163         int is_user;
1164
1165         if (!regs)
1166                 return;
1167
1168         is_user = user_mode(regs);
1169
1170         if (!current || current->pid == 0)
1171                 return;
1172
1173         if (is_user && current->state != TASK_RUNNING)
1174                 return;
1175
1176         if (!is_user)
1177                 perf_callchain_kernel(regs, entry);
1178
1179         if (current->mm)
1180                 perf_callchain_user(regs, entry);
1181 }
1182
1183 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1184 {
1185         struct perf_callchain_entry *entry;
1186
1187         if (in_nmi())
1188                 entry = &__get_cpu_var(nmi_entry);
1189         else
1190                 entry = &__get_cpu_var(irq_entry);
1191
1192         entry->nr = 0;
1193         entry->hv = 0;
1194         entry->kernel = 0;
1195         entry->user = 0;
1196
1197         perf_do_callchain(regs, entry);
1198
1199         return entry;
1200 }